com.c revision 1.263
1 /* $NetBSD: com.c,v 1.263 2007/10/08 16:50:45 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.263 2007/10/08 16:50:45 ad Exp $"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 #include <sys/intr.h> 126 127 #include <machine/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 void com_power(int, void *); 182 183 int com_common_getc(dev_t, struct com_regs *); 184 void com_common_putc(dev_t, struct com_regs *, int); 185 186 int cominit(struct com_regs *, int, int, int, tcflag_t); 187 188 int comcngetc(dev_t); 189 void comcnputc(dev_t, int); 190 void comcnpollc(dev_t, int); 191 192 #define integrate static inline 193 void comsoft(void *); 194 integrate void com_rxsoft(struct com_softc *, struct tty *); 195 integrate void com_txsoft(struct com_softc *, struct tty *); 196 integrate void com_stsoft(struct com_softc *, struct tty *); 197 integrate void com_schedrx(struct com_softc *); 198 void comdiag(void *); 199 200 extern struct cfdriver com_cd; 201 202 dev_type_open(comopen); 203 dev_type_close(comclose); 204 dev_type_read(comread); 205 dev_type_write(comwrite); 206 dev_type_ioctl(comioctl); 207 dev_type_stop(comstop); 208 dev_type_tty(comtty); 209 dev_type_poll(compoll); 210 211 const struct cdevsw com_cdevsw = { 212 comopen, comclose, comread, comwrite, comioctl, 213 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 214 }; 215 216 /* 217 * Make this an option variable one can patch. 218 * But be warned: this must be a power of 2! 219 */ 220 u_int com_rbuf_size = COM_RING_SIZE; 221 222 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 223 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 224 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 225 226 static struct com_regs comconsregs; 227 static int comconsattached; 228 static int comconsrate; 229 static tcflag_t comconscflag; 230 static struct cnm_state com_cnm_state; 231 232 #ifndef __HAVE_TIMECOUNTER 233 static int ppscap = 234 PPS_TSFMT_TSPEC | 235 PPS_CAPTUREASSERT | 236 PPS_CAPTURECLEAR | 237 PPS_OFFSETASSERT | PPS_OFFSETCLEAR; 238 #endif /* !__HAVE_TIMECOUNTER */ 239 240 #ifdef KGDB 241 #include <sys/kgdb.h> 242 243 static struct com_regs comkgdbregs; 244 static int com_kgdb_attached; 245 246 int com_kgdb_getc(void *); 247 void com_kgdb_putc(void *, int); 248 #endif /* KGDB */ 249 250 #ifdef COM_REGMAP 251 /* initializer for typical 16550-ish hardware */ 252 #define COM_REG_16550 { \ 253 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 254 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 255 256 const bus_size_t com_std_map[16] = COM_REG_16550; 257 #endif /* COM_REGMAP */ 258 259 #define COMUNIT_MASK 0x7ffff 260 #define COMDIALOUT_MASK 0x80000 261 262 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 263 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 264 265 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 266 device_is_active(&(sc)->sc_dev)) 267 268 #define BR BUS_SPACE_BARRIER_READ 269 #define BW BUS_SPACE_BARRIER_WRITE 270 #define COM_BARRIER(r, f) \ 271 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 272 273 /*ARGSUSED*/ 274 int 275 comspeed(long speed, long frequency, int type) 276 { 277 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 278 279 int x, err; 280 281 #if 0 282 if (speed == 0) 283 return (0); 284 #endif 285 if (speed <= 0) 286 return (-1); 287 x = divrnd(frequency / 16, speed); 288 if (x <= 0) 289 return (-1); 290 err = divrnd(((quad_t)frequency) * 1000 / 16, speed * x) - 1000; 291 if (err < 0) 292 err = -err; 293 if (err > COM_TOLERANCE) 294 return (-1); 295 return (x); 296 297 #undef divrnd 298 } 299 300 #ifdef COM_DEBUG 301 int com_debug = 0; 302 303 void comstatus(struct com_softc *, const char *); 304 void 305 comstatus(struct com_softc *sc, const char *str) 306 { 307 struct tty *tp = sc->sc_tty; 308 309 printf("%s: %s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 310 sc->sc_dev.dv_xname, str, 311 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 312 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 313 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 314 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 315 sc->sc_tx_stopped ? '+' : '-'); 316 317 printf("%s: %s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 318 sc->sc_dev.dv_xname, str, 319 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 320 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 321 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 322 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 323 sc->sc_rx_flags); 324 } 325 #endif 326 327 int 328 com_probe_subr(struct com_regs *regs) 329 { 330 331 /* force access to id reg */ 332 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 333 CSR_WRITE_1(regs, COM_REG_IIR, 0); 334 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 335 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 336 return (0); 337 338 return (1); 339 } 340 341 int 342 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 343 { 344 struct com_regs regs; 345 346 regs.cr_iot = iot; 347 regs.cr_ioh = ioh; 348 #ifdef COM_REGMAP 349 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 350 #endif 351 352 return com_probe_subr(®s); 353 } 354 355 static void 356 com_enable_debugport(struct com_softc *sc) 357 { 358 359 /* Turn on line break interrupt, set carrier. */ 360 mutex_spin_enter(&sc->sc_lock); 361 sc->sc_ier = IER_ERXRDY; 362 if (sc->sc_type == COM_TYPE_PXA2x0) 363 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 364 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 365 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 366 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 367 mutex_spin_exit(&sc->sc_lock); 368 } 369 370 void 371 com_attach_subr(struct com_softc *sc) 372 { 373 struct com_regs *regsp = &sc->sc_regs; 374 struct tty *tp; 375 #ifdef COM_16650 376 u_int8_t lcr; 377 #endif 378 const char *fifo_msg = NULL; 379 380 aprint_naive("\n"); 381 382 callout_init(&sc->sc_diag_callout, 0); 383 mutex_init(&sc->sc_lock, MUTEX_SPIN, IPL_SERIAL); 384 385 /* Disable interrupts before configuring the device. */ 386 if (sc->sc_type == COM_TYPE_PXA2x0) 387 sc->sc_ier = IER_EUART; 388 else 389 sc->sc_ier = 0; 390 391 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 392 393 if (regsp->cr_iot == comconsregs.cr_iot && 394 regsp->cr_iobase == comconsregs.cr_iobase) { 395 comconsattached = 1; 396 397 /* Make sure the console is always "hardwired". */ 398 delay(10000); /* wait for output to finish */ 399 SET(sc->sc_hwflags, COM_HW_CONSOLE); 400 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 401 } 402 403 /* Probe for FIFO */ 404 switch (sc->sc_type) { 405 case COM_TYPE_HAYESP: 406 goto fifodone; 407 408 case COM_TYPE_AU1x00: 409 sc->sc_fifolen = 16; 410 fifo_msg = "Au1X00 UART, working fifo"; 411 SET(sc->sc_hwflags, COM_HW_FIFO); 412 goto fifodelay; 413 } 414 415 sc->sc_fifolen = 1; 416 /* look for a NS 16550AF UART with FIFOs */ 417 CSR_WRITE_1(regsp, COM_REG_FIFO, 418 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 419 delay(100); 420 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 421 == IIR_FIFO_MASK) 422 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 423 == FIFO_TRIGGER_14) { 424 SET(sc->sc_hwflags, COM_HW_FIFO); 425 426 #ifdef COM_16650 427 /* 428 * IIR changes into the EFR if LCR is set to LCR_EERS 429 * on 16650s. We also know IIR != 0 at this point. 430 * Write 0 into the EFR, and read it. If the result 431 * is 0, we have a 16650. 432 * 433 * Older 16650s were broken; the test to detect them 434 * is taken from the Linux driver. Apparently 435 * setting DLAB enable gives access to the EFR on 436 * these chips. 437 */ 438 lcr = CSR_READ_1(regsp, COM_REG_LCR); 439 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 440 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 441 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 442 CSR_WRITE_1(regsp, COM_REG_LCR, 443 lcr | LCR_DLAB); 444 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 445 CLR(sc->sc_hwflags, COM_HW_FIFO); 446 sc->sc_fifolen = 0; 447 } else { 448 SET(sc->sc_hwflags, COM_HW_FLOW); 449 sc->sc_fifolen = 32; 450 } 451 } else 452 #endif 453 sc->sc_fifolen = 16; 454 455 #ifdef COM_16650 456 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 457 if (sc->sc_fifolen == 0) 458 fifo_msg = "st16650, broken fifo"; 459 else if (sc->sc_fifolen == 32) 460 fifo_msg = "st16650a, working fifo"; 461 else 462 #endif 463 fifo_msg = "ns16550a, working fifo"; 464 } else 465 fifo_msg = "ns16550, broken fifo"; 466 else 467 fifo_msg = "ns8250 or ns16450, no fifo"; 468 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 469 fifodelay: 470 /* 471 * Some chips will clear down both Tx and Rx FIFOs when zero is 472 * written to com_fifo. If this chip is the console, writing zero 473 * results in some of the chip/FIFO description being lost, so delay 474 * printing it until now. 475 */ 476 delay(10); 477 aprint_normal(": %s\n", fifo_msg); 478 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 479 sc->sc_fifolen = 1; 480 aprint_normal("%s: txfifo disabled\n", sc->sc_dev.dv_xname); 481 } 482 483 fifodone: 484 485 tp = ttymalloc(); 486 tp->t_oproc = comstart; 487 tp->t_param = comparam; 488 tp->t_hwiflow = comhwiflow; 489 490 sc->sc_tty = tp; 491 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 492 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 493 sc->sc_rbavail = com_rbuf_size; 494 if (sc->sc_rbuf == NULL) { 495 aprint_error("%s: unable to allocate ring buffer\n", 496 sc->sc_dev.dv_xname); 497 return; 498 } 499 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 500 501 tty_attach(tp); 502 503 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 504 SET(sc->sc_mcr, MCR_IENABLE); 505 506 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 507 int maj; 508 509 /* locate the major number */ 510 maj = cdevsw_lookup_major(&com_cdevsw); 511 512 tp->t_dev = cn_tab->cn_dev = makedev(maj, 513 device_unit(&sc->sc_dev)); 514 515 aprint_normal("%s: console\n", sc->sc_dev.dv_xname); 516 } 517 518 #ifdef KGDB 519 /* 520 * Allow kgdb to "take over" this port. If this is 521 * not the console and is the kgdb device, it has 522 * exclusive use. If it's the console _and_ the 523 * kgdb device, it doesn't. 524 */ 525 if (regsp->cr_iot == comkgdbregs.cr_iot && 526 regsp->cr_iobase == comkgdbregs.cr_iobase) { 527 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 528 com_kgdb_attached = 1; 529 530 SET(sc->sc_hwflags, COM_HW_KGDB); 531 } 532 aprint_normal("%s: kgdb\n", sc->sc_dev.dv_xname); 533 } 534 #endif 535 536 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 537 538 #if NRND > 0 && defined(RND_COM) 539 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 540 RND_TYPE_TTY, 0); 541 #endif 542 543 /* if there are no enable/disable functions, assume the device 544 is always enabled */ 545 if (!sc->enable) 546 sc->enabled = 1; 547 548 com_config(sc); 549 550 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 551 com_power, sc); 552 if (sc->sc_powerhook == NULL) 553 aprint_error("%s: WARNING: unable to establish power hook\n", 554 sc->sc_dev.dv_xname); 555 556 SET(sc->sc_hwflags, COM_HW_DEV_OK); 557 } 558 559 void 560 com_config(struct com_softc *sc) 561 { 562 struct com_regs *regsp = &sc->sc_regs; 563 564 /* Disable interrupts before configuring the device. */ 565 if (sc->sc_type == COM_TYPE_PXA2x0) 566 sc->sc_ier = IER_EUART; 567 else 568 sc->sc_ier = 0; 569 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 570 (void) CSR_READ_1(regsp, COM_REG_IIR); 571 572 #ifdef COM_HAYESP 573 /* Look for a Hayes ESP board. */ 574 if (sc->sc_type == COM_TYPE_HAYESP) { 575 576 /* Set 16550 compatibility mode */ 577 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 578 HAYESP_SETMODE); 579 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 580 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 581 HAYESP_MODE_SCALE); 582 583 /* Set RTS/CTS flow control */ 584 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 585 HAYESP_SETFLOWTYPE); 586 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 587 HAYESP_FLOW_RTS); 588 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 589 HAYESP_FLOW_CTS); 590 591 /* Set flow control levels */ 592 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 593 HAYESP_SETRXFLOW); 594 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 595 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 596 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 597 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 598 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 599 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 600 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 601 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 602 } 603 #endif 604 605 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 606 com_enable_debugport(sc); 607 } 608 609 int 610 com_detach(struct device *self, int flags) 611 { 612 struct com_softc *sc = (struct com_softc *)self; 613 int maj, mn; 614 615 /* kill the power hook */ 616 if (sc->sc_powerhook != NULL) 617 powerhook_disestablish(sc->sc_powerhook); 618 619 /* locate the major number */ 620 maj = cdevsw_lookup_major(&com_cdevsw); 621 622 /* Nuke the vnodes for any open instances. */ 623 mn = device_unit(self); 624 vdevgone(maj, mn, mn, VCHR); 625 626 mn |= COMDIALOUT_MASK; 627 vdevgone(maj, mn, mn, VCHR); 628 629 if (sc->sc_rbuf == NULL) { 630 /* 631 * Ring buffer allocation failed in the com_attach_subr, 632 * only the tty is allocated, and nothing else. 633 */ 634 ttyfree(sc->sc_tty); 635 return 0; 636 } 637 638 /* Free the receive buffer. */ 639 free(sc->sc_rbuf, M_DEVBUF); 640 641 /* Detach and free the tty. */ 642 tty_detach(sc->sc_tty); 643 ttyfree(sc->sc_tty); 644 645 /* Unhook the soft interrupt handler. */ 646 softint_disestablish(sc->sc_si); 647 648 #if NRND > 0 && defined(RND_COM) 649 /* Unhook the entropy source. */ 650 rnd_detach_source(&sc->rnd_source); 651 #endif 652 653 return (0); 654 } 655 656 int 657 com_activate(struct device *self, enum devact act) 658 { 659 struct com_softc *sc = (struct com_softc *)self; 660 int rv = 0; 661 662 mutex_spin_enter(&sc->sc_lock); 663 switch (act) { 664 case DVACT_ACTIVATE: 665 rv = EOPNOTSUPP; 666 break; 667 668 case DVACT_DEACTIVATE: 669 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 670 rv = EBUSY; 671 break; 672 } 673 674 if (sc->disable != NULL && sc->enabled != 0) { 675 (*sc->disable)(sc); 676 sc->enabled = 0; 677 } 678 break; 679 } 680 681 mutex_spin_exit(&sc->sc_lock); 682 return (rv); 683 } 684 685 void 686 com_shutdown(struct com_softc *sc) 687 { 688 struct tty *tp = sc->sc_tty; 689 690 mutex_spin_enter(&sc->sc_lock); 691 692 /* If we were asserting flow control, then deassert it. */ 693 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 694 com_hwiflow(sc); 695 696 /* Clear any break condition set with TIOCSBRK. */ 697 com_break(sc, 0); 698 699 #ifndef __HAVE_TIMECOUNTER 700 /* Turn off PPS capture on last close. */ 701 sc->sc_ppsmask = 0; 702 sc->ppsparam.mode = 0; 703 #endif /* !__HAVE_TIMECOUNTER */ 704 705 /* 706 * Hang up if necessary. Wait a bit, so the other side has time to 707 * notice even if we immediately open the port again. 708 * Avoid tsleeping above splhigh(). 709 */ 710 if (ISSET(tp->t_cflag, HUPCL)) { 711 com_modem(sc, 0); 712 mutex_spin_exit(&sc->sc_lock); 713 /* XXX will only timeout */ 714 (void) kpause(ttclos, false, hz, NULL); 715 mutex_spin_enter(&sc->sc_lock); 716 } 717 718 /* Turn off interrupts. */ 719 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 720 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 721 if (sc->sc_type == COM_TYPE_PXA2x0) 722 sc->sc_ier |= IER_ERXTOUT; 723 } else 724 sc->sc_ier = 0; 725 726 if (sc->sc_type == COM_TYPE_PXA2x0) 727 sc->sc_ier |= IER_EUART; 728 729 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 730 731 if (sc->disable) { 732 #ifdef DIAGNOSTIC 733 if (!sc->enabled) 734 panic("com_shutdown: not enabled?"); 735 #endif 736 (*sc->disable)(sc); 737 sc->enabled = 0; 738 } 739 mutex_spin_exit(&sc->sc_lock); 740 } 741 742 int 743 comopen(dev_t dev, int flag, int mode, struct lwp *l) 744 { 745 struct com_softc *sc; 746 struct tty *tp; 747 int s; 748 int error; 749 750 sc = device_lookup(&com_cd, COMUNIT(dev)); 751 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 752 sc->sc_rbuf == NULL) 753 return (ENXIO); 754 755 if (!device_is_active(&sc->sc_dev)) 756 return (ENXIO); 757 758 #ifdef KGDB 759 /* 760 * If this is the kgdb port, no other use is permitted. 761 */ 762 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 763 return (EBUSY); 764 #endif 765 766 tp = sc->sc_tty; 767 768 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 769 return (EBUSY); 770 771 s = spltty(); 772 773 /* 774 * Do the following iff this is a first open. 775 */ 776 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 777 struct termios t; 778 779 tp->t_dev = dev; 780 781 mutex_spin_enter(&sc->sc_lock); 782 783 if (sc->enable) { 784 if ((*sc->enable)(sc)) { 785 mutex_spin_exit(&sc->sc_lock); 786 splx(s); 787 printf("%s: device enable failed\n", 788 sc->sc_dev.dv_xname); 789 return (EIO); 790 } 791 sc->enabled = 1; 792 com_config(sc); 793 } 794 795 /* Turn on interrupts. */ 796 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 797 if (sc->sc_type == COM_TYPE_PXA2x0) 798 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 799 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 800 801 /* Fetch the current modem control status, needed later. */ 802 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 803 804 /* Clear PPS capture state on first open. */ 805 #ifdef __HAVE_TIMECOUNTER 806 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 807 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 808 pps_init(&sc->sc_pps_state); 809 #else /* !__HAVE_TIMECOUNTER */ 810 sc->sc_ppsmask = 0; 811 sc->ppsparam.mode = 0; 812 #endif /* !__HAVE_TIMECOUNTER */ 813 814 mutex_spin_exit(&sc->sc_lock); 815 816 /* 817 * Initialize the termios status to the defaults. Add in the 818 * sticky bits from TIOCSFLAGS. 819 */ 820 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 821 t.c_ospeed = comconsrate; 822 t.c_cflag = comconscflag; 823 } else { 824 t.c_ospeed = TTYDEF_SPEED; 825 t.c_cflag = TTYDEF_CFLAG; 826 } 827 t.c_ispeed = t.c_ospeed; 828 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 829 SET(t.c_cflag, CLOCAL); 830 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 831 SET(t.c_cflag, CRTSCTS); 832 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 833 SET(t.c_cflag, MDMBUF); 834 /* Make sure comparam() will do something. */ 835 tp->t_ospeed = 0; 836 (void) comparam(tp, &t); 837 tp->t_iflag = TTYDEF_IFLAG; 838 tp->t_oflag = TTYDEF_OFLAG; 839 tp->t_lflag = TTYDEF_LFLAG; 840 ttychars(tp); 841 ttsetwater(tp); 842 843 mutex_spin_enter(&sc->sc_lock); 844 845 /* 846 * Turn on DTR. We must always do this, even if carrier is not 847 * present, because otherwise we'd have to use TIOCSDTR 848 * immediately after setting CLOCAL, which applications do not 849 * expect. We always assert DTR while the device is open 850 * unless explicitly requested to deassert it. 851 */ 852 com_modem(sc, 1); 853 854 /* Clear the input ring, and unblock. */ 855 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 856 sc->sc_rbavail = com_rbuf_size; 857 com_iflush(sc); 858 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 859 com_hwiflow(sc); 860 861 #ifdef COM_DEBUG 862 if (com_debug) 863 comstatus(sc, "comopen "); 864 #endif 865 866 mutex_spin_exit(&sc->sc_lock); 867 } 868 869 splx(s); 870 871 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 872 if (error) 873 goto bad; 874 875 error = (*tp->t_linesw->l_open)(dev, tp); 876 if (error) 877 goto bad; 878 879 return (0); 880 881 bad: 882 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 883 /* 884 * We failed to open the device, and nobody else had it opened. 885 * Clean up the state as appropriate. 886 */ 887 com_shutdown(sc); 888 } 889 890 return (error); 891 } 892 893 int 894 comclose(dev_t dev, int flag, int mode, struct lwp *l) 895 { 896 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 897 struct tty *tp = sc->sc_tty; 898 899 /* XXX This is for cons.c. */ 900 if (!ISSET(tp->t_state, TS_ISOPEN)) 901 return (0); 902 903 (*tp->t_linesw->l_close)(tp, flag); 904 ttyclose(tp); 905 906 if (COM_ISALIVE(sc) == 0) 907 return (0); 908 909 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 910 /* 911 * Although we got a last close, the device may still be in 912 * use; e.g. if this was the dialout node, and there are still 913 * processes waiting for carrier on the non-dialout node. 914 */ 915 com_shutdown(sc); 916 } 917 918 return (0); 919 } 920 921 int 922 comread(dev_t dev, struct uio *uio, int flag) 923 { 924 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 925 struct tty *tp = sc->sc_tty; 926 927 if (COM_ISALIVE(sc) == 0) 928 return (EIO); 929 930 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 931 } 932 933 int 934 comwrite(dev_t dev, struct uio *uio, int flag) 935 { 936 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 937 struct tty *tp = sc->sc_tty; 938 939 if (COM_ISALIVE(sc) == 0) 940 return (EIO); 941 942 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 943 } 944 945 int 946 compoll(dev_t dev, int events, struct lwp *l) 947 { 948 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 949 struct tty *tp = sc->sc_tty; 950 951 if (COM_ISALIVE(sc) == 0) 952 return (POLLHUP); 953 954 return ((*tp->t_linesw->l_poll)(tp, events, l)); 955 } 956 957 struct tty * 958 comtty(dev_t dev) 959 { 960 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 961 struct tty *tp = sc->sc_tty; 962 963 return (tp); 964 } 965 966 int 967 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 968 { 969 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 970 struct tty *tp = sc->sc_tty; 971 int error; 972 973 if (COM_ISALIVE(sc) == 0) 974 return (EIO); 975 976 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 977 if (error != EPASSTHROUGH) 978 return (error); 979 980 error = ttioctl(tp, cmd, data, flag, l); 981 if (error != EPASSTHROUGH) 982 return (error); 983 984 error = 0; 985 switch (cmd) { 986 case TIOCSFLAGS: 987 error = kauth_authorize_device_tty(l->l_cred, 988 KAUTH_DEVICE_TTY_PRIVSET, tp); 989 break; 990 default: 991 /* nothing */ 992 break; 993 } 994 if (error) { 995 return error; 996 } 997 998 mutex_spin_enter(&sc->sc_lock); 999 1000 switch (cmd) { 1001 case TIOCSBRK: 1002 com_break(sc, 1); 1003 break; 1004 1005 case TIOCCBRK: 1006 com_break(sc, 0); 1007 break; 1008 1009 case TIOCSDTR: 1010 com_modem(sc, 1); 1011 break; 1012 1013 case TIOCCDTR: 1014 com_modem(sc, 0); 1015 break; 1016 1017 case TIOCGFLAGS: 1018 *(int *)data = sc->sc_swflags; 1019 break; 1020 1021 case TIOCSFLAGS: 1022 sc->sc_swflags = *(int *)data; 1023 break; 1024 1025 case TIOCMSET: 1026 case TIOCMBIS: 1027 case TIOCMBIC: 1028 tiocm_to_com(sc, cmd, *(int *)data); 1029 break; 1030 1031 case TIOCMGET: 1032 *(int *)data = com_to_tiocm(sc); 1033 break; 1034 1035 #ifdef __HAVE_TIMECOUNTER 1036 case PPS_IOC_CREATE: 1037 case PPS_IOC_DESTROY: 1038 case PPS_IOC_GETPARAMS: 1039 case PPS_IOC_SETPARAMS: 1040 case PPS_IOC_GETCAP: 1041 case PPS_IOC_FETCH: 1042 #ifdef PPS_SYNC 1043 case PPS_IOC_KCBIND: 1044 #endif 1045 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1046 break; 1047 #else /* !__HAVE_TIMECOUNTER */ 1048 case PPS_IOC_CREATE: 1049 break; 1050 1051 case PPS_IOC_DESTROY: 1052 break; 1053 1054 case PPS_IOC_GETPARAMS: { 1055 pps_params_t *pp; 1056 pp = (pps_params_t *)data; 1057 *pp = sc->ppsparam; 1058 break; 1059 } 1060 1061 case PPS_IOC_SETPARAMS: { 1062 pps_params_t *pp; 1063 int mode; 1064 pp = (pps_params_t *)data; 1065 if (pp->mode & ~ppscap) { 1066 error = EINVAL; 1067 break; 1068 } 1069 sc->ppsparam = *pp; 1070 /* 1071 * Compute msr masks from user-specified timestamp state. 1072 */ 1073 mode = sc->ppsparam.mode; 1074 switch (mode & PPS_CAPTUREBOTH) { 1075 case 0: 1076 sc->sc_ppsmask = 0; 1077 break; 1078 1079 case PPS_CAPTUREASSERT: 1080 sc->sc_ppsmask = MSR_DCD; 1081 sc->sc_ppsassert = MSR_DCD; 1082 sc->sc_ppsclear = -1; 1083 break; 1084 1085 case PPS_CAPTURECLEAR: 1086 sc->sc_ppsmask = MSR_DCD; 1087 sc->sc_ppsassert = -1; 1088 sc->sc_ppsclear = 0; 1089 break; 1090 1091 case PPS_CAPTUREBOTH: 1092 sc->sc_ppsmask = MSR_DCD; 1093 sc->sc_ppsassert = MSR_DCD; 1094 sc->sc_ppsclear = 0; 1095 break; 1096 1097 default: 1098 error = EINVAL; 1099 break; 1100 } 1101 break; 1102 } 1103 1104 case PPS_IOC_GETCAP: 1105 *(int*)data = ppscap; 1106 break; 1107 1108 case PPS_IOC_FETCH: { 1109 pps_info_t *pi; 1110 pi = (pps_info_t *)data; 1111 *pi = sc->ppsinfo; 1112 break; 1113 } 1114 1115 #ifdef PPS_SYNC 1116 case PPS_IOC_KCBIND: { 1117 int edge = (*(int *)data) & PPS_CAPTUREBOTH; 1118 1119 if (edge == 0) { 1120 /* 1121 * remove binding for this source; ignore 1122 * the request if this is not the current 1123 * hardpps source 1124 */ 1125 if (pps_kc_hardpps_source == sc) { 1126 pps_kc_hardpps_source = NULL; 1127 pps_kc_hardpps_mode = 0; 1128 } 1129 } else { 1130 /* 1131 * bind hardpps to this source, replacing any 1132 * previously specified source or edges 1133 */ 1134 pps_kc_hardpps_source = sc; 1135 pps_kc_hardpps_mode = edge; 1136 } 1137 break; 1138 } 1139 #endif /* PPS_SYNC */ 1140 #endif /* !__HAVE_TIMECOUNTER */ 1141 1142 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1143 #ifdef __HAVE_TIMECOUNTER 1144 #ifndef PPS_TRAILING_EDGE 1145 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1146 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1147 #else 1148 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1149 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1150 #endif 1151 #else /* !__HAVE_TIMECOUNTER */ 1152 /* 1153 * Some GPS clocks models use the falling rather than 1154 * rising edge as the on-the-second signal. 1155 * The old API has no way to specify PPS polarity. 1156 */ 1157 sc->sc_ppsmask = MSR_DCD; 1158 #ifndef PPS_TRAILING_EDGE 1159 sc->sc_ppsassert = MSR_DCD; 1160 sc->sc_ppsclear = -1; 1161 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1162 &sc->ppsinfo.assert_timestamp); 1163 #else 1164 sc->sc_ppsassert = -1; 1165 sc->sc_ppsclear = 0; 1166 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1167 &sc->ppsinfo.clear_timestamp); 1168 #endif 1169 #endif /* !__HAVE_TIMECOUNTER */ 1170 break; 1171 1172 default: 1173 error = EPASSTHROUGH; 1174 break; 1175 } 1176 1177 mutex_spin_exit(&sc->sc_lock); 1178 1179 #ifdef COM_DEBUG 1180 if (com_debug) 1181 comstatus(sc, "comioctl "); 1182 #endif 1183 1184 return (error); 1185 } 1186 1187 integrate void 1188 com_schedrx(struct com_softc *sc) 1189 { 1190 1191 sc->sc_rx_ready = 1; 1192 1193 /* Wake up the poller. */ 1194 softint_schedule(sc->sc_si); 1195 } 1196 1197 void 1198 com_break(struct com_softc *sc, int onoff) 1199 { 1200 1201 if (onoff) 1202 SET(sc->sc_lcr, LCR_SBREAK); 1203 else 1204 CLR(sc->sc_lcr, LCR_SBREAK); 1205 1206 if (!sc->sc_heldchange) { 1207 if (sc->sc_tx_busy) { 1208 sc->sc_heldtbc = sc->sc_tbc; 1209 sc->sc_tbc = 0; 1210 sc->sc_heldchange = 1; 1211 } else 1212 com_loadchannelregs(sc); 1213 } 1214 } 1215 1216 void 1217 com_modem(struct com_softc *sc, int onoff) 1218 { 1219 1220 if (sc->sc_mcr_dtr == 0) 1221 return; 1222 1223 if (onoff) 1224 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1225 else 1226 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1227 1228 if (!sc->sc_heldchange) { 1229 if (sc->sc_tx_busy) { 1230 sc->sc_heldtbc = sc->sc_tbc; 1231 sc->sc_tbc = 0; 1232 sc->sc_heldchange = 1; 1233 } else 1234 com_loadchannelregs(sc); 1235 } 1236 } 1237 1238 void 1239 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1240 { 1241 u_char combits; 1242 1243 combits = 0; 1244 if (ISSET(ttybits, TIOCM_DTR)) 1245 SET(combits, MCR_DTR); 1246 if (ISSET(ttybits, TIOCM_RTS)) 1247 SET(combits, MCR_RTS); 1248 1249 switch (how) { 1250 case TIOCMBIC: 1251 CLR(sc->sc_mcr, combits); 1252 break; 1253 1254 case TIOCMBIS: 1255 SET(sc->sc_mcr, combits); 1256 break; 1257 1258 case TIOCMSET: 1259 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1260 SET(sc->sc_mcr, combits); 1261 break; 1262 } 1263 1264 if (!sc->sc_heldchange) { 1265 if (sc->sc_tx_busy) { 1266 sc->sc_heldtbc = sc->sc_tbc; 1267 sc->sc_tbc = 0; 1268 sc->sc_heldchange = 1; 1269 } else 1270 com_loadchannelregs(sc); 1271 } 1272 } 1273 1274 int 1275 com_to_tiocm(struct com_softc *sc) 1276 { 1277 u_char combits; 1278 int ttybits = 0; 1279 1280 combits = sc->sc_mcr; 1281 if (ISSET(combits, MCR_DTR)) 1282 SET(ttybits, TIOCM_DTR); 1283 if (ISSET(combits, MCR_RTS)) 1284 SET(ttybits, TIOCM_RTS); 1285 1286 combits = sc->sc_msr; 1287 if (ISSET(combits, MSR_DCD)) 1288 SET(ttybits, TIOCM_CD); 1289 if (ISSET(combits, MSR_CTS)) 1290 SET(ttybits, TIOCM_CTS); 1291 if (ISSET(combits, MSR_DSR)) 1292 SET(ttybits, TIOCM_DSR); 1293 if (ISSET(combits, MSR_RI | MSR_TERI)) 1294 SET(ttybits, TIOCM_RI); 1295 1296 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1297 SET(ttybits, TIOCM_LE); 1298 1299 return (ttybits); 1300 } 1301 1302 static u_char 1303 cflag2lcr(tcflag_t cflag) 1304 { 1305 u_char lcr = 0; 1306 1307 switch (ISSET(cflag, CSIZE)) { 1308 case CS5: 1309 SET(lcr, LCR_5BITS); 1310 break; 1311 case CS6: 1312 SET(lcr, LCR_6BITS); 1313 break; 1314 case CS7: 1315 SET(lcr, LCR_7BITS); 1316 break; 1317 case CS8: 1318 SET(lcr, LCR_8BITS); 1319 break; 1320 } 1321 if (ISSET(cflag, PARENB)) { 1322 SET(lcr, LCR_PENAB); 1323 if (!ISSET(cflag, PARODD)) 1324 SET(lcr, LCR_PEVEN); 1325 } 1326 if (ISSET(cflag, CSTOPB)) 1327 SET(lcr, LCR_STOPB); 1328 1329 return (lcr); 1330 } 1331 1332 int 1333 comparam(struct tty *tp, struct termios *t) 1334 { 1335 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1336 int ospeed; 1337 u_char lcr; 1338 1339 if (COM_ISALIVE(sc) == 0) 1340 return (EIO); 1341 1342 #ifdef COM_HAYESP 1343 if (sc->sc_type == COM_TYPE_HAYESP) { 1344 int prescaler, speed; 1345 1346 /* 1347 * Calculate UART clock prescaler. It should be in 1348 * range of 0 .. 3. 1349 */ 1350 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1351 prescaler++, speed /= 2) 1352 if ((ospeed = comspeed(speed, sc->sc_frequency, 1353 sc->sc_type)) > 0) 1354 break; 1355 1356 if (prescaler == 4) 1357 return (EINVAL); 1358 sc->sc_prescaler = prescaler; 1359 } else 1360 #endif 1361 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1362 1363 /* Check requested parameters. */ 1364 if (ospeed < 0) 1365 return (EINVAL); 1366 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1367 return (EINVAL); 1368 1369 /* 1370 * For the console, always force CLOCAL and !HUPCL, so that the port 1371 * is always active. 1372 */ 1373 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1374 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1375 SET(t->c_cflag, CLOCAL); 1376 CLR(t->c_cflag, HUPCL); 1377 } 1378 1379 /* 1380 * If there were no changes, don't do anything. This avoids dropping 1381 * input and improves performance when all we did was frob things like 1382 * VMIN and VTIME. 1383 */ 1384 if (tp->t_ospeed == t->c_ospeed && 1385 tp->t_cflag == t->c_cflag) 1386 return (0); 1387 1388 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1389 1390 mutex_spin_enter(&sc->sc_lock); 1391 1392 sc->sc_lcr = lcr; 1393 1394 /* 1395 * If we're not in a mode that assumes a connection is present, then 1396 * ignore carrier changes. 1397 */ 1398 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1399 sc->sc_msr_dcd = 0; 1400 else 1401 sc->sc_msr_dcd = MSR_DCD; 1402 /* 1403 * Set the flow control pins depending on the current flow control 1404 * mode. 1405 */ 1406 if (ISSET(t->c_cflag, CRTSCTS)) { 1407 sc->sc_mcr_dtr = MCR_DTR; 1408 sc->sc_mcr_rts = MCR_RTS; 1409 sc->sc_msr_cts = MSR_CTS; 1410 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1411 } else if (ISSET(t->c_cflag, MDMBUF)) { 1412 /* 1413 * For DTR/DCD flow control, make sure we don't toggle DTR for 1414 * carrier detection. 1415 */ 1416 sc->sc_mcr_dtr = 0; 1417 sc->sc_mcr_rts = MCR_DTR; 1418 sc->sc_msr_cts = MSR_DCD; 1419 sc->sc_efr = 0; 1420 } else { 1421 /* 1422 * If no flow control, then always set RTS. This will make 1423 * the other side happy if it mistakenly thinks we're doing 1424 * RTS/CTS flow control. 1425 */ 1426 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1427 sc->sc_mcr_rts = 0; 1428 sc->sc_msr_cts = 0; 1429 sc->sc_efr = 0; 1430 if (ISSET(sc->sc_mcr, MCR_DTR)) 1431 SET(sc->sc_mcr, MCR_RTS); 1432 else 1433 CLR(sc->sc_mcr, MCR_RTS); 1434 } 1435 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1436 1437 #if 0 1438 if (ospeed == 0) 1439 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1440 else 1441 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1442 #endif 1443 1444 sc->sc_dlbl = ospeed; 1445 sc->sc_dlbh = ospeed >> 8; 1446 1447 /* 1448 * Set the FIFO threshold based on the receive speed. 1449 * 1450 * * If it's a low speed, it's probably a mouse or some other 1451 * interactive device, so set the threshold low. 1452 * * If it's a high speed, trim the trigger level down to prevent 1453 * overflows. 1454 * * Otherwise set it a bit higher. 1455 */ 1456 if (sc->sc_type == COM_TYPE_HAYESP) 1457 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1458 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1459 sc->sc_fifo = FIFO_ENABLE | 1460 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1461 else 1462 sc->sc_fifo = 0; 1463 1464 /* And copy to tty. */ 1465 tp->t_ispeed = t->c_ospeed; 1466 tp->t_ospeed = t->c_ospeed; 1467 tp->t_cflag = t->c_cflag; 1468 1469 if (!sc->sc_heldchange) { 1470 if (sc->sc_tx_busy) { 1471 sc->sc_heldtbc = sc->sc_tbc; 1472 sc->sc_tbc = 0; 1473 sc->sc_heldchange = 1; 1474 } else 1475 com_loadchannelregs(sc); 1476 } 1477 1478 if (!ISSET(t->c_cflag, CHWFLOW)) { 1479 /* Disable the high water mark. */ 1480 sc->sc_r_hiwat = 0; 1481 sc->sc_r_lowat = 0; 1482 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1483 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1484 com_schedrx(sc); 1485 } 1486 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1487 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1488 com_hwiflow(sc); 1489 } 1490 } else { 1491 sc->sc_r_hiwat = com_rbuf_hiwat; 1492 sc->sc_r_lowat = com_rbuf_lowat; 1493 } 1494 1495 mutex_spin_exit(&sc->sc_lock); 1496 1497 /* 1498 * Update the tty layer's idea of the carrier bit, in case we changed 1499 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1500 * explicit request. 1501 */ 1502 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1503 1504 #ifdef COM_DEBUG 1505 if (com_debug) 1506 comstatus(sc, "comparam "); 1507 #endif 1508 1509 if (!ISSET(t->c_cflag, CHWFLOW)) { 1510 if (sc->sc_tx_stopped) { 1511 sc->sc_tx_stopped = 0; 1512 comstart(tp); 1513 } 1514 } 1515 1516 return (0); 1517 } 1518 1519 void 1520 com_iflush(struct com_softc *sc) 1521 { 1522 struct com_regs *regsp = &sc->sc_regs; 1523 #ifdef DIAGNOSTIC 1524 int reg; 1525 #endif 1526 int timo; 1527 1528 #ifdef DIAGNOSTIC 1529 reg = 0xffff; 1530 #endif 1531 timo = 50000; 1532 /* flush any pending I/O */ 1533 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1534 && --timo) 1535 #ifdef DIAGNOSTIC 1536 reg = 1537 #else 1538 (void) 1539 #endif 1540 CSR_READ_1(regsp, COM_REG_RXDATA); 1541 #ifdef DIAGNOSTIC 1542 if (!timo) 1543 printf("%s: com_iflush timeout %02x\n", sc->sc_dev.dv_xname, 1544 reg); 1545 #endif 1546 } 1547 1548 void 1549 com_loadchannelregs(struct com_softc *sc) 1550 { 1551 struct com_regs *regsp = &sc->sc_regs; 1552 1553 /* XXXXX necessary? */ 1554 com_iflush(sc); 1555 1556 if (sc->sc_type == COM_TYPE_PXA2x0) 1557 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1558 else 1559 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1560 1561 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1562 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1563 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1564 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1565 } 1566 } 1567 if (sc->sc_type == COM_TYPE_AU1x00) { 1568 /* alchemy has single separate 16-bit clock divisor register */ 1569 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1570 (sc->sc_dlbh << 8)); 1571 } else { 1572 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1573 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1574 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1575 } 1576 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1577 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1578 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1579 #ifdef COM_HAYESP 1580 if (sc->sc_type == COM_TYPE_HAYESP) { 1581 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1582 HAYESP_SETPRESCALER); 1583 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1584 sc->sc_prescaler); 1585 } 1586 #endif 1587 1588 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1589 } 1590 1591 int 1592 comhwiflow(struct tty *tp, int block) 1593 { 1594 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1595 1596 if (COM_ISALIVE(sc) == 0) 1597 return (0); 1598 1599 if (sc->sc_mcr_rts == 0) 1600 return (0); 1601 1602 mutex_spin_enter(&sc->sc_lock); 1603 1604 if (block) { 1605 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1606 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1607 com_hwiflow(sc); 1608 } 1609 } else { 1610 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1611 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1612 com_schedrx(sc); 1613 } 1614 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1615 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1616 com_hwiflow(sc); 1617 } 1618 } 1619 1620 mutex_spin_exit(&sc->sc_lock); 1621 return (1); 1622 } 1623 1624 /* 1625 * (un)block input via hw flowcontrol 1626 */ 1627 void 1628 com_hwiflow(struct com_softc *sc) 1629 { 1630 struct com_regs *regsp= &sc->sc_regs; 1631 1632 if (sc->sc_mcr_rts == 0) 1633 return; 1634 1635 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1636 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1637 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1638 } else { 1639 SET(sc->sc_mcr, sc->sc_mcr_rts); 1640 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1641 } 1642 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1643 } 1644 1645 1646 void 1647 comstart(struct tty *tp) 1648 { 1649 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1650 struct com_regs *regsp = &sc->sc_regs; 1651 int s; 1652 1653 if (COM_ISALIVE(sc) == 0) 1654 return; 1655 1656 s = spltty(); 1657 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1658 goto out; 1659 if (sc->sc_tx_stopped) 1660 goto out; 1661 1662 if (tp->t_outq.c_cc <= tp->t_lowat) { 1663 if (ISSET(tp->t_state, TS_ASLEEP)) { 1664 CLR(tp->t_state, TS_ASLEEP); 1665 wakeup(&tp->t_outq); 1666 } 1667 selwakeup(&tp->t_wsel); 1668 if (tp->t_outq.c_cc == 0) 1669 goto out; 1670 } 1671 1672 /* Grab the first contiguous region of buffer space. */ 1673 { 1674 u_char *tba; 1675 int tbc; 1676 1677 tba = tp->t_outq.c_cf; 1678 tbc = ndqb(&tp->t_outq, 0); 1679 1680 mutex_spin_enter(&sc->sc_lock); 1681 1682 sc->sc_tba = tba; 1683 sc->sc_tbc = tbc; 1684 } 1685 1686 SET(tp->t_state, TS_BUSY); 1687 sc->sc_tx_busy = 1; 1688 1689 /* Enable transmit completion interrupts if necessary. */ 1690 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1691 SET(sc->sc_ier, IER_ETXRDY); 1692 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1693 } 1694 1695 /* Output the first chunk of the contiguous buffer. */ 1696 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1697 u_int n; 1698 1699 n = sc->sc_tbc; 1700 if (n > sc->sc_fifolen) 1701 n = sc->sc_fifolen; 1702 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1703 sc->sc_tbc -= n; 1704 sc->sc_tba += n; 1705 } 1706 1707 mutex_spin_exit(&sc->sc_lock); 1708 out: 1709 splx(s); 1710 return; 1711 } 1712 1713 /* 1714 * Stop output on a line. 1715 */ 1716 void 1717 comstop(struct tty *tp, int flag) 1718 { 1719 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1720 1721 mutex_spin_enter(&sc->sc_lock); 1722 if (ISSET(tp->t_state, TS_BUSY)) { 1723 /* Stop transmitting at the next chunk. */ 1724 sc->sc_tbc = 0; 1725 sc->sc_heldtbc = 0; 1726 if (!ISSET(tp->t_state, TS_TTSTOP)) 1727 SET(tp->t_state, TS_FLUSH); 1728 } 1729 mutex_spin_exit(&sc->sc_lock); 1730 } 1731 1732 void 1733 comdiag(void *arg) 1734 { 1735 struct com_softc *sc = arg; 1736 int overflows, floods; 1737 1738 mutex_spin_enter(&sc->sc_lock); 1739 overflows = sc->sc_overflows; 1740 sc->sc_overflows = 0; 1741 floods = sc->sc_floods; 1742 sc->sc_floods = 0; 1743 sc->sc_errors = 0; 1744 mutex_spin_exit(&sc->sc_lock); 1745 1746 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1747 sc->sc_dev.dv_xname, 1748 overflows, overflows == 1 ? "" : "s", 1749 floods, floods == 1 ? "" : "s"); 1750 } 1751 1752 integrate void 1753 com_rxsoft(struct com_softc *sc, struct tty *tp) 1754 { 1755 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1756 u_char *get, *end; 1757 u_int cc, scc; 1758 u_char lsr; 1759 int code; 1760 1761 end = sc->sc_ebuf; 1762 get = sc->sc_rbget; 1763 scc = cc = com_rbuf_size - sc->sc_rbavail; 1764 1765 if (cc == com_rbuf_size) { 1766 sc->sc_floods++; 1767 if (sc->sc_errors++ == 0) 1768 callout_reset(&sc->sc_diag_callout, 60 * hz, 1769 comdiag, sc); 1770 } 1771 1772 /* If not yet open, drop the entire buffer content here */ 1773 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1774 get += cc << 1; 1775 if (get >= end) 1776 get -= com_rbuf_size << 1; 1777 cc = 0; 1778 } 1779 while (cc) { 1780 code = get[0]; 1781 lsr = get[1]; 1782 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1783 if (ISSET(lsr, LSR_OE)) { 1784 sc->sc_overflows++; 1785 if (sc->sc_errors++ == 0) 1786 callout_reset(&sc->sc_diag_callout, 1787 60 * hz, comdiag, sc); 1788 } 1789 if (ISSET(lsr, LSR_BI | LSR_FE)) 1790 SET(code, TTY_FE); 1791 if (ISSET(lsr, LSR_PE)) 1792 SET(code, TTY_PE); 1793 } 1794 if ((*rint)(code, tp) == -1) { 1795 /* 1796 * The line discipline's buffer is out of space. 1797 */ 1798 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1799 /* 1800 * We're either not using flow control, or the 1801 * line discipline didn't tell us to block for 1802 * some reason. Either way, we have no way to 1803 * know when there's more space available, so 1804 * just drop the rest of the data. 1805 */ 1806 get += cc << 1; 1807 if (get >= end) 1808 get -= com_rbuf_size << 1; 1809 cc = 0; 1810 } else { 1811 /* 1812 * Don't schedule any more receive processing 1813 * until the line discipline tells us there's 1814 * space available (through comhwiflow()). 1815 * Leave the rest of the data in the input 1816 * buffer. 1817 */ 1818 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1819 } 1820 break; 1821 } 1822 get += 2; 1823 if (get >= end) 1824 get = sc->sc_rbuf; 1825 cc--; 1826 } 1827 1828 if (cc != scc) { 1829 sc->sc_rbget = get; 1830 mutex_spin_enter(&sc->sc_lock); 1831 1832 cc = sc->sc_rbavail += scc - cc; 1833 /* Buffers should be ok again, release possible block. */ 1834 if (cc >= sc->sc_r_lowat) { 1835 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1836 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1837 SET(sc->sc_ier, IER_ERXRDY); 1838 #ifdef COM_PXA2X0 1839 if (sc->sc_type == COM_TYPE_PXA2x0) 1840 SET(sc->sc_ier, IER_ERXTOUT); 1841 #endif 1842 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1843 } 1844 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1845 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1846 com_hwiflow(sc); 1847 } 1848 } 1849 mutex_spin_exit(&sc->sc_lock); 1850 } 1851 } 1852 1853 integrate void 1854 com_txsoft(struct com_softc *sc, struct tty *tp) 1855 { 1856 1857 CLR(tp->t_state, TS_BUSY); 1858 if (ISSET(tp->t_state, TS_FLUSH)) 1859 CLR(tp->t_state, TS_FLUSH); 1860 else 1861 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1862 (*tp->t_linesw->l_start)(tp); 1863 } 1864 1865 integrate void 1866 com_stsoft(struct com_softc *sc, struct tty *tp) 1867 { 1868 u_char msr, delta; 1869 1870 mutex_spin_enter(&sc->sc_lock); 1871 msr = sc->sc_msr; 1872 delta = sc->sc_msr_delta; 1873 sc->sc_msr_delta = 0; 1874 mutex_spin_exit(&sc->sc_lock); 1875 1876 if (ISSET(delta, sc->sc_msr_dcd)) { 1877 /* 1878 * Inform the tty layer that carrier detect changed. 1879 */ 1880 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1881 } 1882 1883 if (ISSET(delta, sc->sc_msr_cts)) { 1884 /* Block or unblock output according to flow control. */ 1885 if (ISSET(msr, sc->sc_msr_cts)) { 1886 sc->sc_tx_stopped = 0; 1887 (*tp->t_linesw->l_start)(tp); 1888 } else { 1889 sc->sc_tx_stopped = 1; 1890 } 1891 } 1892 1893 #ifdef COM_DEBUG 1894 if (com_debug) 1895 comstatus(sc, "com_stsoft"); 1896 #endif 1897 } 1898 1899 void 1900 comsoft(void *arg) 1901 { 1902 struct com_softc *sc = arg; 1903 struct tty *tp; 1904 1905 if (COM_ISALIVE(sc) == 0) 1906 return; 1907 1908 tp = sc->sc_tty; 1909 1910 if (sc->sc_rx_ready) { 1911 sc->sc_rx_ready = 0; 1912 com_rxsoft(sc, tp); 1913 } 1914 1915 if (sc->sc_st_check) { 1916 sc->sc_st_check = 0; 1917 com_stsoft(sc, tp); 1918 } 1919 1920 if (sc->sc_tx_done) { 1921 sc->sc_tx_done = 0; 1922 com_txsoft(sc, tp); 1923 } 1924 } 1925 1926 int 1927 comintr(void *arg) 1928 { 1929 struct com_softc *sc = arg; 1930 struct com_regs *regsp = &sc->sc_regs; 1931 1932 u_char *put, *end; 1933 u_int cc; 1934 u_char lsr, iir; 1935 1936 if (COM_ISALIVE(sc) == 0) 1937 return (0); 1938 1939 mutex_spin_enter(&sc->sc_lock); 1940 iir = CSR_READ_1(regsp, COM_REG_IIR); 1941 if (ISSET(iir, IIR_NOPEND)) { 1942 mutex_spin_exit(&sc->sc_lock); 1943 return (0); 1944 } 1945 1946 end = sc->sc_ebuf; 1947 put = sc->sc_rbput; 1948 cc = sc->sc_rbavail; 1949 1950 again: do { 1951 u_char msr, delta; 1952 1953 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1954 if (ISSET(lsr, LSR_BI)) { 1955 int cn_trapped = 0; 1956 1957 cn_check_magic(sc->sc_tty->t_dev, 1958 CNC_BREAK, com_cnm_state); 1959 if (cn_trapped) 1960 continue; 1961 #if defined(KGDB) && !defined(DDB) 1962 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1963 kgdb_connect(1); 1964 continue; 1965 } 1966 #endif 1967 } 1968 1969 if (ISSET(lsr, LSR_RCV_MASK) && 1970 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1971 while (cc > 0) { 1972 int cn_trapped = 0; 1973 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1974 put[1] = lsr; 1975 cn_check_magic(sc->sc_tty->t_dev, 1976 put[0], com_cnm_state); 1977 if (cn_trapped) 1978 goto next; 1979 put += 2; 1980 if (put >= end) 1981 put = sc->sc_rbuf; 1982 cc--; 1983 next: 1984 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1985 if (!ISSET(lsr, LSR_RCV_MASK)) 1986 break; 1987 } 1988 1989 /* 1990 * Current string of incoming characters ended because 1991 * no more data was available or we ran out of space. 1992 * Schedule a receive event if any data was received. 1993 * If we're out of space, turn off receive interrupts. 1994 */ 1995 sc->sc_rbput = put; 1996 sc->sc_rbavail = cc; 1997 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1998 sc->sc_rx_ready = 1; 1999 2000 /* 2001 * See if we are in danger of overflowing a buffer. If 2002 * so, use hardware flow control to ease the pressure. 2003 */ 2004 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2005 cc < sc->sc_r_hiwat) { 2006 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2007 com_hwiflow(sc); 2008 } 2009 2010 /* 2011 * If we're out of space, disable receive interrupts 2012 * until the queue has drained a bit. 2013 */ 2014 if (!cc) { 2015 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2016 #ifdef COM_PXA2X0 2017 if (sc->sc_type == COM_TYPE_PXA2x0) 2018 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2019 else 2020 #endif 2021 CLR(sc->sc_ier, IER_ERXRDY); 2022 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2023 } 2024 } else { 2025 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2026 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2027 continue; 2028 } 2029 } 2030 2031 msr = CSR_READ_1(regsp, COM_REG_MSR); 2032 delta = msr ^ sc->sc_msr; 2033 sc->sc_msr = msr; 2034 #ifdef __HAVE_TIMECOUNTER 2035 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2036 (delta & MSR_DCD)) { 2037 pps_capture(&sc->sc_pps_state); 2038 pps_event(&sc->sc_pps_state, 2039 (msr & MSR_DCD) ? 2040 PPS_CAPTUREASSERT : 2041 PPS_CAPTURECLEAR); 2042 } 2043 #else /* !__HAVE_TIMECOUNTER */ 2044 /* 2045 * Pulse-per-second (PSS) signals on edge of DCD? 2046 * Process these even if line discipline is ignoring DCD. 2047 */ 2048 if (delta & sc->sc_ppsmask) { 2049 struct timeval tv; 2050 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) { 2051 /* XXX nanotime() */ 2052 microtime(&tv); 2053 TIMEVAL_TO_TIMESPEC(&tv, 2054 &sc->ppsinfo.assert_timestamp); 2055 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 2056 timespecadd(&sc->ppsinfo.assert_timestamp, 2057 &sc->ppsparam.assert_offset, 2058 &sc->ppsinfo.assert_timestamp); 2059 } 2060 2061 #ifdef PPS_SYNC 2062 if (pps_kc_hardpps_source == sc && 2063 pps_kc_hardpps_mode & PPS_CAPTUREASSERT) { 2064 hardpps(&tv, tv.tv_usec); 2065 } 2066 #endif 2067 sc->ppsinfo.assert_sequence++; 2068 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2069 2070 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) { 2071 /* XXX nanotime() */ 2072 microtime(&tv); 2073 TIMEVAL_TO_TIMESPEC(&tv, 2074 &sc->ppsinfo.clear_timestamp); 2075 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 2076 timespecadd(&sc->ppsinfo.clear_timestamp, 2077 &sc->ppsparam.clear_offset, 2078 &sc->ppsinfo.clear_timestamp); 2079 } 2080 2081 #ifdef PPS_SYNC 2082 if (pps_kc_hardpps_source == sc && 2083 pps_kc_hardpps_mode & PPS_CAPTURECLEAR) { 2084 hardpps(&tv, tv.tv_usec); 2085 } 2086 #endif 2087 sc->ppsinfo.clear_sequence++; 2088 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2089 } 2090 } 2091 #endif /* !__HAVE_TIMECOUNTER */ 2092 2093 /* 2094 * Process normal status changes 2095 */ 2096 if (ISSET(delta, sc->sc_msr_mask)) { 2097 SET(sc->sc_msr_delta, delta); 2098 2099 /* 2100 * Stop output immediately if we lose the output 2101 * flow control signal or carrier detect. 2102 */ 2103 if (ISSET(~msr, sc->sc_msr_mask)) { 2104 sc->sc_tbc = 0; 2105 sc->sc_heldtbc = 0; 2106 #ifdef COM_DEBUG 2107 if (com_debug) 2108 comstatus(sc, "comintr "); 2109 #endif 2110 } 2111 2112 sc->sc_st_check = 1; 2113 } 2114 } while (!ISSET((iir = 2115 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2116 /* 2117 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2118 * by IIR read, so we can't do this way: `process all interrupts, 2119 * then do TX if possble'. 2120 */ 2121 (iir & IIR_IMASK) != IIR_TXRDY); 2122 2123 /* 2124 * Read LSR again, since there may be an interrupt between 2125 * the last LSR read and IIR read above. 2126 */ 2127 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2128 2129 /* 2130 * See if data can be transmitted as well. 2131 * Schedule tx done event if no data left 2132 * and tty was marked busy. 2133 */ 2134 if (ISSET(lsr, LSR_TXRDY)) { 2135 /* 2136 * If we've delayed a parameter change, do it now, and restart 2137 * output. 2138 */ 2139 if (sc->sc_heldchange) { 2140 com_loadchannelregs(sc); 2141 sc->sc_heldchange = 0; 2142 sc->sc_tbc = sc->sc_heldtbc; 2143 sc->sc_heldtbc = 0; 2144 } 2145 2146 /* Output the next chunk of the contiguous buffer, if any. */ 2147 if (sc->sc_tbc > 0) { 2148 u_int n; 2149 2150 n = sc->sc_tbc; 2151 if (n > sc->sc_fifolen) 2152 n = sc->sc_fifolen; 2153 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2154 sc->sc_tbc -= n; 2155 sc->sc_tba += n; 2156 } else { 2157 /* Disable transmit completion interrupts if necessary. */ 2158 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2159 CLR(sc->sc_ier, IER_ETXRDY); 2160 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2161 } 2162 if (sc->sc_tx_busy) { 2163 sc->sc_tx_busy = 0; 2164 sc->sc_tx_done = 1; 2165 } 2166 } 2167 } 2168 2169 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2170 goto again; 2171 2172 mutex_spin_exit(&sc->sc_lock); 2173 2174 /* Wake up the poller. */ 2175 softint_schedule(sc->sc_si); 2176 2177 #if NRND > 0 && defined(RND_COM) 2178 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2179 #endif 2180 2181 return (1); 2182 } 2183 2184 /* 2185 * The following functions are polled getc and putc routines, shared 2186 * by the console and kgdb glue. 2187 * 2188 * The read-ahead code is so that you can detect pending in-band 2189 * cn_magic in polled mode while doing output rather than having to 2190 * wait until the kernel decides it needs input. 2191 */ 2192 2193 #define MAX_READAHEAD 20 2194 static int com_readahead[MAX_READAHEAD]; 2195 static int com_readaheadcount = 0; 2196 2197 int 2198 com_common_getc(dev_t dev, struct com_regs *regsp) 2199 { 2200 int s = splserial(); 2201 u_char stat, c; 2202 2203 /* got a character from reading things earlier */ 2204 if (com_readaheadcount > 0) { 2205 int i; 2206 2207 c = com_readahead[0]; 2208 for (i = 1; i < com_readaheadcount; i++) { 2209 com_readahead[i-1] = com_readahead[i]; 2210 } 2211 com_readaheadcount--; 2212 splx(s); 2213 return (c); 2214 } 2215 2216 /* block until a character becomes available */ 2217 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2218 ; 2219 2220 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2221 stat = CSR_READ_1(regsp, COM_REG_IIR); 2222 { 2223 int cn_trapped = 0; /* unused */ 2224 #ifdef DDB 2225 extern int db_active; 2226 if (!db_active) 2227 #endif 2228 cn_check_magic(dev, c, com_cnm_state); 2229 } 2230 splx(s); 2231 return (c); 2232 } 2233 2234 void 2235 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2236 { 2237 int s = splserial(); 2238 int cin, stat, timo; 2239 2240 if (com_readaheadcount < MAX_READAHEAD 2241 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2242 int cn_trapped = 0; 2243 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2244 stat = CSR_READ_1(regsp, COM_REG_IIR); 2245 cn_check_magic(dev, cin, com_cnm_state); 2246 com_readahead[com_readaheadcount++] = cin; 2247 } 2248 2249 /* wait for any pending transmission to finish */ 2250 timo = 150000; 2251 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2252 continue; 2253 2254 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2255 COM_BARRIER(regsp, BR | BW); 2256 2257 splx(s); 2258 } 2259 2260 /* 2261 * Initialize UART for use as console or KGDB line. 2262 */ 2263 int 2264 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2265 tcflag_t cflag) 2266 { 2267 2268 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2269 ®sp->cr_ioh)) 2270 return (ENOMEM); /* ??? */ 2271 2272 rate = comspeed(rate, frequency, type); 2273 if (type != COM_TYPE_AU1x00) { 2274 /* no EFR on alchemy */ 2275 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2276 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2277 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2278 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2279 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2280 } else { 2281 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2282 } 2283 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2284 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2285 CSR_WRITE_1(regsp, COM_REG_FIFO, 2286 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2287 #ifdef COM_PXA2X0 2288 if (type == COM_TYPE_PXA2x0) 2289 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2290 else 2291 #endif 2292 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2293 2294 return (0); 2295 } 2296 2297 /* 2298 * Following are all routines needed for COM to act as console 2299 */ 2300 struct consdev comcons = { 2301 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2302 NODEV, CN_NORMAL 2303 }; 2304 2305 2306 int 2307 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2308 tcflag_t cflag) 2309 { 2310 int res; 2311 2312 comconsregs = *regsp; 2313 2314 res = cominit(&comconsregs, rate, frequency, type, cflag); 2315 if (res) 2316 return (res); 2317 2318 cn_tab = &comcons; 2319 cn_init_magic(&com_cnm_state); 2320 cn_set_magic("\047\001"); /* default magic is BREAK */ 2321 2322 comconsrate = rate; 2323 comconscflag = cflag; 2324 2325 return (0); 2326 } 2327 2328 int 2329 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2330 int type, tcflag_t cflag) 2331 { 2332 struct com_regs regs; 2333 2334 memset(®s, 0, sizeof regs); 2335 regs.cr_iot = iot; 2336 regs.cr_iobase = iobase; 2337 regs.cr_nports = COM_NPORTS; 2338 #ifdef COM_REGMAP 2339 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2340 #endif 2341 2342 return comcnattach1(®s, rate, frequency, type, cflag); 2343 } 2344 2345 int 2346 comcngetc(dev_t dev) 2347 { 2348 2349 return (com_common_getc(dev, &comconsregs)); 2350 } 2351 2352 /* 2353 * Console kernel output character routine. 2354 */ 2355 void 2356 comcnputc(dev_t dev, int c) 2357 { 2358 2359 com_common_putc(dev, &comconsregs, c); 2360 } 2361 2362 void 2363 comcnpollc(dev_t dev, int on) 2364 { 2365 2366 } 2367 2368 #ifdef KGDB 2369 int 2370 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2371 tcflag_t cflag) 2372 { 2373 int res; 2374 2375 if (regsp->cr_iot == comconsregs.cr_iot && 2376 regsp->cr_iobase == comconsregs.cr_iobase) { 2377 #if !defined(DDB) 2378 return (EBUSY); /* cannot share with console */ 2379 #else 2380 comkgdbregs = *regsp; 2381 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2382 #endif 2383 } else { 2384 comkgdbregs = *regsp; 2385 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2386 if (res) 2387 return (res); 2388 2389 /* 2390 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2391 * expects this to be initialized 2392 */ 2393 cn_init_magic(&com_cnm_state); 2394 cn_set_magic("\047\001"); 2395 } 2396 2397 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2398 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2399 2400 return (0); 2401 } 2402 2403 int 2404 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2405 int frequency, int type, tcflag_t cflag) 2406 { 2407 struct com_regs regs; 2408 2409 regs.cr_iot = iot; 2410 regs.cr_nports = COM_NPORTS; 2411 regs.cr_iobase = iobase; 2412 #ifdef COM_REGMAP 2413 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2414 #endif 2415 2416 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2417 } 2418 2419 /* ARGSUSED */ 2420 int 2421 com_kgdb_getc(void *arg) 2422 { 2423 2424 return (com_common_getc(NODEV, &comkgdbregs)); 2425 } 2426 2427 /* ARGSUSED */ 2428 void 2429 com_kgdb_putc(void *arg, int c) 2430 { 2431 2432 com_common_putc(NODEV, &comkgdbregs, c); 2433 } 2434 #endif /* KGDB */ 2435 2436 /* helper function to identify the com ports used by 2437 console or KGDB (and not yet autoconf attached) */ 2438 int 2439 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2440 { 2441 bus_space_handle_t help; 2442 2443 if (!comconsattached && 2444 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2445 help = comconsregs.cr_ioh; 2446 #ifdef KGDB 2447 else if (!com_kgdb_attached && 2448 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2449 help = comkgdbregs.cr_ioh; 2450 #endif 2451 else 2452 return (0); 2453 2454 if (ioh) 2455 *ioh = help; 2456 return (1); 2457 } 2458 2459 /* 2460 * this routine exists to serve as a shutdown hook for systems that 2461 * have firmware which doesn't interact properly with a com device in 2462 * FIFO mode. 2463 */ 2464 void 2465 com_cleanup(void *arg) 2466 { 2467 struct com_softc *sc = arg; 2468 2469 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2470 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2471 } 2472 2473 void 2474 com_power(int why, void *arg) 2475 { 2476 struct com_softc *sc = arg; 2477 2478 mutex_spin_enter(&sc->sc_lock); 2479 switch (why) { 2480 case PWR_SUSPEND: 2481 case PWR_STANDBY: 2482 /* XXX should we do something to stop the device? */ 2483 break; 2484 case PWR_RESUME: 2485 com_loadchannelregs(sc); 2486 break; 2487 case PWR_SOFTSUSPEND: 2488 case PWR_SOFTSTANDBY: 2489 case PWR_SOFTRESUME: 2490 break; 2491 } 2492 mutex_spin_exit(&sc->sc_lock); 2493 } 2494
Indexes created Thu Sep 25 16:09:42 GMT 2025