com.c revision 1.265
1 /* $NetBSD: com.c,v 1.265 2007/10/19 11:59:49 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.265 2007/10/19 11:59:49 ad Exp $"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 #include <sys/intr.h> 126 127 #include <sys/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 void com_power(int, void *); 182 183 int com_common_getc(dev_t, struct com_regs *); 184 void com_common_putc(dev_t, struct com_regs *, int); 185 186 int cominit(struct com_regs *, int, int, int, tcflag_t); 187 188 int comcngetc(dev_t); 189 void comcnputc(dev_t, int); 190 void comcnpollc(dev_t, int); 191 192 #define integrate static inline 193 void comsoft(void *); 194 integrate void com_rxsoft(struct com_softc *, struct tty *); 195 integrate void com_txsoft(struct com_softc *, struct tty *); 196 integrate void com_stsoft(struct com_softc *, struct tty *); 197 integrate void com_schedrx(struct com_softc *); 198 void comdiag(void *); 199 200 extern struct cfdriver com_cd; 201 202 dev_type_open(comopen); 203 dev_type_close(comclose); 204 dev_type_read(comread); 205 dev_type_write(comwrite); 206 dev_type_ioctl(comioctl); 207 dev_type_stop(comstop); 208 dev_type_tty(comtty); 209 dev_type_poll(compoll); 210 211 const struct cdevsw com_cdevsw = { 212 comopen, comclose, comread, comwrite, comioctl, 213 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 214 }; 215 216 /* 217 * Make this an option variable one can patch. 218 * But be warned: this must be a power of 2! 219 */ 220 u_int com_rbuf_size = COM_RING_SIZE; 221 222 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 223 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 224 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 225 226 static struct com_regs comconsregs; 227 static int comconsattached; 228 static int comconsrate; 229 static tcflag_t comconscflag; 230 static struct cnm_state com_cnm_state; 231 232 #ifndef __HAVE_TIMECOUNTER 233 static int ppscap = 234 PPS_TSFMT_TSPEC | 235 PPS_CAPTUREASSERT | 236 PPS_CAPTURECLEAR | 237 PPS_OFFSETASSERT | PPS_OFFSETCLEAR; 238 #endif /* !__HAVE_TIMECOUNTER */ 239 240 #ifdef KGDB 241 #include <sys/kgdb.h> 242 243 static struct com_regs comkgdbregs; 244 static int com_kgdb_attached; 245 246 int com_kgdb_getc(void *); 247 void com_kgdb_putc(void *, int); 248 #endif /* KGDB */ 249 250 #ifdef COM_REGMAP 251 /* initializer for typical 16550-ish hardware */ 252 #define COM_REG_16550 { \ 253 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 254 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 255 256 const bus_size_t com_std_map[16] = COM_REG_16550; 257 #endif /* COM_REGMAP */ 258 259 #define COMUNIT_MASK 0x7ffff 260 #define COMDIALOUT_MASK 0x80000 261 262 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 263 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 264 265 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 266 device_is_active(&(sc)->sc_dev)) 267 268 #define BR BUS_SPACE_BARRIER_READ 269 #define BW BUS_SPACE_BARRIER_WRITE 270 #define COM_BARRIER(r, f) \ 271 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 272 273 /*ARGSUSED*/ 274 int 275 comspeed(long speed, long frequency, int type) 276 { 277 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 278 279 int x, err; 280 281 #if 0 282 if (speed == 0) 283 return (0); 284 #endif 285 if (speed <= 0) 286 return (-1); 287 x = divrnd(frequency / 16, speed); 288 if (x <= 0) 289 return (-1); 290 err = divrnd(((quad_t)frequency) * 1000 / 16, speed * x) - 1000; 291 if (err < 0) 292 err = -err; 293 if (err > COM_TOLERANCE) 294 return (-1); 295 return (x); 296 297 #undef divrnd 298 } 299 300 #ifdef COM_DEBUG 301 int com_debug = 0; 302 303 void comstatus(struct com_softc *, const char *); 304 void 305 comstatus(struct com_softc *sc, const char *str) 306 { 307 struct tty *tp = sc->sc_tty; 308 309 printf("%s: %s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 310 sc->sc_dev.dv_xname, str, 311 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 312 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 313 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 314 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 315 sc->sc_tx_stopped ? '+' : '-'); 316 317 printf("%s: %s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 318 sc->sc_dev.dv_xname, str, 319 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 320 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 321 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 322 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 323 sc->sc_rx_flags); 324 } 325 #endif 326 327 int 328 com_probe_subr(struct com_regs *regs) 329 { 330 331 /* force access to id reg */ 332 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 333 CSR_WRITE_1(regs, COM_REG_IIR, 0); 334 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 335 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 336 return (0); 337 338 return (1); 339 } 340 341 int 342 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 343 { 344 struct com_regs regs; 345 346 regs.cr_iot = iot; 347 regs.cr_ioh = ioh; 348 #ifdef COM_REGMAP 349 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 350 #endif 351 352 return com_probe_subr(®s); 353 } 354 355 /* 356 * No locking in this routine; it is only called during attach, 357 * or with the port already locked. 358 */ 359 static void 360 com_enable_debugport(struct com_softc *sc) 361 { 362 363 /* Turn on line break interrupt, set carrier. */ 364 sc->sc_ier = IER_ERXRDY; 365 if (sc->sc_type == COM_TYPE_PXA2x0) 366 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 367 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 368 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 369 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 370 } 371 372 void 373 com_attach_subr(struct com_softc *sc) 374 { 375 struct com_regs *regsp = &sc->sc_regs; 376 struct tty *tp; 377 #ifdef COM_16650 378 u_int8_t lcr; 379 #endif 380 const char *fifo_msg = NULL; 381 382 aprint_naive("\n"); 383 384 callout_init(&sc->sc_diag_callout, 0); 385 mutex_init(&sc->sc_lock, MUTEX_SPIN, IPL_SERIAL); 386 387 /* Disable interrupts before configuring the device. */ 388 if (sc->sc_type == COM_TYPE_PXA2x0) 389 sc->sc_ier = IER_EUART; 390 else 391 sc->sc_ier = 0; 392 393 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 394 395 if (regsp->cr_iot == comconsregs.cr_iot && 396 regsp->cr_iobase == comconsregs.cr_iobase) { 397 comconsattached = 1; 398 399 /* Make sure the console is always "hardwired". */ 400 delay(10000); /* wait for output to finish */ 401 SET(sc->sc_hwflags, COM_HW_CONSOLE); 402 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 403 } 404 405 /* Probe for FIFO */ 406 switch (sc->sc_type) { 407 case COM_TYPE_HAYESP: 408 goto fifodone; 409 410 case COM_TYPE_AU1x00: 411 sc->sc_fifolen = 16; 412 fifo_msg = "Au1X00 UART, working fifo"; 413 SET(sc->sc_hwflags, COM_HW_FIFO); 414 goto fifodelay; 415 } 416 417 sc->sc_fifolen = 1; 418 /* look for a NS 16550AF UART with FIFOs */ 419 CSR_WRITE_1(regsp, COM_REG_FIFO, 420 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 421 delay(100); 422 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 423 == IIR_FIFO_MASK) 424 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 425 == FIFO_TRIGGER_14) { 426 SET(sc->sc_hwflags, COM_HW_FIFO); 427 428 #ifdef COM_16650 429 /* 430 * IIR changes into the EFR if LCR is set to LCR_EERS 431 * on 16650s. We also know IIR != 0 at this point. 432 * Write 0 into the EFR, and read it. If the result 433 * is 0, we have a 16650. 434 * 435 * Older 16650s were broken; the test to detect them 436 * is taken from the Linux driver. Apparently 437 * setting DLAB enable gives access to the EFR on 438 * these chips. 439 */ 440 lcr = CSR_READ_1(regsp, COM_REG_LCR); 441 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 442 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 443 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 444 CSR_WRITE_1(regsp, COM_REG_LCR, 445 lcr | LCR_DLAB); 446 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 447 CLR(sc->sc_hwflags, COM_HW_FIFO); 448 sc->sc_fifolen = 0; 449 } else { 450 SET(sc->sc_hwflags, COM_HW_FLOW); 451 sc->sc_fifolen = 32; 452 } 453 } else 454 #endif 455 sc->sc_fifolen = 16; 456 457 #ifdef COM_16650 458 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 459 if (sc->sc_fifolen == 0) 460 fifo_msg = "st16650, broken fifo"; 461 else if (sc->sc_fifolen == 32) 462 fifo_msg = "st16650a, working fifo"; 463 else 464 #endif 465 fifo_msg = "ns16550a, working fifo"; 466 } else 467 fifo_msg = "ns16550, broken fifo"; 468 else 469 fifo_msg = "ns8250 or ns16450, no fifo"; 470 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 471 fifodelay: 472 /* 473 * Some chips will clear down both Tx and Rx FIFOs when zero is 474 * written to com_fifo. If this chip is the console, writing zero 475 * results in some of the chip/FIFO description being lost, so delay 476 * printing it until now. 477 */ 478 delay(10); 479 aprint_normal(": %s\n", fifo_msg); 480 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 481 sc->sc_fifolen = 1; 482 aprint_normal("%s: txfifo disabled\n", sc->sc_dev.dv_xname); 483 } 484 485 fifodone: 486 487 tp = ttymalloc(); 488 tp->t_oproc = comstart; 489 tp->t_param = comparam; 490 tp->t_hwiflow = comhwiflow; 491 492 sc->sc_tty = tp; 493 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 494 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 495 sc->sc_rbavail = com_rbuf_size; 496 if (sc->sc_rbuf == NULL) { 497 aprint_error("%s: unable to allocate ring buffer\n", 498 sc->sc_dev.dv_xname); 499 return; 500 } 501 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 502 503 tty_attach(tp); 504 505 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 506 SET(sc->sc_mcr, MCR_IENABLE); 507 508 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 509 int maj; 510 511 /* locate the major number */ 512 maj = cdevsw_lookup_major(&com_cdevsw); 513 514 tp->t_dev = cn_tab->cn_dev = makedev(maj, 515 device_unit(&sc->sc_dev)); 516 517 aprint_normal("%s: console\n", sc->sc_dev.dv_xname); 518 } 519 520 #ifdef KGDB 521 /* 522 * Allow kgdb to "take over" this port. If this is 523 * not the console and is the kgdb device, it has 524 * exclusive use. If it's the console _and_ the 525 * kgdb device, it doesn't. 526 */ 527 if (regsp->cr_iot == comkgdbregs.cr_iot && 528 regsp->cr_iobase == comkgdbregs.cr_iobase) { 529 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 530 com_kgdb_attached = 1; 531 532 SET(sc->sc_hwflags, COM_HW_KGDB); 533 } 534 aprint_normal("%s: kgdb\n", sc->sc_dev.dv_xname); 535 } 536 #endif 537 538 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 539 540 #if NRND > 0 && defined(RND_COM) 541 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 542 RND_TYPE_TTY, 0); 543 #endif 544 545 /* if there are no enable/disable functions, assume the device 546 is always enabled */ 547 if (!sc->enable) 548 sc->enabled = 1; 549 550 com_config(sc); 551 552 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 553 com_power, sc); 554 if (sc->sc_powerhook == NULL) 555 aprint_error("%s: WARNING: unable to establish power hook\n", 556 sc->sc_dev.dv_xname); 557 558 SET(sc->sc_hwflags, COM_HW_DEV_OK); 559 } 560 561 void 562 com_config(struct com_softc *sc) 563 { 564 struct com_regs *regsp = &sc->sc_regs; 565 566 /* Disable interrupts before configuring the device. */ 567 if (sc->sc_type == COM_TYPE_PXA2x0) 568 sc->sc_ier = IER_EUART; 569 else 570 sc->sc_ier = 0; 571 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 572 (void) CSR_READ_1(regsp, COM_REG_IIR); 573 574 #ifdef COM_HAYESP 575 /* Look for a Hayes ESP board. */ 576 if (sc->sc_type == COM_TYPE_HAYESP) { 577 578 /* Set 16550 compatibility mode */ 579 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 580 HAYESP_SETMODE); 581 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 582 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 583 HAYESP_MODE_SCALE); 584 585 /* Set RTS/CTS flow control */ 586 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 587 HAYESP_SETFLOWTYPE); 588 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 589 HAYESP_FLOW_RTS); 590 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 591 HAYESP_FLOW_CTS); 592 593 /* Set flow control levels */ 594 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 595 HAYESP_SETRXFLOW); 596 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 597 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 598 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 599 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 600 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 601 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 602 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 603 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 604 } 605 #endif 606 607 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 608 com_enable_debugport(sc); 609 } 610 611 int 612 com_detach(struct device *self, int flags) 613 { 614 struct com_softc *sc = (struct com_softc *)self; 615 int maj, mn; 616 617 /* kill the power hook */ 618 if (sc->sc_powerhook != NULL) 619 powerhook_disestablish(sc->sc_powerhook); 620 621 /* locate the major number */ 622 maj = cdevsw_lookup_major(&com_cdevsw); 623 624 /* Nuke the vnodes for any open instances. */ 625 mn = device_unit(self); 626 vdevgone(maj, mn, mn, VCHR); 627 628 mn |= COMDIALOUT_MASK; 629 vdevgone(maj, mn, mn, VCHR); 630 631 if (sc->sc_rbuf == NULL) { 632 /* 633 * Ring buffer allocation failed in the com_attach_subr, 634 * only the tty is allocated, and nothing else. 635 */ 636 ttyfree(sc->sc_tty); 637 return 0; 638 } 639 640 /* Free the receive buffer. */ 641 free(sc->sc_rbuf, M_DEVBUF); 642 643 /* Detach and free the tty. */ 644 tty_detach(sc->sc_tty); 645 ttyfree(sc->sc_tty); 646 647 /* Unhook the soft interrupt handler. */ 648 softint_disestablish(sc->sc_si); 649 650 #if NRND > 0 && defined(RND_COM) 651 /* Unhook the entropy source. */ 652 rnd_detach_source(&sc->rnd_source); 653 #endif 654 655 return (0); 656 } 657 658 int 659 com_activate(struct device *self, enum devact act) 660 { 661 struct com_softc *sc = (struct com_softc *)self; 662 int rv = 0; 663 664 mutex_spin_enter(&sc->sc_lock); 665 switch (act) { 666 case DVACT_ACTIVATE: 667 rv = EOPNOTSUPP; 668 break; 669 670 case DVACT_DEACTIVATE: 671 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 672 rv = EBUSY; 673 break; 674 } 675 676 if (sc->disable != NULL && sc->enabled != 0) { 677 (*sc->disable)(sc); 678 sc->enabled = 0; 679 } 680 break; 681 } 682 683 mutex_spin_exit(&sc->sc_lock); 684 return (rv); 685 } 686 687 void 688 com_shutdown(struct com_softc *sc) 689 { 690 struct tty *tp = sc->sc_tty; 691 692 mutex_spin_enter(&sc->sc_lock); 693 694 /* If we were asserting flow control, then deassert it. */ 695 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 696 com_hwiflow(sc); 697 698 /* Clear any break condition set with TIOCSBRK. */ 699 com_break(sc, 0); 700 701 #ifndef __HAVE_TIMECOUNTER 702 /* Turn off PPS capture on last close. */ 703 sc->sc_ppsmask = 0; 704 sc->ppsparam.mode = 0; 705 #endif /* !__HAVE_TIMECOUNTER */ 706 707 /* 708 * Hang up if necessary. Wait a bit, so the other side has time to 709 * notice even if we immediately open the port again. 710 * Avoid tsleeping above splhigh(). 711 */ 712 if (ISSET(tp->t_cflag, HUPCL)) { 713 com_modem(sc, 0); 714 mutex_spin_exit(&sc->sc_lock); 715 /* XXX will only timeout */ 716 (void) kpause(ttclos, false, hz, NULL); 717 mutex_spin_enter(&sc->sc_lock); 718 } 719 720 /* Turn off interrupts. */ 721 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 722 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 723 if (sc->sc_type == COM_TYPE_PXA2x0) 724 sc->sc_ier |= IER_ERXTOUT; 725 } else 726 sc->sc_ier = 0; 727 728 if (sc->sc_type == COM_TYPE_PXA2x0) 729 sc->sc_ier |= IER_EUART; 730 731 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 732 733 if (sc->disable) { 734 #ifdef DIAGNOSTIC 735 if (!sc->enabled) 736 panic("com_shutdown: not enabled?"); 737 #endif 738 (*sc->disable)(sc); 739 sc->enabled = 0; 740 } 741 mutex_spin_exit(&sc->sc_lock); 742 } 743 744 int 745 comopen(dev_t dev, int flag, int mode, struct lwp *l) 746 { 747 struct com_softc *sc; 748 struct tty *tp; 749 int s; 750 int error; 751 752 sc = device_lookup(&com_cd, COMUNIT(dev)); 753 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 754 sc->sc_rbuf == NULL) 755 return (ENXIO); 756 757 if (!device_is_active(&sc->sc_dev)) 758 return (ENXIO); 759 760 #ifdef KGDB 761 /* 762 * If this is the kgdb port, no other use is permitted. 763 */ 764 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 765 return (EBUSY); 766 #endif 767 768 tp = sc->sc_tty; 769 770 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 771 return (EBUSY); 772 773 s = spltty(); 774 775 /* 776 * Do the following iff this is a first open. 777 */ 778 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 779 struct termios t; 780 781 tp->t_dev = dev; 782 783 mutex_spin_enter(&sc->sc_lock); 784 785 if (sc->enable) { 786 if ((*sc->enable)(sc)) { 787 mutex_spin_exit(&sc->sc_lock); 788 splx(s); 789 printf("%s: device enable failed\n", 790 sc->sc_dev.dv_xname); 791 return (EIO); 792 } 793 sc->enabled = 1; 794 com_config(sc); 795 } 796 797 /* Turn on interrupts. */ 798 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 799 if (sc->sc_type == COM_TYPE_PXA2x0) 800 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 801 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 802 803 /* Fetch the current modem control status, needed later. */ 804 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 805 806 /* Clear PPS capture state on first open. */ 807 #ifdef __HAVE_TIMECOUNTER 808 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 809 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 810 pps_init(&sc->sc_pps_state); 811 #else /* !__HAVE_TIMECOUNTER */ 812 sc->sc_ppsmask = 0; 813 sc->ppsparam.mode = 0; 814 #endif /* !__HAVE_TIMECOUNTER */ 815 816 mutex_spin_exit(&sc->sc_lock); 817 818 /* 819 * Initialize the termios status to the defaults. Add in the 820 * sticky bits from TIOCSFLAGS. 821 */ 822 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 823 t.c_ospeed = comconsrate; 824 t.c_cflag = comconscflag; 825 } else { 826 t.c_ospeed = TTYDEF_SPEED; 827 t.c_cflag = TTYDEF_CFLAG; 828 } 829 t.c_ispeed = t.c_ospeed; 830 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 831 SET(t.c_cflag, CLOCAL); 832 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 833 SET(t.c_cflag, CRTSCTS); 834 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 835 SET(t.c_cflag, MDMBUF); 836 /* Make sure comparam() will do something. */ 837 tp->t_ospeed = 0; 838 (void) comparam(tp, &t); 839 tp->t_iflag = TTYDEF_IFLAG; 840 tp->t_oflag = TTYDEF_OFLAG; 841 tp->t_lflag = TTYDEF_LFLAG; 842 ttychars(tp); 843 ttsetwater(tp); 844 845 mutex_spin_enter(&sc->sc_lock); 846 847 /* 848 * Turn on DTR. We must always do this, even if carrier is not 849 * present, because otherwise we'd have to use TIOCSDTR 850 * immediately after setting CLOCAL, which applications do not 851 * expect. We always assert DTR while the device is open 852 * unless explicitly requested to deassert it. 853 */ 854 com_modem(sc, 1); 855 856 /* Clear the input ring, and unblock. */ 857 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 858 sc->sc_rbavail = com_rbuf_size; 859 com_iflush(sc); 860 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 861 com_hwiflow(sc); 862 863 #ifdef COM_DEBUG 864 if (com_debug) 865 comstatus(sc, "comopen "); 866 #endif 867 868 mutex_spin_exit(&sc->sc_lock); 869 } 870 871 splx(s); 872 873 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 874 if (error) 875 goto bad; 876 877 error = (*tp->t_linesw->l_open)(dev, tp); 878 if (error) 879 goto bad; 880 881 return (0); 882 883 bad: 884 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 885 /* 886 * We failed to open the device, and nobody else had it opened. 887 * Clean up the state as appropriate. 888 */ 889 com_shutdown(sc); 890 } 891 892 return (error); 893 } 894 895 int 896 comclose(dev_t dev, int flag, int mode, struct lwp *l) 897 { 898 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 899 struct tty *tp = sc->sc_tty; 900 901 /* XXX This is for cons.c. */ 902 if (!ISSET(tp->t_state, TS_ISOPEN)) 903 return (0); 904 905 (*tp->t_linesw->l_close)(tp, flag); 906 ttyclose(tp); 907 908 if (COM_ISALIVE(sc) == 0) 909 return (0); 910 911 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 912 /* 913 * Although we got a last close, the device may still be in 914 * use; e.g. if this was the dialout node, and there are still 915 * processes waiting for carrier on the non-dialout node. 916 */ 917 com_shutdown(sc); 918 } 919 920 return (0); 921 } 922 923 int 924 comread(dev_t dev, struct uio *uio, int flag) 925 { 926 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 927 struct tty *tp = sc->sc_tty; 928 929 if (COM_ISALIVE(sc) == 0) 930 return (EIO); 931 932 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 933 } 934 935 int 936 comwrite(dev_t dev, struct uio *uio, int flag) 937 { 938 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 939 struct tty *tp = sc->sc_tty; 940 941 if (COM_ISALIVE(sc) == 0) 942 return (EIO); 943 944 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 945 } 946 947 int 948 compoll(dev_t dev, int events, struct lwp *l) 949 { 950 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 951 struct tty *tp = sc->sc_tty; 952 953 if (COM_ISALIVE(sc) == 0) 954 return (POLLHUP); 955 956 return ((*tp->t_linesw->l_poll)(tp, events, l)); 957 } 958 959 struct tty * 960 comtty(dev_t dev) 961 { 962 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 963 struct tty *tp = sc->sc_tty; 964 965 return (tp); 966 } 967 968 int 969 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 970 { 971 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 972 struct tty *tp = sc->sc_tty; 973 int error; 974 975 if (COM_ISALIVE(sc) == 0) 976 return (EIO); 977 978 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 979 if (error != EPASSTHROUGH) 980 return (error); 981 982 error = ttioctl(tp, cmd, data, flag, l); 983 if (error != EPASSTHROUGH) 984 return (error); 985 986 error = 0; 987 switch (cmd) { 988 case TIOCSFLAGS: 989 error = kauth_authorize_device_tty(l->l_cred, 990 KAUTH_DEVICE_TTY_PRIVSET, tp); 991 break; 992 default: 993 /* nothing */ 994 break; 995 } 996 if (error) { 997 return error; 998 } 999 1000 mutex_spin_enter(&sc->sc_lock); 1001 1002 switch (cmd) { 1003 case TIOCSBRK: 1004 com_break(sc, 1); 1005 break; 1006 1007 case TIOCCBRK: 1008 com_break(sc, 0); 1009 break; 1010 1011 case TIOCSDTR: 1012 com_modem(sc, 1); 1013 break; 1014 1015 case TIOCCDTR: 1016 com_modem(sc, 0); 1017 break; 1018 1019 case TIOCGFLAGS: 1020 *(int *)data = sc->sc_swflags; 1021 break; 1022 1023 case TIOCSFLAGS: 1024 sc->sc_swflags = *(int *)data; 1025 break; 1026 1027 case TIOCMSET: 1028 case TIOCMBIS: 1029 case TIOCMBIC: 1030 tiocm_to_com(sc, cmd, *(int *)data); 1031 break; 1032 1033 case TIOCMGET: 1034 *(int *)data = com_to_tiocm(sc); 1035 break; 1036 1037 #ifdef __HAVE_TIMECOUNTER 1038 case PPS_IOC_CREATE: 1039 case PPS_IOC_DESTROY: 1040 case PPS_IOC_GETPARAMS: 1041 case PPS_IOC_SETPARAMS: 1042 case PPS_IOC_GETCAP: 1043 case PPS_IOC_FETCH: 1044 #ifdef PPS_SYNC 1045 case PPS_IOC_KCBIND: 1046 #endif 1047 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1048 break; 1049 #else /* !__HAVE_TIMECOUNTER */ 1050 case PPS_IOC_CREATE: 1051 break; 1052 1053 case PPS_IOC_DESTROY: 1054 break; 1055 1056 case PPS_IOC_GETPARAMS: { 1057 pps_params_t *pp; 1058 pp = (pps_params_t *)data; 1059 *pp = sc->ppsparam; 1060 break; 1061 } 1062 1063 case PPS_IOC_SETPARAMS: { 1064 pps_params_t *pp; 1065 int mode; 1066 pp = (pps_params_t *)data; 1067 if (pp->mode & ~ppscap) { 1068 error = EINVAL; 1069 break; 1070 } 1071 sc->ppsparam = *pp; 1072 /* 1073 * Compute msr masks from user-specified timestamp state. 1074 */ 1075 mode = sc->ppsparam.mode; 1076 switch (mode & PPS_CAPTUREBOTH) { 1077 case 0: 1078 sc->sc_ppsmask = 0; 1079 break; 1080 1081 case PPS_CAPTUREASSERT: 1082 sc->sc_ppsmask = MSR_DCD; 1083 sc->sc_ppsassert = MSR_DCD; 1084 sc->sc_ppsclear = -1; 1085 break; 1086 1087 case PPS_CAPTURECLEAR: 1088 sc->sc_ppsmask = MSR_DCD; 1089 sc->sc_ppsassert = -1; 1090 sc->sc_ppsclear = 0; 1091 break; 1092 1093 case PPS_CAPTUREBOTH: 1094 sc->sc_ppsmask = MSR_DCD; 1095 sc->sc_ppsassert = MSR_DCD; 1096 sc->sc_ppsclear = 0; 1097 break; 1098 1099 default: 1100 error = EINVAL; 1101 break; 1102 } 1103 break; 1104 } 1105 1106 case PPS_IOC_GETCAP: 1107 *(int*)data = ppscap; 1108 break; 1109 1110 case PPS_IOC_FETCH: { 1111 pps_info_t *pi; 1112 pi = (pps_info_t *)data; 1113 *pi = sc->ppsinfo; 1114 break; 1115 } 1116 1117 #ifdef PPS_SYNC 1118 case PPS_IOC_KCBIND: { 1119 int edge = (*(int *)data) & PPS_CAPTUREBOTH; 1120 1121 if (edge == 0) { 1122 /* 1123 * remove binding for this source; ignore 1124 * the request if this is not the current 1125 * hardpps source 1126 */ 1127 if (pps_kc_hardpps_source == sc) { 1128 pps_kc_hardpps_source = NULL; 1129 pps_kc_hardpps_mode = 0; 1130 } 1131 } else { 1132 /* 1133 * bind hardpps to this source, replacing any 1134 * previously specified source or edges 1135 */ 1136 pps_kc_hardpps_source = sc; 1137 pps_kc_hardpps_mode = edge; 1138 } 1139 break; 1140 } 1141 #endif /* PPS_SYNC */ 1142 #endif /* !__HAVE_TIMECOUNTER */ 1143 1144 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1145 #ifdef __HAVE_TIMECOUNTER 1146 #ifndef PPS_TRAILING_EDGE 1147 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1148 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1149 #else 1150 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1151 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1152 #endif 1153 #else /* !__HAVE_TIMECOUNTER */ 1154 /* 1155 * Some GPS clocks models use the falling rather than 1156 * rising edge as the on-the-second signal. 1157 * The old API has no way to specify PPS polarity. 1158 */ 1159 sc->sc_ppsmask = MSR_DCD; 1160 #ifndef PPS_TRAILING_EDGE 1161 sc->sc_ppsassert = MSR_DCD; 1162 sc->sc_ppsclear = -1; 1163 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1164 &sc->ppsinfo.assert_timestamp); 1165 #else 1166 sc->sc_ppsassert = -1; 1167 sc->sc_ppsclear = 0; 1168 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1169 &sc->ppsinfo.clear_timestamp); 1170 #endif 1171 #endif /* !__HAVE_TIMECOUNTER */ 1172 break; 1173 1174 default: 1175 error = EPASSTHROUGH; 1176 break; 1177 } 1178 1179 mutex_spin_exit(&sc->sc_lock); 1180 1181 #ifdef COM_DEBUG 1182 if (com_debug) 1183 comstatus(sc, "comioctl "); 1184 #endif 1185 1186 return (error); 1187 } 1188 1189 integrate void 1190 com_schedrx(struct com_softc *sc) 1191 { 1192 1193 sc->sc_rx_ready = 1; 1194 1195 /* Wake up the poller. */ 1196 softint_schedule(sc->sc_si); 1197 } 1198 1199 void 1200 com_break(struct com_softc *sc, int onoff) 1201 { 1202 1203 if (onoff) 1204 SET(sc->sc_lcr, LCR_SBREAK); 1205 else 1206 CLR(sc->sc_lcr, LCR_SBREAK); 1207 1208 if (!sc->sc_heldchange) { 1209 if (sc->sc_tx_busy) { 1210 sc->sc_heldtbc = sc->sc_tbc; 1211 sc->sc_tbc = 0; 1212 sc->sc_heldchange = 1; 1213 } else 1214 com_loadchannelregs(sc); 1215 } 1216 } 1217 1218 void 1219 com_modem(struct com_softc *sc, int onoff) 1220 { 1221 1222 if (sc->sc_mcr_dtr == 0) 1223 return; 1224 1225 if (onoff) 1226 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1227 else 1228 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1229 1230 if (!sc->sc_heldchange) { 1231 if (sc->sc_tx_busy) { 1232 sc->sc_heldtbc = sc->sc_tbc; 1233 sc->sc_tbc = 0; 1234 sc->sc_heldchange = 1; 1235 } else 1236 com_loadchannelregs(sc); 1237 } 1238 } 1239 1240 void 1241 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1242 { 1243 u_char combits; 1244 1245 combits = 0; 1246 if (ISSET(ttybits, TIOCM_DTR)) 1247 SET(combits, MCR_DTR); 1248 if (ISSET(ttybits, TIOCM_RTS)) 1249 SET(combits, MCR_RTS); 1250 1251 switch (how) { 1252 case TIOCMBIC: 1253 CLR(sc->sc_mcr, combits); 1254 break; 1255 1256 case TIOCMBIS: 1257 SET(sc->sc_mcr, combits); 1258 break; 1259 1260 case TIOCMSET: 1261 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1262 SET(sc->sc_mcr, combits); 1263 break; 1264 } 1265 1266 if (!sc->sc_heldchange) { 1267 if (sc->sc_tx_busy) { 1268 sc->sc_heldtbc = sc->sc_tbc; 1269 sc->sc_tbc = 0; 1270 sc->sc_heldchange = 1; 1271 } else 1272 com_loadchannelregs(sc); 1273 } 1274 } 1275 1276 int 1277 com_to_tiocm(struct com_softc *sc) 1278 { 1279 u_char combits; 1280 int ttybits = 0; 1281 1282 combits = sc->sc_mcr; 1283 if (ISSET(combits, MCR_DTR)) 1284 SET(ttybits, TIOCM_DTR); 1285 if (ISSET(combits, MCR_RTS)) 1286 SET(ttybits, TIOCM_RTS); 1287 1288 combits = sc->sc_msr; 1289 if (ISSET(combits, MSR_DCD)) 1290 SET(ttybits, TIOCM_CD); 1291 if (ISSET(combits, MSR_CTS)) 1292 SET(ttybits, TIOCM_CTS); 1293 if (ISSET(combits, MSR_DSR)) 1294 SET(ttybits, TIOCM_DSR); 1295 if (ISSET(combits, MSR_RI | MSR_TERI)) 1296 SET(ttybits, TIOCM_RI); 1297 1298 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1299 SET(ttybits, TIOCM_LE); 1300 1301 return (ttybits); 1302 } 1303 1304 static u_char 1305 cflag2lcr(tcflag_t cflag) 1306 { 1307 u_char lcr = 0; 1308 1309 switch (ISSET(cflag, CSIZE)) { 1310 case CS5: 1311 SET(lcr, LCR_5BITS); 1312 break; 1313 case CS6: 1314 SET(lcr, LCR_6BITS); 1315 break; 1316 case CS7: 1317 SET(lcr, LCR_7BITS); 1318 break; 1319 case CS8: 1320 SET(lcr, LCR_8BITS); 1321 break; 1322 } 1323 if (ISSET(cflag, PARENB)) { 1324 SET(lcr, LCR_PENAB); 1325 if (!ISSET(cflag, PARODD)) 1326 SET(lcr, LCR_PEVEN); 1327 } 1328 if (ISSET(cflag, CSTOPB)) 1329 SET(lcr, LCR_STOPB); 1330 1331 return (lcr); 1332 } 1333 1334 int 1335 comparam(struct tty *tp, struct termios *t) 1336 { 1337 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1338 int ospeed; 1339 u_char lcr; 1340 1341 if (COM_ISALIVE(sc) == 0) 1342 return (EIO); 1343 1344 #ifdef COM_HAYESP 1345 if (sc->sc_type == COM_TYPE_HAYESP) { 1346 int prescaler, speed; 1347 1348 /* 1349 * Calculate UART clock prescaler. It should be in 1350 * range of 0 .. 3. 1351 */ 1352 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1353 prescaler++, speed /= 2) 1354 if ((ospeed = comspeed(speed, sc->sc_frequency, 1355 sc->sc_type)) > 0) 1356 break; 1357 1358 if (prescaler == 4) 1359 return (EINVAL); 1360 sc->sc_prescaler = prescaler; 1361 } else 1362 #endif 1363 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1364 1365 /* Check requested parameters. */ 1366 if (ospeed < 0) 1367 return (EINVAL); 1368 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1369 return (EINVAL); 1370 1371 /* 1372 * For the console, always force CLOCAL and !HUPCL, so that the port 1373 * is always active. 1374 */ 1375 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1376 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1377 SET(t->c_cflag, CLOCAL); 1378 CLR(t->c_cflag, HUPCL); 1379 } 1380 1381 /* 1382 * If there were no changes, don't do anything. This avoids dropping 1383 * input and improves performance when all we did was frob things like 1384 * VMIN and VTIME. 1385 */ 1386 if (tp->t_ospeed == t->c_ospeed && 1387 tp->t_cflag == t->c_cflag) 1388 return (0); 1389 1390 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1391 1392 mutex_spin_enter(&sc->sc_lock); 1393 1394 sc->sc_lcr = lcr; 1395 1396 /* 1397 * If we're not in a mode that assumes a connection is present, then 1398 * ignore carrier changes. 1399 */ 1400 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1401 sc->sc_msr_dcd = 0; 1402 else 1403 sc->sc_msr_dcd = MSR_DCD; 1404 /* 1405 * Set the flow control pins depending on the current flow control 1406 * mode. 1407 */ 1408 if (ISSET(t->c_cflag, CRTSCTS)) { 1409 sc->sc_mcr_dtr = MCR_DTR; 1410 sc->sc_mcr_rts = MCR_RTS; 1411 sc->sc_msr_cts = MSR_CTS; 1412 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1413 } else if (ISSET(t->c_cflag, MDMBUF)) { 1414 /* 1415 * For DTR/DCD flow control, make sure we don't toggle DTR for 1416 * carrier detection. 1417 */ 1418 sc->sc_mcr_dtr = 0; 1419 sc->sc_mcr_rts = MCR_DTR; 1420 sc->sc_msr_cts = MSR_DCD; 1421 sc->sc_efr = 0; 1422 } else { 1423 /* 1424 * If no flow control, then always set RTS. This will make 1425 * the other side happy if it mistakenly thinks we're doing 1426 * RTS/CTS flow control. 1427 */ 1428 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1429 sc->sc_mcr_rts = 0; 1430 sc->sc_msr_cts = 0; 1431 sc->sc_efr = 0; 1432 if (ISSET(sc->sc_mcr, MCR_DTR)) 1433 SET(sc->sc_mcr, MCR_RTS); 1434 else 1435 CLR(sc->sc_mcr, MCR_RTS); 1436 } 1437 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1438 1439 #if 0 1440 if (ospeed == 0) 1441 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1442 else 1443 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1444 #endif 1445 1446 sc->sc_dlbl = ospeed; 1447 sc->sc_dlbh = ospeed >> 8; 1448 1449 /* 1450 * Set the FIFO threshold based on the receive speed. 1451 * 1452 * * If it's a low speed, it's probably a mouse or some other 1453 * interactive device, so set the threshold low. 1454 * * If it's a high speed, trim the trigger level down to prevent 1455 * overflows. 1456 * * Otherwise set it a bit higher. 1457 */ 1458 if (sc->sc_type == COM_TYPE_HAYESP) 1459 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1460 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1461 sc->sc_fifo = FIFO_ENABLE | 1462 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1463 else 1464 sc->sc_fifo = 0; 1465 1466 /* And copy to tty. */ 1467 tp->t_ispeed = t->c_ospeed; 1468 tp->t_ospeed = t->c_ospeed; 1469 tp->t_cflag = t->c_cflag; 1470 1471 if (!sc->sc_heldchange) { 1472 if (sc->sc_tx_busy) { 1473 sc->sc_heldtbc = sc->sc_tbc; 1474 sc->sc_tbc = 0; 1475 sc->sc_heldchange = 1; 1476 } else 1477 com_loadchannelregs(sc); 1478 } 1479 1480 if (!ISSET(t->c_cflag, CHWFLOW)) { 1481 /* Disable the high water mark. */ 1482 sc->sc_r_hiwat = 0; 1483 sc->sc_r_lowat = 0; 1484 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1485 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1486 com_schedrx(sc); 1487 } 1488 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1489 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1490 com_hwiflow(sc); 1491 } 1492 } else { 1493 sc->sc_r_hiwat = com_rbuf_hiwat; 1494 sc->sc_r_lowat = com_rbuf_lowat; 1495 } 1496 1497 mutex_spin_exit(&sc->sc_lock); 1498 1499 /* 1500 * Update the tty layer's idea of the carrier bit, in case we changed 1501 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1502 * explicit request. 1503 */ 1504 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1505 1506 #ifdef COM_DEBUG 1507 if (com_debug) 1508 comstatus(sc, "comparam "); 1509 #endif 1510 1511 if (!ISSET(t->c_cflag, CHWFLOW)) { 1512 if (sc->sc_tx_stopped) { 1513 sc->sc_tx_stopped = 0; 1514 comstart(tp); 1515 } 1516 } 1517 1518 return (0); 1519 } 1520 1521 void 1522 com_iflush(struct com_softc *sc) 1523 { 1524 struct com_regs *regsp = &sc->sc_regs; 1525 #ifdef DIAGNOSTIC 1526 int reg; 1527 #endif 1528 int timo; 1529 1530 #ifdef DIAGNOSTIC 1531 reg = 0xffff; 1532 #endif 1533 timo = 50000; 1534 /* flush any pending I/O */ 1535 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1536 && --timo) 1537 #ifdef DIAGNOSTIC 1538 reg = 1539 #else 1540 (void) 1541 #endif 1542 CSR_READ_1(regsp, COM_REG_RXDATA); 1543 #ifdef DIAGNOSTIC 1544 if (!timo) 1545 printf("%s: com_iflush timeout %02x\n", sc->sc_dev.dv_xname, 1546 reg); 1547 #endif 1548 } 1549 1550 void 1551 com_loadchannelregs(struct com_softc *sc) 1552 { 1553 struct com_regs *regsp = &sc->sc_regs; 1554 1555 /* XXXXX necessary? */ 1556 com_iflush(sc); 1557 1558 if (sc->sc_type == COM_TYPE_PXA2x0) 1559 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1560 else 1561 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1562 1563 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1564 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1565 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1566 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1567 } 1568 } 1569 if (sc->sc_type == COM_TYPE_AU1x00) { 1570 /* alchemy has single separate 16-bit clock divisor register */ 1571 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1572 (sc->sc_dlbh << 8)); 1573 } else { 1574 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1575 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1576 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1577 } 1578 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1579 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1580 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1581 #ifdef COM_HAYESP 1582 if (sc->sc_type == COM_TYPE_HAYESP) { 1583 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1584 HAYESP_SETPRESCALER); 1585 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1586 sc->sc_prescaler); 1587 } 1588 #endif 1589 1590 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1591 } 1592 1593 int 1594 comhwiflow(struct tty *tp, int block) 1595 { 1596 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1597 1598 if (COM_ISALIVE(sc) == 0) 1599 return (0); 1600 1601 if (sc->sc_mcr_rts == 0) 1602 return (0); 1603 1604 mutex_spin_enter(&sc->sc_lock); 1605 1606 if (block) { 1607 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1608 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1609 com_hwiflow(sc); 1610 } 1611 } else { 1612 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1613 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1614 com_schedrx(sc); 1615 } 1616 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1617 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1618 com_hwiflow(sc); 1619 } 1620 } 1621 1622 mutex_spin_exit(&sc->sc_lock); 1623 return (1); 1624 } 1625 1626 /* 1627 * (un)block input via hw flowcontrol 1628 */ 1629 void 1630 com_hwiflow(struct com_softc *sc) 1631 { 1632 struct com_regs *regsp= &sc->sc_regs; 1633 1634 if (sc->sc_mcr_rts == 0) 1635 return; 1636 1637 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1638 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1639 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1640 } else { 1641 SET(sc->sc_mcr, sc->sc_mcr_rts); 1642 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1643 } 1644 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1645 } 1646 1647 1648 void 1649 comstart(struct tty *tp) 1650 { 1651 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1652 struct com_regs *regsp = &sc->sc_regs; 1653 int s; 1654 1655 if (COM_ISALIVE(sc) == 0) 1656 return; 1657 1658 s = spltty(); 1659 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1660 goto out; 1661 if (sc->sc_tx_stopped) 1662 goto out; 1663 1664 if (tp->t_outq.c_cc <= tp->t_lowat) { 1665 if (ISSET(tp->t_state, TS_ASLEEP)) { 1666 CLR(tp->t_state, TS_ASLEEP); 1667 wakeup(&tp->t_outq); 1668 } 1669 selwakeup(&tp->t_wsel); 1670 if (tp->t_outq.c_cc == 0) 1671 goto out; 1672 } 1673 1674 /* Grab the first contiguous region of buffer space. */ 1675 { 1676 u_char *tba; 1677 int tbc; 1678 1679 tba = tp->t_outq.c_cf; 1680 tbc = ndqb(&tp->t_outq, 0); 1681 1682 mutex_spin_enter(&sc->sc_lock); 1683 1684 sc->sc_tba = tba; 1685 sc->sc_tbc = tbc; 1686 } 1687 1688 SET(tp->t_state, TS_BUSY); 1689 sc->sc_tx_busy = 1; 1690 1691 /* Enable transmit completion interrupts if necessary. */ 1692 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1693 SET(sc->sc_ier, IER_ETXRDY); 1694 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1695 } 1696 1697 /* Output the first chunk of the contiguous buffer. */ 1698 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1699 u_int n; 1700 1701 n = sc->sc_tbc; 1702 if (n > sc->sc_fifolen) 1703 n = sc->sc_fifolen; 1704 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1705 sc->sc_tbc -= n; 1706 sc->sc_tba += n; 1707 } 1708 1709 mutex_spin_exit(&sc->sc_lock); 1710 out: 1711 splx(s); 1712 return; 1713 } 1714 1715 /* 1716 * Stop output on a line. 1717 */ 1718 void 1719 comstop(struct tty *tp, int flag) 1720 { 1721 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1722 1723 mutex_spin_enter(&sc->sc_lock); 1724 if (ISSET(tp->t_state, TS_BUSY)) { 1725 /* Stop transmitting at the next chunk. */ 1726 sc->sc_tbc = 0; 1727 sc->sc_heldtbc = 0; 1728 if (!ISSET(tp->t_state, TS_TTSTOP)) 1729 SET(tp->t_state, TS_FLUSH); 1730 } 1731 mutex_spin_exit(&sc->sc_lock); 1732 } 1733 1734 void 1735 comdiag(void *arg) 1736 { 1737 struct com_softc *sc = arg; 1738 int overflows, floods; 1739 1740 mutex_spin_enter(&sc->sc_lock); 1741 overflows = sc->sc_overflows; 1742 sc->sc_overflows = 0; 1743 floods = sc->sc_floods; 1744 sc->sc_floods = 0; 1745 sc->sc_errors = 0; 1746 mutex_spin_exit(&sc->sc_lock); 1747 1748 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1749 sc->sc_dev.dv_xname, 1750 overflows, overflows == 1 ? "" : "s", 1751 floods, floods == 1 ? "" : "s"); 1752 } 1753 1754 integrate void 1755 com_rxsoft(struct com_softc *sc, struct tty *tp) 1756 { 1757 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1758 u_char *get, *end; 1759 u_int cc, scc; 1760 u_char lsr; 1761 int code; 1762 1763 end = sc->sc_ebuf; 1764 get = sc->sc_rbget; 1765 scc = cc = com_rbuf_size - sc->sc_rbavail; 1766 1767 if (cc == com_rbuf_size) { 1768 sc->sc_floods++; 1769 if (sc->sc_errors++ == 0) 1770 callout_reset(&sc->sc_diag_callout, 60 * hz, 1771 comdiag, sc); 1772 } 1773 1774 /* If not yet open, drop the entire buffer content here */ 1775 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1776 get += cc << 1; 1777 if (get >= end) 1778 get -= com_rbuf_size << 1; 1779 cc = 0; 1780 } 1781 while (cc) { 1782 code = get[0]; 1783 lsr = get[1]; 1784 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1785 if (ISSET(lsr, LSR_OE)) { 1786 sc->sc_overflows++; 1787 if (sc->sc_errors++ == 0) 1788 callout_reset(&sc->sc_diag_callout, 1789 60 * hz, comdiag, sc); 1790 } 1791 if (ISSET(lsr, LSR_BI | LSR_FE)) 1792 SET(code, TTY_FE); 1793 if (ISSET(lsr, LSR_PE)) 1794 SET(code, TTY_PE); 1795 } 1796 if ((*rint)(code, tp) == -1) { 1797 /* 1798 * The line discipline's buffer is out of space. 1799 */ 1800 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1801 /* 1802 * We're either not using flow control, or the 1803 * line discipline didn't tell us to block for 1804 * some reason. Either way, we have no way to 1805 * know when there's more space available, so 1806 * just drop the rest of the data. 1807 */ 1808 get += cc << 1; 1809 if (get >= end) 1810 get -= com_rbuf_size << 1; 1811 cc = 0; 1812 } else { 1813 /* 1814 * Don't schedule any more receive processing 1815 * until the line discipline tells us there's 1816 * space available (through comhwiflow()). 1817 * Leave the rest of the data in the input 1818 * buffer. 1819 */ 1820 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1821 } 1822 break; 1823 } 1824 get += 2; 1825 if (get >= end) 1826 get = sc->sc_rbuf; 1827 cc--; 1828 } 1829 1830 if (cc != scc) { 1831 sc->sc_rbget = get; 1832 mutex_spin_enter(&sc->sc_lock); 1833 1834 cc = sc->sc_rbavail += scc - cc; 1835 /* Buffers should be ok again, release possible block. */ 1836 if (cc >= sc->sc_r_lowat) { 1837 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1838 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1839 SET(sc->sc_ier, IER_ERXRDY); 1840 #ifdef COM_PXA2X0 1841 if (sc->sc_type == COM_TYPE_PXA2x0) 1842 SET(sc->sc_ier, IER_ERXTOUT); 1843 #endif 1844 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1845 } 1846 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1847 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1848 com_hwiflow(sc); 1849 } 1850 } 1851 mutex_spin_exit(&sc->sc_lock); 1852 } 1853 } 1854 1855 integrate void 1856 com_txsoft(struct com_softc *sc, struct tty *tp) 1857 { 1858 1859 CLR(tp->t_state, TS_BUSY); 1860 if (ISSET(tp->t_state, TS_FLUSH)) 1861 CLR(tp->t_state, TS_FLUSH); 1862 else 1863 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1864 (*tp->t_linesw->l_start)(tp); 1865 } 1866 1867 integrate void 1868 com_stsoft(struct com_softc *sc, struct tty *tp) 1869 { 1870 u_char msr, delta; 1871 1872 mutex_spin_enter(&sc->sc_lock); 1873 msr = sc->sc_msr; 1874 delta = sc->sc_msr_delta; 1875 sc->sc_msr_delta = 0; 1876 mutex_spin_exit(&sc->sc_lock); 1877 1878 if (ISSET(delta, sc->sc_msr_dcd)) { 1879 /* 1880 * Inform the tty layer that carrier detect changed. 1881 */ 1882 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1883 } 1884 1885 if (ISSET(delta, sc->sc_msr_cts)) { 1886 /* Block or unblock output according to flow control. */ 1887 if (ISSET(msr, sc->sc_msr_cts)) { 1888 sc->sc_tx_stopped = 0; 1889 (*tp->t_linesw->l_start)(tp); 1890 } else { 1891 sc->sc_tx_stopped = 1; 1892 } 1893 } 1894 1895 #ifdef COM_DEBUG 1896 if (com_debug) 1897 comstatus(sc, "com_stsoft"); 1898 #endif 1899 } 1900 1901 void 1902 comsoft(void *arg) 1903 { 1904 struct com_softc *sc = arg; 1905 struct tty *tp; 1906 1907 if (COM_ISALIVE(sc) == 0) 1908 return; 1909 1910 tp = sc->sc_tty; 1911 1912 if (sc->sc_rx_ready) { 1913 sc->sc_rx_ready = 0; 1914 com_rxsoft(sc, tp); 1915 } 1916 1917 if (sc->sc_st_check) { 1918 sc->sc_st_check = 0; 1919 com_stsoft(sc, tp); 1920 } 1921 1922 if (sc->sc_tx_done) { 1923 sc->sc_tx_done = 0; 1924 com_txsoft(sc, tp); 1925 } 1926 } 1927 1928 int 1929 comintr(void *arg) 1930 { 1931 struct com_softc *sc = arg; 1932 struct com_regs *regsp = &sc->sc_regs; 1933 1934 u_char *put, *end; 1935 u_int cc; 1936 u_char lsr, iir; 1937 1938 if (COM_ISALIVE(sc) == 0) 1939 return (0); 1940 1941 mutex_spin_enter(&sc->sc_lock); 1942 iir = CSR_READ_1(regsp, COM_REG_IIR); 1943 if (ISSET(iir, IIR_NOPEND)) { 1944 mutex_spin_exit(&sc->sc_lock); 1945 return (0); 1946 } 1947 1948 end = sc->sc_ebuf; 1949 put = sc->sc_rbput; 1950 cc = sc->sc_rbavail; 1951 1952 again: do { 1953 u_char msr, delta; 1954 1955 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1956 if (ISSET(lsr, LSR_BI)) { 1957 int cn_trapped = 0; 1958 1959 cn_check_magic(sc->sc_tty->t_dev, 1960 CNC_BREAK, com_cnm_state); 1961 if (cn_trapped) 1962 continue; 1963 #if defined(KGDB) && !defined(DDB) 1964 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1965 kgdb_connect(1); 1966 continue; 1967 } 1968 #endif 1969 } 1970 1971 if (ISSET(lsr, LSR_RCV_MASK) && 1972 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1973 while (cc > 0) { 1974 int cn_trapped = 0; 1975 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1976 put[1] = lsr; 1977 cn_check_magic(sc->sc_tty->t_dev, 1978 put[0], com_cnm_state); 1979 if (cn_trapped) 1980 goto next; 1981 put += 2; 1982 if (put >= end) 1983 put = sc->sc_rbuf; 1984 cc--; 1985 next: 1986 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1987 if (!ISSET(lsr, LSR_RCV_MASK)) 1988 break; 1989 } 1990 1991 /* 1992 * Current string of incoming characters ended because 1993 * no more data was available or we ran out of space. 1994 * Schedule a receive event if any data was received. 1995 * If we're out of space, turn off receive interrupts. 1996 */ 1997 sc->sc_rbput = put; 1998 sc->sc_rbavail = cc; 1999 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2000 sc->sc_rx_ready = 1; 2001 2002 /* 2003 * See if we are in danger of overflowing a buffer. If 2004 * so, use hardware flow control to ease the pressure. 2005 */ 2006 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2007 cc < sc->sc_r_hiwat) { 2008 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2009 com_hwiflow(sc); 2010 } 2011 2012 /* 2013 * If we're out of space, disable receive interrupts 2014 * until the queue has drained a bit. 2015 */ 2016 if (!cc) { 2017 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2018 #ifdef COM_PXA2X0 2019 if (sc->sc_type == COM_TYPE_PXA2x0) 2020 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2021 else 2022 #endif 2023 CLR(sc->sc_ier, IER_ERXRDY); 2024 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2025 } 2026 } else { 2027 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2028 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2029 continue; 2030 } 2031 } 2032 2033 msr = CSR_READ_1(regsp, COM_REG_MSR); 2034 delta = msr ^ sc->sc_msr; 2035 sc->sc_msr = msr; 2036 #ifdef __HAVE_TIMECOUNTER 2037 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2038 (delta & MSR_DCD)) { 2039 pps_capture(&sc->sc_pps_state); 2040 pps_event(&sc->sc_pps_state, 2041 (msr & MSR_DCD) ? 2042 PPS_CAPTUREASSERT : 2043 PPS_CAPTURECLEAR); 2044 } 2045 #else /* !__HAVE_TIMECOUNTER */ 2046 /* 2047 * Pulse-per-second (PSS) signals on edge of DCD? 2048 * Process these even if line discipline is ignoring DCD. 2049 */ 2050 if (delta & sc->sc_ppsmask) { 2051 struct timeval tv; 2052 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) { 2053 /* XXX nanotime() */ 2054 microtime(&tv); 2055 TIMEVAL_TO_TIMESPEC(&tv, 2056 &sc->ppsinfo.assert_timestamp); 2057 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 2058 timespecadd(&sc->ppsinfo.assert_timestamp, 2059 &sc->ppsparam.assert_offset, 2060 &sc->ppsinfo.assert_timestamp); 2061 } 2062 2063 #ifdef PPS_SYNC 2064 if (pps_kc_hardpps_source == sc && 2065 pps_kc_hardpps_mode & PPS_CAPTUREASSERT) { 2066 hardpps(&tv, tv.tv_usec); 2067 } 2068 #endif 2069 sc->ppsinfo.assert_sequence++; 2070 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2071 2072 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) { 2073 /* XXX nanotime() */ 2074 microtime(&tv); 2075 TIMEVAL_TO_TIMESPEC(&tv, 2076 &sc->ppsinfo.clear_timestamp); 2077 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 2078 timespecadd(&sc->ppsinfo.clear_timestamp, 2079 &sc->ppsparam.clear_offset, 2080 &sc->ppsinfo.clear_timestamp); 2081 } 2082 2083 #ifdef PPS_SYNC 2084 if (pps_kc_hardpps_source == sc && 2085 pps_kc_hardpps_mode & PPS_CAPTURECLEAR) { 2086 hardpps(&tv, tv.tv_usec); 2087 } 2088 #endif 2089 sc->ppsinfo.clear_sequence++; 2090 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2091 } 2092 } 2093 #endif /* !__HAVE_TIMECOUNTER */ 2094 2095 /* 2096 * Process normal status changes 2097 */ 2098 if (ISSET(delta, sc->sc_msr_mask)) { 2099 SET(sc->sc_msr_delta, delta); 2100 2101 /* 2102 * Stop output immediately if we lose the output 2103 * flow control signal or carrier detect. 2104 */ 2105 if (ISSET(~msr, sc->sc_msr_mask)) { 2106 sc->sc_tbc = 0; 2107 sc->sc_heldtbc = 0; 2108 #ifdef COM_DEBUG 2109 if (com_debug) 2110 comstatus(sc, "comintr "); 2111 #endif 2112 } 2113 2114 sc->sc_st_check = 1; 2115 } 2116 } while (!ISSET((iir = 2117 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2118 /* 2119 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2120 * by IIR read, so we can't do this way: `process all interrupts, 2121 * then do TX if possble'. 2122 */ 2123 (iir & IIR_IMASK) != IIR_TXRDY); 2124 2125 /* 2126 * Read LSR again, since there may be an interrupt between 2127 * the last LSR read and IIR read above. 2128 */ 2129 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2130 2131 /* 2132 * See if data can be transmitted as well. 2133 * Schedule tx done event if no data left 2134 * and tty was marked busy. 2135 */ 2136 if (ISSET(lsr, LSR_TXRDY)) { 2137 /* 2138 * If we've delayed a parameter change, do it now, and restart 2139 * output. 2140 */ 2141 if (sc->sc_heldchange) { 2142 com_loadchannelregs(sc); 2143 sc->sc_heldchange = 0; 2144 sc->sc_tbc = sc->sc_heldtbc; 2145 sc->sc_heldtbc = 0; 2146 } 2147 2148 /* Output the next chunk of the contiguous buffer, if any. */ 2149 if (sc->sc_tbc > 0) { 2150 u_int n; 2151 2152 n = sc->sc_tbc; 2153 if (n > sc->sc_fifolen) 2154 n = sc->sc_fifolen; 2155 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2156 sc->sc_tbc -= n; 2157 sc->sc_tba += n; 2158 } else { 2159 /* Disable transmit completion interrupts if necessary. */ 2160 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2161 CLR(sc->sc_ier, IER_ETXRDY); 2162 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2163 } 2164 if (sc->sc_tx_busy) { 2165 sc->sc_tx_busy = 0; 2166 sc->sc_tx_done = 1; 2167 } 2168 } 2169 } 2170 2171 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2172 goto again; 2173 2174 mutex_spin_exit(&sc->sc_lock); 2175 2176 /* Wake up the poller. */ 2177 softint_schedule(sc->sc_si); 2178 2179 #if NRND > 0 && defined(RND_COM) 2180 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2181 #endif 2182 2183 return (1); 2184 } 2185 2186 /* 2187 * The following functions are polled getc and putc routines, shared 2188 * by the console and kgdb glue. 2189 * 2190 * The read-ahead code is so that you can detect pending in-band 2191 * cn_magic in polled mode while doing output rather than having to 2192 * wait until the kernel decides it needs input. 2193 */ 2194 2195 #define MAX_READAHEAD 20 2196 static int com_readahead[MAX_READAHEAD]; 2197 static int com_readaheadcount = 0; 2198 2199 int 2200 com_common_getc(dev_t dev, struct com_regs *regsp) 2201 { 2202 int s = splserial(); 2203 u_char stat, c; 2204 2205 /* got a character from reading things earlier */ 2206 if (com_readaheadcount > 0) { 2207 int i; 2208 2209 c = com_readahead[0]; 2210 for (i = 1; i < com_readaheadcount; i++) { 2211 com_readahead[i-1] = com_readahead[i]; 2212 } 2213 com_readaheadcount--; 2214 splx(s); 2215 return (c); 2216 } 2217 2218 /* block until a character becomes available */ 2219 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2220 ; 2221 2222 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2223 stat = CSR_READ_1(regsp, COM_REG_IIR); 2224 { 2225 int cn_trapped = 0; /* unused */ 2226 #ifdef DDB 2227 extern int db_active; 2228 if (!db_active) 2229 #endif 2230 cn_check_magic(dev, c, com_cnm_state); 2231 } 2232 splx(s); 2233 return (c); 2234 } 2235 2236 void 2237 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2238 { 2239 int s = splserial(); 2240 int cin, stat, timo; 2241 2242 if (com_readaheadcount < MAX_READAHEAD 2243 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2244 int cn_trapped = 0; 2245 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2246 stat = CSR_READ_1(regsp, COM_REG_IIR); 2247 cn_check_magic(dev, cin, com_cnm_state); 2248 com_readahead[com_readaheadcount++] = cin; 2249 } 2250 2251 /* wait for any pending transmission to finish */ 2252 timo = 150000; 2253 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2254 continue; 2255 2256 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2257 COM_BARRIER(regsp, BR | BW); 2258 2259 splx(s); 2260 } 2261 2262 /* 2263 * Initialize UART for use as console or KGDB line. 2264 */ 2265 int 2266 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2267 tcflag_t cflag) 2268 { 2269 2270 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2271 ®sp->cr_ioh)) 2272 return (ENOMEM); /* ??? */ 2273 2274 rate = comspeed(rate, frequency, type); 2275 if (type != COM_TYPE_AU1x00) { 2276 /* no EFR on alchemy */ 2277 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2278 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2279 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2280 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2281 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2282 } else { 2283 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2284 } 2285 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2286 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2287 CSR_WRITE_1(regsp, COM_REG_FIFO, 2288 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2289 #ifdef COM_PXA2X0 2290 if (type == COM_TYPE_PXA2x0) 2291 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2292 else 2293 #endif 2294 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2295 2296 return (0); 2297 } 2298 2299 /* 2300 * Following are all routines needed for COM to act as console 2301 */ 2302 struct consdev comcons = { 2303 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2304 NODEV, CN_NORMAL 2305 }; 2306 2307 2308 int 2309 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2310 tcflag_t cflag) 2311 { 2312 int res; 2313 2314 comconsregs = *regsp; 2315 2316 res = cominit(&comconsregs, rate, frequency, type, cflag); 2317 if (res) 2318 return (res); 2319 2320 cn_tab = &comcons; 2321 cn_init_magic(&com_cnm_state); 2322 cn_set_magic("\047\001"); /* default magic is BREAK */ 2323 2324 comconsrate = rate; 2325 comconscflag = cflag; 2326 2327 return (0); 2328 } 2329 2330 int 2331 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2332 int type, tcflag_t cflag) 2333 { 2334 struct com_regs regs; 2335 2336 memset(®s, 0, sizeof regs); 2337 regs.cr_iot = iot; 2338 regs.cr_iobase = iobase; 2339 regs.cr_nports = COM_NPORTS; 2340 #ifdef COM_REGMAP 2341 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2342 #endif 2343 2344 return comcnattach1(®s, rate, frequency, type, cflag); 2345 } 2346 2347 int 2348 comcngetc(dev_t dev) 2349 { 2350 2351 return (com_common_getc(dev, &comconsregs)); 2352 } 2353 2354 /* 2355 * Console kernel output character routine. 2356 */ 2357 void 2358 comcnputc(dev_t dev, int c) 2359 { 2360 2361 com_common_putc(dev, &comconsregs, c); 2362 } 2363 2364 void 2365 comcnpollc(dev_t dev, int on) 2366 { 2367 2368 } 2369 2370 #ifdef KGDB 2371 int 2372 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2373 tcflag_t cflag) 2374 { 2375 int res; 2376 2377 if (regsp->cr_iot == comconsregs.cr_iot && 2378 regsp->cr_iobase == comconsregs.cr_iobase) { 2379 #if !defined(DDB) 2380 return (EBUSY); /* cannot share with console */ 2381 #else 2382 comkgdbregs = *regsp; 2383 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2384 #endif 2385 } else { 2386 comkgdbregs = *regsp; 2387 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2388 if (res) 2389 return (res); 2390 2391 /* 2392 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2393 * expects this to be initialized 2394 */ 2395 cn_init_magic(&com_cnm_state); 2396 cn_set_magic("\047\001"); 2397 } 2398 2399 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2400 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2401 2402 return (0); 2403 } 2404 2405 int 2406 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2407 int frequency, int type, tcflag_t cflag) 2408 { 2409 struct com_regs regs; 2410 2411 regs.cr_iot = iot; 2412 regs.cr_nports = COM_NPORTS; 2413 regs.cr_iobase = iobase; 2414 #ifdef COM_REGMAP 2415 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2416 #endif 2417 2418 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2419 } 2420 2421 /* ARGSUSED */ 2422 int 2423 com_kgdb_getc(void *arg) 2424 { 2425 2426 return (com_common_getc(NODEV, &comkgdbregs)); 2427 } 2428 2429 /* ARGSUSED */ 2430 void 2431 com_kgdb_putc(void *arg, int c) 2432 { 2433 2434 com_common_putc(NODEV, &comkgdbregs, c); 2435 } 2436 #endif /* KGDB */ 2437 2438 /* helper function to identify the com ports used by 2439 console or KGDB (and not yet autoconf attached) */ 2440 int 2441 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2442 { 2443 bus_space_handle_t help; 2444 2445 if (!comconsattached && 2446 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2447 help = comconsregs.cr_ioh; 2448 #ifdef KGDB 2449 else if (!com_kgdb_attached && 2450 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2451 help = comkgdbregs.cr_ioh; 2452 #endif 2453 else 2454 return (0); 2455 2456 if (ioh) 2457 *ioh = help; 2458 return (1); 2459 } 2460 2461 /* 2462 * this routine exists to serve as a shutdown hook for systems that 2463 * have firmware which doesn't interact properly with a com device in 2464 * FIFO mode. 2465 */ 2466 void 2467 com_cleanup(void *arg) 2468 { 2469 struct com_softc *sc = arg; 2470 2471 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2472 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2473 } 2474 2475 void 2476 com_power(int why, void *arg) 2477 { 2478 struct com_softc *sc = arg; 2479 2480 mutex_spin_enter(&sc->sc_lock); 2481 switch (why) { 2482 case PWR_SUSPEND: 2483 case PWR_STANDBY: 2484 /* XXX should we do something to stop the device? */ 2485 break; 2486 case PWR_RESUME: 2487 com_loadchannelregs(sc); 2488 break; 2489 case PWR_SOFTSUSPEND: 2490 case PWR_SOFTSTANDBY: 2491 case PWR_SOFTRESUME: 2492 break; 2493 } 2494 mutex_spin_exit(&sc->sc_lock); 2495 } 2496
Indexes created Wed Sep 24 05:09:52 GMT 2025