com.c revision 1.268
1 /* $NetBSD: com.c,v 1.268 2007/12/14 03:36:54 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1991 The Regents of the University of California. 41 * All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. Neither the name of the University nor the names of its contributors 52 * may be used to endorse or promote products derived from this software 53 * without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 56 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 58 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 61 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 62 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 63 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 64 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 65 * SUCH DAMAGE. 66 * 67 * @(#)com.c 7.5 (Berkeley) 5/16/91 68 */ 69 70 /* 71 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 72 * Supports automatic hardware flow control on StarTech ST16C650A UART 73 */ 74 75 #include <sys/cdefs.h> 76 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.268 2007/12/14 03:36:54 dyoung Exp $"); 77 78 #include "opt_com.h" 79 #include "opt_ddb.h" 80 #include "opt_kgdb.h" 81 #include "opt_lockdebug.h" 82 #include "opt_multiprocessor.h" 83 #include "opt_ntp.h" 84 85 #include "rnd.h" 86 #if NRND > 0 && defined(RND_COM) 87 #include <sys/rnd.h> 88 #endif 89 90 /* The COM16650 option was renamed to COM_16650. */ 91 #ifdef COM16650 92 #error Obsolete COM16650 option; use COM_16650 instead. 93 #endif 94 95 /* 96 * Override cnmagic(9) macro before including <sys/systm.h>. 97 * We need to know if cn_check_magic triggered debugger, so set a flag. 98 * Callers of cn_check_magic must declare int cn_trapped = 0; 99 * XXX: this is *ugly*! 100 */ 101 #define cn_trap() \ 102 do { \ 103 console_debugger(); \ 104 cn_trapped = 1; \ 105 } while (/* CONSTCOND */ 0) 106 107 #include <sys/param.h> 108 #include <sys/systm.h> 109 #include <sys/ioctl.h> 110 #include <sys/select.h> 111 #include <sys/poll.h> 112 #include <sys/tty.h> 113 #include <sys/proc.h> 114 #include <sys/user.h> 115 #include <sys/conf.h> 116 #include <sys/file.h> 117 #include <sys/uio.h> 118 #include <sys/kernel.h> 119 #include <sys/syslog.h> 120 #include <sys/device.h> 121 #include <sys/malloc.h> 122 #include <sys/timepps.h> 123 #include <sys/vnode.h> 124 #include <sys/kauth.h> 125 #include <sys/intr.h> 126 127 #include <sys/bus.h> 128 129 #include <dev/ic/comreg.h> 130 #include <dev/ic/comvar.h> 131 #include <dev/ic/ns16550reg.h> 132 #include <dev/ic/st16650reg.h> 133 #ifdef COM_HAYESP 134 #include <dev/ic/hayespreg.h> 135 #endif 136 #define com_lcr com_cfcr 137 #include <dev/cons.h> 138 139 #ifdef COM_REGMAP 140 #define CSR_WRITE_1(r, o, v) \ 141 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 142 #define CSR_READ_1(r, o) \ 143 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 144 #define CSR_WRITE_2(r, o, v) \ 145 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 146 #define CSR_READ_2(r, o) \ 147 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 148 #define CSR_WRITE_MULTI(r, o, p, n) \ 149 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 150 #else 151 #define CSR_WRITE_1(r, o, v) \ 152 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 153 #define CSR_READ_1(r, o) \ 154 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 155 #define CSR_WRITE_2(r, o, v) \ 156 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 157 #define CSR_READ_2(r, o) \ 158 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 159 #define CSR_WRITE_MULTI(r, o, p, n) \ 160 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 161 #endif 162 163 164 static void com_enable_debugport(struct com_softc *); 165 166 void com_config(struct com_softc *); 167 void com_shutdown(struct com_softc *); 168 int comspeed(long, long, int); 169 static u_char cflag2lcr(tcflag_t); 170 int comparam(struct tty *, struct termios *); 171 void comstart(struct tty *); 172 int comhwiflow(struct tty *, int); 173 174 void com_loadchannelregs(struct com_softc *); 175 void com_hwiflow(struct com_softc *); 176 void com_break(struct com_softc *, int); 177 void com_modem(struct com_softc *, int); 178 void tiocm_to_com(struct com_softc *, u_long, int); 179 int com_to_tiocm(struct com_softc *); 180 void com_iflush(struct com_softc *); 181 182 int com_common_getc(dev_t, struct com_regs *); 183 void com_common_putc(dev_t, struct com_regs *, int); 184 185 int cominit(struct com_regs *, int, int, int, tcflag_t); 186 187 int comcngetc(dev_t); 188 void comcnputc(dev_t, int); 189 void comcnpollc(dev_t, int); 190 191 #define integrate static inline 192 void comsoft(void *); 193 integrate void com_rxsoft(struct com_softc *, struct tty *); 194 integrate void com_txsoft(struct com_softc *, struct tty *); 195 integrate void com_stsoft(struct com_softc *, struct tty *); 196 integrate void com_schedrx(struct com_softc *); 197 void comdiag(void *); 198 199 extern struct cfdriver com_cd; 200 201 dev_type_open(comopen); 202 dev_type_close(comclose); 203 dev_type_read(comread); 204 dev_type_write(comwrite); 205 dev_type_ioctl(comioctl); 206 dev_type_stop(comstop); 207 dev_type_tty(comtty); 208 dev_type_poll(compoll); 209 210 const struct cdevsw com_cdevsw = { 211 comopen, comclose, comread, comwrite, comioctl, 212 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 213 }; 214 215 /* 216 * Make this an option variable one can patch. 217 * But be warned: this must be a power of 2! 218 */ 219 u_int com_rbuf_size = COM_RING_SIZE; 220 221 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 222 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 223 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 224 225 static struct com_regs comconsregs; 226 static int comconsattached; 227 static int comconsrate; 228 static tcflag_t comconscflag; 229 static struct cnm_state com_cnm_state; 230 231 #ifndef __HAVE_TIMECOUNTER 232 static int ppscap = 233 PPS_TSFMT_TSPEC | 234 PPS_CAPTUREASSERT | 235 PPS_CAPTURECLEAR | 236 PPS_OFFSETASSERT | PPS_OFFSETCLEAR; 237 #endif /* !__HAVE_TIMECOUNTER */ 238 239 #ifdef KGDB 240 #include <sys/kgdb.h> 241 242 static struct com_regs comkgdbregs; 243 static int com_kgdb_attached; 244 245 int com_kgdb_getc(void *); 246 void com_kgdb_putc(void *, int); 247 #endif /* KGDB */ 248 249 #ifdef COM_REGMAP 250 /* initializer for typical 16550-ish hardware */ 251 #define COM_REG_16550 { \ 252 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 253 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 254 255 const bus_size_t com_std_map[16] = COM_REG_16550; 256 #endif /* COM_REGMAP */ 257 258 #define COMUNIT_MASK 0x7ffff 259 #define COMDIALOUT_MASK 0x80000 260 261 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 262 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 263 264 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 265 device_is_active(&(sc)->sc_dev)) 266 267 #define BR BUS_SPACE_BARRIER_READ 268 #define BW BUS_SPACE_BARRIER_WRITE 269 #define COM_BARRIER(r, f) \ 270 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 271 272 /*ARGSUSED*/ 273 int 274 comspeed(long speed, long frequency, int type) 275 { 276 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 277 278 int x, err; 279 280 #if 0 281 if (speed == 0) 282 return (0); 283 #endif 284 if (speed <= 0) 285 return (-1); 286 x = divrnd(frequency / 16, speed); 287 if (x <= 0) 288 return (-1); 289 err = divrnd(((quad_t)frequency) * 1000 / 16, speed * x) - 1000; 290 if (err < 0) 291 err = -err; 292 if (err > COM_TOLERANCE) 293 return (-1); 294 return (x); 295 296 #undef divrnd 297 } 298 299 #ifdef COM_DEBUG 300 int com_debug = 0; 301 302 void comstatus(struct com_softc *, const char *); 303 void 304 comstatus(struct com_softc *sc, const char *str) 305 { 306 struct tty *tp = sc->sc_tty; 307 308 printf("%s: %s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 309 sc->sc_dev.dv_xname, str, 310 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 311 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 312 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 313 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 314 sc->sc_tx_stopped ? '+' : '-'); 315 316 printf("%s: %s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 317 sc->sc_dev.dv_xname, str, 318 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 319 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 320 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 321 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 322 sc->sc_rx_flags); 323 } 324 #endif 325 326 int 327 com_probe_subr(struct com_regs *regs) 328 { 329 330 /* force access to id reg */ 331 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 332 CSR_WRITE_1(regs, COM_REG_IIR, 0); 333 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 334 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 335 return (0); 336 337 return (1); 338 } 339 340 int 341 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 342 { 343 struct com_regs regs; 344 345 regs.cr_iot = iot; 346 regs.cr_ioh = ioh; 347 #ifdef COM_REGMAP 348 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 349 #endif 350 351 return com_probe_subr(®s); 352 } 353 354 /* 355 * No locking in this routine; it is only called during attach, 356 * or with the port already locked. 357 */ 358 static void 359 com_enable_debugport(struct com_softc *sc) 360 { 361 362 /* Turn on line break interrupt, set carrier. */ 363 sc->sc_ier = IER_ERXRDY; 364 if (sc->sc_type == COM_TYPE_PXA2x0) 365 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 366 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 367 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 368 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 369 } 370 371 void 372 com_attach_subr(struct com_softc *sc) 373 { 374 struct com_regs *regsp = &sc->sc_regs; 375 struct tty *tp; 376 #ifdef COM_16650 377 u_int8_t lcr; 378 #endif 379 const char *fifo_msg = NULL; 380 381 aprint_naive("\n"); 382 383 callout_init(&sc->sc_diag_callout, 0); 384 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 385 386 /* Disable interrupts before configuring the device. */ 387 if (sc->sc_type == COM_TYPE_PXA2x0) 388 sc->sc_ier = IER_EUART; 389 else 390 sc->sc_ier = 0; 391 392 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 393 394 if (regsp->cr_iot == comconsregs.cr_iot && 395 regsp->cr_iobase == comconsregs.cr_iobase) { 396 comconsattached = 1; 397 398 /* Make sure the console is always "hardwired". */ 399 delay(10000); /* wait for output to finish */ 400 SET(sc->sc_hwflags, COM_HW_CONSOLE); 401 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 402 } 403 404 /* Probe for FIFO */ 405 switch (sc->sc_type) { 406 case COM_TYPE_HAYESP: 407 goto fifodone; 408 409 case COM_TYPE_AU1x00: 410 sc->sc_fifolen = 16; 411 fifo_msg = "Au1X00 UART, working fifo"; 412 SET(sc->sc_hwflags, COM_HW_FIFO); 413 goto fifodelay; 414 } 415 416 sc->sc_fifolen = 1; 417 /* look for a NS 16550AF UART with FIFOs */ 418 CSR_WRITE_1(regsp, COM_REG_FIFO, 419 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 420 delay(100); 421 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 422 == IIR_FIFO_MASK) 423 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 424 == FIFO_TRIGGER_14) { 425 SET(sc->sc_hwflags, COM_HW_FIFO); 426 427 #ifdef COM_16650 428 /* 429 * IIR changes into the EFR if LCR is set to LCR_EERS 430 * on 16650s. We also know IIR != 0 at this point. 431 * Write 0 into the EFR, and read it. If the result 432 * is 0, we have a 16650. 433 * 434 * Older 16650s were broken; the test to detect them 435 * is taken from the Linux driver. Apparently 436 * setting DLAB enable gives access to the EFR on 437 * these chips. 438 */ 439 lcr = CSR_READ_1(regsp, COM_REG_LCR); 440 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 441 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 442 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 443 CSR_WRITE_1(regsp, COM_REG_LCR, 444 lcr | LCR_DLAB); 445 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 446 CLR(sc->sc_hwflags, COM_HW_FIFO); 447 sc->sc_fifolen = 0; 448 } else { 449 SET(sc->sc_hwflags, COM_HW_FLOW); 450 sc->sc_fifolen = 32; 451 } 452 } else 453 #endif 454 sc->sc_fifolen = 16; 455 456 #ifdef COM_16650 457 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 458 if (sc->sc_fifolen == 0) 459 fifo_msg = "st16650, broken fifo"; 460 else if (sc->sc_fifolen == 32) 461 fifo_msg = "st16650a, working fifo"; 462 else 463 #endif 464 fifo_msg = "ns16550a, working fifo"; 465 } else 466 fifo_msg = "ns16550, broken fifo"; 467 else 468 fifo_msg = "ns8250 or ns16450, no fifo"; 469 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 470 fifodelay: 471 /* 472 * Some chips will clear down both Tx and Rx FIFOs when zero is 473 * written to com_fifo. If this chip is the console, writing zero 474 * results in some of the chip/FIFO description being lost, so delay 475 * printing it until now. 476 */ 477 delay(10); 478 aprint_normal(": %s\n", fifo_msg); 479 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 480 sc->sc_fifolen = 1; 481 aprint_normal("%s: txfifo disabled\n", sc->sc_dev.dv_xname); 482 } 483 484 fifodone: 485 486 tp = ttymalloc(); 487 tp->t_oproc = comstart; 488 tp->t_param = comparam; 489 tp->t_hwiflow = comhwiflow; 490 491 sc->sc_tty = tp; 492 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 493 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 494 sc->sc_rbavail = com_rbuf_size; 495 if (sc->sc_rbuf == NULL) { 496 aprint_error("%s: unable to allocate ring buffer\n", 497 sc->sc_dev.dv_xname); 498 return; 499 } 500 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 501 502 tty_attach(tp); 503 504 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 505 SET(sc->sc_mcr, MCR_IENABLE); 506 507 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 508 int maj; 509 510 /* locate the major number */ 511 maj = cdevsw_lookup_major(&com_cdevsw); 512 513 tp->t_dev = cn_tab->cn_dev = makedev(maj, 514 device_unit(&sc->sc_dev)); 515 516 aprint_normal("%s: console\n", sc->sc_dev.dv_xname); 517 } 518 519 #ifdef KGDB 520 /* 521 * Allow kgdb to "take over" this port. If this is 522 * not the console and is the kgdb device, it has 523 * exclusive use. If it's the console _and_ the 524 * kgdb device, it doesn't. 525 */ 526 if (regsp->cr_iot == comkgdbregs.cr_iot && 527 regsp->cr_iobase == comkgdbregs.cr_iobase) { 528 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 529 com_kgdb_attached = 1; 530 531 SET(sc->sc_hwflags, COM_HW_KGDB); 532 } 533 aprint_normal("%s: kgdb\n", sc->sc_dev.dv_xname); 534 } 535 #endif 536 537 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 538 539 #if NRND > 0 && defined(RND_COM) 540 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 541 RND_TYPE_TTY, 0); 542 #endif 543 544 /* if there are no enable/disable functions, assume the device 545 is always enabled */ 546 if (!sc->enable) 547 sc->enabled = 1; 548 549 com_config(sc); 550 551 SET(sc->sc_hwflags, COM_HW_DEV_OK); 552 } 553 554 void 555 com_config(struct com_softc *sc) 556 { 557 struct com_regs *regsp = &sc->sc_regs; 558 559 /* Disable interrupts before configuring the device. */ 560 if (sc->sc_type == COM_TYPE_PXA2x0) 561 sc->sc_ier = IER_EUART; 562 else 563 sc->sc_ier = 0; 564 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 565 (void) CSR_READ_1(regsp, COM_REG_IIR); 566 567 #ifdef COM_HAYESP 568 /* Look for a Hayes ESP board. */ 569 if (sc->sc_type == COM_TYPE_HAYESP) { 570 571 /* Set 16550 compatibility mode */ 572 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 573 HAYESP_SETMODE); 574 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 575 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 576 HAYESP_MODE_SCALE); 577 578 /* Set RTS/CTS flow control */ 579 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 580 HAYESP_SETFLOWTYPE); 581 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 582 HAYESP_FLOW_RTS); 583 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 584 HAYESP_FLOW_CTS); 585 586 /* Set flow control levels */ 587 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 588 HAYESP_SETRXFLOW); 589 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 590 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 591 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 592 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 593 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 594 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 595 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 596 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 597 } 598 #endif 599 600 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 601 com_enable_debugport(sc); 602 } 603 604 int 605 com_detach(struct device *self, int flags) 606 { 607 struct com_softc *sc = (struct com_softc *)self; 608 int maj, mn; 609 610 /* locate the major number */ 611 maj = cdevsw_lookup_major(&com_cdevsw); 612 613 /* Nuke the vnodes for any open instances. */ 614 mn = device_unit(self); 615 vdevgone(maj, mn, mn, VCHR); 616 617 mn |= COMDIALOUT_MASK; 618 vdevgone(maj, mn, mn, VCHR); 619 620 if (sc->sc_rbuf == NULL) { 621 /* 622 * Ring buffer allocation failed in the com_attach_subr, 623 * only the tty is allocated, and nothing else. 624 */ 625 ttyfree(sc->sc_tty); 626 return 0; 627 } 628 629 /* Free the receive buffer. */ 630 free(sc->sc_rbuf, M_DEVBUF); 631 632 /* Detach and free the tty. */ 633 tty_detach(sc->sc_tty); 634 ttyfree(sc->sc_tty); 635 636 /* Unhook the soft interrupt handler. */ 637 softint_disestablish(sc->sc_si); 638 639 #if NRND > 0 && defined(RND_COM) 640 /* Unhook the entropy source. */ 641 rnd_detach_source(&sc->rnd_source); 642 #endif 643 644 return (0); 645 } 646 647 int 648 com_activate(struct device *self, enum devact act) 649 { 650 struct com_softc *sc = (struct com_softc *)self; 651 int rv = 0; 652 653 mutex_spin_enter(&sc->sc_lock); 654 switch (act) { 655 case DVACT_ACTIVATE: 656 rv = EOPNOTSUPP; 657 break; 658 659 case DVACT_DEACTIVATE: 660 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 661 rv = EBUSY; 662 break; 663 } 664 665 if (sc->disable != NULL && sc->enabled != 0) { 666 (*sc->disable)(sc); 667 sc->enabled = 0; 668 } 669 break; 670 } 671 672 mutex_spin_exit(&sc->sc_lock); 673 return (rv); 674 } 675 676 void 677 com_shutdown(struct com_softc *sc) 678 { 679 struct tty *tp = sc->sc_tty; 680 681 mutex_spin_enter(&sc->sc_lock); 682 683 /* If we were asserting flow control, then deassert it. */ 684 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 685 com_hwiflow(sc); 686 687 /* Clear any break condition set with TIOCSBRK. */ 688 com_break(sc, 0); 689 690 #ifndef __HAVE_TIMECOUNTER 691 /* Turn off PPS capture on last close. */ 692 sc->sc_ppsmask = 0; 693 sc->ppsparam.mode = 0; 694 #endif /* !__HAVE_TIMECOUNTER */ 695 696 /* 697 * Hang up if necessary. Wait a bit, so the other side has time to 698 * notice even if we immediately open the port again. 699 * Avoid tsleeping above splhigh(). 700 */ 701 if (ISSET(tp->t_cflag, HUPCL)) { 702 com_modem(sc, 0); 703 mutex_spin_exit(&sc->sc_lock); 704 /* XXX will only timeout */ 705 (void) kpause(ttclos, false, hz, NULL); 706 mutex_spin_enter(&sc->sc_lock); 707 } 708 709 /* Turn off interrupts. */ 710 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 711 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 712 if (sc->sc_type == COM_TYPE_PXA2x0) 713 sc->sc_ier |= IER_ERXTOUT; 714 } else 715 sc->sc_ier = 0; 716 717 if (sc->sc_type == COM_TYPE_PXA2x0) 718 sc->sc_ier |= IER_EUART; 719 720 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 721 722 if (sc->disable) { 723 #ifdef DIAGNOSTIC 724 if (!sc->enabled) 725 panic("com_shutdown: not enabled?"); 726 #endif 727 (*sc->disable)(sc); 728 sc->enabled = 0; 729 } 730 mutex_spin_exit(&sc->sc_lock); 731 } 732 733 int 734 comopen(dev_t dev, int flag, int mode, struct lwp *l) 735 { 736 struct com_softc *sc; 737 struct tty *tp; 738 int s; 739 int error; 740 741 sc = device_lookup(&com_cd, COMUNIT(dev)); 742 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 743 sc->sc_rbuf == NULL) 744 return (ENXIO); 745 746 if (!device_is_active(&sc->sc_dev)) 747 return (ENXIO); 748 749 #ifdef KGDB 750 /* 751 * If this is the kgdb port, no other use is permitted. 752 */ 753 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 754 return (EBUSY); 755 #endif 756 757 tp = sc->sc_tty; 758 759 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 760 return (EBUSY); 761 762 s = spltty(); 763 764 /* 765 * Do the following iff this is a first open. 766 */ 767 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 768 struct termios t; 769 770 tp->t_dev = dev; 771 772 mutex_spin_enter(&sc->sc_lock); 773 774 if (sc->enable) { 775 if ((*sc->enable)(sc)) { 776 mutex_spin_exit(&sc->sc_lock); 777 splx(s); 778 printf("%s: device enable failed\n", 779 sc->sc_dev.dv_xname); 780 return (EIO); 781 } 782 sc->enabled = 1; 783 com_config(sc); 784 } 785 786 /* Turn on interrupts. */ 787 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 788 if (sc->sc_type == COM_TYPE_PXA2x0) 789 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 790 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 791 792 /* Fetch the current modem control status, needed later. */ 793 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 794 795 /* Clear PPS capture state on first open. */ 796 #ifdef __HAVE_TIMECOUNTER 797 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 798 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 799 pps_init(&sc->sc_pps_state); 800 #else /* !__HAVE_TIMECOUNTER */ 801 sc->sc_ppsmask = 0; 802 sc->ppsparam.mode = 0; 803 #endif /* !__HAVE_TIMECOUNTER */ 804 805 mutex_spin_exit(&sc->sc_lock); 806 807 /* 808 * Initialize the termios status to the defaults. Add in the 809 * sticky bits from TIOCSFLAGS. 810 */ 811 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 812 t.c_ospeed = comconsrate; 813 t.c_cflag = comconscflag; 814 } else { 815 t.c_ospeed = TTYDEF_SPEED; 816 t.c_cflag = TTYDEF_CFLAG; 817 } 818 t.c_ispeed = t.c_ospeed; 819 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 820 SET(t.c_cflag, CLOCAL); 821 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 822 SET(t.c_cflag, CRTSCTS); 823 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 824 SET(t.c_cflag, MDMBUF); 825 /* Make sure comparam() will do something. */ 826 tp->t_ospeed = 0; 827 (void) comparam(tp, &t); 828 tp->t_iflag = TTYDEF_IFLAG; 829 tp->t_oflag = TTYDEF_OFLAG; 830 tp->t_lflag = TTYDEF_LFLAG; 831 ttychars(tp); 832 ttsetwater(tp); 833 834 mutex_spin_enter(&sc->sc_lock); 835 836 /* 837 * Turn on DTR. We must always do this, even if carrier is not 838 * present, because otherwise we'd have to use TIOCSDTR 839 * immediately after setting CLOCAL, which applications do not 840 * expect. We always assert DTR while the device is open 841 * unless explicitly requested to deassert it. 842 */ 843 com_modem(sc, 1); 844 845 /* Clear the input ring, and unblock. */ 846 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 847 sc->sc_rbavail = com_rbuf_size; 848 com_iflush(sc); 849 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 850 com_hwiflow(sc); 851 852 #ifdef COM_DEBUG 853 if (com_debug) 854 comstatus(sc, "comopen "); 855 #endif 856 857 mutex_spin_exit(&sc->sc_lock); 858 } 859 860 splx(s); 861 862 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 863 if (error) 864 goto bad; 865 866 error = (*tp->t_linesw->l_open)(dev, tp); 867 if (error) 868 goto bad; 869 870 return (0); 871 872 bad: 873 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 874 /* 875 * We failed to open the device, and nobody else had it opened. 876 * Clean up the state as appropriate. 877 */ 878 com_shutdown(sc); 879 } 880 881 return (error); 882 } 883 884 int 885 comclose(dev_t dev, int flag, int mode, struct lwp *l) 886 { 887 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 888 struct tty *tp = sc->sc_tty; 889 890 /* XXX This is for cons.c. */ 891 if (!ISSET(tp->t_state, TS_ISOPEN)) 892 return (0); 893 894 (*tp->t_linesw->l_close)(tp, flag); 895 ttyclose(tp); 896 897 if (COM_ISALIVE(sc) == 0) 898 return (0); 899 900 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 901 /* 902 * Although we got a last close, the device may still be in 903 * use; e.g. if this was the dialout node, and there are still 904 * processes waiting for carrier on the non-dialout node. 905 */ 906 com_shutdown(sc); 907 } 908 909 return (0); 910 } 911 912 int 913 comread(dev_t dev, struct uio *uio, int flag) 914 { 915 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 916 struct tty *tp = sc->sc_tty; 917 918 if (COM_ISALIVE(sc) == 0) 919 return (EIO); 920 921 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 922 } 923 924 int 925 comwrite(dev_t dev, struct uio *uio, int flag) 926 { 927 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 928 struct tty *tp = sc->sc_tty; 929 930 if (COM_ISALIVE(sc) == 0) 931 return (EIO); 932 933 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 934 } 935 936 int 937 compoll(dev_t dev, int events, struct lwp *l) 938 { 939 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 940 struct tty *tp = sc->sc_tty; 941 942 if (COM_ISALIVE(sc) == 0) 943 return (POLLHUP); 944 945 return ((*tp->t_linesw->l_poll)(tp, events, l)); 946 } 947 948 struct tty * 949 comtty(dev_t dev) 950 { 951 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 952 struct tty *tp = sc->sc_tty; 953 954 return (tp); 955 } 956 957 int 958 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 959 { 960 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(dev)); 961 struct tty *tp = sc->sc_tty; 962 int error; 963 964 if (COM_ISALIVE(sc) == 0) 965 return (EIO); 966 967 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 968 if (error != EPASSTHROUGH) 969 return (error); 970 971 error = ttioctl(tp, cmd, data, flag, l); 972 if (error != EPASSTHROUGH) 973 return (error); 974 975 error = 0; 976 switch (cmd) { 977 case TIOCSFLAGS: 978 error = kauth_authorize_device_tty(l->l_cred, 979 KAUTH_DEVICE_TTY_PRIVSET, tp); 980 break; 981 default: 982 /* nothing */ 983 break; 984 } 985 if (error) { 986 return error; 987 } 988 989 mutex_spin_enter(&sc->sc_lock); 990 991 switch (cmd) { 992 case TIOCSBRK: 993 com_break(sc, 1); 994 break; 995 996 case TIOCCBRK: 997 com_break(sc, 0); 998 break; 999 1000 case TIOCSDTR: 1001 com_modem(sc, 1); 1002 break; 1003 1004 case TIOCCDTR: 1005 com_modem(sc, 0); 1006 break; 1007 1008 case TIOCGFLAGS: 1009 *(int *)data = sc->sc_swflags; 1010 break; 1011 1012 case TIOCSFLAGS: 1013 sc->sc_swflags = *(int *)data; 1014 break; 1015 1016 case TIOCMSET: 1017 case TIOCMBIS: 1018 case TIOCMBIC: 1019 tiocm_to_com(sc, cmd, *(int *)data); 1020 break; 1021 1022 case TIOCMGET: 1023 *(int *)data = com_to_tiocm(sc); 1024 break; 1025 1026 #ifdef __HAVE_TIMECOUNTER 1027 case PPS_IOC_CREATE: 1028 case PPS_IOC_DESTROY: 1029 case PPS_IOC_GETPARAMS: 1030 case PPS_IOC_SETPARAMS: 1031 case PPS_IOC_GETCAP: 1032 case PPS_IOC_FETCH: 1033 #ifdef PPS_SYNC 1034 case PPS_IOC_KCBIND: 1035 #endif 1036 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1037 break; 1038 #else /* !__HAVE_TIMECOUNTER */ 1039 case PPS_IOC_CREATE: 1040 break; 1041 1042 case PPS_IOC_DESTROY: 1043 break; 1044 1045 case PPS_IOC_GETPARAMS: { 1046 pps_params_t *pp; 1047 pp = (pps_params_t *)data; 1048 *pp = sc->ppsparam; 1049 break; 1050 } 1051 1052 case PPS_IOC_SETPARAMS: { 1053 pps_params_t *pp; 1054 int mode; 1055 pp = (pps_params_t *)data; 1056 if (pp->mode & ~ppscap) { 1057 error = EINVAL; 1058 break; 1059 } 1060 sc->ppsparam = *pp; 1061 /* 1062 * Compute msr masks from user-specified timestamp state. 1063 */ 1064 mode = sc->ppsparam.mode; 1065 switch (mode & PPS_CAPTUREBOTH) { 1066 case 0: 1067 sc->sc_ppsmask = 0; 1068 break; 1069 1070 case PPS_CAPTUREASSERT: 1071 sc->sc_ppsmask = MSR_DCD; 1072 sc->sc_ppsassert = MSR_DCD; 1073 sc->sc_ppsclear = -1; 1074 break; 1075 1076 case PPS_CAPTURECLEAR: 1077 sc->sc_ppsmask = MSR_DCD; 1078 sc->sc_ppsassert = -1; 1079 sc->sc_ppsclear = 0; 1080 break; 1081 1082 case PPS_CAPTUREBOTH: 1083 sc->sc_ppsmask = MSR_DCD; 1084 sc->sc_ppsassert = MSR_DCD; 1085 sc->sc_ppsclear = 0; 1086 break; 1087 1088 default: 1089 error = EINVAL; 1090 break; 1091 } 1092 break; 1093 } 1094 1095 case PPS_IOC_GETCAP: 1096 *(int*)data = ppscap; 1097 break; 1098 1099 case PPS_IOC_FETCH: { 1100 pps_info_t *pi; 1101 pi = (pps_info_t *)data; 1102 *pi = sc->ppsinfo; 1103 break; 1104 } 1105 1106 #ifdef PPS_SYNC 1107 case PPS_IOC_KCBIND: { 1108 int edge = (*(int *)data) & PPS_CAPTUREBOTH; 1109 1110 if (edge == 0) { 1111 /* 1112 * remove binding for this source; ignore 1113 * the request if this is not the current 1114 * hardpps source 1115 */ 1116 if (pps_kc_hardpps_source == sc) { 1117 pps_kc_hardpps_source = NULL; 1118 pps_kc_hardpps_mode = 0; 1119 } 1120 } else { 1121 /* 1122 * bind hardpps to this source, replacing any 1123 * previously specified source or edges 1124 */ 1125 pps_kc_hardpps_source = sc; 1126 pps_kc_hardpps_mode = edge; 1127 } 1128 break; 1129 } 1130 #endif /* PPS_SYNC */ 1131 #endif /* !__HAVE_TIMECOUNTER */ 1132 1133 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1134 #ifdef __HAVE_TIMECOUNTER 1135 #ifndef PPS_TRAILING_EDGE 1136 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1137 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1138 #else 1139 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1140 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1141 #endif 1142 #else /* !__HAVE_TIMECOUNTER */ 1143 /* 1144 * Some GPS clocks models use the falling rather than 1145 * rising edge as the on-the-second signal. 1146 * The old API has no way to specify PPS polarity. 1147 */ 1148 sc->sc_ppsmask = MSR_DCD; 1149 #ifndef PPS_TRAILING_EDGE 1150 sc->sc_ppsassert = MSR_DCD; 1151 sc->sc_ppsclear = -1; 1152 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1153 &sc->ppsinfo.assert_timestamp); 1154 #else 1155 sc->sc_ppsassert = -1; 1156 sc->sc_ppsclear = 0; 1157 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1158 &sc->ppsinfo.clear_timestamp); 1159 #endif 1160 #endif /* !__HAVE_TIMECOUNTER */ 1161 break; 1162 1163 default: 1164 error = EPASSTHROUGH; 1165 break; 1166 } 1167 1168 mutex_spin_exit(&sc->sc_lock); 1169 1170 #ifdef COM_DEBUG 1171 if (com_debug) 1172 comstatus(sc, "comioctl "); 1173 #endif 1174 1175 return (error); 1176 } 1177 1178 integrate void 1179 com_schedrx(struct com_softc *sc) 1180 { 1181 1182 sc->sc_rx_ready = 1; 1183 1184 /* Wake up the poller. */ 1185 softint_schedule(sc->sc_si); 1186 } 1187 1188 void 1189 com_break(struct com_softc *sc, int onoff) 1190 { 1191 1192 if (onoff) 1193 SET(sc->sc_lcr, LCR_SBREAK); 1194 else 1195 CLR(sc->sc_lcr, LCR_SBREAK); 1196 1197 if (!sc->sc_heldchange) { 1198 if (sc->sc_tx_busy) { 1199 sc->sc_heldtbc = sc->sc_tbc; 1200 sc->sc_tbc = 0; 1201 sc->sc_heldchange = 1; 1202 } else 1203 com_loadchannelregs(sc); 1204 } 1205 } 1206 1207 void 1208 com_modem(struct com_softc *sc, int onoff) 1209 { 1210 1211 if (sc->sc_mcr_dtr == 0) 1212 return; 1213 1214 if (onoff) 1215 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1216 else 1217 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1218 1219 if (!sc->sc_heldchange) { 1220 if (sc->sc_tx_busy) { 1221 sc->sc_heldtbc = sc->sc_tbc; 1222 sc->sc_tbc = 0; 1223 sc->sc_heldchange = 1; 1224 } else 1225 com_loadchannelregs(sc); 1226 } 1227 } 1228 1229 void 1230 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1231 { 1232 u_char combits; 1233 1234 combits = 0; 1235 if (ISSET(ttybits, TIOCM_DTR)) 1236 SET(combits, MCR_DTR); 1237 if (ISSET(ttybits, TIOCM_RTS)) 1238 SET(combits, MCR_RTS); 1239 1240 switch (how) { 1241 case TIOCMBIC: 1242 CLR(sc->sc_mcr, combits); 1243 break; 1244 1245 case TIOCMBIS: 1246 SET(sc->sc_mcr, combits); 1247 break; 1248 1249 case TIOCMSET: 1250 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1251 SET(sc->sc_mcr, combits); 1252 break; 1253 } 1254 1255 if (!sc->sc_heldchange) { 1256 if (sc->sc_tx_busy) { 1257 sc->sc_heldtbc = sc->sc_tbc; 1258 sc->sc_tbc = 0; 1259 sc->sc_heldchange = 1; 1260 } else 1261 com_loadchannelregs(sc); 1262 } 1263 } 1264 1265 int 1266 com_to_tiocm(struct com_softc *sc) 1267 { 1268 u_char combits; 1269 int ttybits = 0; 1270 1271 combits = sc->sc_mcr; 1272 if (ISSET(combits, MCR_DTR)) 1273 SET(ttybits, TIOCM_DTR); 1274 if (ISSET(combits, MCR_RTS)) 1275 SET(ttybits, TIOCM_RTS); 1276 1277 combits = sc->sc_msr; 1278 if (ISSET(combits, MSR_DCD)) 1279 SET(ttybits, TIOCM_CD); 1280 if (ISSET(combits, MSR_CTS)) 1281 SET(ttybits, TIOCM_CTS); 1282 if (ISSET(combits, MSR_DSR)) 1283 SET(ttybits, TIOCM_DSR); 1284 if (ISSET(combits, MSR_RI | MSR_TERI)) 1285 SET(ttybits, TIOCM_RI); 1286 1287 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1288 SET(ttybits, TIOCM_LE); 1289 1290 return (ttybits); 1291 } 1292 1293 static u_char 1294 cflag2lcr(tcflag_t cflag) 1295 { 1296 u_char lcr = 0; 1297 1298 switch (ISSET(cflag, CSIZE)) { 1299 case CS5: 1300 SET(lcr, LCR_5BITS); 1301 break; 1302 case CS6: 1303 SET(lcr, LCR_6BITS); 1304 break; 1305 case CS7: 1306 SET(lcr, LCR_7BITS); 1307 break; 1308 case CS8: 1309 SET(lcr, LCR_8BITS); 1310 break; 1311 } 1312 if (ISSET(cflag, PARENB)) { 1313 SET(lcr, LCR_PENAB); 1314 if (!ISSET(cflag, PARODD)) 1315 SET(lcr, LCR_PEVEN); 1316 } 1317 if (ISSET(cflag, CSTOPB)) 1318 SET(lcr, LCR_STOPB); 1319 1320 return (lcr); 1321 } 1322 1323 int 1324 comparam(struct tty *tp, struct termios *t) 1325 { 1326 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1327 int ospeed; 1328 u_char lcr; 1329 1330 if (COM_ISALIVE(sc) == 0) 1331 return (EIO); 1332 1333 #ifdef COM_HAYESP 1334 if (sc->sc_type == COM_TYPE_HAYESP) { 1335 int prescaler, speed; 1336 1337 /* 1338 * Calculate UART clock prescaler. It should be in 1339 * range of 0 .. 3. 1340 */ 1341 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1342 prescaler++, speed /= 2) 1343 if ((ospeed = comspeed(speed, sc->sc_frequency, 1344 sc->sc_type)) > 0) 1345 break; 1346 1347 if (prescaler == 4) 1348 return (EINVAL); 1349 sc->sc_prescaler = prescaler; 1350 } else 1351 #endif 1352 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1353 1354 /* Check requested parameters. */ 1355 if (ospeed < 0) 1356 return (EINVAL); 1357 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1358 return (EINVAL); 1359 1360 /* 1361 * For the console, always force CLOCAL and !HUPCL, so that the port 1362 * is always active. 1363 */ 1364 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1365 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1366 SET(t->c_cflag, CLOCAL); 1367 CLR(t->c_cflag, HUPCL); 1368 } 1369 1370 /* 1371 * If there were no changes, don't do anything. This avoids dropping 1372 * input and improves performance when all we did was frob things like 1373 * VMIN and VTIME. 1374 */ 1375 if (tp->t_ospeed == t->c_ospeed && 1376 tp->t_cflag == t->c_cflag) 1377 return (0); 1378 1379 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1380 1381 mutex_spin_enter(&sc->sc_lock); 1382 1383 sc->sc_lcr = lcr; 1384 1385 /* 1386 * If we're not in a mode that assumes a connection is present, then 1387 * ignore carrier changes. 1388 */ 1389 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1390 sc->sc_msr_dcd = 0; 1391 else 1392 sc->sc_msr_dcd = MSR_DCD; 1393 /* 1394 * Set the flow control pins depending on the current flow control 1395 * mode. 1396 */ 1397 if (ISSET(t->c_cflag, CRTSCTS)) { 1398 sc->sc_mcr_dtr = MCR_DTR; 1399 sc->sc_mcr_rts = MCR_RTS; 1400 sc->sc_msr_cts = MSR_CTS; 1401 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1402 } else if (ISSET(t->c_cflag, MDMBUF)) { 1403 /* 1404 * For DTR/DCD flow control, make sure we don't toggle DTR for 1405 * carrier detection. 1406 */ 1407 sc->sc_mcr_dtr = 0; 1408 sc->sc_mcr_rts = MCR_DTR; 1409 sc->sc_msr_cts = MSR_DCD; 1410 sc->sc_efr = 0; 1411 } else { 1412 /* 1413 * If no flow control, then always set RTS. This will make 1414 * the other side happy if it mistakenly thinks we're doing 1415 * RTS/CTS flow control. 1416 */ 1417 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1418 sc->sc_mcr_rts = 0; 1419 sc->sc_msr_cts = 0; 1420 sc->sc_efr = 0; 1421 if (ISSET(sc->sc_mcr, MCR_DTR)) 1422 SET(sc->sc_mcr, MCR_RTS); 1423 else 1424 CLR(sc->sc_mcr, MCR_RTS); 1425 } 1426 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1427 1428 #if 0 1429 if (ospeed == 0) 1430 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1431 else 1432 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1433 #endif 1434 1435 sc->sc_dlbl = ospeed; 1436 sc->sc_dlbh = ospeed >> 8; 1437 1438 /* 1439 * Set the FIFO threshold based on the receive speed. 1440 * 1441 * * If it's a low speed, it's probably a mouse or some other 1442 * interactive device, so set the threshold low. 1443 * * If it's a high speed, trim the trigger level down to prevent 1444 * overflows. 1445 * * Otherwise set it a bit higher. 1446 */ 1447 if (sc->sc_type == COM_TYPE_HAYESP) 1448 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1449 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 1450 sc->sc_fifo = FIFO_ENABLE | 1451 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8); 1452 else 1453 sc->sc_fifo = 0; 1454 1455 /* And copy to tty. */ 1456 tp->t_ispeed = t->c_ospeed; 1457 tp->t_ospeed = t->c_ospeed; 1458 tp->t_cflag = t->c_cflag; 1459 1460 if (!sc->sc_heldchange) { 1461 if (sc->sc_tx_busy) { 1462 sc->sc_heldtbc = sc->sc_tbc; 1463 sc->sc_tbc = 0; 1464 sc->sc_heldchange = 1; 1465 } else 1466 com_loadchannelregs(sc); 1467 } 1468 1469 if (!ISSET(t->c_cflag, CHWFLOW)) { 1470 /* Disable the high water mark. */ 1471 sc->sc_r_hiwat = 0; 1472 sc->sc_r_lowat = 0; 1473 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1474 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1475 com_schedrx(sc); 1476 } 1477 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1478 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1479 com_hwiflow(sc); 1480 } 1481 } else { 1482 sc->sc_r_hiwat = com_rbuf_hiwat; 1483 sc->sc_r_lowat = com_rbuf_lowat; 1484 } 1485 1486 mutex_spin_exit(&sc->sc_lock); 1487 1488 /* 1489 * Update the tty layer's idea of the carrier bit, in case we changed 1490 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1491 * explicit request. 1492 */ 1493 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1494 1495 #ifdef COM_DEBUG 1496 if (com_debug) 1497 comstatus(sc, "comparam "); 1498 #endif 1499 1500 if (!ISSET(t->c_cflag, CHWFLOW)) { 1501 if (sc->sc_tx_stopped) { 1502 sc->sc_tx_stopped = 0; 1503 comstart(tp); 1504 } 1505 } 1506 1507 return (0); 1508 } 1509 1510 void 1511 com_iflush(struct com_softc *sc) 1512 { 1513 struct com_regs *regsp = &sc->sc_regs; 1514 #ifdef DIAGNOSTIC 1515 int reg; 1516 #endif 1517 int timo; 1518 1519 #ifdef DIAGNOSTIC 1520 reg = 0xffff; 1521 #endif 1522 timo = 50000; 1523 /* flush any pending I/O */ 1524 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1525 && --timo) 1526 #ifdef DIAGNOSTIC 1527 reg = 1528 #else 1529 (void) 1530 #endif 1531 CSR_READ_1(regsp, COM_REG_RXDATA); 1532 #ifdef DIAGNOSTIC 1533 if (!timo) 1534 printf("%s: com_iflush timeout %02x\n", sc->sc_dev.dv_xname, 1535 reg); 1536 #endif 1537 } 1538 1539 void 1540 com_loadchannelregs(struct com_softc *sc) 1541 { 1542 struct com_regs *regsp = &sc->sc_regs; 1543 1544 /* XXXXX necessary? */ 1545 com_iflush(sc); 1546 1547 if (sc->sc_type == COM_TYPE_PXA2x0) 1548 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1549 else 1550 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1551 1552 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1553 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1554 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1555 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1556 } 1557 } 1558 if (sc->sc_type == COM_TYPE_AU1x00) { 1559 /* alchemy has single separate 16-bit clock divisor register */ 1560 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1561 (sc->sc_dlbh << 8)); 1562 } else { 1563 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1564 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1565 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1566 } 1567 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1568 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1569 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1570 #ifdef COM_HAYESP 1571 if (sc->sc_type == COM_TYPE_HAYESP) { 1572 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1573 HAYESP_SETPRESCALER); 1574 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1575 sc->sc_prescaler); 1576 } 1577 #endif 1578 1579 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1580 } 1581 1582 int 1583 comhwiflow(struct tty *tp, int block) 1584 { 1585 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1586 1587 if (COM_ISALIVE(sc) == 0) 1588 return (0); 1589 1590 if (sc->sc_mcr_rts == 0) 1591 return (0); 1592 1593 mutex_spin_enter(&sc->sc_lock); 1594 1595 if (block) { 1596 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1597 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1598 com_hwiflow(sc); 1599 } 1600 } else { 1601 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1602 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1603 com_schedrx(sc); 1604 } 1605 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1606 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1607 com_hwiflow(sc); 1608 } 1609 } 1610 1611 mutex_spin_exit(&sc->sc_lock); 1612 return (1); 1613 } 1614 1615 /* 1616 * (un)block input via hw flowcontrol 1617 */ 1618 void 1619 com_hwiflow(struct com_softc *sc) 1620 { 1621 struct com_regs *regsp= &sc->sc_regs; 1622 1623 if (sc->sc_mcr_rts == 0) 1624 return; 1625 1626 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1627 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1628 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1629 } else { 1630 SET(sc->sc_mcr, sc->sc_mcr_rts); 1631 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1632 } 1633 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1634 } 1635 1636 1637 void 1638 comstart(struct tty *tp) 1639 { 1640 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1641 struct com_regs *regsp = &sc->sc_regs; 1642 int s; 1643 1644 if (COM_ISALIVE(sc) == 0) 1645 return; 1646 1647 s = spltty(); 1648 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1649 goto out; 1650 if (sc->sc_tx_stopped) 1651 goto out; 1652 if (!ttypull(tp)) 1653 goto out; 1654 1655 /* Grab the first contiguous region of buffer space. */ 1656 { 1657 u_char *tba; 1658 int tbc; 1659 1660 tba = tp->t_outq.c_cf; 1661 tbc = ndqb(&tp->t_outq, 0); 1662 1663 mutex_spin_enter(&sc->sc_lock); 1664 1665 sc->sc_tba = tba; 1666 sc->sc_tbc = tbc; 1667 } 1668 1669 SET(tp->t_state, TS_BUSY); 1670 sc->sc_tx_busy = 1; 1671 1672 /* Enable transmit completion interrupts if necessary. */ 1673 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1674 SET(sc->sc_ier, IER_ETXRDY); 1675 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1676 } 1677 1678 /* Output the first chunk of the contiguous buffer. */ 1679 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1680 u_int n; 1681 1682 n = sc->sc_tbc; 1683 if (n > sc->sc_fifolen) 1684 n = sc->sc_fifolen; 1685 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1686 sc->sc_tbc -= n; 1687 sc->sc_tba += n; 1688 } 1689 1690 mutex_spin_exit(&sc->sc_lock); 1691 out: 1692 splx(s); 1693 return; 1694 } 1695 1696 /* 1697 * Stop output on a line. 1698 */ 1699 void 1700 comstop(struct tty *tp, int flag) 1701 { 1702 struct com_softc *sc = device_lookup(&com_cd, COMUNIT(tp->t_dev)); 1703 1704 mutex_spin_enter(&sc->sc_lock); 1705 if (ISSET(tp->t_state, TS_BUSY)) { 1706 /* Stop transmitting at the next chunk. */ 1707 sc->sc_tbc = 0; 1708 sc->sc_heldtbc = 0; 1709 if (!ISSET(tp->t_state, TS_TTSTOP)) 1710 SET(tp->t_state, TS_FLUSH); 1711 } 1712 mutex_spin_exit(&sc->sc_lock); 1713 } 1714 1715 void 1716 comdiag(void *arg) 1717 { 1718 struct com_softc *sc = arg; 1719 int overflows, floods; 1720 1721 mutex_spin_enter(&sc->sc_lock); 1722 overflows = sc->sc_overflows; 1723 sc->sc_overflows = 0; 1724 floods = sc->sc_floods; 1725 sc->sc_floods = 0; 1726 sc->sc_errors = 0; 1727 mutex_spin_exit(&sc->sc_lock); 1728 1729 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1730 sc->sc_dev.dv_xname, 1731 overflows, overflows == 1 ? "" : "s", 1732 floods, floods == 1 ? "" : "s"); 1733 } 1734 1735 integrate void 1736 com_rxsoft(struct com_softc *sc, struct tty *tp) 1737 { 1738 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1739 u_char *get, *end; 1740 u_int cc, scc; 1741 u_char lsr; 1742 int code; 1743 1744 end = sc->sc_ebuf; 1745 get = sc->sc_rbget; 1746 scc = cc = com_rbuf_size - sc->sc_rbavail; 1747 1748 if (cc == com_rbuf_size) { 1749 sc->sc_floods++; 1750 if (sc->sc_errors++ == 0) 1751 callout_reset(&sc->sc_diag_callout, 60 * hz, 1752 comdiag, sc); 1753 } 1754 1755 /* If not yet open, drop the entire buffer content here */ 1756 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1757 get += cc << 1; 1758 if (get >= end) 1759 get -= com_rbuf_size << 1; 1760 cc = 0; 1761 } 1762 while (cc) { 1763 code = get[0]; 1764 lsr = get[1]; 1765 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1766 if (ISSET(lsr, LSR_OE)) { 1767 sc->sc_overflows++; 1768 if (sc->sc_errors++ == 0) 1769 callout_reset(&sc->sc_diag_callout, 1770 60 * hz, comdiag, sc); 1771 } 1772 if (ISSET(lsr, LSR_BI | LSR_FE)) 1773 SET(code, TTY_FE); 1774 if (ISSET(lsr, LSR_PE)) 1775 SET(code, TTY_PE); 1776 } 1777 if ((*rint)(code, tp) == -1) { 1778 /* 1779 * The line discipline's buffer is out of space. 1780 */ 1781 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1782 /* 1783 * We're either not using flow control, or the 1784 * line discipline didn't tell us to block for 1785 * some reason. Either way, we have no way to 1786 * know when there's more space available, so 1787 * just drop the rest of the data. 1788 */ 1789 get += cc << 1; 1790 if (get >= end) 1791 get -= com_rbuf_size << 1; 1792 cc = 0; 1793 } else { 1794 /* 1795 * Don't schedule any more receive processing 1796 * until the line discipline tells us there's 1797 * space available (through comhwiflow()). 1798 * Leave the rest of the data in the input 1799 * buffer. 1800 */ 1801 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1802 } 1803 break; 1804 } 1805 get += 2; 1806 if (get >= end) 1807 get = sc->sc_rbuf; 1808 cc--; 1809 } 1810 1811 if (cc != scc) { 1812 sc->sc_rbget = get; 1813 mutex_spin_enter(&sc->sc_lock); 1814 1815 cc = sc->sc_rbavail += scc - cc; 1816 /* Buffers should be ok again, release possible block. */ 1817 if (cc >= sc->sc_r_lowat) { 1818 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1819 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1820 SET(sc->sc_ier, IER_ERXRDY); 1821 #ifdef COM_PXA2X0 1822 if (sc->sc_type == COM_TYPE_PXA2x0) 1823 SET(sc->sc_ier, IER_ERXTOUT); 1824 #endif 1825 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1826 } 1827 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1828 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1829 com_hwiflow(sc); 1830 } 1831 } 1832 mutex_spin_exit(&sc->sc_lock); 1833 } 1834 } 1835 1836 integrate void 1837 com_txsoft(struct com_softc *sc, struct tty *tp) 1838 { 1839 1840 CLR(tp->t_state, TS_BUSY); 1841 if (ISSET(tp->t_state, TS_FLUSH)) 1842 CLR(tp->t_state, TS_FLUSH); 1843 else 1844 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1845 (*tp->t_linesw->l_start)(tp); 1846 } 1847 1848 integrate void 1849 com_stsoft(struct com_softc *sc, struct tty *tp) 1850 { 1851 u_char msr, delta; 1852 1853 mutex_spin_enter(&sc->sc_lock); 1854 msr = sc->sc_msr; 1855 delta = sc->sc_msr_delta; 1856 sc->sc_msr_delta = 0; 1857 mutex_spin_exit(&sc->sc_lock); 1858 1859 if (ISSET(delta, sc->sc_msr_dcd)) { 1860 /* 1861 * Inform the tty layer that carrier detect changed. 1862 */ 1863 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1864 } 1865 1866 if (ISSET(delta, sc->sc_msr_cts)) { 1867 /* Block or unblock output according to flow control. */ 1868 if (ISSET(msr, sc->sc_msr_cts)) { 1869 sc->sc_tx_stopped = 0; 1870 (*tp->t_linesw->l_start)(tp); 1871 } else { 1872 sc->sc_tx_stopped = 1; 1873 } 1874 } 1875 1876 #ifdef COM_DEBUG 1877 if (com_debug) 1878 comstatus(sc, "com_stsoft"); 1879 #endif 1880 } 1881 1882 void 1883 comsoft(void *arg) 1884 { 1885 struct com_softc *sc = arg; 1886 struct tty *tp; 1887 1888 if (COM_ISALIVE(sc) == 0) 1889 return; 1890 1891 tp = sc->sc_tty; 1892 1893 if (sc->sc_rx_ready) { 1894 sc->sc_rx_ready = 0; 1895 com_rxsoft(sc, tp); 1896 } 1897 1898 if (sc->sc_st_check) { 1899 sc->sc_st_check = 0; 1900 com_stsoft(sc, tp); 1901 } 1902 1903 if (sc->sc_tx_done) { 1904 sc->sc_tx_done = 0; 1905 com_txsoft(sc, tp); 1906 } 1907 } 1908 1909 int 1910 comintr(void *arg) 1911 { 1912 struct com_softc *sc = arg; 1913 struct com_regs *regsp = &sc->sc_regs; 1914 1915 u_char *put, *end; 1916 u_int cc; 1917 u_char lsr, iir; 1918 1919 if (COM_ISALIVE(sc) == 0) 1920 return (0); 1921 1922 mutex_spin_enter(&sc->sc_lock); 1923 iir = CSR_READ_1(regsp, COM_REG_IIR); 1924 if (ISSET(iir, IIR_NOPEND)) { 1925 mutex_spin_exit(&sc->sc_lock); 1926 return (0); 1927 } 1928 1929 end = sc->sc_ebuf; 1930 put = sc->sc_rbput; 1931 cc = sc->sc_rbavail; 1932 1933 again: do { 1934 u_char msr, delta; 1935 1936 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1937 if (ISSET(lsr, LSR_BI)) { 1938 int cn_trapped = 0; 1939 1940 cn_check_magic(sc->sc_tty->t_dev, 1941 CNC_BREAK, com_cnm_state); 1942 if (cn_trapped) 1943 continue; 1944 #if defined(KGDB) && !defined(DDB) 1945 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1946 kgdb_connect(1); 1947 continue; 1948 } 1949 #endif 1950 } 1951 1952 if (ISSET(lsr, LSR_RCV_MASK) && 1953 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1954 while (cc > 0) { 1955 int cn_trapped = 0; 1956 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1957 put[1] = lsr; 1958 cn_check_magic(sc->sc_tty->t_dev, 1959 put[0], com_cnm_state); 1960 if (cn_trapped) 1961 goto next; 1962 put += 2; 1963 if (put >= end) 1964 put = sc->sc_rbuf; 1965 cc--; 1966 next: 1967 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1968 if (!ISSET(lsr, LSR_RCV_MASK)) 1969 break; 1970 } 1971 1972 /* 1973 * Current string of incoming characters ended because 1974 * no more data was available or we ran out of space. 1975 * Schedule a receive event if any data was received. 1976 * If we're out of space, turn off receive interrupts. 1977 */ 1978 sc->sc_rbput = put; 1979 sc->sc_rbavail = cc; 1980 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1981 sc->sc_rx_ready = 1; 1982 1983 /* 1984 * See if we are in danger of overflowing a buffer. If 1985 * so, use hardware flow control to ease the pressure. 1986 */ 1987 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1988 cc < sc->sc_r_hiwat) { 1989 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1990 com_hwiflow(sc); 1991 } 1992 1993 /* 1994 * If we're out of space, disable receive interrupts 1995 * until the queue has drained a bit. 1996 */ 1997 if (!cc) { 1998 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1999 #ifdef COM_PXA2X0 2000 if (sc->sc_type == COM_TYPE_PXA2x0) 2001 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2002 else 2003 #endif 2004 CLR(sc->sc_ier, IER_ERXRDY); 2005 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2006 } 2007 } else { 2008 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2009 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2010 continue; 2011 } 2012 } 2013 2014 msr = CSR_READ_1(regsp, COM_REG_MSR); 2015 delta = msr ^ sc->sc_msr; 2016 sc->sc_msr = msr; 2017 #ifdef __HAVE_TIMECOUNTER 2018 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2019 (delta & MSR_DCD)) { 2020 pps_capture(&sc->sc_pps_state); 2021 pps_event(&sc->sc_pps_state, 2022 (msr & MSR_DCD) ? 2023 PPS_CAPTUREASSERT : 2024 PPS_CAPTURECLEAR); 2025 } 2026 #else /* !__HAVE_TIMECOUNTER */ 2027 /* 2028 * Pulse-per-second (PSS) signals on edge of DCD? 2029 * Process these even if line discipline is ignoring DCD. 2030 */ 2031 if (delta & sc->sc_ppsmask) { 2032 struct timeval tv; 2033 if ((msr & sc->sc_ppsmask) == sc->sc_ppsassert) { 2034 /* XXX nanotime() */ 2035 microtime(&tv); 2036 TIMEVAL_TO_TIMESPEC(&tv, 2037 &sc->ppsinfo.assert_timestamp); 2038 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 2039 timespecadd(&sc->ppsinfo.assert_timestamp, 2040 &sc->ppsparam.assert_offset, 2041 &sc->ppsinfo.assert_timestamp); 2042 } 2043 2044 #ifdef PPS_SYNC 2045 if (pps_kc_hardpps_source == sc && 2046 pps_kc_hardpps_mode & PPS_CAPTUREASSERT) { 2047 hardpps(&tv, tv.tv_usec); 2048 } 2049 #endif 2050 sc->ppsinfo.assert_sequence++; 2051 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2052 2053 } else if ((msr & sc->sc_ppsmask) == sc->sc_ppsclear) { 2054 /* XXX nanotime() */ 2055 microtime(&tv); 2056 TIMEVAL_TO_TIMESPEC(&tv, 2057 &sc->ppsinfo.clear_timestamp); 2058 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 2059 timespecadd(&sc->ppsinfo.clear_timestamp, 2060 &sc->ppsparam.clear_offset, 2061 &sc->ppsinfo.clear_timestamp); 2062 } 2063 2064 #ifdef PPS_SYNC 2065 if (pps_kc_hardpps_source == sc && 2066 pps_kc_hardpps_mode & PPS_CAPTURECLEAR) { 2067 hardpps(&tv, tv.tv_usec); 2068 } 2069 #endif 2070 sc->ppsinfo.clear_sequence++; 2071 sc->ppsinfo.current_mode = sc->ppsparam.mode; 2072 } 2073 } 2074 #endif /* !__HAVE_TIMECOUNTER */ 2075 2076 /* 2077 * Process normal status changes 2078 */ 2079 if (ISSET(delta, sc->sc_msr_mask)) { 2080 SET(sc->sc_msr_delta, delta); 2081 2082 /* 2083 * Stop output immediately if we lose the output 2084 * flow control signal or carrier detect. 2085 */ 2086 if (ISSET(~msr, sc->sc_msr_mask)) { 2087 sc->sc_tbc = 0; 2088 sc->sc_heldtbc = 0; 2089 #ifdef COM_DEBUG 2090 if (com_debug) 2091 comstatus(sc, "comintr "); 2092 #endif 2093 } 2094 2095 sc->sc_st_check = 1; 2096 } 2097 } while (!ISSET((iir = 2098 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2099 /* 2100 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2101 * by IIR read, so we can't do this way: `process all interrupts, 2102 * then do TX if possble'. 2103 */ 2104 (iir & IIR_IMASK) != IIR_TXRDY); 2105 2106 /* 2107 * Read LSR again, since there may be an interrupt between 2108 * the last LSR read and IIR read above. 2109 */ 2110 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2111 2112 /* 2113 * See if data can be transmitted as well. 2114 * Schedule tx done event if no data left 2115 * and tty was marked busy. 2116 */ 2117 if (ISSET(lsr, LSR_TXRDY)) { 2118 /* 2119 * If we've delayed a parameter change, do it now, and restart 2120 * output. 2121 */ 2122 if (sc->sc_heldchange) { 2123 com_loadchannelregs(sc); 2124 sc->sc_heldchange = 0; 2125 sc->sc_tbc = sc->sc_heldtbc; 2126 sc->sc_heldtbc = 0; 2127 } 2128 2129 /* Output the next chunk of the contiguous buffer, if any. */ 2130 if (sc->sc_tbc > 0) { 2131 u_int n; 2132 2133 n = sc->sc_tbc; 2134 if (n > sc->sc_fifolen) 2135 n = sc->sc_fifolen; 2136 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2137 sc->sc_tbc -= n; 2138 sc->sc_tba += n; 2139 } else { 2140 /* Disable transmit completion interrupts if necessary. */ 2141 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2142 CLR(sc->sc_ier, IER_ETXRDY); 2143 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2144 } 2145 if (sc->sc_tx_busy) { 2146 sc->sc_tx_busy = 0; 2147 sc->sc_tx_done = 1; 2148 } 2149 } 2150 } 2151 2152 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2153 goto again; 2154 2155 mutex_spin_exit(&sc->sc_lock); 2156 2157 /* Wake up the poller. */ 2158 softint_schedule(sc->sc_si); 2159 2160 #if NRND > 0 && defined(RND_COM) 2161 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2162 #endif 2163 2164 return (1); 2165 } 2166 2167 /* 2168 * The following functions are polled getc and putc routines, shared 2169 * by the console and kgdb glue. 2170 * 2171 * The read-ahead code is so that you can detect pending in-band 2172 * cn_magic in polled mode while doing output rather than having to 2173 * wait until the kernel decides it needs input. 2174 */ 2175 2176 #define MAX_READAHEAD 20 2177 static int com_readahead[MAX_READAHEAD]; 2178 static int com_readaheadcount = 0; 2179 2180 int 2181 com_common_getc(dev_t dev, struct com_regs *regsp) 2182 { 2183 int s = splserial(); 2184 u_char stat, c; 2185 2186 /* got a character from reading things earlier */ 2187 if (com_readaheadcount > 0) { 2188 int i; 2189 2190 c = com_readahead[0]; 2191 for (i = 1; i < com_readaheadcount; i++) { 2192 com_readahead[i-1] = com_readahead[i]; 2193 } 2194 com_readaheadcount--; 2195 splx(s); 2196 return (c); 2197 } 2198 2199 /* block until a character becomes available */ 2200 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2201 ; 2202 2203 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2204 stat = CSR_READ_1(regsp, COM_REG_IIR); 2205 { 2206 int cn_trapped = 0; /* unused */ 2207 #ifdef DDB 2208 extern int db_active; 2209 if (!db_active) 2210 #endif 2211 cn_check_magic(dev, c, com_cnm_state); 2212 } 2213 splx(s); 2214 return (c); 2215 } 2216 2217 void 2218 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2219 { 2220 int s = splserial(); 2221 int cin, stat, timo; 2222 2223 if (com_readaheadcount < MAX_READAHEAD 2224 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2225 int cn_trapped = 0; 2226 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2227 stat = CSR_READ_1(regsp, COM_REG_IIR); 2228 cn_check_magic(dev, cin, com_cnm_state); 2229 com_readahead[com_readaheadcount++] = cin; 2230 } 2231 2232 /* wait for any pending transmission to finish */ 2233 timo = 150000; 2234 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2235 continue; 2236 2237 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2238 COM_BARRIER(regsp, BR | BW); 2239 2240 splx(s); 2241 } 2242 2243 /* 2244 * Initialize UART for use as console or KGDB line. 2245 */ 2246 int 2247 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2248 tcflag_t cflag) 2249 { 2250 2251 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2252 ®sp->cr_ioh)) 2253 return (ENOMEM); /* ??? */ 2254 2255 rate = comspeed(rate, frequency, type); 2256 if (type != COM_TYPE_AU1x00) { 2257 /* no EFR on alchemy */ 2258 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2259 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2260 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2261 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2262 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2263 } else { 2264 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2265 } 2266 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2267 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2268 CSR_WRITE_1(regsp, COM_REG_FIFO, 2269 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2270 #ifdef COM_PXA2X0 2271 if (type == COM_TYPE_PXA2x0) 2272 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2273 else 2274 #endif 2275 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2276 2277 return (0); 2278 } 2279 2280 /* 2281 * Following are all routines needed for COM to act as console 2282 */ 2283 struct consdev comcons = { 2284 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2285 NODEV, CN_NORMAL 2286 }; 2287 2288 2289 int 2290 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2291 tcflag_t cflag) 2292 { 2293 int res; 2294 2295 comconsregs = *regsp; 2296 2297 res = cominit(&comconsregs, rate, frequency, type, cflag); 2298 if (res) 2299 return (res); 2300 2301 cn_tab = &comcons; 2302 cn_init_magic(&com_cnm_state); 2303 cn_set_magic("\047\001"); /* default magic is BREAK */ 2304 2305 comconsrate = rate; 2306 comconscflag = cflag; 2307 2308 return (0); 2309 } 2310 2311 int 2312 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2313 int type, tcflag_t cflag) 2314 { 2315 struct com_regs regs; 2316 2317 memset(®s, 0, sizeof regs); 2318 regs.cr_iot = iot; 2319 regs.cr_iobase = iobase; 2320 regs.cr_nports = COM_NPORTS; 2321 #ifdef COM_REGMAP 2322 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2323 #endif 2324 2325 return comcnattach1(®s, rate, frequency, type, cflag); 2326 } 2327 2328 int 2329 comcngetc(dev_t dev) 2330 { 2331 2332 return (com_common_getc(dev, &comconsregs)); 2333 } 2334 2335 /* 2336 * Console kernel output character routine. 2337 */ 2338 void 2339 comcnputc(dev_t dev, int c) 2340 { 2341 2342 com_common_putc(dev, &comconsregs, c); 2343 } 2344 2345 void 2346 comcnpollc(dev_t dev, int on) 2347 { 2348 2349 } 2350 2351 #ifdef KGDB 2352 int 2353 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2354 tcflag_t cflag) 2355 { 2356 int res; 2357 2358 if (regsp->cr_iot == comconsregs.cr_iot && 2359 regsp->cr_iobase == comconsregs.cr_iobase) { 2360 #if !defined(DDB) 2361 return (EBUSY); /* cannot share with console */ 2362 #else 2363 comkgdbregs = *regsp; 2364 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2365 #endif 2366 } else { 2367 comkgdbregs = *regsp; 2368 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2369 if (res) 2370 return (res); 2371 2372 /* 2373 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2374 * expects this to be initialized 2375 */ 2376 cn_init_magic(&com_cnm_state); 2377 cn_set_magic("\047\001"); 2378 } 2379 2380 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2381 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2382 2383 return (0); 2384 } 2385 2386 int 2387 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2388 int frequency, int type, tcflag_t cflag) 2389 { 2390 struct com_regs regs; 2391 2392 regs.cr_iot = iot; 2393 regs.cr_nports = COM_NPORTS; 2394 regs.cr_iobase = iobase; 2395 #ifdef COM_REGMAP 2396 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2397 #endif 2398 2399 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2400 } 2401 2402 /* ARGSUSED */ 2403 int 2404 com_kgdb_getc(void *arg) 2405 { 2406 2407 return (com_common_getc(NODEV, &comkgdbregs)); 2408 } 2409 2410 /* ARGSUSED */ 2411 void 2412 com_kgdb_putc(void *arg, int c) 2413 { 2414 2415 com_common_putc(NODEV, &comkgdbregs, c); 2416 } 2417 #endif /* KGDB */ 2418 2419 /* helper function to identify the com ports used by 2420 console or KGDB (and not yet autoconf attached) */ 2421 int 2422 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2423 { 2424 bus_space_handle_t help; 2425 2426 if (!comconsattached && 2427 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2428 help = comconsregs.cr_ioh; 2429 #ifdef KGDB 2430 else if (!com_kgdb_attached && 2431 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2432 help = comkgdbregs.cr_ioh; 2433 #endif 2434 else 2435 return (0); 2436 2437 if (ioh) 2438 *ioh = help; 2439 return (1); 2440 } 2441 2442 /* 2443 * this routine exists to serve as a shutdown hook for systems that 2444 * have firmware which doesn't interact properly with a com device in 2445 * FIFO mode. 2446 */ 2447 void 2448 com_cleanup(void *arg) 2449 { 2450 struct com_softc *sc = arg; 2451 2452 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2453 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2454 } 2455 2456 bool 2457 com_resume(device_t dev) 2458 { 2459 struct com_softc *sc = device_private(dev); 2460 2461 mutex_spin_enter(&sc->sc_lock); 2462 com_loadchannelregs(sc); 2463 mutex_spin_exit(&sc->sc_lock); 2464 2465 return true; 2466 } 2467
Indexes created Tue Sep 23 23:09:58 GMT 2025