com.c revision 1.281
1 /* com.c,v 1.262.2.3 2008/01/09 01:52:50 matt Exp */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "com.c,v 1.262.2.3 2008/01/09 01:52:50 matt Exp"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 #if NRND > 0 && defined(RND_COM) 80 #include <sys/rnd.h> 81 #endif 82 83 /* The COM16650 option was renamed to COM_16650. */ 84 #ifdef COM16650 85 #error Obsolete COM16650 option; use COM_16650 instead. 86 #endif 87 88 /* 89 * Override cnmagic(9) macro before including <sys/systm.h>. 90 * We need to know if cn_check_magic triggered debugger, so set a flag. 91 * Callers of cn_check_magic must declare int cn_trapped = 0; 92 * XXX: this is *ugly*! 93 */ 94 #define cn_trap() \ 95 do { \ 96 console_debugger(); \ 97 cn_trapped = 1; \ 98 } while (/* CONSTCOND */ 0) 99 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/ioctl.h> 103 #include <sys/select.h> 104 #include <sys/poll.h> 105 #include <sys/tty.h> 106 #include <sys/proc.h> 107 #include <sys/user.h> 108 #include <sys/conf.h> 109 #include <sys/file.h> 110 #include <sys/uio.h> 111 #include <sys/kernel.h> 112 #include <sys/syslog.h> 113 #include <sys/device.h> 114 #include <sys/malloc.h> 115 #include <sys/timepps.h> 116 #include <sys/vnode.h> 117 #include <sys/kauth.h> 118 #include <sys/intr.h> 119 120 #include <sys/bus.h> 121 122 #include <dev/ic/comreg.h> 123 #include <dev/ic/comvar.h> 124 #include <dev/ic/ns16550reg.h> 125 #include <dev/ic/st16650reg.h> 126 #ifdef COM_HAYESP 127 #include <dev/ic/hayespreg.h> 128 #endif 129 #define com_lcr com_cfcr 130 #include <dev/cons.h> 131 132 #ifdef COM_REGMAP 133 #define CSR_WRITE_1(r, o, v) \ 134 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 135 #define CSR_READ_1(r, o) \ 136 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 137 #define CSR_WRITE_2(r, o, v) \ 138 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 139 #define CSR_READ_2(r, o) \ 140 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 141 #define CSR_WRITE_MULTI(r, o, p, n) \ 142 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 143 #else 144 #define CSR_WRITE_1(r, o, v) \ 145 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 146 #define CSR_READ_1(r, o) \ 147 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 148 #define CSR_WRITE_2(r, o, v) \ 149 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 150 #define CSR_READ_2(r, o) \ 151 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 152 #define CSR_WRITE_MULTI(r, o, p, n) \ 153 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 154 #endif 155 156 157 static void com_enable_debugport(struct com_softc *); 158 159 void com_config(struct com_softc *); 160 void com_shutdown(struct com_softc *); 161 int comspeed(long, long, int); 162 static u_char cflag2lcr(tcflag_t); 163 int comparam(struct tty *, struct termios *); 164 void comstart(struct tty *); 165 int comhwiflow(struct tty *, int); 166 167 void com_loadchannelregs(struct com_softc *); 168 void com_hwiflow(struct com_softc *); 169 void com_break(struct com_softc *, int); 170 void com_modem(struct com_softc *, int); 171 void tiocm_to_com(struct com_softc *, u_long, int); 172 int com_to_tiocm(struct com_softc *); 173 void com_iflush(struct com_softc *); 174 175 int com_common_getc(dev_t, struct com_regs *); 176 void com_common_putc(dev_t, struct com_regs *, int); 177 178 int cominit(struct com_regs *, int, int, int, tcflag_t); 179 180 int comcngetc(dev_t); 181 void comcnputc(dev_t, int); 182 void comcnpollc(dev_t, int); 183 184 #define integrate static inline 185 void comsoft(void *); 186 integrate void com_rxsoft(struct com_softc *, struct tty *); 187 integrate void com_txsoft(struct com_softc *, struct tty *); 188 integrate void com_stsoft(struct com_softc *, struct tty *); 189 integrate void com_schedrx(struct com_softc *); 190 void comdiag(void *); 191 192 extern struct cfdriver com_cd; 193 194 dev_type_open(comopen); 195 dev_type_close(comclose); 196 dev_type_read(comread); 197 dev_type_write(comwrite); 198 dev_type_ioctl(comioctl); 199 dev_type_stop(comstop); 200 dev_type_tty(comtty); 201 dev_type_poll(compoll); 202 203 const struct cdevsw com_cdevsw = { 204 comopen, comclose, comread, comwrite, comioctl, 205 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 206 }; 207 208 /* 209 * Make this an option variable one can patch. 210 * But be warned: this must be a power of 2! 211 */ 212 u_int com_rbuf_size = COM_RING_SIZE; 213 214 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 215 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 216 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 217 218 static struct com_regs comconsregs; 219 static int comconsattached; 220 static int comconsrate; 221 static tcflag_t comconscflag; 222 static struct cnm_state com_cnm_state; 223 224 #ifdef KGDB 225 #include <sys/kgdb.h> 226 227 static struct com_regs comkgdbregs; 228 static int com_kgdb_attached; 229 230 int com_kgdb_getc(void *); 231 void com_kgdb_putc(void *, int); 232 #endif /* KGDB */ 233 234 #ifdef COM_REGMAP 235 /* initializer for typical 16550-ish hardware */ 236 #define COM_REG_16550 { \ 237 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 238 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 239 240 const bus_size_t com_std_map[16] = COM_REG_16550; 241 #endif /* COM_REGMAP */ 242 243 #define COMUNIT_MASK 0x7ffff 244 #define COMDIALOUT_MASK 0x80000 245 246 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 247 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 248 249 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 250 device_is_active((sc)->sc_dev)) 251 252 #define BR BUS_SPACE_BARRIER_READ 253 #define BW BUS_SPACE_BARRIER_WRITE 254 #define COM_BARRIER(r, f) \ 255 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 256 257 /*ARGSUSED*/ 258 int 259 comspeed(long speed, long frequency, int type) 260 { 261 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 262 263 int x, err; 264 int divisor = 16; 265 266 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 267 divisor = 13; 268 } 269 270 #if 0 271 if (speed == 0) 272 return (0); 273 #endif 274 if (speed <= 0) 275 return (-1); 276 x = divrnd(frequency / divisor, speed); 277 if (x <= 0) 278 return (-1); 279 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 280 if (err < 0) 281 err = -err; 282 if (err > COM_TOLERANCE) 283 return (-1); 284 return (x); 285 286 #undef divrnd 287 } 288 289 #ifdef COM_DEBUG 290 int com_debug = 0; 291 292 void comstatus(struct com_softc *, const char *); 293 void 294 comstatus(struct com_softc *sc, const char *str) 295 { 296 struct tty *tp = sc->sc_tty; 297 298 aprint_normal_dev(sc->sc_dev, 299 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 300 str, 301 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 302 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 303 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 304 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 305 sc->sc_tx_stopped ? '+' : '-'); 306 307 aprint_normal_dev(sc->sc_dev, 308 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 309 str, 310 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 311 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 312 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 313 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 314 sc->sc_rx_flags); 315 } 316 #endif 317 318 int 319 com_probe_subr(struct com_regs *regs) 320 { 321 322 /* force access to id reg */ 323 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 324 CSR_WRITE_1(regs, COM_REG_IIR, 0); 325 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 326 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 327 return (0); 328 329 return (1); 330 } 331 332 int 333 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 334 { 335 struct com_regs regs; 336 337 regs.cr_iot = iot; 338 regs.cr_ioh = ioh; 339 #ifdef COM_REGMAP 340 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 341 #endif 342 343 return com_probe_subr(®s); 344 } 345 346 /* 347 * No locking in this routine; it is only called during attach, 348 * or with the port already locked. 349 */ 350 static void 351 com_enable_debugport(struct com_softc *sc) 352 { 353 354 /* Turn on line break interrupt, set carrier. */ 355 sc->sc_ier = IER_ERXRDY; 356 if (sc->sc_type == COM_TYPE_PXA2x0) 357 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 358 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 359 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 360 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 361 } 362 363 void 364 com_attach_subr(struct com_softc *sc) 365 { 366 struct com_regs *regsp = &sc->sc_regs; 367 struct tty *tp; 368 #ifdef COM_16650 369 u_int8_t lcr; 370 #endif 371 const char *fifo_msg = NULL; 372 373 aprint_naive("\n"); 374 375 callout_init(&sc->sc_diag_callout, 0); 376 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 377 378 /* Disable interrupts before configuring the device. */ 379 if (sc->sc_type == COM_TYPE_PXA2x0) 380 sc->sc_ier = IER_EUART; 381 else 382 sc->sc_ier = 0; 383 384 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 385 386 if (regsp->cr_iot == comconsregs.cr_iot && 387 regsp->cr_iobase == comconsregs.cr_iobase) { 388 comconsattached = 1; 389 390 /* Make sure the console is always "hardwired". */ 391 delay(10000); /* wait for output to finish */ 392 SET(sc->sc_hwflags, COM_HW_CONSOLE); 393 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 394 } 395 396 /* Probe for FIFO */ 397 switch (sc->sc_type) { 398 case COM_TYPE_HAYESP: 399 goto fifodone; 400 401 case COM_TYPE_AU1x00: 402 sc->sc_fifolen = 16; 403 fifo_msg = "Au1X00 UART, working fifo"; 404 SET(sc->sc_hwflags, COM_HW_FIFO); 405 goto fifodelay; 406 407 case COM_TYPE_OMAP: 408 sc->sc_fifolen = 64; 409 fifo_msg = "OMAP UART, working fifo"; 410 SET(sc->sc_hwflags, COM_HW_FIFO); 411 goto fifodelay; 412 } 413 414 sc->sc_fifolen = 1; 415 /* look for a NS 16550AF UART with FIFOs */ 416 CSR_WRITE_1(regsp, COM_REG_FIFO, 417 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 418 delay(100); 419 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 420 == IIR_FIFO_MASK) 421 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 422 == FIFO_TRIGGER_14) { 423 SET(sc->sc_hwflags, COM_HW_FIFO); 424 425 #ifdef COM_16650 426 /* 427 * IIR changes into the EFR if LCR is set to LCR_EERS 428 * on 16650s. We also know IIR != 0 at this point. 429 * Write 0 into the EFR, and read it. If the result 430 * is 0, we have a 16650. 431 * 432 * Older 16650s were broken; the test to detect them 433 * is taken from the Linux driver. Apparently 434 * setting DLAB enable gives access to the EFR on 435 * these chips. 436 */ 437 lcr = CSR_READ_1(regsp, COM_REG_LCR); 438 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 439 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 440 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 441 CSR_WRITE_1(regsp, COM_REG_LCR, 442 lcr | LCR_DLAB); 443 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 444 CLR(sc->sc_hwflags, COM_HW_FIFO); 445 sc->sc_fifolen = 0; 446 } else { 447 SET(sc->sc_hwflags, COM_HW_FLOW); 448 sc->sc_fifolen = 32; 449 } 450 } else 451 #endif 452 sc->sc_fifolen = 16; 453 454 #ifdef COM_16650 455 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 456 if (sc->sc_fifolen == 0) 457 fifo_msg = "st16650, broken fifo"; 458 else if (sc->sc_fifolen == 32) 459 fifo_msg = "st16650a, working fifo"; 460 else 461 #endif 462 fifo_msg = "ns16550a, working fifo"; 463 } else 464 fifo_msg = "ns16550, broken fifo"; 465 else 466 fifo_msg = "ns8250 or ns16450, no fifo"; 467 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 468 fifodelay: 469 /* 470 * Some chips will clear down both Tx and Rx FIFOs when zero is 471 * written to com_fifo. If this chip is the console, writing zero 472 * results in some of the chip/FIFO description being lost, so delay 473 * printing it until now. 474 */ 475 delay(10); 476 aprint_normal(": %s\n", fifo_msg); 477 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 478 sc->sc_fifolen = 1; 479 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 480 } 481 482 fifodone: 483 484 tp = ttymalloc(); 485 tp->t_oproc = comstart; 486 tp->t_param = comparam; 487 tp->t_hwiflow = comhwiflow; 488 489 sc->sc_tty = tp; 490 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 491 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 492 sc->sc_rbavail = com_rbuf_size; 493 if (sc->sc_rbuf == NULL) { 494 aprint_error_dev(sc->sc_dev, 495 "unable to allocate ring buffer\n"); 496 return; 497 } 498 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 499 500 tty_attach(tp); 501 502 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 503 SET(sc->sc_mcr, MCR_IENABLE); 504 505 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 506 int maj; 507 508 /* locate the major number */ 509 maj = cdevsw_lookup_major(&com_cdevsw); 510 511 tp->t_dev = cn_tab->cn_dev = makedev(maj, 512 device_unit(sc->sc_dev)); 513 514 aprint_normal_dev(sc->sc_dev, "console\n"); 515 } 516 517 #ifdef KGDB 518 /* 519 * Allow kgdb to "take over" this port. If this is 520 * not the console and is the kgdb device, it has 521 * exclusive use. If it's the console _and_ the 522 * kgdb device, it doesn't. 523 */ 524 if (regsp->cr_iot == comkgdbregs.cr_iot && 525 regsp->cr_iobase == comkgdbregs.cr_iobase) { 526 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 527 com_kgdb_attached = 1; 528 529 SET(sc->sc_hwflags, COM_HW_KGDB); 530 } 531 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 532 } 533 #endif 534 535 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 536 537 #if NRND > 0 && defined(RND_COM) 538 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 539 RND_TYPE_TTY, 0); 540 #endif 541 542 /* if there are no enable/disable functions, assume the device 543 is always enabled */ 544 if (!sc->enable) 545 sc->enabled = 1; 546 547 com_config(sc); 548 549 SET(sc->sc_hwflags, COM_HW_DEV_OK); 550 } 551 552 void 553 com_config(struct com_softc *sc) 554 { 555 struct com_regs *regsp = &sc->sc_regs; 556 557 /* Disable interrupts before configuring the device. */ 558 if (sc->sc_type == COM_TYPE_PXA2x0) 559 sc->sc_ier = IER_EUART; 560 else 561 sc->sc_ier = 0; 562 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 563 (void) CSR_READ_1(regsp, COM_REG_IIR); 564 565 #ifdef COM_HAYESP 566 /* Look for a Hayes ESP board. */ 567 if (sc->sc_type == COM_TYPE_HAYESP) { 568 569 /* Set 16550 compatibility mode */ 570 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 571 HAYESP_SETMODE); 572 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 573 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 574 HAYESP_MODE_SCALE); 575 576 /* Set RTS/CTS flow control */ 577 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 578 HAYESP_SETFLOWTYPE); 579 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 580 HAYESP_FLOW_RTS); 581 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 582 HAYESP_FLOW_CTS); 583 584 /* Set flow control levels */ 585 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 586 HAYESP_SETRXFLOW); 587 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 588 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 589 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 590 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 591 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 592 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 593 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 594 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 595 } 596 #endif 597 598 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 599 com_enable_debugport(sc); 600 } 601 602 int 603 com_detach(device_t self, int flags) 604 { 605 struct com_softc *sc = device_private(self); 606 int maj, mn; 607 608 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 609 return EBUSY; 610 611 /* locate the major number */ 612 maj = cdevsw_lookup_major(&com_cdevsw); 613 614 /* Nuke the vnodes for any open instances. */ 615 mn = device_unit(self); 616 vdevgone(maj, mn, mn, VCHR); 617 618 mn |= COMDIALOUT_MASK; 619 vdevgone(maj, mn, mn, VCHR); 620 621 if (sc->sc_rbuf == NULL) { 622 /* 623 * Ring buffer allocation failed in the com_attach_subr, 624 * only the tty is allocated, and nothing else. 625 */ 626 ttyfree(sc->sc_tty); 627 return 0; 628 } 629 630 /* Free the receive buffer. */ 631 free(sc->sc_rbuf, M_DEVBUF); 632 633 /* Detach and free the tty. */ 634 tty_detach(sc->sc_tty); 635 ttyfree(sc->sc_tty); 636 637 /* Unhook the soft interrupt handler. */ 638 softint_disestablish(sc->sc_si); 639 640 #if NRND > 0 && defined(RND_COM) 641 /* Unhook the entropy source. */ 642 rnd_detach_source(&sc->rnd_source); 643 #endif 644 callout_destroy(&sc->sc_diag_callout); 645 646 /* Destroy the lock. */ 647 mutex_destroy(&sc->sc_lock); 648 649 return (0); 650 } 651 652 int 653 com_activate(device_t self, enum devact act) 654 { 655 struct com_softc *sc = device_private(self); 656 int rv = 0; 657 658 switch (act) { 659 case DVACT_ACTIVATE: 660 rv = EOPNOTSUPP; 661 break; 662 663 case DVACT_DEACTIVATE: 664 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 665 rv = EBUSY; 666 break; 667 } 668 669 if (sc->disable != NULL && sc->enabled != 0) { 670 (*sc->disable)(sc); 671 sc->enabled = 0; 672 } 673 break; 674 } 675 676 if (sc->sc_type == COM_TYPE_OMAP) { 677 /* enable but mode is based on speed */ 678 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 679 CSR_WRITE_1(&sc->sc_regs, COM_REG_MDR1, MDR1_MODE_UART_13X); 680 } else { 681 CSR_WRITE_1(&sc->sc_regs, COM_REG_MDR1, MDR1_MODE_UART_16X); 682 } 683 } 684 mutex_spin_exit(&sc->sc_lock); 685 return (rv); 686 } 687 688 void 689 com_shutdown(struct com_softc *sc) 690 { 691 struct tty *tp = sc->sc_tty; 692 693 mutex_spin_enter(&sc->sc_lock); 694 695 /* If we were asserting flow control, then deassert it. */ 696 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 697 com_hwiflow(sc); 698 699 /* Clear any break condition set with TIOCSBRK. */ 700 com_break(sc, 0); 701 702 /* 703 * Hang up if necessary. Wait a bit, so the other side has time to 704 * notice even if we immediately open the port again. 705 * Avoid tsleeping above splhigh(). 706 */ 707 if (ISSET(tp->t_cflag, HUPCL)) { 708 com_modem(sc, 0); 709 mutex_spin_exit(&sc->sc_lock); 710 /* XXX will only timeout */ 711 (void) kpause(ttclos, false, hz, NULL); 712 mutex_spin_enter(&sc->sc_lock); 713 } 714 715 /* Turn off interrupts. */ 716 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 717 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 718 if (sc->sc_type == COM_TYPE_PXA2x0) 719 sc->sc_ier |= IER_ERXTOUT; 720 } else 721 sc->sc_ier = 0; 722 723 if (sc->sc_type == COM_TYPE_PXA2x0) 724 sc->sc_ier |= IER_EUART; 725 726 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 727 728 mutex_spin_exit(&sc->sc_lock); 729 730 if (sc->disable) { 731 #ifdef DIAGNOSTIC 732 if (!sc->enabled) 733 panic("com_shutdown: not enabled?"); 734 #endif 735 (*sc->disable)(sc); 736 sc->enabled = 0; 737 } 738 } 739 740 int 741 comopen(dev_t dev, int flag, int mode, struct lwp *l) 742 { 743 struct com_softc *sc; 744 struct tty *tp; 745 int s; 746 int error; 747 748 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 749 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 750 sc->sc_rbuf == NULL) 751 return (ENXIO); 752 753 if (!device_is_active(sc->sc_dev)) 754 return (ENXIO); 755 756 #ifdef KGDB 757 /* 758 * If this is the kgdb port, no other use is permitted. 759 */ 760 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 761 return (EBUSY); 762 #endif 763 764 tp = sc->sc_tty; 765 766 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 767 return (EBUSY); 768 769 s = spltty(); 770 771 /* 772 * Do the following iff this is a first open. 773 */ 774 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 775 struct termios t; 776 777 tp->t_dev = dev; 778 779 780 if (sc->enable) { 781 if ((*sc->enable)(sc)) { 782 splx(s); 783 aprint_error_dev(sc->sc_dev, 784 "device enable failed\n"); 785 return (EIO); 786 } 787 mutex_spin_enter(&sc->sc_lock); 788 sc->enabled = 1; 789 com_config(sc); 790 } else { 791 mutex_spin_enter(&sc->sc_lock); 792 } 793 794 /* Turn on interrupts. */ 795 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 796 if (sc->sc_type == COM_TYPE_PXA2x0) 797 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 798 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 799 800 /* Fetch the current modem control status, needed later. */ 801 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 802 803 /* Clear PPS capture state on first open. */ 804 mutex_spin_enter(&timecounter_lock); 805 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 806 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 807 pps_init(&sc->sc_pps_state); 808 mutex_spin_exit(&timecounter_lock); 809 810 mutex_spin_exit(&sc->sc_lock); 811 812 /* 813 * Initialize the termios status to the defaults. Add in the 814 * sticky bits from TIOCSFLAGS. 815 */ 816 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 817 t.c_ospeed = comconsrate; 818 t.c_cflag = comconscflag; 819 } else { 820 t.c_ospeed = TTYDEF_SPEED; 821 t.c_cflag = TTYDEF_CFLAG; 822 } 823 t.c_ispeed = t.c_ospeed; 824 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 825 SET(t.c_cflag, CLOCAL); 826 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 827 SET(t.c_cflag, CRTSCTS); 828 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 829 SET(t.c_cflag, MDMBUF); 830 /* Make sure comparam() will do something. */ 831 tp->t_ospeed = 0; 832 (void) comparam(tp, &t); 833 tp->t_iflag = TTYDEF_IFLAG; 834 tp->t_oflag = TTYDEF_OFLAG; 835 tp->t_lflag = TTYDEF_LFLAG; 836 ttychars(tp); 837 ttsetwater(tp); 838 839 mutex_spin_enter(&sc->sc_lock); 840 841 /* 842 * Turn on DTR. We must always do this, even if carrier is not 843 * present, because otherwise we'd have to use TIOCSDTR 844 * immediately after setting CLOCAL, which applications do not 845 * expect. We always assert DTR while the device is open 846 * unless explicitly requested to deassert it. 847 */ 848 com_modem(sc, 1); 849 850 /* Clear the input ring, and unblock. */ 851 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 852 sc->sc_rbavail = com_rbuf_size; 853 com_iflush(sc); 854 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 855 com_hwiflow(sc); 856 857 #ifdef COM_DEBUG 858 if (com_debug) 859 comstatus(sc, "comopen "); 860 #endif 861 862 mutex_spin_exit(&sc->sc_lock); 863 } 864 865 splx(s); 866 867 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 868 if (error) 869 goto bad; 870 871 error = (*tp->t_linesw->l_open)(dev, tp); 872 if (error) 873 goto bad; 874 875 return (0); 876 877 bad: 878 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 879 /* 880 * We failed to open the device, and nobody else had it opened. 881 * Clean up the state as appropriate. 882 */ 883 com_shutdown(sc); 884 } 885 886 return (error); 887 } 888 889 int 890 comclose(dev_t dev, int flag, int mode, struct lwp *l) 891 { 892 struct com_softc *sc = 893 device_lookup_private(&com_cd, COMUNIT(dev)); 894 struct tty *tp = sc->sc_tty; 895 896 /* XXX This is for cons.c. */ 897 if (!ISSET(tp->t_state, TS_ISOPEN)) 898 return (0); 899 900 (*tp->t_linesw->l_close)(tp, flag); 901 ttyclose(tp); 902 903 if (COM_ISALIVE(sc) == 0) 904 return (0); 905 906 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 907 /* 908 * Although we got a last close, the device may still be in 909 * use; e.g. if this was the dialout node, and there are still 910 * processes waiting for carrier on the non-dialout node. 911 */ 912 com_shutdown(sc); 913 } 914 915 return (0); 916 } 917 918 int 919 comread(dev_t dev, struct uio *uio, int flag) 920 { 921 struct com_softc *sc = 922 device_lookup_private(&com_cd, COMUNIT(dev)); 923 struct tty *tp = sc->sc_tty; 924 925 if (COM_ISALIVE(sc) == 0) 926 return (EIO); 927 928 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 929 } 930 931 int 932 comwrite(dev_t dev, struct uio *uio, int flag) 933 { 934 struct com_softc *sc = 935 device_lookup_private(&com_cd, COMUNIT(dev)); 936 struct tty *tp = sc->sc_tty; 937 938 if (COM_ISALIVE(sc) == 0) 939 return (EIO); 940 941 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 942 } 943 944 int 945 compoll(dev_t dev, int events, struct lwp *l) 946 { 947 struct com_softc *sc = 948 device_lookup_private(&com_cd, COMUNIT(dev)); 949 struct tty *tp = sc->sc_tty; 950 951 if (COM_ISALIVE(sc) == 0) 952 return (POLLHUP); 953 954 return ((*tp->t_linesw->l_poll)(tp, events, l)); 955 } 956 957 struct tty * 958 comtty(dev_t dev) 959 { 960 struct com_softc *sc = 961 device_lookup_private(&com_cd, COMUNIT(dev)); 962 struct tty *tp = sc->sc_tty; 963 964 return (tp); 965 } 966 967 int 968 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 969 { 970 struct com_softc *sc; 971 struct tty *tp; 972 int error; 973 974 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 975 if (sc == NULL) 976 return ENXIO; 977 if (COM_ISALIVE(sc) == 0) 978 return (EIO); 979 980 tp = sc->sc_tty; 981 982 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 983 if (error != EPASSTHROUGH) 984 return (error); 985 986 error = ttioctl(tp, cmd, data, flag, l); 987 if (error != EPASSTHROUGH) 988 return (error); 989 990 error = 0; 991 switch (cmd) { 992 case TIOCSFLAGS: 993 error = kauth_authorize_device_tty(l->l_cred, 994 KAUTH_DEVICE_TTY_PRIVSET, tp); 995 break; 996 default: 997 /* nothing */ 998 break; 999 } 1000 if (error) { 1001 return error; 1002 } 1003 1004 mutex_spin_enter(&sc->sc_lock); 1005 1006 switch (cmd) { 1007 case TIOCSBRK: 1008 com_break(sc, 1); 1009 break; 1010 1011 case TIOCCBRK: 1012 com_break(sc, 0); 1013 break; 1014 1015 case TIOCSDTR: 1016 com_modem(sc, 1); 1017 break; 1018 1019 case TIOCCDTR: 1020 com_modem(sc, 0); 1021 break; 1022 1023 case TIOCGFLAGS: 1024 *(int *)data = sc->sc_swflags; 1025 break; 1026 1027 case TIOCSFLAGS: 1028 sc->sc_swflags = *(int *)data; 1029 break; 1030 1031 case TIOCMSET: 1032 case TIOCMBIS: 1033 case TIOCMBIC: 1034 tiocm_to_com(sc, cmd, *(int *)data); 1035 break; 1036 1037 case TIOCMGET: 1038 *(int *)data = com_to_tiocm(sc); 1039 break; 1040 1041 case PPS_IOC_CREATE: 1042 case PPS_IOC_DESTROY: 1043 case PPS_IOC_GETPARAMS: 1044 case PPS_IOC_SETPARAMS: 1045 case PPS_IOC_GETCAP: 1046 case PPS_IOC_FETCH: 1047 #ifdef PPS_SYNC 1048 case PPS_IOC_KCBIND: 1049 #endif 1050 mutex_spin_enter(&timecounter_lock); 1051 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1052 mutex_spin_exit(&timecounter_lock); 1053 break; 1054 1055 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1056 mutex_spin_enter(&timecounter_lock); 1057 #ifndef PPS_TRAILING_EDGE 1058 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1059 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1060 #else 1061 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1062 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1063 #endif 1064 mutex_spin_exit(&timecounter_lock); 1065 break; 1066 1067 default: 1068 error = EPASSTHROUGH; 1069 break; 1070 } 1071 1072 mutex_spin_exit(&sc->sc_lock); 1073 1074 #ifdef COM_DEBUG 1075 if (com_debug) 1076 comstatus(sc, "comioctl "); 1077 #endif 1078 1079 return (error); 1080 } 1081 1082 integrate void 1083 com_schedrx(struct com_softc *sc) 1084 { 1085 1086 sc->sc_rx_ready = 1; 1087 1088 /* Wake up the poller. */ 1089 softint_schedule(sc->sc_si); 1090 } 1091 1092 void 1093 com_break(struct com_softc *sc, int onoff) 1094 { 1095 1096 if (onoff) 1097 SET(sc->sc_lcr, LCR_SBREAK); 1098 else 1099 CLR(sc->sc_lcr, LCR_SBREAK); 1100 1101 if (!sc->sc_heldchange) { 1102 if (sc->sc_tx_busy) { 1103 sc->sc_heldtbc = sc->sc_tbc; 1104 sc->sc_tbc = 0; 1105 sc->sc_heldchange = 1; 1106 } else 1107 com_loadchannelregs(sc); 1108 } 1109 } 1110 1111 void 1112 com_modem(struct com_softc *sc, int onoff) 1113 { 1114 1115 if (sc->sc_mcr_dtr == 0) 1116 return; 1117 1118 if (onoff) 1119 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1120 else 1121 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1122 1123 if (!sc->sc_heldchange) { 1124 if (sc->sc_tx_busy) { 1125 sc->sc_heldtbc = sc->sc_tbc; 1126 sc->sc_tbc = 0; 1127 sc->sc_heldchange = 1; 1128 } else 1129 com_loadchannelregs(sc); 1130 } 1131 } 1132 1133 void 1134 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1135 { 1136 u_char combits; 1137 1138 combits = 0; 1139 if (ISSET(ttybits, TIOCM_DTR)) 1140 SET(combits, MCR_DTR); 1141 if (ISSET(ttybits, TIOCM_RTS)) 1142 SET(combits, MCR_RTS); 1143 1144 switch (how) { 1145 case TIOCMBIC: 1146 CLR(sc->sc_mcr, combits); 1147 break; 1148 1149 case TIOCMBIS: 1150 SET(sc->sc_mcr, combits); 1151 break; 1152 1153 case TIOCMSET: 1154 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1155 SET(sc->sc_mcr, combits); 1156 break; 1157 } 1158 1159 if (!sc->sc_heldchange) { 1160 if (sc->sc_tx_busy) { 1161 sc->sc_heldtbc = sc->sc_tbc; 1162 sc->sc_tbc = 0; 1163 sc->sc_heldchange = 1; 1164 } else 1165 com_loadchannelregs(sc); 1166 } 1167 } 1168 1169 int 1170 com_to_tiocm(struct com_softc *sc) 1171 { 1172 u_char combits; 1173 int ttybits = 0; 1174 1175 combits = sc->sc_mcr; 1176 if (ISSET(combits, MCR_DTR)) 1177 SET(ttybits, TIOCM_DTR); 1178 if (ISSET(combits, MCR_RTS)) 1179 SET(ttybits, TIOCM_RTS); 1180 1181 combits = sc->sc_msr; 1182 if (ISSET(combits, MSR_DCD)) 1183 SET(ttybits, TIOCM_CD); 1184 if (ISSET(combits, MSR_CTS)) 1185 SET(ttybits, TIOCM_CTS); 1186 if (ISSET(combits, MSR_DSR)) 1187 SET(ttybits, TIOCM_DSR); 1188 if (ISSET(combits, MSR_RI | MSR_TERI)) 1189 SET(ttybits, TIOCM_RI); 1190 1191 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1192 SET(ttybits, TIOCM_LE); 1193 1194 return (ttybits); 1195 } 1196 1197 static u_char 1198 cflag2lcr(tcflag_t cflag) 1199 { 1200 u_char lcr = 0; 1201 1202 switch (ISSET(cflag, CSIZE)) { 1203 case CS5: 1204 SET(lcr, LCR_5BITS); 1205 break; 1206 case CS6: 1207 SET(lcr, LCR_6BITS); 1208 break; 1209 case CS7: 1210 SET(lcr, LCR_7BITS); 1211 break; 1212 case CS8: 1213 SET(lcr, LCR_8BITS); 1214 break; 1215 } 1216 if (ISSET(cflag, PARENB)) { 1217 SET(lcr, LCR_PENAB); 1218 if (!ISSET(cflag, PARODD)) 1219 SET(lcr, LCR_PEVEN); 1220 } 1221 if (ISSET(cflag, CSTOPB)) 1222 SET(lcr, LCR_STOPB); 1223 1224 return (lcr); 1225 } 1226 1227 int 1228 comparam(struct tty *tp, struct termios *t) 1229 { 1230 struct com_softc *sc = 1231 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1232 int ospeed; 1233 u_char lcr; 1234 1235 if (COM_ISALIVE(sc) == 0) 1236 return (EIO); 1237 1238 #ifdef COM_HAYESP 1239 if (sc->sc_type == COM_TYPE_HAYESP) { 1240 int prescaler, speed; 1241 1242 /* 1243 * Calculate UART clock prescaler. It should be in 1244 * range of 0 .. 3. 1245 */ 1246 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1247 prescaler++, speed /= 2) 1248 if ((ospeed = comspeed(speed, sc->sc_frequency, 1249 sc->sc_type)) > 0) 1250 break; 1251 1252 if (prescaler == 4) 1253 return (EINVAL); 1254 sc->sc_prescaler = prescaler; 1255 } else 1256 #endif 1257 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1258 1259 /* Check requested parameters. */ 1260 if (ospeed < 0) 1261 return (EINVAL); 1262 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1263 return (EINVAL); 1264 1265 /* 1266 * For the console, always force CLOCAL and !HUPCL, so that the port 1267 * is always active. 1268 */ 1269 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1270 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1271 SET(t->c_cflag, CLOCAL); 1272 CLR(t->c_cflag, HUPCL); 1273 } 1274 1275 /* 1276 * If there were no changes, don't do anything. This avoids dropping 1277 * input and improves performance when all we did was frob things like 1278 * VMIN and VTIME. 1279 */ 1280 if (tp->t_ospeed == t->c_ospeed && 1281 tp->t_cflag == t->c_cflag) 1282 return (0); 1283 1284 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1285 1286 mutex_spin_enter(&sc->sc_lock); 1287 1288 sc->sc_lcr = lcr; 1289 1290 /* 1291 * If we're not in a mode that assumes a connection is present, then 1292 * ignore carrier changes. 1293 */ 1294 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1295 sc->sc_msr_dcd = 0; 1296 else 1297 sc->sc_msr_dcd = MSR_DCD; 1298 /* 1299 * Set the flow control pins depending on the current flow control 1300 * mode. 1301 */ 1302 if (ISSET(t->c_cflag, CRTSCTS)) { 1303 sc->sc_mcr_dtr = MCR_DTR; 1304 sc->sc_mcr_rts = MCR_RTS; 1305 sc->sc_msr_cts = MSR_CTS; 1306 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1307 } else if (ISSET(t->c_cflag, MDMBUF)) { 1308 /* 1309 * For DTR/DCD flow control, make sure we don't toggle DTR for 1310 * carrier detection. 1311 */ 1312 sc->sc_mcr_dtr = 0; 1313 sc->sc_mcr_rts = MCR_DTR; 1314 sc->sc_msr_cts = MSR_DCD; 1315 sc->sc_efr = 0; 1316 } else { 1317 /* 1318 * If no flow control, then always set RTS. This will make 1319 * the other side happy if it mistakenly thinks we're doing 1320 * RTS/CTS flow control. 1321 */ 1322 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1323 sc->sc_mcr_rts = 0; 1324 sc->sc_msr_cts = 0; 1325 sc->sc_efr = 0; 1326 if (ISSET(sc->sc_mcr, MCR_DTR)) 1327 SET(sc->sc_mcr, MCR_RTS); 1328 else 1329 CLR(sc->sc_mcr, MCR_RTS); 1330 } 1331 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1332 1333 #if 0 1334 if (ospeed == 0) 1335 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1336 else 1337 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1338 #endif 1339 1340 sc->sc_dlbl = ospeed; 1341 sc->sc_dlbh = ospeed >> 8; 1342 1343 /* 1344 * Set the FIFO threshold based on the receive speed. 1345 * 1346 * * If it's a low speed, it's probably a mouse or some other 1347 * interactive device, so set the threshold low. 1348 * * If it's a high speed, trim the trigger level down to prevent 1349 * overflows. 1350 * * Otherwise set it a bit higher. 1351 */ 1352 if (sc->sc_type == COM_TYPE_HAYESP) 1353 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1354 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1355 if (t->c_ospeed <= 1200) 1356 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1357 else if (t->c_ospeed <= 38400) 1358 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1359 else 1360 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1361 } else 1362 sc->sc_fifo = 0; 1363 1364 /* And copy to tty. */ 1365 tp->t_ispeed = t->c_ospeed; 1366 tp->t_ospeed = t->c_ospeed; 1367 tp->t_cflag = t->c_cflag; 1368 1369 if (!sc->sc_heldchange) { 1370 if (sc->sc_tx_busy) { 1371 sc->sc_heldtbc = sc->sc_tbc; 1372 sc->sc_tbc = 0; 1373 sc->sc_heldchange = 1; 1374 } else 1375 com_loadchannelregs(sc); 1376 } 1377 1378 if (!ISSET(t->c_cflag, CHWFLOW)) { 1379 /* Disable the high water mark. */ 1380 sc->sc_r_hiwat = 0; 1381 sc->sc_r_lowat = 0; 1382 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1383 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1384 com_schedrx(sc); 1385 } 1386 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1387 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1388 com_hwiflow(sc); 1389 } 1390 } else { 1391 sc->sc_r_hiwat = com_rbuf_hiwat; 1392 sc->sc_r_lowat = com_rbuf_lowat; 1393 } 1394 1395 mutex_spin_exit(&sc->sc_lock); 1396 1397 /* 1398 * Update the tty layer's idea of the carrier bit, in case we changed 1399 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1400 * explicit request. 1401 */ 1402 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1403 1404 #ifdef COM_DEBUG 1405 if (com_debug) 1406 comstatus(sc, "comparam "); 1407 #endif 1408 1409 if (!ISSET(t->c_cflag, CHWFLOW)) { 1410 if (sc->sc_tx_stopped) { 1411 sc->sc_tx_stopped = 0; 1412 comstart(tp); 1413 } 1414 } 1415 1416 return (0); 1417 } 1418 1419 void 1420 com_iflush(struct com_softc *sc) 1421 { 1422 struct com_regs *regsp = &sc->sc_regs; 1423 #ifdef DIAGNOSTIC 1424 int reg; 1425 #endif 1426 int timo; 1427 1428 #ifdef DIAGNOSTIC 1429 reg = 0xffff; 1430 #endif 1431 timo = 50000; 1432 /* flush any pending I/O */ 1433 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1434 && --timo) 1435 #ifdef DIAGNOSTIC 1436 reg = 1437 #else 1438 (void) 1439 #endif 1440 CSR_READ_1(regsp, COM_REG_RXDATA); 1441 #ifdef DIAGNOSTIC 1442 if (!timo) 1443 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1444 #endif 1445 } 1446 1447 void 1448 com_loadchannelregs(struct com_softc *sc) 1449 { 1450 struct com_regs *regsp = &sc->sc_regs; 1451 1452 /* XXXXX necessary? */ 1453 com_iflush(sc); 1454 1455 if (sc->sc_type == COM_TYPE_PXA2x0) 1456 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1457 else 1458 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1459 1460 if (sc->sc_type == COM_TYPE_OMAP) { 1461 /* disable before changing settings */ 1462 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1463 } 1464 1465 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1466 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1467 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1468 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1469 } 1470 } 1471 if (sc->sc_type == COM_TYPE_AU1x00) { 1472 /* alchemy has single separate 16-bit clock divisor register */ 1473 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1474 (sc->sc_dlbh << 8)); 1475 } else { 1476 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1477 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1478 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1479 } 1480 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1481 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1482 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1483 #ifdef COM_HAYESP 1484 if (sc->sc_type == COM_TYPE_HAYESP) { 1485 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1486 HAYESP_SETPRESCALER); 1487 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1488 sc->sc_prescaler); 1489 } 1490 #endif 1491 if (sc->sc_type == COM_TYPE_OMAP) { 1492 /* setup the fifos. the FCR value is not used as long 1493 as SCR[6] and SCR[7] are 0, which they are at reset 1494 and we never touch the SCR register */ 1495 uint8_t rx_fifo_trig = 40; 1496 uint8_t tx_fifo_trig = 60; 1497 uint8_t rx_start = 8; 1498 uint8_t rx_halt = 60; 1499 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1500 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1501 1502 /* enable access to TCR & TLR */ 1503 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1504 1505 /* write tcr and tlr values */ 1506 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1507 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1508 1509 /* disable access to TCR & TLR */ 1510 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1511 1512 /* enable again, but mode is based on speed */ 1513 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1514 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1515 } else { 1516 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1517 } 1518 } 1519 1520 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1521 } 1522 1523 int 1524 comhwiflow(struct tty *tp, int block) 1525 { 1526 struct com_softc *sc = 1527 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1528 1529 if (COM_ISALIVE(sc) == 0) 1530 return (0); 1531 1532 if (sc->sc_mcr_rts == 0) 1533 return (0); 1534 1535 mutex_spin_enter(&sc->sc_lock); 1536 1537 if (block) { 1538 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1539 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1540 com_hwiflow(sc); 1541 } 1542 } else { 1543 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1544 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1545 com_schedrx(sc); 1546 } 1547 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1548 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1549 com_hwiflow(sc); 1550 } 1551 } 1552 1553 mutex_spin_exit(&sc->sc_lock); 1554 return (1); 1555 } 1556 1557 /* 1558 * (un)block input via hw flowcontrol 1559 */ 1560 void 1561 com_hwiflow(struct com_softc *sc) 1562 { 1563 struct com_regs *regsp= &sc->sc_regs; 1564 1565 if (sc->sc_mcr_rts == 0) 1566 return; 1567 1568 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1569 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1570 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1571 } else { 1572 SET(sc->sc_mcr, sc->sc_mcr_rts); 1573 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1574 } 1575 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1576 } 1577 1578 1579 void 1580 comstart(struct tty *tp) 1581 { 1582 struct com_softc *sc = 1583 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1584 struct com_regs *regsp = &sc->sc_regs; 1585 int s; 1586 1587 if (COM_ISALIVE(sc) == 0) 1588 return; 1589 1590 s = spltty(); 1591 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1592 goto out; 1593 if (sc->sc_tx_stopped) 1594 goto out; 1595 if (!ttypull(tp)) 1596 goto out; 1597 1598 /* Grab the first contiguous region of buffer space. */ 1599 { 1600 u_char *tba; 1601 int tbc; 1602 1603 tba = tp->t_outq.c_cf; 1604 tbc = ndqb(&tp->t_outq, 0); 1605 1606 mutex_spin_enter(&sc->sc_lock); 1607 1608 sc->sc_tba = tba; 1609 sc->sc_tbc = tbc; 1610 } 1611 1612 SET(tp->t_state, TS_BUSY); 1613 sc->sc_tx_busy = 1; 1614 1615 /* Enable transmit completion interrupts if necessary. */ 1616 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1617 SET(sc->sc_ier, IER_ETXRDY); 1618 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1619 } 1620 1621 /* Output the first chunk of the contiguous buffer. */ 1622 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1623 u_int n; 1624 1625 n = sc->sc_tbc; 1626 if (n > sc->sc_fifolen) 1627 n = sc->sc_fifolen; 1628 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1629 sc->sc_tbc -= n; 1630 sc->sc_tba += n; 1631 } 1632 1633 mutex_spin_exit(&sc->sc_lock); 1634 out: 1635 splx(s); 1636 return; 1637 } 1638 1639 /* 1640 * Stop output on a line. 1641 */ 1642 void 1643 comstop(struct tty *tp, int flag) 1644 { 1645 struct com_softc *sc = 1646 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1647 1648 mutex_spin_enter(&sc->sc_lock); 1649 if (ISSET(tp->t_state, TS_BUSY)) { 1650 /* Stop transmitting at the next chunk. */ 1651 sc->sc_tbc = 0; 1652 sc->sc_heldtbc = 0; 1653 if (!ISSET(tp->t_state, TS_TTSTOP)) 1654 SET(tp->t_state, TS_FLUSH); 1655 } 1656 mutex_spin_exit(&sc->sc_lock); 1657 } 1658 1659 void 1660 comdiag(void *arg) 1661 { 1662 struct com_softc *sc = arg; 1663 int overflows, floods; 1664 1665 mutex_spin_enter(&sc->sc_lock); 1666 overflows = sc->sc_overflows; 1667 sc->sc_overflows = 0; 1668 floods = sc->sc_floods; 1669 sc->sc_floods = 0; 1670 sc->sc_errors = 0; 1671 mutex_spin_exit(&sc->sc_lock); 1672 1673 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1674 device_xname(sc->sc_dev), 1675 overflows, overflows == 1 ? "" : "s", 1676 floods, floods == 1 ? "" : "s"); 1677 } 1678 1679 integrate void 1680 com_rxsoft(struct com_softc *sc, struct tty *tp) 1681 { 1682 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1683 u_char *get, *end; 1684 u_int cc, scc; 1685 u_char lsr; 1686 int code; 1687 1688 end = sc->sc_ebuf; 1689 get = sc->sc_rbget; 1690 scc = cc = com_rbuf_size - sc->sc_rbavail; 1691 1692 if (cc == com_rbuf_size) { 1693 sc->sc_floods++; 1694 if (sc->sc_errors++ == 0) 1695 callout_reset(&sc->sc_diag_callout, 60 * hz, 1696 comdiag, sc); 1697 } 1698 1699 /* If not yet open, drop the entire buffer content here */ 1700 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1701 get += cc << 1; 1702 if (get >= end) 1703 get -= com_rbuf_size << 1; 1704 cc = 0; 1705 } 1706 while (cc) { 1707 code = get[0]; 1708 lsr = get[1]; 1709 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1710 if (ISSET(lsr, LSR_OE)) { 1711 sc->sc_overflows++; 1712 if (sc->sc_errors++ == 0) 1713 callout_reset(&sc->sc_diag_callout, 1714 60 * hz, comdiag, sc); 1715 } 1716 if (ISSET(lsr, LSR_BI | LSR_FE)) 1717 SET(code, TTY_FE); 1718 if (ISSET(lsr, LSR_PE)) 1719 SET(code, TTY_PE); 1720 } 1721 if ((*rint)(code, tp) == -1) { 1722 /* 1723 * The line discipline's buffer is out of space. 1724 */ 1725 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1726 /* 1727 * We're either not using flow control, or the 1728 * line discipline didn't tell us to block for 1729 * some reason. Either way, we have no way to 1730 * know when there's more space available, so 1731 * just drop the rest of the data. 1732 */ 1733 get += cc << 1; 1734 if (get >= end) 1735 get -= com_rbuf_size << 1; 1736 cc = 0; 1737 } else { 1738 /* 1739 * Don't schedule any more receive processing 1740 * until the line discipline tells us there's 1741 * space available (through comhwiflow()). 1742 * Leave the rest of the data in the input 1743 * buffer. 1744 */ 1745 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1746 } 1747 break; 1748 } 1749 get += 2; 1750 if (get >= end) 1751 get = sc->sc_rbuf; 1752 cc--; 1753 } 1754 1755 if (cc != scc) { 1756 sc->sc_rbget = get; 1757 mutex_spin_enter(&sc->sc_lock); 1758 1759 cc = sc->sc_rbavail += scc - cc; 1760 /* Buffers should be ok again, release possible block. */ 1761 if (cc >= sc->sc_r_lowat) { 1762 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1763 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1764 SET(sc->sc_ier, IER_ERXRDY); 1765 #ifdef COM_PXA2X0 1766 if (sc->sc_type == COM_TYPE_PXA2x0) 1767 SET(sc->sc_ier, IER_ERXTOUT); 1768 #endif 1769 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1770 } 1771 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1772 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1773 com_hwiflow(sc); 1774 } 1775 } 1776 mutex_spin_exit(&sc->sc_lock); 1777 } 1778 } 1779 1780 integrate void 1781 com_txsoft(struct com_softc *sc, struct tty *tp) 1782 { 1783 1784 CLR(tp->t_state, TS_BUSY); 1785 if (ISSET(tp->t_state, TS_FLUSH)) 1786 CLR(tp->t_state, TS_FLUSH); 1787 else 1788 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1789 (*tp->t_linesw->l_start)(tp); 1790 } 1791 1792 integrate void 1793 com_stsoft(struct com_softc *sc, struct tty *tp) 1794 { 1795 u_char msr, delta; 1796 1797 mutex_spin_enter(&sc->sc_lock); 1798 msr = sc->sc_msr; 1799 delta = sc->sc_msr_delta; 1800 sc->sc_msr_delta = 0; 1801 mutex_spin_exit(&sc->sc_lock); 1802 1803 if (ISSET(delta, sc->sc_msr_dcd)) { 1804 /* 1805 * Inform the tty layer that carrier detect changed. 1806 */ 1807 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1808 } 1809 1810 if (ISSET(delta, sc->sc_msr_cts)) { 1811 /* Block or unblock output according to flow control. */ 1812 if (ISSET(msr, sc->sc_msr_cts)) { 1813 sc->sc_tx_stopped = 0; 1814 (*tp->t_linesw->l_start)(tp); 1815 } else { 1816 sc->sc_tx_stopped = 1; 1817 } 1818 } 1819 1820 #ifdef COM_DEBUG 1821 if (com_debug) 1822 comstatus(sc, "com_stsoft"); 1823 #endif 1824 } 1825 1826 void 1827 comsoft(void *arg) 1828 { 1829 struct com_softc *sc = arg; 1830 struct tty *tp; 1831 1832 if (COM_ISALIVE(sc) == 0) 1833 return; 1834 1835 tp = sc->sc_tty; 1836 1837 if (sc->sc_rx_ready) { 1838 sc->sc_rx_ready = 0; 1839 com_rxsoft(sc, tp); 1840 } 1841 1842 if (sc->sc_st_check) { 1843 sc->sc_st_check = 0; 1844 com_stsoft(sc, tp); 1845 } 1846 1847 if (sc->sc_tx_done) { 1848 sc->sc_tx_done = 0; 1849 com_txsoft(sc, tp); 1850 } 1851 } 1852 1853 int 1854 comintr(void *arg) 1855 { 1856 struct com_softc *sc = arg; 1857 struct com_regs *regsp = &sc->sc_regs; 1858 1859 u_char *put, *end; 1860 u_int cc; 1861 u_char lsr, iir; 1862 1863 if (COM_ISALIVE(sc) == 0) 1864 return (0); 1865 1866 mutex_spin_enter(&sc->sc_lock); 1867 iir = CSR_READ_1(regsp, COM_REG_IIR); 1868 if (ISSET(iir, IIR_NOPEND)) { 1869 mutex_spin_exit(&sc->sc_lock); 1870 return (0); 1871 } 1872 1873 end = sc->sc_ebuf; 1874 put = sc->sc_rbput; 1875 cc = sc->sc_rbavail; 1876 1877 again: do { 1878 u_char msr, delta; 1879 1880 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1881 if (ISSET(lsr, LSR_BI)) { 1882 int cn_trapped = 0; 1883 1884 cn_check_magic(sc->sc_tty->t_dev, 1885 CNC_BREAK, com_cnm_state); 1886 if (cn_trapped) 1887 continue; 1888 #if defined(KGDB) && !defined(DDB) 1889 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1890 kgdb_connect(1); 1891 continue; 1892 } 1893 #endif 1894 } 1895 1896 if (ISSET(lsr, LSR_RCV_MASK) && 1897 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1898 while (cc > 0) { 1899 int cn_trapped = 0; 1900 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1901 put[1] = lsr; 1902 cn_check_magic(sc->sc_tty->t_dev, 1903 put[0], com_cnm_state); 1904 if (cn_trapped) 1905 goto next; 1906 put += 2; 1907 if (put >= end) 1908 put = sc->sc_rbuf; 1909 cc--; 1910 next: 1911 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1912 if (!ISSET(lsr, LSR_RCV_MASK)) 1913 break; 1914 } 1915 1916 /* 1917 * Current string of incoming characters ended because 1918 * no more data was available or we ran out of space. 1919 * Schedule a receive event if any data was received. 1920 * If we're out of space, turn off receive interrupts. 1921 */ 1922 sc->sc_rbput = put; 1923 sc->sc_rbavail = cc; 1924 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1925 sc->sc_rx_ready = 1; 1926 1927 /* 1928 * See if we are in danger of overflowing a buffer. If 1929 * so, use hardware flow control to ease the pressure. 1930 */ 1931 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1932 cc < sc->sc_r_hiwat) { 1933 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1934 com_hwiflow(sc); 1935 } 1936 1937 /* 1938 * If we're out of space, disable receive interrupts 1939 * until the queue has drained a bit. 1940 */ 1941 if (!cc) { 1942 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1943 #ifdef COM_PXA2X0 1944 if (sc->sc_type == COM_TYPE_PXA2x0) 1945 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 1946 else 1947 #endif 1948 CLR(sc->sc_ier, IER_ERXRDY); 1949 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1950 } 1951 } else { 1952 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 1953 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 1954 continue; 1955 } 1956 } 1957 1958 msr = CSR_READ_1(regsp, COM_REG_MSR); 1959 delta = msr ^ sc->sc_msr; 1960 sc->sc_msr = msr; 1961 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1962 (delta & MSR_DCD)) { 1963 mutex_spin_enter(&timecounter_lock); 1964 pps_capture(&sc->sc_pps_state); 1965 pps_event(&sc->sc_pps_state, 1966 (msr & MSR_DCD) ? 1967 PPS_CAPTUREASSERT : 1968 PPS_CAPTURECLEAR); 1969 mutex_spin_exit(&timecounter_lock); 1970 } 1971 1972 /* 1973 * Process normal status changes 1974 */ 1975 if (ISSET(delta, sc->sc_msr_mask)) { 1976 SET(sc->sc_msr_delta, delta); 1977 1978 /* 1979 * Stop output immediately if we lose the output 1980 * flow control signal or carrier detect. 1981 */ 1982 if (ISSET(~msr, sc->sc_msr_mask)) { 1983 sc->sc_tbc = 0; 1984 sc->sc_heldtbc = 0; 1985 #ifdef COM_DEBUG 1986 if (com_debug) 1987 comstatus(sc, "comintr "); 1988 #endif 1989 } 1990 1991 sc->sc_st_check = 1; 1992 } 1993 } while (!ISSET((iir = 1994 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 1995 /* 1996 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 1997 * by IIR read, so we can't do this way: `process all interrupts, 1998 * then do TX if possble'. 1999 */ 2000 (iir & IIR_IMASK) != IIR_TXRDY); 2001 2002 /* 2003 * Read LSR again, since there may be an interrupt between 2004 * the last LSR read and IIR read above. 2005 */ 2006 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2007 2008 /* 2009 * See if data can be transmitted as well. 2010 * Schedule tx done event if no data left 2011 * and tty was marked busy. 2012 */ 2013 if (ISSET(lsr, LSR_TXRDY)) { 2014 /* 2015 * If we've delayed a parameter change, do it now, and restart 2016 * output. 2017 */ 2018 if (sc->sc_heldchange) { 2019 com_loadchannelregs(sc); 2020 sc->sc_heldchange = 0; 2021 sc->sc_tbc = sc->sc_heldtbc; 2022 sc->sc_heldtbc = 0; 2023 } 2024 2025 /* Output the next chunk of the contiguous buffer, if any. */ 2026 if (sc->sc_tbc > 0) { 2027 u_int n; 2028 2029 n = sc->sc_tbc; 2030 if (n > sc->sc_fifolen) 2031 n = sc->sc_fifolen; 2032 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2033 sc->sc_tbc -= n; 2034 sc->sc_tba += n; 2035 } else { 2036 /* Disable transmit completion interrupts if necessary. */ 2037 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2038 CLR(sc->sc_ier, IER_ETXRDY); 2039 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2040 } 2041 if (sc->sc_tx_busy) { 2042 sc->sc_tx_busy = 0; 2043 sc->sc_tx_done = 1; 2044 } 2045 } 2046 } 2047 2048 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2049 goto again; 2050 2051 mutex_spin_exit(&sc->sc_lock); 2052 2053 /* Wake up the poller. */ 2054 softint_schedule(sc->sc_si); 2055 2056 #if NRND > 0 && defined(RND_COM) 2057 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2058 #endif 2059 2060 return (1); 2061 } 2062 2063 /* 2064 * The following functions are polled getc and putc routines, shared 2065 * by the console and kgdb glue. 2066 * 2067 * The read-ahead code is so that you can detect pending in-band 2068 * cn_magic in polled mode while doing output rather than having to 2069 * wait until the kernel decides it needs input. 2070 */ 2071 2072 #define MAX_READAHEAD 20 2073 static int com_readahead[MAX_READAHEAD]; 2074 static int com_readaheadcount = 0; 2075 2076 int 2077 com_common_getc(dev_t dev, struct com_regs *regsp) 2078 { 2079 int s = splserial(); 2080 u_char stat, c; 2081 2082 /* got a character from reading things earlier */ 2083 if (com_readaheadcount > 0) { 2084 int i; 2085 2086 c = com_readahead[0]; 2087 for (i = 1; i < com_readaheadcount; i++) { 2088 com_readahead[i-1] = com_readahead[i]; 2089 } 2090 com_readaheadcount--; 2091 splx(s); 2092 return (c); 2093 } 2094 2095 /* block until a character becomes available */ 2096 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2097 ; 2098 2099 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2100 stat = CSR_READ_1(regsp, COM_REG_IIR); 2101 { 2102 int cn_trapped = 0; /* unused */ 2103 #ifdef DDB 2104 extern int db_active; 2105 if (!db_active) 2106 #endif 2107 cn_check_magic(dev, c, com_cnm_state); 2108 } 2109 splx(s); 2110 return (c); 2111 } 2112 2113 void 2114 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2115 { 2116 int s = splserial(); 2117 int cin, stat, timo; 2118 2119 if (com_readaheadcount < MAX_READAHEAD 2120 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2121 int cn_trapped = 0; 2122 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2123 stat = CSR_READ_1(regsp, COM_REG_IIR); 2124 cn_check_magic(dev, cin, com_cnm_state); 2125 com_readahead[com_readaheadcount++] = cin; 2126 } 2127 2128 /* wait for any pending transmission to finish */ 2129 timo = 150000; 2130 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2131 continue; 2132 2133 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2134 COM_BARRIER(regsp, BR | BW); 2135 2136 splx(s); 2137 } 2138 2139 /* 2140 * Initialize UART for use as console or KGDB line. 2141 */ 2142 int 2143 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2144 tcflag_t cflag) 2145 { 2146 2147 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2148 ®sp->cr_ioh)) 2149 return (ENOMEM); /* ??? */ 2150 2151 if (type == COM_TYPE_OMAP) { 2152 /* disable before changing settings */ 2153 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2154 } 2155 2156 rate = comspeed(rate, frequency, type); 2157 if (type != COM_TYPE_AU1x00) { 2158 /* no EFR on alchemy */ 2159 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2160 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2161 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2162 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2163 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2164 } else { 2165 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2166 } 2167 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2168 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2169 CSR_WRITE_1(regsp, COM_REG_FIFO, 2170 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2171 2172 if (type == COM_TYPE_OMAP) { 2173 /* setup the fifos. the FCR value is not used as long 2174 as SCR[6] and SCR[7] are 0, which they are at reset 2175 and we never touch the SCR register */ 2176 uint8_t rx_fifo_trig = 40; 2177 uint8_t tx_fifo_trig = 60; 2178 uint8_t rx_start = 8; 2179 uint8_t rx_halt = 60; 2180 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2181 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2182 2183 /* enable access to TCR & TLR */ 2184 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2185 2186 /* write tcr and tlr values */ 2187 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2188 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2189 2190 /* disable access to TCR & TLR */ 2191 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2192 2193 /* enable again, but mode is based on speed */ 2194 if (rate > 230400) { 2195 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2196 } else { 2197 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2198 } 2199 } 2200 2201 #ifdef COM_PXA2X0 2202 if (type == COM_TYPE_PXA2x0) 2203 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2204 else 2205 #endif 2206 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2207 2208 return (0); 2209 } 2210 2211 /* 2212 * Following are all routines needed for COM to act as console 2213 */ 2214 struct consdev comcons = { 2215 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2216 NODEV, CN_NORMAL 2217 }; 2218 2219 2220 int 2221 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2222 tcflag_t cflag) 2223 { 2224 int res; 2225 2226 comconsregs = *regsp; 2227 2228 res = cominit(&comconsregs, rate, frequency, type, cflag); 2229 if (res) 2230 return (res); 2231 2232 cn_tab = &comcons; 2233 cn_init_magic(&com_cnm_state); 2234 cn_set_magic("\047\001"); /* default magic is BREAK */ 2235 2236 comconsrate = rate; 2237 comconscflag = cflag; 2238 2239 return (0); 2240 } 2241 2242 int 2243 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2244 int type, tcflag_t cflag) 2245 { 2246 struct com_regs regs; 2247 2248 memset(®s, 0, sizeof regs); 2249 regs.cr_iot = iot; 2250 regs.cr_iobase = iobase; 2251 regs.cr_nports = COM_NPORTS; 2252 #ifdef COM_REGMAP 2253 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2254 #endif 2255 2256 return comcnattach1(®s, rate, frequency, type, cflag); 2257 } 2258 2259 int 2260 comcngetc(dev_t dev) 2261 { 2262 2263 return (com_common_getc(dev, &comconsregs)); 2264 } 2265 2266 /* 2267 * Console kernel output character routine. 2268 */ 2269 void 2270 comcnputc(dev_t dev, int c) 2271 { 2272 2273 com_common_putc(dev, &comconsregs, c); 2274 } 2275 2276 void 2277 comcnpollc(dev_t dev, int on) 2278 { 2279 2280 } 2281 2282 #ifdef KGDB 2283 int 2284 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2285 tcflag_t cflag) 2286 { 2287 int res; 2288 2289 if (regsp->cr_iot == comconsregs.cr_iot && 2290 regsp->cr_iobase == comconsregs.cr_iobase) { 2291 #if !defined(DDB) 2292 return (EBUSY); /* cannot share with console */ 2293 #else 2294 comkgdbregs = *regsp; 2295 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2296 #endif 2297 } else { 2298 comkgdbregs = *regsp; 2299 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2300 if (res) 2301 return (res); 2302 2303 /* 2304 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2305 * expects this to be initialized 2306 */ 2307 cn_init_magic(&com_cnm_state); 2308 cn_set_magic("\047\001"); 2309 } 2310 2311 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2312 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2313 2314 return (0); 2315 } 2316 2317 int 2318 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2319 int frequency, int type, tcflag_t cflag) 2320 { 2321 struct com_regs regs; 2322 2323 regs.cr_iot = iot; 2324 regs.cr_nports = COM_NPORTS; 2325 regs.cr_iobase = iobase; 2326 #ifdef COM_REGMAP 2327 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2328 #endif 2329 2330 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2331 } 2332 2333 /* ARGSUSED */ 2334 int 2335 com_kgdb_getc(void *arg) 2336 { 2337 2338 return (com_common_getc(NODEV, &comkgdbregs)); 2339 } 2340 2341 /* ARGSUSED */ 2342 void 2343 com_kgdb_putc(void *arg, int c) 2344 { 2345 2346 com_common_putc(NODEV, &comkgdbregs, c); 2347 } 2348 #endif /* KGDB */ 2349 2350 /* helper function to identify the com ports used by 2351 console or KGDB (and not yet autoconf attached) */ 2352 int 2353 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2354 { 2355 bus_space_handle_t help; 2356 2357 if (!comconsattached && 2358 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2359 help = comconsregs.cr_ioh; 2360 #ifdef KGDB 2361 else if (!com_kgdb_attached && 2362 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2363 help = comkgdbregs.cr_ioh; 2364 #endif 2365 else 2366 return (0); 2367 2368 if (ioh) 2369 *ioh = help; 2370 return (1); 2371 } 2372 2373 /* 2374 * this routine exists to serve as a shutdown hook for systems that 2375 * have firmware which doesn't interact properly with a com device in 2376 * FIFO mode. 2377 */ 2378 bool 2379 com_cleanup(device_t self, int how) 2380 { 2381 struct com_softc *sc = device_private(self); 2382 2383 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2384 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2385 2386 return true; 2387 } 2388 2389 bool 2390 com_suspend(device_t self PMF_FN_ARGS) 2391 { 2392 struct com_softc *sc = device_private(self); 2393 2394 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2395 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2396 2397 return true; 2398 } 2399 2400 bool 2401 com_resume(device_t self PMF_FN_ARGS) 2402 { 2403 struct com_softc *sc = device_private(self); 2404 2405 mutex_spin_enter(&sc->sc_lock); 2406 com_loadchannelregs(sc); 2407 mutex_spin_exit(&sc->sc_lock); 2408 2409 return true; 2410 } 2411
Indexes created Wed Sep 24 15:09:51 GMT 2025