com.c revision 1.281.2.1
1 /* com.c,v 1.262.2.3 2008/01/09 01:52:50 matt Exp */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "com.c,v 1.262.2.3 2008/01/09 01:52:50 matt Exp"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 #if NRND > 0 && defined(RND_COM) 80 #include <sys/rnd.h> 81 #endif 82 83 /* The COM16650 option was renamed to COM_16650. */ 84 #ifdef COM16650 85 #error Obsolete COM16650 option; use COM_16650 instead. 86 #endif 87 88 /* 89 * Override cnmagic(9) macro before including <sys/systm.h>. 90 * We need to know if cn_check_magic triggered debugger, so set a flag. 91 * Callers of cn_check_magic must declare int cn_trapped = 0; 92 * XXX: this is *ugly*! 93 */ 94 #define cn_trap() \ 95 do { \ 96 console_debugger(); \ 97 cn_trapped = 1; \ 98 } while (/* CONSTCOND */ 0) 99 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/ioctl.h> 103 #include <sys/select.h> 104 #include <sys/poll.h> 105 #include <sys/tty.h> 106 #include <sys/proc.h> 107 #include <sys/user.h> 108 #include <sys/conf.h> 109 #include <sys/file.h> 110 #include <sys/uio.h> 111 #include <sys/kernel.h> 112 #include <sys/syslog.h> 113 #include <sys/device.h> 114 #include <sys/malloc.h> 115 #include <sys/timepps.h> 116 #include <sys/vnode.h> 117 #include <sys/kauth.h> 118 #include <sys/intr.h> 119 120 #include <sys/bus.h> 121 122 #include <dev/ic/comreg.h> 123 #include <dev/ic/comvar.h> 124 #include <dev/ic/ns16550reg.h> 125 #include <dev/ic/st16650reg.h> 126 #ifdef COM_HAYESP 127 #include <dev/ic/hayespreg.h> 128 #endif 129 #define com_lcr com_cfcr 130 #include <dev/cons.h> 131 132 #ifdef COM_REGMAP 133 #define CSR_WRITE_1(r, o, v) \ 134 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 135 #define CSR_READ_1(r, o) \ 136 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 137 #define CSR_WRITE_2(r, o, v) \ 138 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 139 #define CSR_READ_2(r, o) \ 140 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 141 #define CSR_WRITE_MULTI(r, o, p, n) \ 142 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 143 #else 144 #define CSR_WRITE_1(r, o, v) \ 145 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 146 #define CSR_READ_1(r, o) \ 147 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 148 #define CSR_WRITE_2(r, o, v) \ 149 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 150 #define CSR_READ_2(r, o) \ 151 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 152 #define CSR_WRITE_MULTI(r, o, p, n) \ 153 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 154 #endif 155 156 157 static void com_enable_debugport(struct com_softc *); 158 159 void com_config(struct com_softc *); 160 void com_shutdown(struct com_softc *); 161 int comspeed(long, long, int); 162 static u_char cflag2lcr(tcflag_t); 163 int comparam(struct tty *, struct termios *); 164 void comstart(struct tty *); 165 int comhwiflow(struct tty *, int); 166 167 void com_loadchannelregs(struct com_softc *); 168 void com_hwiflow(struct com_softc *); 169 void com_break(struct com_softc *, int); 170 void com_modem(struct com_softc *, int); 171 void tiocm_to_com(struct com_softc *, u_long, int); 172 int com_to_tiocm(struct com_softc *); 173 void com_iflush(struct com_softc *); 174 175 int com_common_getc(dev_t, struct com_regs *); 176 void com_common_putc(dev_t, struct com_regs *, int); 177 178 int cominit(struct com_regs *, int, int, int, tcflag_t); 179 180 int comcngetc(dev_t); 181 void comcnputc(dev_t, int); 182 void comcnpollc(dev_t, int); 183 184 #define integrate static inline 185 void comsoft(void *); 186 integrate void com_rxsoft(struct com_softc *, struct tty *); 187 integrate void com_txsoft(struct com_softc *, struct tty *); 188 integrate void com_stsoft(struct com_softc *, struct tty *); 189 integrate void com_schedrx(struct com_softc *); 190 void comdiag(void *); 191 192 extern struct cfdriver com_cd; 193 194 dev_type_open(comopen); 195 dev_type_close(comclose); 196 dev_type_read(comread); 197 dev_type_write(comwrite); 198 dev_type_ioctl(comioctl); 199 dev_type_stop(comstop); 200 dev_type_tty(comtty); 201 dev_type_poll(compoll); 202 203 const struct cdevsw com_cdevsw = { 204 comopen, comclose, comread, comwrite, comioctl, 205 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 206 }; 207 208 /* 209 * Make this an option variable one can patch. 210 * But be warned: this must be a power of 2! 211 */ 212 u_int com_rbuf_size = COM_RING_SIZE; 213 214 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 215 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 216 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 217 218 static struct com_regs comconsregs; 219 static int comconsattached; 220 static int comconsrate; 221 static tcflag_t comconscflag; 222 static struct cnm_state com_cnm_state; 223 224 #ifdef KGDB 225 #include <sys/kgdb.h> 226 227 static struct com_regs comkgdbregs; 228 static int com_kgdb_attached; 229 230 int com_kgdb_getc(void *); 231 void com_kgdb_putc(void *, int); 232 #endif /* KGDB */ 233 234 #ifdef COM_REGMAP 235 /* initializer for typical 16550-ish hardware */ 236 #define COM_REG_16550 { \ 237 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 238 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 239 240 const bus_size_t com_std_map[16] = COM_REG_16550; 241 #endif /* COM_REGMAP */ 242 243 #define COMUNIT_MASK 0x7ffff 244 #define COMDIALOUT_MASK 0x80000 245 246 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 247 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 248 249 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 250 device_is_active((sc)->sc_dev)) 251 252 #define BR BUS_SPACE_BARRIER_READ 253 #define BW BUS_SPACE_BARRIER_WRITE 254 #define COM_BARRIER(r, f) \ 255 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 256 257 /*ARGSUSED*/ 258 int 259 comspeed(long speed, long frequency, int type) 260 { 261 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 262 263 int x, err; 264 int divisor = 16; 265 266 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 267 divisor = 13; 268 } 269 270 #if 0 271 if (speed == 0) 272 return (0); 273 #endif 274 if (speed <= 0) 275 return (-1); 276 x = divrnd(frequency / divisor, speed); 277 if (x <= 0) 278 return (-1); 279 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 280 if (err < 0) 281 err = -err; 282 if (err > COM_TOLERANCE) 283 return (-1); 284 return (x); 285 286 #undef divrnd 287 } 288 289 #ifdef COM_DEBUG 290 int com_debug = 0; 291 292 void comstatus(struct com_softc *, const char *); 293 void 294 comstatus(struct com_softc *sc, const char *str) 295 { 296 struct tty *tp = sc->sc_tty; 297 298 aprint_normal_dev(sc->sc_dev, 299 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 300 str, 301 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 302 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 303 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 304 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 305 sc->sc_tx_stopped ? '+' : '-'); 306 307 aprint_normal_dev(sc->sc_dev, 308 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 309 str, 310 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 311 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 312 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 313 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 314 sc->sc_rx_flags); 315 } 316 #endif 317 318 int 319 com_probe_subr(struct com_regs *regs) 320 { 321 322 /* force access to id reg */ 323 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 324 CSR_WRITE_1(regs, COM_REG_IIR, 0); 325 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 326 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 327 return (0); 328 329 return (1); 330 } 331 332 int 333 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 334 { 335 struct com_regs regs; 336 337 regs.cr_iot = iot; 338 regs.cr_ioh = ioh; 339 #ifdef COM_REGMAP 340 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 341 #endif 342 343 return com_probe_subr(®s); 344 } 345 346 /* 347 * No locking in this routine; it is only called during attach, 348 * or with the port already locked. 349 */ 350 static void 351 com_enable_debugport(struct com_softc *sc) 352 { 353 354 /* Turn on line break interrupt, set carrier. */ 355 sc->sc_ier = IER_ERXRDY; 356 if (sc->sc_type == COM_TYPE_PXA2x0) 357 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 358 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 359 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 360 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 361 } 362 363 void 364 com_attach_subr(struct com_softc *sc) 365 { 366 struct com_regs *regsp = &sc->sc_regs; 367 struct tty *tp; 368 #ifdef COM_16650 369 u_int8_t lcr; 370 #endif 371 const char *fifo_msg = NULL; 372 373 aprint_naive("\n"); 374 375 callout_init(&sc->sc_diag_callout, 0); 376 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 377 378 /* Disable interrupts before configuring the device. */ 379 if (sc->sc_type == COM_TYPE_PXA2x0) 380 sc->sc_ier = IER_EUART; 381 else 382 sc->sc_ier = 0; 383 384 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 385 386 if (regsp->cr_iot == comconsregs.cr_iot && 387 regsp->cr_iobase == comconsregs.cr_iobase) { 388 comconsattached = 1; 389 390 /* Make sure the console is always "hardwired". */ 391 delay(10000); /* wait for output to finish */ 392 SET(sc->sc_hwflags, COM_HW_CONSOLE); 393 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 394 } 395 396 /* Probe for FIFO */ 397 switch (sc->sc_type) { 398 case COM_TYPE_HAYESP: 399 goto fifodone; 400 401 case COM_TYPE_AU1x00: 402 sc->sc_fifolen = 16; 403 fifo_msg = "Au1X00 UART, working fifo"; 404 SET(sc->sc_hwflags, COM_HW_FIFO); 405 goto fifodelay; 406 407 case COM_TYPE_OMAP: 408 sc->sc_fifolen = 64; 409 fifo_msg = "OMAP UART, working fifo"; 410 SET(sc->sc_hwflags, COM_HW_FIFO); 411 goto fifodelay; 412 } 413 414 sc->sc_fifolen = 1; 415 /* look for a NS 16550AF UART with FIFOs */ 416 CSR_WRITE_1(regsp, COM_REG_FIFO, 417 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 418 delay(100); 419 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 420 == IIR_FIFO_MASK) 421 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 422 == FIFO_TRIGGER_14) { 423 SET(sc->sc_hwflags, COM_HW_FIFO); 424 425 #ifdef COM_16650 426 /* 427 * IIR changes into the EFR if LCR is set to LCR_EERS 428 * on 16650s. We also know IIR != 0 at this point. 429 * Write 0 into the EFR, and read it. If the result 430 * is 0, we have a 16650. 431 * 432 * Older 16650s were broken; the test to detect them 433 * is taken from the Linux driver. Apparently 434 * setting DLAB enable gives access to the EFR on 435 * these chips. 436 */ 437 lcr = CSR_READ_1(regsp, COM_REG_LCR); 438 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 439 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 440 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 441 CSR_WRITE_1(regsp, COM_REG_LCR, 442 lcr | LCR_DLAB); 443 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 444 CLR(sc->sc_hwflags, COM_HW_FIFO); 445 sc->sc_fifolen = 0; 446 } else { 447 SET(sc->sc_hwflags, COM_HW_FLOW); 448 sc->sc_fifolen = 32; 449 } 450 } else 451 #endif 452 sc->sc_fifolen = 16; 453 454 #ifdef COM_16650 455 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 456 if (sc->sc_fifolen == 0) 457 fifo_msg = "st16650, broken fifo"; 458 else if (sc->sc_fifolen == 32) 459 fifo_msg = "st16650a, working fifo"; 460 else 461 #endif 462 fifo_msg = "ns16550a, working fifo"; 463 } else 464 fifo_msg = "ns16550, broken fifo"; 465 else 466 fifo_msg = "ns8250 or ns16450, no fifo"; 467 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 468 fifodelay: 469 /* 470 * Some chips will clear down both Tx and Rx FIFOs when zero is 471 * written to com_fifo. If this chip is the console, writing zero 472 * results in some of the chip/FIFO description being lost, so delay 473 * printing it until now. 474 */ 475 delay(10); 476 aprint_normal(": %s\n", fifo_msg); 477 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 478 sc->sc_fifolen = 1; 479 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 480 } 481 482 fifodone: 483 484 tp = ttymalloc(); 485 tp->t_oproc = comstart; 486 tp->t_param = comparam; 487 tp->t_hwiflow = comhwiflow; 488 489 sc->sc_tty = tp; 490 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 491 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 492 sc->sc_rbavail = com_rbuf_size; 493 if (sc->sc_rbuf == NULL) { 494 aprint_error_dev(sc->sc_dev, 495 "unable to allocate ring buffer\n"); 496 return; 497 } 498 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 499 500 tty_attach(tp); 501 502 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 503 SET(sc->sc_mcr, MCR_IENABLE); 504 505 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 506 int maj; 507 508 /* locate the major number */ 509 maj = cdevsw_lookup_major(&com_cdevsw); 510 511 tp->t_dev = cn_tab->cn_dev = makedev(maj, 512 device_unit(sc->sc_dev)); 513 514 aprint_normal_dev(sc->sc_dev, "console\n"); 515 } 516 517 #ifdef KGDB 518 /* 519 * Allow kgdb to "take over" this port. If this is 520 * not the console and is the kgdb device, it has 521 * exclusive use. If it's the console _and_ the 522 * kgdb device, it doesn't. 523 */ 524 if (regsp->cr_iot == comkgdbregs.cr_iot && 525 regsp->cr_iobase == comkgdbregs.cr_iobase) { 526 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 527 com_kgdb_attached = 1; 528 529 SET(sc->sc_hwflags, COM_HW_KGDB); 530 } 531 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 532 } 533 #endif 534 535 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 536 537 #if NRND > 0 && defined(RND_COM) 538 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 539 RND_TYPE_TTY, 0); 540 #endif 541 542 /* if there are no enable/disable functions, assume the device 543 is always enabled */ 544 if (!sc->enable) 545 sc->enabled = 1; 546 547 com_config(sc); 548 549 SET(sc->sc_hwflags, COM_HW_DEV_OK); 550 } 551 552 void 553 com_config(struct com_softc *sc) 554 { 555 struct com_regs *regsp = &sc->sc_regs; 556 557 /* Disable interrupts before configuring the device. */ 558 if (sc->sc_type == COM_TYPE_PXA2x0) 559 sc->sc_ier = IER_EUART; 560 else 561 sc->sc_ier = 0; 562 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 563 (void) CSR_READ_1(regsp, COM_REG_IIR); 564 565 #ifdef COM_HAYESP 566 /* Look for a Hayes ESP board. */ 567 if (sc->sc_type == COM_TYPE_HAYESP) { 568 569 /* Set 16550 compatibility mode */ 570 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 571 HAYESP_SETMODE); 572 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 573 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 574 HAYESP_MODE_SCALE); 575 576 /* Set RTS/CTS flow control */ 577 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 578 HAYESP_SETFLOWTYPE); 579 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 580 HAYESP_FLOW_RTS); 581 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 582 HAYESP_FLOW_CTS); 583 584 /* Set flow control levels */ 585 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 586 HAYESP_SETRXFLOW); 587 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 588 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 589 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 590 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 591 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 592 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 593 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 594 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 595 } 596 #endif 597 598 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 599 com_enable_debugport(sc); 600 } 601 602 int 603 com_detach(device_t self, int flags) 604 { 605 struct com_softc *sc = device_private(self); 606 int maj, mn; 607 608 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 609 return EBUSY; 610 611 /* locate the major number */ 612 maj = cdevsw_lookup_major(&com_cdevsw); 613 614 /* Nuke the vnodes for any open instances. */ 615 mn = device_unit(self); 616 vdevgone(maj, mn, mn, VCHR); 617 618 mn |= COMDIALOUT_MASK; 619 vdevgone(maj, mn, mn, VCHR); 620 621 if (sc->sc_rbuf == NULL) { 622 /* 623 * Ring buffer allocation failed in the com_attach_subr, 624 * only the tty is allocated, and nothing else. 625 */ 626 ttyfree(sc->sc_tty); 627 return 0; 628 } 629 630 /* Free the receive buffer. */ 631 free(sc->sc_rbuf, M_DEVBUF); 632 633 /* Detach and free the tty. */ 634 tty_detach(sc->sc_tty); 635 ttyfree(sc->sc_tty); 636 637 /* Unhook the soft interrupt handler. */ 638 softint_disestablish(sc->sc_si); 639 640 #if NRND > 0 && defined(RND_COM) 641 /* Unhook the entropy source. */ 642 rnd_detach_source(&sc->rnd_source); 643 #endif 644 callout_destroy(&sc->sc_diag_callout); 645 646 /* Destroy the lock. */ 647 mutex_destroy(&sc->sc_lock); 648 649 return (0); 650 } 651 652 int 653 com_activate(device_t self, enum devact act) 654 { 655 struct com_softc *sc = device_private(self); 656 int rv = 0; 657 658 switch (act) { 659 case DVACT_ACTIVATE: 660 rv = EOPNOTSUPP; 661 break; 662 663 case DVACT_DEACTIVATE: 664 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 665 rv = EBUSY; 666 break; 667 } 668 669 if (sc->disable != NULL && sc->enabled != 0) { 670 (*sc->disable)(sc); 671 sc->enabled = 0; 672 } 673 break; 674 } 675 676 return (rv); 677 } 678 679 void 680 com_shutdown(struct com_softc *sc) 681 { 682 struct tty *tp = sc->sc_tty; 683 684 mutex_spin_enter(&sc->sc_lock); 685 686 /* If we were asserting flow control, then deassert it. */ 687 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 688 com_hwiflow(sc); 689 690 /* Clear any break condition set with TIOCSBRK. */ 691 com_break(sc, 0); 692 693 /* 694 * Hang up if necessary. Wait a bit, so the other side has time to 695 * notice even if we immediately open the port again. 696 * Avoid tsleeping above splhigh(). 697 */ 698 if (ISSET(tp->t_cflag, HUPCL)) { 699 com_modem(sc, 0); 700 mutex_spin_exit(&sc->sc_lock); 701 /* XXX will only timeout */ 702 (void) kpause(ttclos, false, hz, NULL); 703 mutex_spin_enter(&sc->sc_lock); 704 } 705 706 /* Turn off interrupts. */ 707 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 708 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 709 if (sc->sc_type == COM_TYPE_PXA2x0) 710 sc->sc_ier |= IER_ERXTOUT; 711 } else 712 sc->sc_ier = 0; 713 714 if (sc->sc_type == COM_TYPE_PXA2x0) 715 sc->sc_ier |= IER_EUART; 716 717 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 718 719 mutex_spin_exit(&sc->sc_lock); 720 721 if (sc->disable) { 722 #ifdef DIAGNOSTIC 723 if (!sc->enabled) 724 panic("com_shutdown: not enabled?"); 725 #endif 726 (*sc->disable)(sc); 727 sc->enabled = 0; 728 } 729 } 730 731 int 732 comopen(dev_t dev, int flag, int mode, struct lwp *l) 733 { 734 struct com_softc *sc; 735 struct tty *tp; 736 int s; 737 int error; 738 739 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 740 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 741 sc->sc_rbuf == NULL) 742 return (ENXIO); 743 744 if (!device_is_active(sc->sc_dev)) 745 return (ENXIO); 746 747 #ifdef KGDB 748 /* 749 * If this is the kgdb port, no other use is permitted. 750 */ 751 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 752 return (EBUSY); 753 #endif 754 755 tp = sc->sc_tty; 756 757 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 758 return (EBUSY); 759 760 s = spltty(); 761 762 /* 763 * Do the following iff this is a first open. 764 */ 765 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 766 struct termios t; 767 768 tp->t_dev = dev; 769 770 771 if (sc->enable) { 772 if ((*sc->enable)(sc)) { 773 splx(s); 774 aprint_error_dev(sc->sc_dev, 775 "device enable failed\n"); 776 return (EIO); 777 } 778 mutex_spin_enter(&sc->sc_lock); 779 sc->enabled = 1; 780 com_config(sc); 781 } else { 782 mutex_spin_enter(&sc->sc_lock); 783 } 784 785 /* Turn on interrupts. */ 786 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 787 if (sc->sc_type == COM_TYPE_PXA2x0) 788 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 789 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 790 791 /* Fetch the current modem control status, needed later. */ 792 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 793 794 /* Clear PPS capture state on first open. */ 795 mutex_spin_enter(&timecounter_lock); 796 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 797 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 798 pps_init(&sc->sc_pps_state); 799 mutex_spin_exit(&timecounter_lock); 800 801 mutex_spin_exit(&sc->sc_lock); 802 803 /* 804 * Initialize the termios status to the defaults. Add in the 805 * sticky bits from TIOCSFLAGS. 806 */ 807 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 808 t.c_ospeed = comconsrate; 809 t.c_cflag = comconscflag; 810 } else { 811 t.c_ospeed = TTYDEF_SPEED; 812 t.c_cflag = TTYDEF_CFLAG; 813 } 814 t.c_ispeed = t.c_ospeed; 815 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 816 SET(t.c_cflag, CLOCAL); 817 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 818 SET(t.c_cflag, CRTSCTS); 819 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 820 SET(t.c_cflag, MDMBUF); 821 /* Make sure comparam() will do something. */ 822 tp->t_ospeed = 0; 823 (void) comparam(tp, &t); 824 tp->t_iflag = TTYDEF_IFLAG; 825 tp->t_oflag = TTYDEF_OFLAG; 826 tp->t_lflag = TTYDEF_LFLAG; 827 ttychars(tp); 828 ttsetwater(tp); 829 830 mutex_spin_enter(&sc->sc_lock); 831 832 /* 833 * Turn on DTR. We must always do this, even if carrier is not 834 * present, because otherwise we'd have to use TIOCSDTR 835 * immediately after setting CLOCAL, which applications do not 836 * expect. We always assert DTR while the device is open 837 * unless explicitly requested to deassert it. 838 */ 839 com_modem(sc, 1); 840 841 /* Clear the input ring, and unblock. */ 842 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 843 sc->sc_rbavail = com_rbuf_size; 844 com_iflush(sc); 845 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 846 com_hwiflow(sc); 847 848 #ifdef COM_DEBUG 849 if (com_debug) 850 comstatus(sc, "comopen "); 851 #endif 852 853 mutex_spin_exit(&sc->sc_lock); 854 } 855 856 splx(s); 857 858 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 859 if (error) 860 goto bad; 861 862 error = (*tp->t_linesw->l_open)(dev, tp); 863 if (error) 864 goto bad; 865 866 return (0); 867 868 bad: 869 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 870 /* 871 * We failed to open the device, and nobody else had it opened. 872 * Clean up the state as appropriate. 873 */ 874 com_shutdown(sc); 875 } 876 877 return (error); 878 } 879 880 int 881 comclose(dev_t dev, int flag, int mode, struct lwp *l) 882 { 883 struct com_softc *sc = 884 device_lookup_private(&com_cd, COMUNIT(dev)); 885 struct tty *tp = sc->sc_tty; 886 887 /* XXX This is for cons.c. */ 888 if (!ISSET(tp->t_state, TS_ISOPEN)) 889 return (0); 890 891 (*tp->t_linesw->l_close)(tp, flag); 892 ttyclose(tp); 893 894 if (COM_ISALIVE(sc) == 0) 895 return (0); 896 897 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 898 /* 899 * Although we got a last close, the device may still be in 900 * use; e.g. if this was the dialout node, and there are still 901 * processes waiting for carrier on the non-dialout node. 902 */ 903 com_shutdown(sc); 904 } 905 906 return (0); 907 } 908 909 int 910 comread(dev_t dev, struct uio *uio, int flag) 911 { 912 struct com_softc *sc = 913 device_lookup_private(&com_cd, COMUNIT(dev)); 914 struct tty *tp = sc->sc_tty; 915 916 if (COM_ISALIVE(sc) == 0) 917 return (EIO); 918 919 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 920 } 921 922 int 923 comwrite(dev_t dev, struct uio *uio, int flag) 924 { 925 struct com_softc *sc = 926 device_lookup_private(&com_cd, COMUNIT(dev)); 927 struct tty *tp = sc->sc_tty; 928 929 if (COM_ISALIVE(sc) == 0) 930 return (EIO); 931 932 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 933 } 934 935 int 936 compoll(dev_t dev, int events, struct lwp *l) 937 { 938 struct com_softc *sc = 939 device_lookup_private(&com_cd, COMUNIT(dev)); 940 struct tty *tp = sc->sc_tty; 941 942 if (COM_ISALIVE(sc) == 0) 943 return (POLLHUP); 944 945 return ((*tp->t_linesw->l_poll)(tp, events, l)); 946 } 947 948 struct tty * 949 comtty(dev_t dev) 950 { 951 struct com_softc *sc = 952 device_lookup_private(&com_cd, COMUNIT(dev)); 953 struct tty *tp = sc->sc_tty; 954 955 return (tp); 956 } 957 958 int 959 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 960 { 961 struct com_softc *sc; 962 struct tty *tp; 963 int error; 964 965 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 966 if (sc == NULL) 967 return ENXIO; 968 if (COM_ISALIVE(sc) == 0) 969 return (EIO); 970 971 tp = sc->sc_tty; 972 973 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 974 if (error != EPASSTHROUGH) 975 return (error); 976 977 error = ttioctl(tp, cmd, data, flag, l); 978 if (error != EPASSTHROUGH) 979 return (error); 980 981 error = 0; 982 switch (cmd) { 983 case TIOCSFLAGS: 984 error = kauth_authorize_device_tty(l->l_cred, 985 KAUTH_DEVICE_TTY_PRIVSET, tp); 986 break; 987 default: 988 /* nothing */ 989 break; 990 } 991 if (error) { 992 return error; 993 } 994 995 mutex_spin_enter(&sc->sc_lock); 996 997 switch (cmd) { 998 case TIOCSBRK: 999 com_break(sc, 1); 1000 break; 1001 1002 case TIOCCBRK: 1003 com_break(sc, 0); 1004 break; 1005 1006 case TIOCSDTR: 1007 com_modem(sc, 1); 1008 break; 1009 1010 case TIOCCDTR: 1011 com_modem(sc, 0); 1012 break; 1013 1014 case TIOCGFLAGS: 1015 *(int *)data = sc->sc_swflags; 1016 break; 1017 1018 case TIOCSFLAGS: 1019 sc->sc_swflags = *(int *)data; 1020 break; 1021 1022 case TIOCMSET: 1023 case TIOCMBIS: 1024 case TIOCMBIC: 1025 tiocm_to_com(sc, cmd, *(int *)data); 1026 break; 1027 1028 case TIOCMGET: 1029 *(int *)data = com_to_tiocm(sc); 1030 break; 1031 1032 case PPS_IOC_CREATE: 1033 case PPS_IOC_DESTROY: 1034 case PPS_IOC_GETPARAMS: 1035 case PPS_IOC_SETPARAMS: 1036 case PPS_IOC_GETCAP: 1037 case PPS_IOC_FETCH: 1038 #ifdef PPS_SYNC 1039 case PPS_IOC_KCBIND: 1040 #endif 1041 mutex_spin_enter(&timecounter_lock); 1042 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1043 mutex_spin_exit(&timecounter_lock); 1044 break; 1045 1046 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1047 mutex_spin_enter(&timecounter_lock); 1048 #ifndef PPS_TRAILING_EDGE 1049 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1050 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1051 #else 1052 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1053 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1054 #endif 1055 mutex_spin_exit(&timecounter_lock); 1056 break; 1057 1058 default: 1059 error = EPASSTHROUGH; 1060 break; 1061 } 1062 1063 mutex_spin_exit(&sc->sc_lock); 1064 1065 #ifdef COM_DEBUG 1066 if (com_debug) 1067 comstatus(sc, "comioctl "); 1068 #endif 1069 1070 return (error); 1071 } 1072 1073 integrate void 1074 com_schedrx(struct com_softc *sc) 1075 { 1076 1077 sc->sc_rx_ready = 1; 1078 1079 /* Wake up the poller. */ 1080 softint_schedule(sc->sc_si); 1081 } 1082 1083 void 1084 com_break(struct com_softc *sc, int onoff) 1085 { 1086 1087 if (onoff) 1088 SET(sc->sc_lcr, LCR_SBREAK); 1089 else 1090 CLR(sc->sc_lcr, LCR_SBREAK); 1091 1092 if (!sc->sc_heldchange) { 1093 if (sc->sc_tx_busy) { 1094 sc->sc_heldtbc = sc->sc_tbc; 1095 sc->sc_tbc = 0; 1096 sc->sc_heldchange = 1; 1097 } else 1098 com_loadchannelregs(sc); 1099 } 1100 } 1101 1102 void 1103 com_modem(struct com_softc *sc, int onoff) 1104 { 1105 1106 if (sc->sc_mcr_dtr == 0) 1107 return; 1108 1109 if (onoff) 1110 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1111 else 1112 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1113 1114 if (!sc->sc_heldchange) { 1115 if (sc->sc_tx_busy) { 1116 sc->sc_heldtbc = sc->sc_tbc; 1117 sc->sc_tbc = 0; 1118 sc->sc_heldchange = 1; 1119 } else 1120 com_loadchannelregs(sc); 1121 } 1122 } 1123 1124 void 1125 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1126 { 1127 u_char combits; 1128 1129 combits = 0; 1130 if (ISSET(ttybits, TIOCM_DTR)) 1131 SET(combits, MCR_DTR); 1132 if (ISSET(ttybits, TIOCM_RTS)) 1133 SET(combits, MCR_RTS); 1134 1135 switch (how) { 1136 case TIOCMBIC: 1137 CLR(sc->sc_mcr, combits); 1138 break; 1139 1140 case TIOCMBIS: 1141 SET(sc->sc_mcr, combits); 1142 break; 1143 1144 case TIOCMSET: 1145 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1146 SET(sc->sc_mcr, combits); 1147 break; 1148 } 1149 1150 if (!sc->sc_heldchange) { 1151 if (sc->sc_tx_busy) { 1152 sc->sc_heldtbc = sc->sc_tbc; 1153 sc->sc_tbc = 0; 1154 sc->sc_heldchange = 1; 1155 } else 1156 com_loadchannelregs(sc); 1157 } 1158 } 1159 1160 int 1161 com_to_tiocm(struct com_softc *sc) 1162 { 1163 u_char combits; 1164 int ttybits = 0; 1165 1166 combits = sc->sc_mcr; 1167 if (ISSET(combits, MCR_DTR)) 1168 SET(ttybits, TIOCM_DTR); 1169 if (ISSET(combits, MCR_RTS)) 1170 SET(ttybits, TIOCM_RTS); 1171 1172 combits = sc->sc_msr; 1173 if (ISSET(combits, MSR_DCD)) 1174 SET(ttybits, TIOCM_CD); 1175 if (ISSET(combits, MSR_CTS)) 1176 SET(ttybits, TIOCM_CTS); 1177 if (ISSET(combits, MSR_DSR)) 1178 SET(ttybits, TIOCM_DSR); 1179 if (ISSET(combits, MSR_RI | MSR_TERI)) 1180 SET(ttybits, TIOCM_RI); 1181 1182 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1183 SET(ttybits, TIOCM_LE); 1184 1185 return (ttybits); 1186 } 1187 1188 static u_char 1189 cflag2lcr(tcflag_t cflag) 1190 { 1191 u_char lcr = 0; 1192 1193 switch (ISSET(cflag, CSIZE)) { 1194 case CS5: 1195 SET(lcr, LCR_5BITS); 1196 break; 1197 case CS6: 1198 SET(lcr, LCR_6BITS); 1199 break; 1200 case CS7: 1201 SET(lcr, LCR_7BITS); 1202 break; 1203 case CS8: 1204 SET(lcr, LCR_8BITS); 1205 break; 1206 } 1207 if (ISSET(cflag, PARENB)) { 1208 SET(lcr, LCR_PENAB); 1209 if (!ISSET(cflag, PARODD)) 1210 SET(lcr, LCR_PEVEN); 1211 } 1212 if (ISSET(cflag, CSTOPB)) 1213 SET(lcr, LCR_STOPB); 1214 1215 return (lcr); 1216 } 1217 1218 int 1219 comparam(struct tty *tp, struct termios *t) 1220 { 1221 struct com_softc *sc = 1222 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1223 int ospeed; 1224 u_char lcr; 1225 1226 if (COM_ISALIVE(sc) == 0) 1227 return (EIO); 1228 1229 #ifdef COM_HAYESP 1230 if (sc->sc_type == COM_TYPE_HAYESP) { 1231 int prescaler, speed; 1232 1233 /* 1234 * Calculate UART clock prescaler. It should be in 1235 * range of 0 .. 3. 1236 */ 1237 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1238 prescaler++, speed /= 2) 1239 if ((ospeed = comspeed(speed, sc->sc_frequency, 1240 sc->sc_type)) > 0) 1241 break; 1242 1243 if (prescaler == 4) 1244 return (EINVAL); 1245 sc->sc_prescaler = prescaler; 1246 } else 1247 #endif 1248 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1249 1250 /* Check requested parameters. */ 1251 if (ospeed < 0) 1252 return (EINVAL); 1253 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1254 return (EINVAL); 1255 1256 /* 1257 * For the console, always force CLOCAL and !HUPCL, so that the port 1258 * is always active. 1259 */ 1260 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1261 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1262 SET(t->c_cflag, CLOCAL); 1263 CLR(t->c_cflag, HUPCL); 1264 } 1265 1266 /* 1267 * If there were no changes, don't do anything. This avoids dropping 1268 * input and improves performance when all we did was frob things like 1269 * VMIN and VTIME. 1270 */ 1271 if (tp->t_ospeed == t->c_ospeed && 1272 tp->t_cflag == t->c_cflag) 1273 return (0); 1274 1275 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1276 1277 mutex_spin_enter(&sc->sc_lock); 1278 1279 sc->sc_lcr = lcr; 1280 1281 /* 1282 * If we're not in a mode that assumes a connection is present, then 1283 * ignore carrier changes. 1284 */ 1285 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1286 sc->sc_msr_dcd = 0; 1287 else 1288 sc->sc_msr_dcd = MSR_DCD; 1289 /* 1290 * Set the flow control pins depending on the current flow control 1291 * mode. 1292 */ 1293 if (ISSET(t->c_cflag, CRTSCTS)) { 1294 sc->sc_mcr_dtr = MCR_DTR; 1295 sc->sc_mcr_rts = MCR_RTS; 1296 sc->sc_msr_cts = MSR_CTS; 1297 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1298 } else if (ISSET(t->c_cflag, MDMBUF)) { 1299 /* 1300 * For DTR/DCD flow control, make sure we don't toggle DTR for 1301 * carrier detection. 1302 */ 1303 sc->sc_mcr_dtr = 0; 1304 sc->sc_mcr_rts = MCR_DTR; 1305 sc->sc_msr_cts = MSR_DCD; 1306 sc->sc_efr = 0; 1307 } else { 1308 /* 1309 * If no flow control, then always set RTS. This will make 1310 * the other side happy if it mistakenly thinks we're doing 1311 * RTS/CTS flow control. 1312 */ 1313 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1314 sc->sc_mcr_rts = 0; 1315 sc->sc_msr_cts = 0; 1316 sc->sc_efr = 0; 1317 if (ISSET(sc->sc_mcr, MCR_DTR)) 1318 SET(sc->sc_mcr, MCR_RTS); 1319 else 1320 CLR(sc->sc_mcr, MCR_RTS); 1321 } 1322 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1323 1324 #if 0 1325 if (ospeed == 0) 1326 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1327 else 1328 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1329 #endif 1330 1331 sc->sc_dlbl = ospeed; 1332 sc->sc_dlbh = ospeed >> 8; 1333 1334 /* 1335 * Set the FIFO threshold based on the receive speed. 1336 * 1337 * * If it's a low speed, it's probably a mouse or some other 1338 * interactive device, so set the threshold low. 1339 * * If it's a high speed, trim the trigger level down to prevent 1340 * overflows. 1341 * * Otherwise set it a bit higher. 1342 */ 1343 if (sc->sc_type == COM_TYPE_HAYESP) 1344 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1345 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1346 if (t->c_ospeed <= 1200) 1347 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1348 else if (t->c_ospeed <= 38400) 1349 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1350 else 1351 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1352 } else 1353 sc->sc_fifo = 0; 1354 1355 /* And copy to tty. */ 1356 tp->t_ispeed = t->c_ospeed; 1357 tp->t_ospeed = t->c_ospeed; 1358 tp->t_cflag = t->c_cflag; 1359 1360 if (!sc->sc_heldchange) { 1361 if (sc->sc_tx_busy) { 1362 sc->sc_heldtbc = sc->sc_tbc; 1363 sc->sc_tbc = 0; 1364 sc->sc_heldchange = 1; 1365 } else 1366 com_loadchannelregs(sc); 1367 } 1368 1369 if (!ISSET(t->c_cflag, CHWFLOW)) { 1370 /* Disable the high water mark. */ 1371 sc->sc_r_hiwat = 0; 1372 sc->sc_r_lowat = 0; 1373 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1374 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1375 com_schedrx(sc); 1376 } 1377 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1378 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1379 com_hwiflow(sc); 1380 } 1381 } else { 1382 sc->sc_r_hiwat = com_rbuf_hiwat; 1383 sc->sc_r_lowat = com_rbuf_lowat; 1384 } 1385 1386 mutex_spin_exit(&sc->sc_lock); 1387 1388 /* 1389 * Update the tty layer's idea of the carrier bit, in case we changed 1390 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1391 * explicit request. 1392 */ 1393 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1394 1395 #ifdef COM_DEBUG 1396 if (com_debug) 1397 comstatus(sc, "comparam "); 1398 #endif 1399 1400 if (!ISSET(t->c_cflag, CHWFLOW)) { 1401 if (sc->sc_tx_stopped) { 1402 sc->sc_tx_stopped = 0; 1403 comstart(tp); 1404 } 1405 } 1406 1407 return (0); 1408 } 1409 1410 void 1411 com_iflush(struct com_softc *sc) 1412 { 1413 struct com_regs *regsp = &sc->sc_regs; 1414 #ifdef DIAGNOSTIC 1415 int reg; 1416 #endif 1417 int timo; 1418 1419 #ifdef DIAGNOSTIC 1420 reg = 0xffff; 1421 #endif 1422 timo = 50000; 1423 /* flush any pending I/O */ 1424 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1425 && --timo) 1426 #ifdef DIAGNOSTIC 1427 reg = 1428 #else 1429 (void) 1430 #endif 1431 CSR_READ_1(regsp, COM_REG_RXDATA); 1432 #ifdef DIAGNOSTIC 1433 if (!timo) 1434 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1435 #endif 1436 } 1437 1438 void 1439 com_loadchannelregs(struct com_softc *sc) 1440 { 1441 struct com_regs *regsp = &sc->sc_regs; 1442 1443 /* XXXXX necessary? */ 1444 com_iflush(sc); 1445 1446 if (sc->sc_type == COM_TYPE_PXA2x0) 1447 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1448 else 1449 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1450 1451 if (sc->sc_type == COM_TYPE_OMAP) { 1452 /* disable before changing settings */ 1453 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1454 } 1455 1456 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1457 if (sc->sc_type != COM_TYPE_AU1x00) { /* no EFR on alchemy */ 1458 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1459 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1460 } 1461 } 1462 if (sc->sc_type == COM_TYPE_AU1x00) { 1463 /* alchemy has single separate 16-bit clock divisor register */ 1464 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1465 (sc->sc_dlbh << 8)); 1466 } else { 1467 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1468 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1469 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1470 } 1471 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1472 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1473 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1474 #ifdef COM_HAYESP 1475 if (sc->sc_type == COM_TYPE_HAYESP) { 1476 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1477 HAYESP_SETPRESCALER); 1478 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1479 sc->sc_prescaler); 1480 } 1481 #endif 1482 if (sc->sc_type == COM_TYPE_OMAP) { 1483 /* setup the fifos. the FCR value is not used as long 1484 as SCR[6] and SCR[7] are 0, which they are at reset 1485 and we never touch the SCR register */ 1486 uint8_t rx_fifo_trig = 40; 1487 uint8_t tx_fifo_trig = 60; 1488 uint8_t rx_start = 8; 1489 uint8_t rx_halt = 60; 1490 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1491 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1492 1493 /* enable access to TCR & TLR */ 1494 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1495 1496 /* write tcr and tlr values */ 1497 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1498 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1499 1500 /* disable access to TCR & TLR */ 1501 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1502 1503 /* enable again, but mode is based on speed */ 1504 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1505 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1506 } else { 1507 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1508 } 1509 } 1510 1511 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1512 } 1513 1514 int 1515 comhwiflow(struct tty *tp, int block) 1516 { 1517 struct com_softc *sc = 1518 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1519 1520 if (COM_ISALIVE(sc) == 0) 1521 return (0); 1522 1523 if (sc->sc_mcr_rts == 0) 1524 return (0); 1525 1526 mutex_spin_enter(&sc->sc_lock); 1527 1528 if (block) { 1529 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1530 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1531 com_hwiflow(sc); 1532 } 1533 } else { 1534 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1535 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1536 com_schedrx(sc); 1537 } 1538 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1539 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1540 com_hwiflow(sc); 1541 } 1542 } 1543 1544 mutex_spin_exit(&sc->sc_lock); 1545 return (1); 1546 } 1547 1548 /* 1549 * (un)block input via hw flowcontrol 1550 */ 1551 void 1552 com_hwiflow(struct com_softc *sc) 1553 { 1554 struct com_regs *regsp= &sc->sc_regs; 1555 1556 if (sc->sc_mcr_rts == 0) 1557 return; 1558 1559 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1560 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1561 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1562 } else { 1563 SET(sc->sc_mcr, sc->sc_mcr_rts); 1564 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1565 } 1566 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1567 } 1568 1569 1570 void 1571 comstart(struct tty *tp) 1572 { 1573 struct com_softc *sc = 1574 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1575 struct com_regs *regsp = &sc->sc_regs; 1576 int s; 1577 1578 if (COM_ISALIVE(sc) == 0) 1579 return; 1580 1581 s = spltty(); 1582 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1583 goto out; 1584 if (sc->sc_tx_stopped) 1585 goto out; 1586 if (!ttypull(tp)) 1587 goto out; 1588 1589 /* Grab the first contiguous region of buffer space. */ 1590 { 1591 u_char *tba; 1592 int tbc; 1593 1594 tba = tp->t_outq.c_cf; 1595 tbc = ndqb(&tp->t_outq, 0); 1596 1597 mutex_spin_enter(&sc->sc_lock); 1598 1599 sc->sc_tba = tba; 1600 sc->sc_tbc = tbc; 1601 } 1602 1603 SET(tp->t_state, TS_BUSY); 1604 sc->sc_tx_busy = 1; 1605 1606 /* Enable transmit completion interrupts if necessary. */ 1607 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1608 SET(sc->sc_ier, IER_ETXRDY); 1609 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1610 } 1611 1612 /* Output the first chunk of the contiguous buffer. */ 1613 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1614 u_int n; 1615 1616 n = sc->sc_tbc; 1617 if (n > sc->sc_fifolen) 1618 n = sc->sc_fifolen; 1619 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1620 sc->sc_tbc -= n; 1621 sc->sc_tba += n; 1622 } 1623 1624 mutex_spin_exit(&sc->sc_lock); 1625 out: 1626 splx(s); 1627 return; 1628 } 1629 1630 /* 1631 * Stop output on a line. 1632 */ 1633 void 1634 comstop(struct tty *tp, int flag) 1635 { 1636 struct com_softc *sc = 1637 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1638 1639 mutex_spin_enter(&sc->sc_lock); 1640 if (ISSET(tp->t_state, TS_BUSY)) { 1641 /* Stop transmitting at the next chunk. */ 1642 sc->sc_tbc = 0; 1643 sc->sc_heldtbc = 0; 1644 if (!ISSET(tp->t_state, TS_TTSTOP)) 1645 SET(tp->t_state, TS_FLUSH); 1646 } 1647 mutex_spin_exit(&sc->sc_lock); 1648 } 1649 1650 void 1651 comdiag(void *arg) 1652 { 1653 struct com_softc *sc = arg; 1654 int overflows, floods; 1655 1656 mutex_spin_enter(&sc->sc_lock); 1657 overflows = sc->sc_overflows; 1658 sc->sc_overflows = 0; 1659 floods = sc->sc_floods; 1660 sc->sc_floods = 0; 1661 sc->sc_errors = 0; 1662 mutex_spin_exit(&sc->sc_lock); 1663 1664 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1665 device_xname(sc->sc_dev), 1666 overflows, overflows == 1 ? "" : "s", 1667 floods, floods == 1 ? "" : "s"); 1668 } 1669 1670 integrate void 1671 com_rxsoft(struct com_softc *sc, struct tty *tp) 1672 { 1673 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1674 u_char *get, *end; 1675 u_int cc, scc; 1676 u_char lsr; 1677 int code; 1678 1679 end = sc->sc_ebuf; 1680 get = sc->sc_rbget; 1681 scc = cc = com_rbuf_size - sc->sc_rbavail; 1682 1683 if (cc == com_rbuf_size) { 1684 sc->sc_floods++; 1685 if (sc->sc_errors++ == 0) 1686 callout_reset(&sc->sc_diag_callout, 60 * hz, 1687 comdiag, sc); 1688 } 1689 1690 /* If not yet open, drop the entire buffer content here */ 1691 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1692 get += cc << 1; 1693 if (get >= end) 1694 get -= com_rbuf_size << 1; 1695 cc = 0; 1696 } 1697 while (cc) { 1698 code = get[0]; 1699 lsr = get[1]; 1700 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1701 if (ISSET(lsr, LSR_OE)) { 1702 sc->sc_overflows++; 1703 if (sc->sc_errors++ == 0) 1704 callout_reset(&sc->sc_diag_callout, 1705 60 * hz, comdiag, sc); 1706 } 1707 if (ISSET(lsr, LSR_BI | LSR_FE)) 1708 SET(code, TTY_FE); 1709 if (ISSET(lsr, LSR_PE)) 1710 SET(code, TTY_PE); 1711 } 1712 if ((*rint)(code, tp) == -1) { 1713 /* 1714 * The line discipline's buffer is out of space. 1715 */ 1716 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1717 /* 1718 * We're either not using flow control, or the 1719 * line discipline didn't tell us to block for 1720 * some reason. Either way, we have no way to 1721 * know when there's more space available, so 1722 * just drop the rest of the data. 1723 */ 1724 get += cc << 1; 1725 if (get >= end) 1726 get -= com_rbuf_size << 1; 1727 cc = 0; 1728 } else { 1729 /* 1730 * Don't schedule any more receive processing 1731 * until the line discipline tells us there's 1732 * space available (through comhwiflow()). 1733 * Leave the rest of the data in the input 1734 * buffer. 1735 */ 1736 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1737 } 1738 break; 1739 } 1740 get += 2; 1741 if (get >= end) 1742 get = sc->sc_rbuf; 1743 cc--; 1744 } 1745 1746 if (cc != scc) { 1747 sc->sc_rbget = get; 1748 mutex_spin_enter(&sc->sc_lock); 1749 1750 cc = sc->sc_rbavail += scc - cc; 1751 /* Buffers should be ok again, release possible block. */ 1752 if (cc >= sc->sc_r_lowat) { 1753 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1754 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1755 SET(sc->sc_ier, IER_ERXRDY); 1756 #ifdef COM_PXA2X0 1757 if (sc->sc_type == COM_TYPE_PXA2x0) 1758 SET(sc->sc_ier, IER_ERXTOUT); 1759 #endif 1760 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1761 } 1762 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1763 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1764 com_hwiflow(sc); 1765 } 1766 } 1767 mutex_spin_exit(&sc->sc_lock); 1768 } 1769 } 1770 1771 integrate void 1772 com_txsoft(struct com_softc *sc, struct tty *tp) 1773 { 1774 1775 CLR(tp->t_state, TS_BUSY); 1776 if (ISSET(tp->t_state, TS_FLUSH)) 1777 CLR(tp->t_state, TS_FLUSH); 1778 else 1779 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1780 (*tp->t_linesw->l_start)(tp); 1781 } 1782 1783 integrate void 1784 com_stsoft(struct com_softc *sc, struct tty *tp) 1785 { 1786 u_char msr, delta; 1787 1788 mutex_spin_enter(&sc->sc_lock); 1789 msr = sc->sc_msr; 1790 delta = sc->sc_msr_delta; 1791 sc->sc_msr_delta = 0; 1792 mutex_spin_exit(&sc->sc_lock); 1793 1794 if (ISSET(delta, sc->sc_msr_dcd)) { 1795 /* 1796 * Inform the tty layer that carrier detect changed. 1797 */ 1798 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1799 } 1800 1801 if (ISSET(delta, sc->sc_msr_cts)) { 1802 /* Block or unblock output according to flow control. */ 1803 if (ISSET(msr, sc->sc_msr_cts)) { 1804 sc->sc_tx_stopped = 0; 1805 (*tp->t_linesw->l_start)(tp); 1806 } else { 1807 sc->sc_tx_stopped = 1; 1808 } 1809 } 1810 1811 #ifdef COM_DEBUG 1812 if (com_debug) 1813 comstatus(sc, "com_stsoft"); 1814 #endif 1815 } 1816 1817 void 1818 comsoft(void *arg) 1819 { 1820 struct com_softc *sc = arg; 1821 struct tty *tp; 1822 1823 if (COM_ISALIVE(sc) == 0) 1824 return; 1825 1826 tp = sc->sc_tty; 1827 1828 if (sc->sc_rx_ready) { 1829 sc->sc_rx_ready = 0; 1830 com_rxsoft(sc, tp); 1831 } 1832 1833 if (sc->sc_st_check) { 1834 sc->sc_st_check = 0; 1835 com_stsoft(sc, tp); 1836 } 1837 1838 if (sc->sc_tx_done) { 1839 sc->sc_tx_done = 0; 1840 com_txsoft(sc, tp); 1841 } 1842 } 1843 1844 int 1845 comintr(void *arg) 1846 { 1847 struct com_softc *sc = arg; 1848 struct com_regs *regsp = &sc->sc_regs; 1849 1850 u_char *put, *end; 1851 u_int cc; 1852 u_char lsr, iir; 1853 1854 if (COM_ISALIVE(sc) == 0) 1855 return (0); 1856 1857 mutex_spin_enter(&sc->sc_lock); 1858 iir = CSR_READ_1(regsp, COM_REG_IIR); 1859 if (ISSET(iir, IIR_NOPEND)) { 1860 mutex_spin_exit(&sc->sc_lock); 1861 return (0); 1862 } 1863 1864 end = sc->sc_ebuf; 1865 put = sc->sc_rbput; 1866 cc = sc->sc_rbavail; 1867 1868 again: do { 1869 u_char msr, delta; 1870 1871 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1872 if (ISSET(lsr, LSR_BI)) { 1873 int cn_trapped = 0; 1874 1875 cn_check_magic(sc->sc_tty->t_dev, 1876 CNC_BREAK, com_cnm_state); 1877 if (cn_trapped) 1878 continue; 1879 #if defined(KGDB) && !defined(DDB) 1880 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1881 kgdb_connect(1); 1882 continue; 1883 } 1884 #endif 1885 } 1886 1887 if (ISSET(lsr, LSR_RCV_MASK) && 1888 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1889 while (cc > 0) { 1890 int cn_trapped = 0; 1891 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1892 put[1] = lsr; 1893 cn_check_magic(sc->sc_tty->t_dev, 1894 put[0], com_cnm_state); 1895 if (cn_trapped) 1896 goto next; 1897 put += 2; 1898 if (put >= end) 1899 put = sc->sc_rbuf; 1900 cc--; 1901 next: 1902 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1903 if (!ISSET(lsr, LSR_RCV_MASK)) 1904 break; 1905 } 1906 1907 /* 1908 * Current string of incoming characters ended because 1909 * no more data was available or we ran out of space. 1910 * Schedule a receive event if any data was received. 1911 * If we're out of space, turn off receive interrupts. 1912 */ 1913 sc->sc_rbput = put; 1914 sc->sc_rbavail = cc; 1915 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1916 sc->sc_rx_ready = 1; 1917 1918 /* 1919 * See if we are in danger of overflowing a buffer. If 1920 * so, use hardware flow control to ease the pressure. 1921 */ 1922 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1923 cc < sc->sc_r_hiwat) { 1924 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1925 com_hwiflow(sc); 1926 } 1927 1928 /* 1929 * If we're out of space, disable receive interrupts 1930 * until the queue has drained a bit. 1931 */ 1932 if (!cc) { 1933 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1934 #ifdef COM_PXA2X0 1935 if (sc->sc_type == COM_TYPE_PXA2x0) 1936 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 1937 else 1938 #endif 1939 CLR(sc->sc_ier, IER_ERXRDY); 1940 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1941 } 1942 } else { 1943 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 1944 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 1945 continue; 1946 } 1947 } 1948 1949 msr = CSR_READ_1(regsp, COM_REG_MSR); 1950 delta = msr ^ sc->sc_msr; 1951 sc->sc_msr = msr; 1952 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1953 (delta & MSR_DCD)) { 1954 mutex_spin_enter(&timecounter_lock); 1955 pps_capture(&sc->sc_pps_state); 1956 pps_event(&sc->sc_pps_state, 1957 (msr & MSR_DCD) ? 1958 PPS_CAPTUREASSERT : 1959 PPS_CAPTURECLEAR); 1960 mutex_spin_exit(&timecounter_lock); 1961 } 1962 1963 /* 1964 * Process normal status changes 1965 */ 1966 if (ISSET(delta, sc->sc_msr_mask)) { 1967 SET(sc->sc_msr_delta, delta); 1968 1969 /* 1970 * Stop output immediately if we lose the output 1971 * flow control signal or carrier detect. 1972 */ 1973 if (ISSET(~msr, sc->sc_msr_mask)) { 1974 sc->sc_tbc = 0; 1975 sc->sc_heldtbc = 0; 1976 #ifdef COM_DEBUG 1977 if (com_debug) 1978 comstatus(sc, "comintr "); 1979 #endif 1980 } 1981 1982 sc->sc_st_check = 1; 1983 } 1984 } while (!ISSET((iir = 1985 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 1986 /* 1987 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 1988 * by IIR read, so we can't do this way: `process all interrupts, 1989 * then do TX if possble'. 1990 */ 1991 (iir & IIR_IMASK) != IIR_TXRDY); 1992 1993 /* 1994 * Read LSR again, since there may be an interrupt between 1995 * the last LSR read and IIR read above. 1996 */ 1997 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1998 1999 /* 2000 * See if data can be transmitted as well. 2001 * Schedule tx done event if no data left 2002 * and tty was marked busy. 2003 */ 2004 if (ISSET(lsr, LSR_TXRDY)) { 2005 /* 2006 * If we've delayed a parameter change, do it now, and restart 2007 * output. 2008 */ 2009 if (sc->sc_heldchange) { 2010 com_loadchannelregs(sc); 2011 sc->sc_heldchange = 0; 2012 sc->sc_tbc = sc->sc_heldtbc; 2013 sc->sc_heldtbc = 0; 2014 } 2015 2016 /* Output the next chunk of the contiguous buffer, if any. */ 2017 if (sc->sc_tbc > 0) { 2018 u_int n; 2019 2020 n = sc->sc_tbc; 2021 if (n > sc->sc_fifolen) 2022 n = sc->sc_fifolen; 2023 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2024 sc->sc_tbc -= n; 2025 sc->sc_tba += n; 2026 } else { 2027 /* Disable transmit completion interrupts if necessary. */ 2028 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2029 CLR(sc->sc_ier, IER_ETXRDY); 2030 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2031 } 2032 if (sc->sc_tx_busy) { 2033 sc->sc_tx_busy = 0; 2034 sc->sc_tx_done = 1; 2035 } 2036 } 2037 } 2038 2039 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2040 goto again; 2041 2042 mutex_spin_exit(&sc->sc_lock); 2043 2044 /* Wake up the poller. */ 2045 softint_schedule(sc->sc_si); 2046 2047 #if NRND > 0 && defined(RND_COM) 2048 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2049 #endif 2050 2051 return (1); 2052 } 2053 2054 /* 2055 * The following functions are polled getc and putc routines, shared 2056 * by the console and kgdb glue. 2057 * 2058 * The read-ahead code is so that you can detect pending in-band 2059 * cn_magic in polled mode while doing output rather than having to 2060 * wait until the kernel decides it needs input. 2061 */ 2062 2063 #define MAX_READAHEAD 20 2064 static int com_readahead[MAX_READAHEAD]; 2065 static int com_readaheadcount = 0; 2066 2067 int 2068 com_common_getc(dev_t dev, struct com_regs *regsp) 2069 { 2070 int s = splserial(); 2071 u_char stat, c; 2072 2073 /* got a character from reading things earlier */ 2074 if (com_readaheadcount > 0) { 2075 int i; 2076 2077 c = com_readahead[0]; 2078 for (i = 1; i < com_readaheadcount; i++) { 2079 com_readahead[i-1] = com_readahead[i]; 2080 } 2081 com_readaheadcount--; 2082 splx(s); 2083 return (c); 2084 } 2085 2086 /* block until a character becomes available */ 2087 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2088 ; 2089 2090 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2091 stat = CSR_READ_1(regsp, COM_REG_IIR); 2092 { 2093 int cn_trapped = 0; /* unused */ 2094 #ifdef DDB 2095 extern int db_active; 2096 if (!db_active) 2097 #endif 2098 cn_check_magic(dev, c, com_cnm_state); 2099 } 2100 splx(s); 2101 return (c); 2102 } 2103 2104 void 2105 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2106 { 2107 int s = splserial(); 2108 int cin, stat, timo; 2109 2110 if (com_readaheadcount < MAX_READAHEAD 2111 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2112 int cn_trapped = 0; 2113 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2114 stat = CSR_READ_1(regsp, COM_REG_IIR); 2115 cn_check_magic(dev, cin, com_cnm_state); 2116 com_readahead[com_readaheadcount++] = cin; 2117 } 2118 2119 /* wait for any pending transmission to finish */ 2120 timo = 150000; 2121 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2122 continue; 2123 2124 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2125 COM_BARRIER(regsp, BR | BW); 2126 2127 splx(s); 2128 } 2129 2130 /* 2131 * Initialize UART for use as console or KGDB line. 2132 */ 2133 int 2134 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2135 tcflag_t cflag) 2136 { 2137 2138 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2139 ®sp->cr_ioh)) 2140 return (ENOMEM); /* ??? */ 2141 2142 if (type == COM_TYPE_OMAP) { 2143 /* disable before changing settings */ 2144 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2145 } 2146 2147 rate = comspeed(rate, frequency, type); 2148 if (type != COM_TYPE_AU1x00) { 2149 /* no EFR on alchemy */ 2150 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2151 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2152 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2153 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2154 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2155 } else { 2156 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2157 } 2158 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2159 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2160 CSR_WRITE_1(regsp, COM_REG_FIFO, 2161 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2162 2163 if (type == COM_TYPE_OMAP) { 2164 /* setup the fifos. the FCR value is not used as long 2165 as SCR[6] and SCR[7] are 0, which they are at reset 2166 and we never touch the SCR register */ 2167 uint8_t rx_fifo_trig = 40; 2168 uint8_t tx_fifo_trig = 60; 2169 uint8_t rx_start = 8; 2170 uint8_t rx_halt = 60; 2171 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2172 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2173 2174 /* enable access to TCR & TLR */ 2175 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2176 2177 /* write tcr and tlr values */ 2178 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2179 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2180 2181 /* disable access to TCR & TLR */ 2182 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2183 2184 /* enable again, but mode is based on speed */ 2185 if (rate > 230400) { 2186 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2187 } else { 2188 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2189 } 2190 } 2191 2192 #ifdef COM_PXA2X0 2193 if (type == COM_TYPE_PXA2x0) 2194 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2195 else 2196 #endif 2197 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2198 2199 return (0); 2200 } 2201 2202 /* 2203 * Following are all routines needed for COM to act as console 2204 */ 2205 struct consdev comcons = { 2206 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2207 NODEV, CN_NORMAL 2208 }; 2209 2210 2211 int 2212 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2213 tcflag_t cflag) 2214 { 2215 int res; 2216 2217 comconsregs = *regsp; 2218 2219 res = cominit(&comconsregs, rate, frequency, type, cflag); 2220 if (res) 2221 return (res); 2222 2223 cn_tab = &comcons; 2224 cn_init_magic(&com_cnm_state); 2225 cn_set_magic("\047\001"); /* default magic is BREAK */ 2226 2227 comconsrate = rate; 2228 comconscflag = cflag; 2229 2230 return (0); 2231 } 2232 2233 int 2234 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2235 int type, tcflag_t cflag) 2236 { 2237 struct com_regs regs; 2238 2239 memset(®s, 0, sizeof regs); 2240 regs.cr_iot = iot; 2241 regs.cr_iobase = iobase; 2242 regs.cr_nports = COM_NPORTS; 2243 #ifdef COM_REGMAP 2244 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2245 #endif 2246 2247 return comcnattach1(®s, rate, frequency, type, cflag); 2248 } 2249 2250 int 2251 comcngetc(dev_t dev) 2252 { 2253 2254 return (com_common_getc(dev, &comconsregs)); 2255 } 2256 2257 /* 2258 * Console kernel output character routine. 2259 */ 2260 void 2261 comcnputc(dev_t dev, int c) 2262 { 2263 2264 com_common_putc(dev, &comconsregs, c); 2265 } 2266 2267 void 2268 comcnpollc(dev_t dev, int on) 2269 { 2270 2271 } 2272 2273 #ifdef KGDB 2274 int 2275 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2276 tcflag_t cflag) 2277 { 2278 int res; 2279 2280 if (regsp->cr_iot == comconsregs.cr_iot && 2281 regsp->cr_iobase == comconsregs.cr_iobase) { 2282 #if !defined(DDB) 2283 return (EBUSY); /* cannot share with console */ 2284 #else 2285 comkgdbregs = *regsp; 2286 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2287 #endif 2288 } else { 2289 comkgdbregs = *regsp; 2290 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2291 if (res) 2292 return (res); 2293 2294 /* 2295 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2296 * expects this to be initialized 2297 */ 2298 cn_init_magic(&com_cnm_state); 2299 cn_set_magic("\047\001"); 2300 } 2301 2302 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2303 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2304 2305 return (0); 2306 } 2307 2308 int 2309 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2310 int frequency, int type, tcflag_t cflag) 2311 { 2312 struct com_regs regs; 2313 2314 regs.cr_iot = iot; 2315 regs.cr_nports = COM_NPORTS; 2316 regs.cr_iobase = iobase; 2317 #ifdef COM_REGMAP 2318 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2319 #endif 2320 2321 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2322 } 2323 2324 /* ARGSUSED */ 2325 int 2326 com_kgdb_getc(void *arg) 2327 { 2328 2329 return (com_common_getc(NODEV, &comkgdbregs)); 2330 } 2331 2332 /* ARGSUSED */ 2333 void 2334 com_kgdb_putc(void *arg, int c) 2335 { 2336 2337 com_common_putc(NODEV, &comkgdbregs, c); 2338 } 2339 #endif /* KGDB */ 2340 2341 /* helper function to identify the com ports used by 2342 console or KGDB (and not yet autoconf attached) */ 2343 int 2344 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2345 { 2346 bus_space_handle_t help; 2347 2348 if (!comconsattached && 2349 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2350 help = comconsregs.cr_ioh; 2351 #ifdef KGDB 2352 else if (!com_kgdb_attached && 2353 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2354 help = comkgdbregs.cr_ioh; 2355 #endif 2356 else 2357 return (0); 2358 2359 if (ioh) 2360 *ioh = help; 2361 return (1); 2362 } 2363 2364 /* 2365 * this routine exists to serve as a shutdown hook for systems that 2366 * have firmware which doesn't interact properly with a com device in 2367 * FIFO mode. 2368 */ 2369 bool 2370 com_cleanup(device_t self, int how) 2371 { 2372 struct com_softc *sc = device_private(self); 2373 2374 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2375 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2376 2377 return true; 2378 } 2379 2380 bool 2381 com_suspend(device_t self PMF_FN_ARGS) 2382 { 2383 struct com_softc *sc = device_private(self); 2384 2385 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2386 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2387 2388 return true; 2389 } 2390 2391 bool 2392 com_resume(device_t self PMF_FN_ARGS) 2393 { 2394 struct com_softc *sc = device_private(self); 2395 2396 mutex_spin_enter(&sc->sc_lock); 2397 com_loadchannelregs(sc); 2398 mutex_spin_exit(&sc->sc_lock); 2399 2400 return true; 2401 } 2402
Indexes created Mon Oct 20 16:09:52 GMT 2025