com.c revision 1.284
1 /* com.c,v 1.262.2.3 2008/01/09 01:52:50 matt Exp */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "com.c,v 1.262.2.3 2008/01/09 01:52:50 matt Exp"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 #if NRND > 0 && defined(RND_COM) 80 #include <sys/rnd.h> 81 #endif 82 83 /* The COM16650 option was renamed to COM_16650. */ 84 #ifdef COM16650 85 #error Obsolete COM16650 option; use COM_16650 instead. 86 #endif 87 88 /* 89 * Override cnmagic(9) macro before including <sys/systm.h>. 90 * We need to know if cn_check_magic triggered debugger, so set a flag. 91 * Callers of cn_check_magic must declare int cn_trapped = 0; 92 * XXX: this is *ugly*! 93 */ 94 #define cn_trap() \ 95 do { \ 96 console_debugger(); \ 97 cn_trapped = 1; \ 98 } while (/* CONSTCOND */ 0) 99 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/ioctl.h> 103 #include <sys/select.h> 104 #include <sys/poll.h> 105 #include <sys/tty.h> 106 #include <sys/proc.h> 107 #include <sys/user.h> 108 #include <sys/conf.h> 109 #include <sys/file.h> 110 #include <sys/uio.h> 111 #include <sys/kernel.h> 112 #include <sys/syslog.h> 113 #include <sys/device.h> 114 #include <sys/malloc.h> 115 #include <sys/timepps.h> 116 #include <sys/vnode.h> 117 #include <sys/kauth.h> 118 #include <sys/intr.h> 119 120 #include <sys/bus.h> 121 122 #include <dev/ic/comreg.h> 123 #include <dev/ic/comvar.h> 124 #include <dev/ic/ns16550reg.h> 125 #include <dev/ic/st16650reg.h> 126 #ifdef COM_HAYESP 127 #include <dev/ic/hayespreg.h> 128 #endif 129 #define com_lcr com_cfcr 130 #include <dev/cons.h> 131 132 #ifdef COM_REGMAP 133 #define CSR_WRITE_1(r, o, v) \ 134 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 135 #define CSR_READ_1(r, o) \ 136 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 137 #define CSR_WRITE_2(r, o, v) \ 138 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 139 #define CSR_READ_2(r, o) \ 140 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 141 #define CSR_WRITE_MULTI(r, o, p, n) \ 142 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 143 #else 144 #define CSR_WRITE_1(r, o, v) \ 145 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 146 #define CSR_READ_1(r, o) \ 147 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 148 #define CSR_WRITE_2(r, o, v) \ 149 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 150 #define CSR_READ_2(r, o) \ 151 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 152 #define CSR_WRITE_MULTI(r, o, p, n) \ 153 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 154 #endif 155 156 157 static void com_enable_debugport(struct com_softc *); 158 159 void com_config(struct com_softc *); 160 void com_shutdown(struct com_softc *); 161 int comspeed(long, long, int); 162 static u_char cflag2lcr(tcflag_t); 163 int comparam(struct tty *, struct termios *); 164 void comstart(struct tty *); 165 int comhwiflow(struct tty *, int); 166 167 void com_loadchannelregs(struct com_softc *); 168 void com_hwiflow(struct com_softc *); 169 void com_break(struct com_softc *, int); 170 void com_modem(struct com_softc *, int); 171 void tiocm_to_com(struct com_softc *, u_long, int); 172 int com_to_tiocm(struct com_softc *); 173 void com_iflush(struct com_softc *); 174 175 int com_common_getc(dev_t, struct com_regs *); 176 void com_common_putc(dev_t, struct com_regs *, int); 177 178 int cominit(struct com_regs *, int, int, int, tcflag_t); 179 180 int comcngetc(dev_t); 181 void comcnputc(dev_t, int); 182 void comcnpollc(dev_t, int); 183 184 #define integrate static inline 185 void comsoft(void *); 186 integrate void com_rxsoft(struct com_softc *, struct tty *); 187 integrate void com_txsoft(struct com_softc *, struct tty *); 188 integrate void com_stsoft(struct com_softc *, struct tty *); 189 integrate void com_schedrx(struct com_softc *); 190 void comdiag(void *); 191 192 extern struct cfdriver com_cd; 193 194 dev_type_open(comopen); 195 dev_type_close(comclose); 196 dev_type_read(comread); 197 dev_type_write(comwrite); 198 dev_type_ioctl(comioctl); 199 dev_type_stop(comstop); 200 dev_type_tty(comtty); 201 dev_type_poll(compoll); 202 203 const struct cdevsw com_cdevsw = { 204 comopen, comclose, comread, comwrite, comioctl, 205 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 206 }; 207 208 /* 209 * Make this an option variable one can patch. 210 * But be warned: this must be a power of 2! 211 */ 212 u_int com_rbuf_size = COM_RING_SIZE; 213 214 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 215 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 216 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 217 218 static struct com_regs comconsregs; 219 static int comconsattached; 220 static int comconsrate; 221 static tcflag_t comconscflag; 222 static struct cnm_state com_cnm_state; 223 224 #ifdef KGDB 225 #include <sys/kgdb.h> 226 227 static struct com_regs comkgdbregs; 228 static int com_kgdb_attached; 229 230 int com_kgdb_getc(void *); 231 void com_kgdb_putc(void *, int); 232 #endif /* KGDB */ 233 234 #ifdef COM_REGMAP 235 /* initializer for typical 16550-ish hardware */ 236 #define COM_REG_16550 { \ 237 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 238 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 239 240 const bus_size_t com_std_map[16] = COM_REG_16550; 241 #endif /* COM_REGMAP */ 242 243 #define COMUNIT_MASK 0x7ffff 244 #define COMDIALOUT_MASK 0x80000 245 246 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 247 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 248 249 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 250 device_is_active((sc)->sc_dev)) 251 252 #define BR BUS_SPACE_BARRIER_READ 253 #define BW BUS_SPACE_BARRIER_WRITE 254 #define COM_BARRIER(r, f) \ 255 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 256 257 /*ARGSUSED*/ 258 int 259 comspeed(long speed, long frequency, int type) 260 { 261 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 262 263 int x, err; 264 int divisor = 16; 265 266 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 267 divisor = 13; 268 } 269 270 #if 0 271 if (speed == 0) 272 return (0); 273 #endif 274 if (speed <= 0) 275 return (-1); 276 x = divrnd(frequency / divisor, speed); 277 if (x <= 0) 278 return (-1); 279 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 280 if (err < 0) 281 err = -err; 282 if (err > COM_TOLERANCE) 283 return (-1); 284 return (x); 285 286 #undef divrnd 287 } 288 289 #ifdef COM_DEBUG 290 int com_debug = 0; 291 292 void comstatus(struct com_softc *, const char *); 293 void 294 comstatus(struct com_softc *sc, const char *str) 295 { 296 struct tty *tp = sc->sc_tty; 297 298 aprint_normal_dev(sc->sc_dev, 299 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 300 str, 301 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 302 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 303 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 304 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 305 sc->sc_tx_stopped ? '+' : '-'); 306 307 aprint_normal_dev(sc->sc_dev, 308 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 309 str, 310 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 311 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 312 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 313 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 314 sc->sc_rx_flags); 315 } 316 #endif 317 318 int 319 com_probe_subr(struct com_regs *regs) 320 { 321 322 /* force access to id reg */ 323 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 324 CSR_WRITE_1(regs, COM_REG_IIR, 0); 325 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 326 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 327 return (0); 328 329 return (1); 330 } 331 332 int 333 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 334 { 335 struct com_regs regs; 336 337 regs.cr_iot = iot; 338 regs.cr_ioh = ioh; 339 #ifdef COM_REGMAP 340 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));; 341 #endif 342 343 return com_probe_subr(®s); 344 } 345 346 /* 347 * No locking in this routine; it is only called during attach, 348 * or with the port already locked. 349 */ 350 static void 351 com_enable_debugport(struct com_softc *sc) 352 { 353 354 /* Turn on line break interrupt, set carrier. */ 355 sc->sc_ier = IER_ERXRDY; 356 if (sc->sc_type == COM_TYPE_PXA2x0) 357 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 358 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 359 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 360 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 361 } 362 363 void 364 com_attach_subr(struct com_softc *sc) 365 { 366 struct com_regs *regsp = &sc->sc_regs; 367 struct tty *tp; 368 #ifdef COM_16650 369 u_int8_t lcr; 370 #endif 371 const char *fifo_msg = NULL; 372 373 aprint_naive("\n"); 374 375 callout_init(&sc->sc_diag_callout, 0); 376 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 377 378 /* Disable interrupts before configuring the device. */ 379 if (sc->sc_type == COM_TYPE_PXA2x0) 380 sc->sc_ier = IER_EUART; 381 else 382 sc->sc_ier = 0; 383 384 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 385 386 if (regsp->cr_iot == comconsregs.cr_iot && 387 regsp->cr_iobase == comconsregs.cr_iobase) { 388 comconsattached = 1; 389 390 /* Make sure the console is always "hardwired". */ 391 delay(10000); /* wait for output to finish */ 392 SET(sc->sc_hwflags, COM_HW_CONSOLE); 393 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 394 } 395 396 /* Probe for FIFO */ 397 switch (sc->sc_type) { 398 case COM_TYPE_HAYESP: 399 goto fifodone; 400 401 case COM_TYPE_AU1x00: 402 sc->sc_fifolen = 16; 403 fifo_msg = "Au1X00 UART, working fifo"; 404 SET(sc->sc_hwflags, COM_HW_FIFO); 405 goto fifodelay; 406 407 case COM_TYPE_OMAP: 408 sc->sc_fifolen = 64; 409 fifo_msg = "OMAP UART, working fifo"; 410 SET(sc->sc_hwflags, COM_HW_FIFO); 411 goto fifodelay; 412 } 413 414 sc->sc_fifolen = 1; 415 /* look for a NS 16550AF UART with FIFOs */ 416 CSR_WRITE_1(regsp, COM_REG_FIFO, 417 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 418 delay(100); 419 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 420 == IIR_FIFO_MASK) 421 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 422 == FIFO_TRIGGER_14) { 423 SET(sc->sc_hwflags, COM_HW_FIFO); 424 425 #ifdef COM_16650 426 /* 427 * IIR changes into the EFR if LCR is set to LCR_EERS 428 * on 16650s. We also know IIR != 0 at this point. 429 * Write 0 into the EFR, and read it. If the result 430 * is 0, we have a 16650. 431 * 432 * Older 16650s were broken; the test to detect them 433 * is taken from the Linux driver. Apparently 434 * setting DLAB enable gives access to the EFR on 435 * these chips. 436 */ 437 if (sc->sc_type != COM_TYPE_16550_NOERS) { 438 lcr = CSR_READ_1(regsp, COM_REG_LCR); 439 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 440 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 441 442 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 443 CSR_WRITE_1(regsp, COM_REG_LCR, 444 lcr | LCR_DLAB); 445 CLR(sc->sc_hwflags, COM_HW_FIFO); 446 sc->sc_fifolen = 0; 447 } else { 448 SET(sc->sc_hwflags, COM_HW_FLOW); 449 sc->sc_fifolen = 32; 450 } 451 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 452 } else 453 #endif 454 sc->sc_fifolen = 16; 455 456 #ifdef COM_16650 457 if (sc->sc_fifolen == 0) 458 fifo_msg = "st16650, broken fifo"; 459 else if (sc->sc_fifolen == 32) 460 fifo_msg = "st16650a, working fifo"; 461 else 462 #endif 463 fifo_msg = "ns16550a, working fifo"; 464 } else 465 fifo_msg = "ns16550, broken fifo"; 466 else 467 fifo_msg = "ns8250 or ns16450, no fifo"; 468 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 469 fifodelay: 470 /* 471 * Some chips will clear down both Tx and Rx FIFOs when zero is 472 * written to com_fifo. If this chip is the console, writing zero 473 * results in some of the chip/FIFO description being lost, so delay 474 * printing it until now. 475 */ 476 delay(10); 477 aprint_normal(": %s\n", fifo_msg); 478 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 479 sc->sc_fifolen = 1; 480 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 481 } 482 483 fifodone: 484 485 tp = ttymalloc(); 486 tp->t_oproc = comstart; 487 tp->t_param = comparam; 488 tp->t_hwiflow = comhwiflow; 489 490 sc->sc_tty = tp; 491 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 492 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 493 sc->sc_rbavail = com_rbuf_size; 494 if (sc->sc_rbuf == NULL) { 495 aprint_error_dev(sc->sc_dev, 496 "unable to allocate ring buffer\n"); 497 return; 498 } 499 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 500 501 tty_attach(tp); 502 503 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 504 SET(sc->sc_mcr, MCR_IENABLE); 505 506 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 507 int maj; 508 509 /* locate the major number */ 510 maj = cdevsw_lookup_major(&com_cdevsw); 511 512 tp->t_dev = cn_tab->cn_dev = makedev(maj, 513 device_unit(sc->sc_dev)); 514 515 aprint_normal_dev(sc->sc_dev, "console\n"); 516 } 517 518 #ifdef KGDB 519 /* 520 * Allow kgdb to "take over" this port. If this is 521 * not the console and is the kgdb device, it has 522 * exclusive use. If it's the console _and_ the 523 * kgdb device, it doesn't. 524 */ 525 if (regsp->cr_iot == comkgdbregs.cr_iot && 526 regsp->cr_iobase == comkgdbregs.cr_iobase) { 527 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 528 com_kgdb_attached = 1; 529 530 SET(sc->sc_hwflags, COM_HW_KGDB); 531 } 532 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 533 } 534 #endif 535 536 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 537 538 #if NRND > 0 && defined(RND_COM) 539 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 540 RND_TYPE_TTY, 0); 541 #endif 542 543 /* if there are no enable/disable functions, assume the device 544 is always enabled */ 545 if (!sc->enable) 546 sc->enabled = 1; 547 548 com_config(sc); 549 550 SET(sc->sc_hwflags, COM_HW_DEV_OK); 551 } 552 553 void 554 com_config(struct com_softc *sc) 555 { 556 struct com_regs *regsp = &sc->sc_regs; 557 558 /* Disable interrupts before configuring the device. */ 559 if (sc->sc_type == COM_TYPE_PXA2x0) 560 sc->sc_ier = IER_EUART; 561 else 562 sc->sc_ier = 0; 563 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 564 (void) CSR_READ_1(regsp, COM_REG_IIR); 565 566 #ifdef COM_HAYESP 567 /* Look for a Hayes ESP board. */ 568 if (sc->sc_type == COM_TYPE_HAYESP) { 569 570 /* Set 16550 compatibility mode */ 571 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 572 HAYESP_SETMODE); 573 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 574 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 575 HAYESP_MODE_SCALE); 576 577 /* Set RTS/CTS flow control */ 578 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 579 HAYESP_SETFLOWTYPE); 580 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 581 HAYESP_FLOW_RTS); 582 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 583 HAYESP_FLOW_CTS); 584 585 /* Set flow control levels */ 586 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 587 HAYESP_SETRXFLOW); 588 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 589 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 590 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 591 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 592 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 593 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 594 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 595 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 596 } 597 #endif 598 599 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 600 com_enable_debugport(sc); 601 } 602 603 int 604 com_detach(device_t self, int flags) 605 { 606 struct com_softc *sc = device_private(self); 607 int maj, mn; 608 609 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 610 return EBUSY; 611 612 /* locate the major number */ 613 maj = cdevsw_lookup_major(&com_cdevsw); 614 615 /* Nuke the vnodes for any open instances. */ 616 mn = device_unit(self); 617 vdevgone(maj, mn, mn, VCHR); 618 619 mn |= COMDIALOUT_MASK; 620 vdevgone(maj, mn, mn, VCHR); 621 622 if (sc->sc_rbuf == NULL) { 623 /* 624 * Ring buffer allocation failed in the com_attach_subr, 625 * only the tty is allocated, and nothing else. 626 */ 627 ttyfree(sc->sc_tty); 628 return 0; 629 } 630 631 /* Free the receive buffer. */ 632 free(sc->sc_rbuf, M_DEVBUF); 633 634 /* Detach and free the tty. */ 635 tty_detach(sc->sc_tty); 636 ttyfree(sc->sc_tty); 637 638 /* Unhook the soft interrupt handler. */ 639 softint_disestablish(sc->sc_si); 640 641 #if NRND > 0 && defined(RND_COM) 642 /* Unhook the entropy source. */ 643 rnd_detach_source(&sc->rnd_source); 644 #endif 645 callout_destroy(&sc->sc_diag_callout); 646 647 /* Destroy the lock. */ 648 mutex_destroy(&sc->sc_lock); 649 650 return (0); 651 } 652 653 int 654 com_activate(device_t self, enum devact act) 655 { 656 struct com_softc *sc = device_private(self); 657 int rv = 0; 658 659 switch (act) { 660 case DVACT_ACTIVATE: 661 rv = EOPNOTSUPP; 662 break; 663 664 case DVACT_DEACTIVATE: 665 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) { 666 rv = EBUSY; 667 break; 668 } 669 670 if (sc->disable != NULL && sc->enabled != 0) { 671 (*sc->disable)(sc); 672 sc->enabled = 0; 673 } 674 break; 675 } 676 677 return (rv); 678 } 679 680 void 681 com_shutdown(struct com_softc *sc) 682 { 683 struct tty *tp = sc->sc_tty; 684 685 mutex_spin_enter(&sc->sc_lock); 686 687 /* If we were asserting flow control, then deassert it. */ 688 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 689 com_hwiflow(sc); 690 691 /* Clear any break condition set with TIOCSBRK. */ 692 com_break(sc, 0); 693 694 /* 695 * Hang up if necessary. Wait a bit, so the other side has time to 696 * notice even if we immediately open the port again. 697 * Avoid tsleeping above splhigh(). 698 */ 699 if (ISSET(tp->t_cflag, HUPCL)) { 700 com_modem(sc, 0); 701 mutex_spin_exit(&sc->sc_lock); 702 /* XXX will only timeout */ 703 (void) kpause(ttclos, false, hz, NULL); 704 mutex_spin_enter(&sc->sc_lock); 705 } 706 707 /* Turn off interrupts. */ 708 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 709 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 710 if (sc->sc_type == COM_TYPE_PXA2x0) 711 sc->sc_ier |= IER_ERXTOUT; 712 } else 713 sc->sc_ier = 0; 714 715 if (sc->sc_type == COM_TYPE_PXA2x0) 716 sc->sc_ier |= IER_EUART; 717 718 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 719 720 mutex_spin_exit(&sc->sc_lock); 721 722 if (sc->disable) { 723 #ifdef DIAGNOSTIC 724 if (!sc->enabled) 725 panic("com_shutdown: not enabled?"); 726 #endif 727 (*sc->disable)(sc); 728 sc->enabled = 0; 729 } 730 } 731 732 int 733 comopen(dev_t dev, int flag, int mode, struct lwp *l) 734 { 735 struct com_softc *sc; 736 struct tty *tp; 737 int s; 738 int error; 739 740 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 741 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 742 sc->sc_rbuf == NULL) 743 return (ENXIO); 744 745 if (!device_is_active(sc->sc_dev)) 746 return (ENXIO); 747 748 #ifdef KGDB 749 /* 750 * If this is the kgdb port, no other use is permitted. 751 */ 752 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 753 return (EBUSY); 754 #endif 755 756 tp = sc->sc_tty; 757 758 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 759 return (EBUSY); 760 761 s = spltty(); 762 763 /* 764 * Do the following iff this is a first open. 765 */ 766 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 767 struct termios t; 768 769 tp->t_dev = dev; 770 771 772 if (sc->enable) { 773 if ((*sc->enable)(sc)) { 774 splx(s); 775 aprint_error_dev(sc->sc_dev, 776 "device enable failed\n"); 777 return (EIO); 778 } 779 mutex_spin_enter(&sc->sc_lock); 780 sc->enabled = 1; 781 com_config(sc); 782 } else { 783 mutex_spin_enter(&sc->sc_lock); 784 } 785 786 /* Turn on interrupts. */ 787 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 788 if (sc->sc_type == COM_TYPE_PXA2x0) 789 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 790 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 791 792 /* Fetch the current modem control status, needed later. */ 793 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 794 795 /* Clear PPS capture state on first open. */ 796 mutex_spin_enter(&timecounter_lock); 797 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 798 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 799 pps_init(&sc->sc_pps_state); 800 mutex_spin_exit(&timecounter_lock); 801 802 mutex_spin_exit(&sc->sc_lock); 803 804 /* 805 * Initialize the termios status to the defaults. Add in the 806 * sticky bits from TIOCSFLAGS. 807 */ 808 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 809 t.c_ospeed = comconsrate; 810 t.c_cflag = comconscflag; 811 } else { 812 t.c_ospeed = TTYDEF_SPEED; 813 t.c_cflag = TTYDEF_CFLAG; 814 } 815 t.c_ispeed = t.c_ospeed; 816 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 817 SET(t.c_cflag, CLOCAL); 818 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 819 SET(t.c_cflag, CRTSCTS); 820 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 821 SET(t.c_cflag, MDMBUF); 822 /* Make sure comparam() will do something. */ 823 tp->t_ospeed = 0; 824 (void) comparam(tp, &t); 825 tp->t_iflag = TTYDEF_IFLAG; 826 tp->t_oflag = TTYDEF_OFLAG; 827 tp->t_lflag = TTYDEF_LFLAG; 828 ttychars(tp); 829 ttsetwater(tp); 830 831 mutex_spin_enter(&sc->sc_lock); 832 833 /* 834 * Turn on DTR. We must always do this, even if carrier is not 835 * present, because otherwise we'd have to use TIOCSDTR 836 * immediately after setting CLOCAL, which applications do not 837 * expect. We always assert DTR while the device is open 838 * unless explicitly requested to deassert it. 839 */ 840 com_modem(sc, 1); 841 842 /* Clear the input ring, and unblock. */ 843 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 844 sc->sc_rbavail = com_rbuf_size; 845 com_iflush(sc); 846 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 847 com_hwiflow(sc); 848 849 #ifdef COM_DEBUG 850 if (com_debug) 851 comstatus(sc, "comopen "); 852 #endif 853 854 mutex_spin_exit(&sc->sc_lock); 855 } 856 857 splx(s); 858 859 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 860 if (error) 861 goto bad; 862 863 error = (*tp->t_linesw->l_open)(dev, tp); 864 if (error) 865 goto bad; 866 867 return (0); 868 869 bad: 870 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 871 /* 872 * We failed to open the device, and nobody else had it opened. 873 * Clean up the state as appropriate. 874 */ 875 com_shutdown(sc); 876 } 877 878 return (error); 879 } 880 881 int 882 comclose(dev_t dev, int flag, int mode, struct lwp *l) 883 { 884 struct com_softc *sc = 885 device_lookup_private(&com_cd, COMUNIT(dev)); 886 struct tty *tp = sc->sc_tty; 887 888 /* XXX This is for cons.c. */ 889 if (!ISSET(tp->t_state, TS_ISOPEN)) 890 return (0); 891 892 (*tp->t_linesw->l_close)(tp, flag); 893 ttyclose(tp); 894 895 if (COM_ISALIVE(sc) == 0) 896 return (0); 897 898 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 899 /* 900 * Although we got a last close, the device may still be in 901 * use; e.g. if this was the dialout node, and there are still 902 * processes waiting for carrier on the non-dialout node. 903 */ 904 com_shutdown(sc); 905 } 906 907 return (0); 908 } 909 910 int 911 comread(dev_t dev, struct uio *uio, int flag) 912 { 913 struct com_softc *sc = 914 device_lookup_private(&com_cd, COMUNIT(dev)); 915 struct tty *tp = sc->sc_tty; 916 917 if (COM_ISALIVE(sc) == 0) 918 return (EIO); 919 920 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 921 } 922 923 int 924 comwrite(dev_t dev, struct uio *uio, int flag) 925 { 926 struct com_softc *sc = 927 device_lookup_private(&com_cd, COMUNIT(dev)); 928 struct tty *tp = sc->sc_tty; 929 930 if (COM_ISALIVE(sc) == 0) 931 return (EIO); 932 933 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 934 } 935 936 int 937 compoll(dev_t dev, int events, struct lwp *l) 938 { 939 struct com_softc *sc = 940 device_lookup_private(&com_cd, COMUNIT(dev)); 941 struct tty *tp = sc->sc_tty; 942 943 if (COM_ISALIVE(sc) == 0) 944 return (POLLHUP); 945 946 return ((*tp->t_linesw->l_poll)(tp, events, l)); 947 } 948 949 struct tty * 950 comtty(dev_t dev) 951 { 952 struct com_softc *sc = 953 device_lookup_private(&com_cd, COMUNIT(dev)); 954 struct tty *tp = sc->sc_tty; 955 956 return (tp); 957 } 958 959 int 960 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 961 { 962 struct com_softc *sc; 963 struct tty *tp; 964 int error; 965 966 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 967 if (sc == NULL) 968 return ENXIO; 969 if (COM_ISALIVE(sc) == 0) 970 return (EIO); 971 972 tp = sc->sc_tty; 973 974 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 975 if (error != EPASSTHROUGH) 976 return (error); 977 978 error = ttioctl(tp, cmd, data, flag, l); 979 if (error != EPASSTHROUGH) 980 return (error); 981 982 error = 0; 983 switch (cmd) { 984 case TIOCSFLAGS: 985 error = kauth_authorize_device_tty(l->l_cred, 986 KAUTH_DEVICE_TTY_PRIVSET, tp); 987 break; 988 default: 989 /* nothing */ 990 break; 991 } 992 if (error) { 993 return error; 994 } 995 996 mutex_spin_enter(&sc->sc_lock); 997 998 switch (cmd) { 999 case TIOCSBRK: 1000 com_break(sc, 1); 1001 break; 1002 1003 case TIOCCBRK: 1004 com_break(sc, 0); 1005 break; 1006 1007 case TIOCSDTR: 1008 com_modem(sc, 1); 1009 break; 1010 1011 case TIOCCDTR: 1012 com_modem(sc, 0); 1013 break; 1014 1015 case TIOCGFLAGS: 1016 *(int *)data = sc->sc_swflags; 1017 break; 1018 1019 case TIOCSFLAGS: 1020 sc->sc_swflags = *(int *)data; 1021 break; 1022 1023 case TIOCMSET: 1024 case TIOCMBIS: 1025 case TIOCMBIC: 1026 tiocm_to_com(sc, cmd, *(int *)data); 1027 break; 1028 1029 case TIOCMGET: 1030 *(int *)data = com_to_tiocm(sc); 1031 break; 1032 1033 case PPS_IOC_CREATE: 1034 case PPS_IOC_DESTROY: 1035 case PPS_IOC_GETPARAMS: 1036 case PPS_IOC_SETPARAMS: 1037 case PPS_IOC_GETCAP: 1038 case PPS_IOC_FETCH: 1039 #ifdef PPS_SYNC 1040 case PPS_IOC_KCBIND: 1041 #endif 1042 mutex_spin_enter(&timecounter_lock); 1043 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1044 mutex_spin_exit(&timecounter_lock); 1045 break; 1046 1047 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1048 mutex_spin_enter(&timecounter_lock); 1049 #ifndef PPS_TRAILING_EDGE 1050 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1051 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1052 #else 1053 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1054 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1055 #endif 1056 mutex_spin_exit(&timecounter_lock); 1057 break; 1058 1059 default: 1060 error = EPASSTHROUGH; 1061 break; 1062 } 1063 1064 mutex_spin_exit(&sc->sc_lock); 1065 1066 #ifdef COM_DEBUG 1067 if (com_debug) 1068 comstatus(sc, "comioctl "); 1069 #endif 1070 1071 return (error); 1072 } 1073 1074 integrate void 1075 com_schedrx(struct com_softc *sc) 1076 { 1077 1078 sc->sc_rx_ready = 1; 1079 1080 /* Wake up the poller. */ 1081 softint_schedule(sc->sc_si); 1082 } 1083 1084 void 1085 com_break(struct com_softc *sc, int onoff) 1086 { 1087 1088 if (onoff) 1089 SET(sc->sc_lcr, LCR_SBREAK); 1090 else 1091 CLR(sc->sc_lcr, LCR_SBREAK); 1092 1093 if (!sc->sc_heldchange) { 1094 if (sc->sc_tx_busy) { 1095 sc->sc_heldtbc = sc->sc_tbc; 1096 sc->sc_tbc = 0; 1097 sc->sc_heldchange = 1; 1098 } else 1099 com_loadchannelregs(sc); 1100 } 1101 } 1102 1103 void 1104 com_modem(struct com_softc *sc, int onoff) 1105 { 1106 1107 if (sc->sc_mcr_dtr == 0) 1108 return; 1109 1110 if (onoff) 1111 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1112 else 1113 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1114 1115 if (!sc->sc_heldchange) { 1116 if (sc->sc_tx_busy) { 1117 sc->sc_heldtbc = sc->sc_tbc; 1118 sc->sc_tbc = 0; 1119 sc->sc_heldchange = 1; 1120 } else 1121 com_loadchannelregs(sc); 1122 } 1123 } 1124 1125 void 1126 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1127 { 1128 u_char combits; 1129 1130 combits = 0; 1131 if (ISSET(ttybits, TIOCM_DTR)) 1132 SET(combits, MCR_DTR); 1133 if (ISSET(ttybits, TIOCM_RTS)) 1134 SET(combits, MCR_RTS); 1135 1136 switch (how) { 1137 case TIOCMBIC: 1138 CLR(sc->sc_mcr, combits); 1139 break; 1140 1141 case TIOCMBIS: 1142 SET(sc->sc_mcr, combits); 1143 break; 1144 1145 case TIOCMSET: 1146 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1147 SET(sc->sc_mcr, combits); 1148 break; 1149 } 1150 1151 if (!sc->sc_heldchange) { 1152 if (sc->sc_tx_busy) { 1153 sc->sc_heldtbc = sc->sc_tbc; 1154 sc->sc_tbc = 0; 1155 sc->sc_heldchange = 1; 1156 } else 1157 com_loadchannelregs(sc); 1158 } 1159 } 1160 1161 int 1162 com_to_tiocm(struct com_softc *sc) 1163 { 1164 u_char combits; 1165 int ttybits = 0; 1166 1167 combits = sc->sc_mcr; 1168 if (ISSET(combits, MCR_DTR)) 1169 SET(ttybits, TIOCM_DTR); 1170 if (ISSET(combits, MCR_RTS)) 1171 SET(ttybits, TIOCM_RTS); 1172 1173 combits = sc->sc_msr; 1174 if (ISSET(combits, MSR_DCD)) 1175 SET(ttybits, TIOCM_CD); 1176 if (ISSET(combits, MSR_CTS)) 1177 SET(ttybits, TIOCM_CTS); 1178 if (ISSET(combits, MSR_DSR)) 1179 SET(ttybits, TIOCM_DSR); 1180 if (ISSET(combits, MSR_RI | MSR_TERI)) 1181 SET(ttybits, TIOCM_RI); 1182 1183 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1184 SET(ttybits, TIOCM_LE); 1185 1186 return (ttybits); 1187 } 1188 1189 static u_char 1190 cflag2lcr(tcflag_t cflag) 1191 { 1192 u_char lcr = 0; 1193 1194 switch (ISSET(cflag, CSIZE)) { 1195 case CS5: 1196 SET(lcr, LCR_5BITS); 1197 break; 1198 case CS6: 1199 SET(lcr, LCR_6BITS); 1200 break; 1201 case CS7: 1202 SET(lcr, LCR_7BITS); 1203 break; 1204 case CS8: 1205 SET(lcr, LCR_8BITS); 1206 break; 1207 } 1208 if (ISSET(cflag, PARENB)) { 1209 SET(lcr, LCR_PENAB); 1210 if (!ISSET(cflag, PARODD)) 1211 SET(lcr, LCR_PEVEN); 1212 } 1213 if (ISSET(cflag, CSTOPB)) 1214 SET(lcr, LCR_STOPB); 1215 1216 return (lcr); 1217 } 1218 1219 int 1220 comparam(struct tty *tp, struct termios *t) 1221 { 1222 struct com_softc *sc = 1223 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1224 int ospeed; 1225 u_char lcr; 1226 1227 if (COM_ISALIVE(sc) == 0) 1228 return (EIO); 1229 1230 #ifdef COM_HAYESP 1231 if (sc->sc_type == COM_TYPE_HAYESP) { 1232 int prescaler, speed; 1233 1234 /* 1235 * Calculate UART clock prescaler. It should be in 1236 * range of 0 .. 3. 1237 */ 1238 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1239 prescaler++, speed /= 2) 1240 if ((ospeed = comspeed(speed, sc->sc_frequency, 1241 sc->sc_type)) > 0) 1242 break; 1243 1244 if (prescaler == 4) 1245 return (EINVAL); 1246 sc->sc_prescaler = prescaler; 1247 } else 1248 #endif 1249 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1250 1251 /* Check requested parameters. */ 1252 if (ospeed < 0) 1253 return (EINVAL); 1254 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1255 return (EINVAL); 1256 1257 /* 1258 * For the console, always force CLOCAL and !HUPCL, so that the port 1259 * is always active. 1260 */ 1261 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1262 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1263 SET(t->c_cflag, CLOCAL); 1264 CLR(t->c_cflag, HUPCL); 1265 } 1266 1267 /* 1268 * If there were no changes, don't do anything. This avoids dropping 1269 * input and improves performance when all we did was frob things like 1270 * VMIN and VTIME. 1271 */ 1272 if (tp->t_ospeed == t->c_ospeed && 1273 tp->t_cflag == t->c_cflag) 1274 return (0); 1275 1276 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1277 1278 mutex_spin_enter(&sc->sc_lock); 1279 1280 sc->sc_lcr = lcr; 1281 1282 /* 1283 * If we're not in a mode that assumes a connection is present, then 1284 * ignore carrier changes. 1285 */ 1286 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1287 sc->sc_msr_dcd = 0; 1288 else 1289 sc->sc_msr_dcd = MSR_DCD; 1290 /* 1291 * Set the flow control pins depending on the current flow control 1292 * mode. 1293 */ 1294 if (ISSET(t->c_cflag, CRTSCTS)) { 1295 sc->sc_mcr_dtr = MCR_DTR; 1296 sc->sc_mcr_rts = MCR_RTS; 1297 sc->sc_msr_cts = MSR_CTS; 1298 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1299 } else if (ISSET(t->c_cflag, MDMBUF)) { 1300 /* 1301 * For DTR/DCD flow control, make sure we don't toggle DTR for 1302 * carrier detection. 1303 */ 1304 sc->sc_mcr_dtr = 0; 1305 sc->sc_mcr_rts = MCR_DTR; 1306 sc->sc_msr_cts = MSR_DCD; 1307 sc->sc_efr = 0; 1308 } else { 1309 /* 1310 * If no flow control, then always set RTS. This will make 1311 * the other side happy if it mistakenly thinks we're doing 1312 * RTS/CTS flow control. 1313 */ 1314 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1315 sc->sc_mcr_rts = 0; 1316 sc->sc_msr_cts = 0; 1317 sc->sc_efr = 0; 1318 if (ISSET(sc->sc_mcr, MCR_DTR)) 1319 SET(sc->sc_mcr, MCR_RTS); 1320 else 1321 CLR(sc->sc_mcr, MCR_RTS); 1322 } 1323 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1324 1325 #if 0 1326 if (ospeed == 0) 1327 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1328 else 1329 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1330 #endif 1331 1332 sc->sc_dlbl = ospeed; 1333 sc->sc_dlbh = ospeed >> 8; 1334 1335 /* 1336 * Set the FIFO threshold based on the receive speed. 1337 * 1338 * * If it's a low speed, it's probably a mouse or some other 1339 * interactive device, so set the threshold low. 1340 * * If it's a high speed, trim the trigger level down to prevent 1341 * overflows. 1342 * * Otherwise set it a bit higher. 1343 */ 1344 if (sc->sc_type == COM_TYPE_HAYESP) 1345 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1346 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1347 if (t->c_ospeed <= 1200) 1348 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1349 else if (t->c_ospeed <= 38400) 1350 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1351 else 1352 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1353 } else 1354 sc->sc_fifo = 0; 1355 1356 /* And copy to tty. */ 1357 tp->t_ispeed = t->c_ospeed; 1358 tp->t_ospeed = t->c_ospeed; 1359 tp->t_cflag = t->c_cflag; 1360 1361 if (!sc->sc_heldchange) { 1362 if (sc->sc_tx_busy) { 1363 sc->sc_heldtbc = sc->sc_tbc; 1364 sc->sc_tbc = 0; 1365 sc->sc_heldchange = 1; 1366 } else 1367 com_loadchannelregs(sc); 1368 } 1369 1370 if (!ISSET(t->c_cflag, CHWFLOW)) { 1371 /* Disable the high water mark. */ 1372 sc->sc_r_hiwat = 0; 1373 sc->sc_r_lowat = 0; 1374 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1375 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1376 com_schedrx(sc); 1377 } 1378 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1379 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1380 com_hwiflow(sc); 1381 } 1382 } else { 1383 sc->sc_r_hiwat = com_rbuf_hiwat; 1384 sc->sc_r_lowat = com_rbuf_lowat; 1385 } 1386 1387 mutex_spin_exit(&sc->sc_lock); 1388 1389 /* 1390 * Update the tty layer's idea of the carrier bit, in case we changed 1391 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1392 * explicit request. 1393 */ 1394 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1395 1396 #ifdef COM_DEBUG 1397 if (com_debug) 1398 comstatus(sc, "comparam "); 1399 #endif 1400 1401 if (!ISSET(t->c_cflag, CHWFLOW)) { 1402 if (sc->sc_tx_stopped) { 1403 sc->sc_tx_stopped = 0; 1404 comstart(tp); 1405 } 1406 } 1407 1408 return (0); 1409 } 1410 1411 void 1412 com_iflush(struct com_softc *sc) 1413 { 1414 struct com_regs *regsp = &sc->sc_regs; 1415 #ifdef DIAGNOSTIC 1416 int reg; 1417 #endif 1418 int timo; 1419 1420 #ifdef DIAGNOSTIC 1421 reg = 0xffff; 1422 #endif 1423 timo = 50000; 1424 /* flush any pending I/O */ 1425 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1426 && --timo) 1427 #ifdef DIAGNOSTIC 1428 reg = 1429 #else 1430 (void) 1431 #endif 1432 CSR_READ_1(regsp, COM_REG_RXDATA); 1433 #ifdef DIAGNOSTIC 1434 if (!timo) 1435 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1436 #endif 1437 } 1438 1439 void 1440 com_loadchannelregs(struct com_softc *sc) 1441 { 1442 struct com_regs *regsp = &sc->sc_regs; 1443 1444 /* XXXXX necessary? */ 1445 com_iflush(sc); 1446 1447 if (sc->sc_type == COM_TYPE_PXA2x0) 1448 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1449 else 1450 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1451 1452 if (sc->sc_type == COM_TYPE_OMAP) { 1453 /* disable before changing settings */ 1454 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1455 } 1456 1457 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1458 if (sc->sc_type != COM_TYPE_AU1x00 1459 && sc->sc_type != COM_TYPE_16550_NOERS) { 1460 /* no EFR on alchemy */ 1461 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1462 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1463 } 1464 } 1465 if (sc->sc_type == COM_TYPE_AU1x00) { 1466 /* alchemy has single separate 16-bit clock divisor register */ 1467 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1468 (sc->sc_dlbh << 8)); 1469 } else { 1470 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1471 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1472 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1473 } 1474 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1475 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1476 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1477 #ifdef COM_HAYESP 1478 if (sc->sc_type == COM_TYPE_HAYESP) { 1479 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1480 HAYESP_SETPRESCALER); 1481 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1482 sc->sc_prescaler); 1483 } 1484 #endif 1485 if (sc->sc_type == COM_TYPE_OMAP) { 1486 /* setup the fifos. the FCR value is not used as long 1487 as SCR[6] and SCR[7] are 0, which they are at reset 1488 and we never touch the SCR register */ 1489 uint8_t rx_fifo_trig = 40; 1490 uint8_t tx_fifo_trig = 60; 1491 uint8_t rx_start = 8; 1492 uint8_t rx_halt = 60; 1493 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1494 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1495 1496 /* enable access to TCR & TLR */ 1497 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1498 1499 /* write tcr and tlr values */ 1500 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1501 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1502 1503 /* disable access to TCR & TLR */ 1504 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1505 1506 /* enable again, but mode is based on speed */ 1507 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1508 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1509 } else { 1510 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1511 } 1512 } 1513 1514 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1515 } 1516 1517 int 1518 comhwiflow(struct tty *tp, int block) 1519 { 1520 struct com_softc *sc = 1521 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1522 1523 if (COM_ISALIVE(sc) == 0) 1524 return (0); 1525 1526 if (sc->sc_mcr_rts == 0) 1527 return (0); 1528 1529 mutex_spin_enter(&sc->sc_lock); 1530 1531 if (block) { 1532 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1533 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1534 com_hwiflow(sc); 1535 } 1536 } else { 1537 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1538 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1539 com_schedrx(sc); 1540 } 1541 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1542 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1543 com_hwiflow(sc); 1544 } 1545 } 1546 1547 mutex_spin_exit(&sc->sc_lock); 1548 return (1); 1549 } 1550 1551 /* 1552 * (un)block input via hw flowcontrol 1553 */ 1554 void 1555 com_hwiflow(struct com_softc *sc) 1556 { 1557 struct com_regs *regsp= &sc->sc_regs; 1558 1559 if (sc->sc_mcr_rts == 0) 1560 return; 1561 1562 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1563 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1564 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1565 } else { 1566 SET(sc->sc_mcr, sc->sc_mcr_rts); 1567 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1568 } 1569 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1570 } 1571 1572 1573 void 1574 comstart(struct tty *tp) 1575 { 1576 struct com_softc *sc = 1577 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1578 struct com_regs *regsp = &sc->sc_regs; 1579 int s; 1580 1581 if (COM_ISALIVE(sc) == 0) 1582 return; 1583 1584 s = spltty(); 1585 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1586 goto out; 1587 if (sc->sc_tx_stopped) 1588 goto out; 1589 if (!ttypull(tp)) 1590 goto out; 1591 1592 /* Grab the first contiguous region of buffer space. */ 1593 { 1594 u_char *tba; 1595 int tbc; 1596 1597 tba = tp->t_outq.c_cf; 1598 tbc = ndqb(&tp->t_outq, 0); 1599 1600 mutex_spin_enter(&sc->sc_lock); 1601 1602 sc->sc_tba = tba; 1603 sc->sc_tbc = tbc; 1604 } 1605 1606 SET(tp->t_state, TS_BUSY); 1607 sc->sc_tx_busy = 1; 1608 1609 /* Enable transmit completion interrupts if necessary. */ 1610 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1611 SET(sc->sc_ier, IER_ETXRDY); 1612 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1613 } 1614 1615 /* Output the first chunk of the contiguous buffer. */ 1616 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1617 u_int n; 1618 1619 n = sc->sc_tbc; 1620 if (n > sc->sc_fifolen) 1621 n = sc->sc_fifolen; 1622 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1623 sc->sc_tbc -= n; 1624 sc->sc_tba += n; 1625 } 1626 1627 mutex_spin_exit(&sc->sc_lock); 1628 out: 1629 splx(s); 1630 return; 1631 } 1632 1633 /* 1634 * Stop output on a line. 1635 */ 1636 void 1637 comstop(struct tty *tp, int flag) 1638 { 1639 struct com_softc *sc = 1640 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1641 1642 mutex_spin_enter(&sc->sc_lock); 1643 if (ISSET(tp->t_state, TS_BUSY)) { 1644 /* Stop transmitting at the next chunk. */ 1645 sc->sc_tbc = 0; 1646 sc->sc_heldtbc = 0; 1647 if (!ISSET(tp->t_state, TS_TTSTOP)) 1648 SET(tp->t_state, TS_FLUSH); 1649 } 1650 mutex_spin_exit(&sc->sc_lock); 1651 } 1652 1653 void 1654 comdiag(void *arg) 1655 { 1656 struct com_softc *sc = arg; 1657 int overflows, floods; 1658 1659 mutex_spin_enter(&sc->sc_lock); 1660 overflows = sc->sc_overflows; 1661 sc->sc_overflows = 0; 1662 floods = sc->sc_floods; 1663 sc->sc_floods = 0; 1664 sc->sc_errors = 0; 1665 mutex_spin_exit(&sc->sc_lock); 1666 1667 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1668 device_xname(sc->sc_dev), 1669 overflows, overflows == 1 ? "" : "s", 1670 floods, floods == 1 ? "" : "s"); 1671 } 1672 1673 integrate void 1674 com_rxsoft(struct com_softc *sc, struct tty *tp) 1675 { 1676 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1677 u_char *get, *end; 1678 u_int cc, scc; 1679 u_char lsr; 1680 int code; 1681 1682 end = sc->sc_ebuf; 1683 get = sc->sc_rbget; 1684 scc = cc = com_rbuf_size - sc->sc_rbavail; 1685 1686 if (cc == com_rbuf_size) { 1687 sc->sc_floods++; 1688 if (sc->sc_errors++ == 0) 1689 callout_reset(&sc->sc_diag_callout, 60 * hz, 1690 comdiag, sc); 1691 } 1692 1693 /* If not yet open, drop the entire buffer content here */ 1694 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1695 get += cc << 1; 1696 if (get >= end) 1697 get -= com_rbuf_size << 1; 1698 cc = 0; 1699 } 1700 while (cc) { 1701 code = get[0]; 1702 lsr = get[1]; 1703 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1704 if (ISSET(lsr, LSR_OE)) { 1705 sc->sc_overflows++; 1706 if (sc->sc_errors++ == 0) 1707 callout_reset(&sc->sc_diag_callout, 1708 60 * hz, comdiag, sc); 1709 } 1710 if (ISSET(lsr, LSR_BI | LSR_FE)) 1711 SET(code, TTY_FE); 1712 if (ISSET(lsr, LSR_PE)) 1713 SET(code, TTY_PE); 1714 } 1715 if ((*rint)(code, tp) == -1) { 1716 /* 1717 * The line discipline's buffer is out of space. 1718 */ 1719 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1720 /* 1721 * We're either not using flow control, or the 1722 * line discipline didn't tell us to block for 1723 * some reason. Either way, we have no way to 1724 * know when there's more space available, so 1725 * just drop the rest of the data. 1726 */ 1727 get += cc << 1; 1728 if (get >= end) 1729 get -= com_rbuf_size << 1; 1730 cc = 0; 1731 } else { 1732 /* 1733 * Don't schedule any more receive processing 1734 * until the line discipline tells us there's 1735 * space available (through comhwiflow()). 1736 * Leave the rest of the data in the input 1737 * buffer. 1738 */ 1739 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1740 } 1741 break; 1742 } 1743 get += 2; 1744 if (get >= end) 1745 get = sc->sc_rbuf; 1746 cc--; 1747 } 1748 1749 if (cc != scc) { 1750 sc->sc_rbget = get; 1751 mutex_spin_enter(&sc->sc_lock); 1752 1753 cc = sc->sc_rbavail += scc - cc; 1754 /* Buffers should be ok again, release possible block. */ 1755 if (cc >= sc->sc_r_lowat) { 1756 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1757 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1758 SET(sc->sc_ier, IER_ERXRDY); 1759 #ifdef COM_PXA2X0 1760 if (sc->sc_type == COM_TYPE_PXA2x0) 1761 SET(sc->sc_ier, IER_ERXTOUT); 1762 #endif 1763 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1764 } 1765 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1766 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1767 com_hwiflow(sc); 1768 } 1769 } 1770 mutex_spin_exit(&sc->sc_lock); 1771 } 1772 } 1773 1774 integrate void 1775 com_txsoft(struct com_softc *sc, struct tty *tp) 1776 { 1777 1778 CLR(tp->t_state, TS_BUSY); 1779 if (ISSET(tp->t_state, TS_FLUSH)) 1780 CLR(tp->t_state, TS_FLUSH); 1781 else 1782 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1783 (*tp->t_linesw->l_start)(tp); 1784 } 1785 1786 integrate void 1787 com_stsoft(struct com_softc *sc, struct tty *tp) 1788 { 1789 u_char msr, delta; 1790 1791 mutex_spin_enter(&sc->sc_lock); 1792 msr = sc->sc_msr; 1793 delta = sc->sc_msr_delta; 1794 sc->sc_msr_delta = 0; 1795 mutex_spin_exit(&sc->sc_lock); 1796 1797 if (ISSET(delta, sc->sc_msr_dcd)) { 1798 /* 1799 * Inform the tty layer that carrier detect changed. 1800 */ 1801 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1802 } 1803 1804 if (ISSET(delta, sc->sc_msr_cts)) { 1805 /* Block or unblock output according to flow control. */ 1806 if (ISSET(msr, sc->sc_msr_cts)) { 1807 sc->sc_tx_stopped = 0; 1808 (*tp->t_linesw->l_start)(tp); 1809 } else { 1810 sc->sc_tx_stopped = 1; 1811 } 1812 } 1813 1814 #ifdef COM_DEBUG 1815 if (com_debug) 1816 comstatus(sc, "com_stsoft"); 1817 #endif 1818 } 1819 1820 void 1821 comsoft(void *arg) 1822 { 1823 struct com_softc *sc = arg; 1824 struct tty *tp; 1825 1826 if (COM_ISALIVE(sc) == 0) 1827 return; 1828 1829 tp = sc->sc_tty; 1830 1831 if (sc->sc_rx_ready) { 1832 sc->sc_rx_ready = 0; 1833 com_rxsoft(sc, tp); 1834 } 1835 1836 if (sc->sc_st_check) { 1837 sc->sc_st_check = 0; 1838 com_stsoft(sc, tp); 1839 } 1840 1841 if (sc->sc_tx_done) { 1842 sc->sc_tx_done = 0; 1843 com_txsoft(sc, tp); 1844 } 1845 } 1846 1847 int 1848 comintr(void *arg) 1849 { 1850 struct com_softc *sc = arg; 1851 struct com_regs *regsp = &sc->sc_regs; 1852 1853 u_char *put, *end; 1854 u_int cc; 1855 u_char lsr, iir; 1856 1857 if (COM_ISALIVE(sc) == 0) 1858 return (0); 1859 1860 mutex_spin_enter(&sc->sc_lock); 1861 iir = CSR_READ_1(regsp, COM_REG_IIR); 1862 if (ISSET(iir, IIR_NOPEND)) { 1863 mutex_spin_exit(&sc->sc_lock); 1864 return (0); 1865 } 1866 1867 end = sc->sc_ebuf; 1868 put = sc->sc_rbput; 1869 cc = sc->sc_rbavail; 1870 1871 again: do { 1872 u_char msr, delta; 1873 1874 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1875 if (ISSET(lsr, LSR_BI)) { 1876 int cn_trapped = 0; 1877 1878 cn_check_magic(sc->sc_tty->t_dev, 1879 CNC_BREAK, com_cnm_state); 1880 if (cn_trapped) 1881 continue; 1882 #if defined(KGDB) && !defined(DDB) 1883 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1884 kgdb_connect(1); 1885 continue; 1886 } 1887 #endif 1888 } 1889 1890 if (ISSET(lsr, LSR_RCV_MASK) && 1891 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1892 while (cc > 0) { 1893 int cn_trapped = 0; 1894 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1895 put[1] = lsr; 1896 cn_check_magic(sc->sc_tty->t_dev, 1897 put[0], com_cnm_state); 1898 if (cn_trapped) 1899 goto next; 1900 put += 2; 1901 if (put >= end) 1902 put = sc->sc_rbuf; 1903 cc--; 1904 next: 1905 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1906 if (!ISSET(lsr, LSR_RCV_MASK)) 1907 break; 1908 } 1909 1910 /* 1911 * Current string of incoming characters ended because 1912 * no more data was available or we ran out of space. 1913 * Schedule a receive event if any data was received. 1914 * If we're out of space, turn off receive interrupts. 1915 */ 1916 sc->sc_rbput = put; 1917 sc->sc_rbavail = cc; 1918 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1919 sc->sc_rx_ready = 1; 1920 1921 /* 1922 * See if we are in danger of overflowing a buffer. If 1923 * so, use hardware flow control to ease the pressure. 1924 */ 1925 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1926 cc < sc->sc_r_hiwat) { 1927 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1928 com_hwiflow(sc); 1929 } 1930 1931 /* 1932 * If we're out of space, disable receive interrupts 1933 * until the queue has drained a bit. 1934 */ 1935 if (!cc) { 1936 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1937 #ifdef COM_PXA2X0 1938 if (sc->sc_type == COM_TYPE_PXA2x0) 1939 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 1940 else 1941 #endif 1942 CLR(sc->sc_ier, IER_ERXRDY); 1943 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1944 } 1945 } else { 1946 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 1947 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 1948 continue; 1949 } 1950 } 1951 1952 msr = CSR_READ_1(regsp, COM_REG_MSR); 1953 delta = msr ^ sc->sc_msr; 1954 sc->sc_msr = msr; 1955 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1956 (delta & MSR_DCD)) { 1957 mutex_spin_enter(&timecounter_lock); 1958 pps_capture(&sc->sc_pps_state); 1959 pps_event(&sc->sc_pps_state, 1960 (msr & MSR_DCD) ? 1961 PPS_CAPTUREASSERT : 1962 PPS_CAPTURECLEAR); 1963 mutex_spin_exit(&timecounter_lock); 1964 } 1965 1966 /* 1967 * Process normal status changes 1968 */ 1969 if (ISSET(delta, sc->sc_msr_mask)) { 1970 SET(sc->sc_msr_delta, delta); 1971 1972 /* 1973 * Stop output immediately if we lose the output 1974 * flow control signal or carrier detect. 1975 */ 1976 if (ISSET(~msr, sc->sc_msr_mask)) { 1977 sc->sc_tbc = 0; 1978 sc->sc_heldtbc = 0; 1979 #ifdef COM_DEBUG 1980 if (com_debug) 1981 comstatus(sc, "comintr "); 1982 #endif 1983 } 1984 1985 sc->sc_st_check = 1; 1986 } 1987 } while (!ISSET((iir = 1988 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 1989 /* 1990 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 1991 * by IIR read, so we can't do this way: `process all interrupts, 1992 * then do TX if possble'. 1993 */ 1994 (iir & IIR_IMASK) != IIR_TXRDY); 1995 1996 /* 1997 * Read LSR again, since there may be an interrupt between 1998 * the last LSR read and IIR read above. 1999 */ 2000 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2001 2002 /* 2003 * See if data can be transmitted as well. 2004 * Schedule tx done event if no data left 2005 * and tty was marked busy. 2006 */ 2007 if (ISSET(lsr, LSR_TXRDY)) { 2008 /* 2009 * If we've delayed a parameter change, do it now, and restart 2010 * output. 2011 */ 2012 if (sc->sc_heldchange) { 2013 com_loadchannelregs(sc); 2014 sc->sc_heldchange = 0; 2015 sc->sc_tbc = sc->sc_heldtbc; 2016 sc->sc_heldtbc = 0; 2017 } 2018 2019 /* Output the next chunk of the contiguous buffer, if any. */ 2020 if (sc->sc_tbc > 0) { 2021 u_int n; 2022 2023 n = sc->sc_tbc; 2024 if (n > sc->sc_fifolen) 2025 n = sc->sc_fifolen; 2026 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2027 sc->sc_tbc -= n; 2028 sc->sc_tba += n; 2029 } else { 2030 /* Disable transmit completion interrupts if necessary. */ 2031 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2032 CLR(sc->sc_ier, IER_ETXRDY); 2033 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2034 } 2035 if (sc->sc_tx_busy) { 2036 sc->sc_tx_busy = 0; 2037 sc->sc_tx_done = 1; 2038 } 2039 } 2040 } 2041 2042 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2043 goto again; 2044 2045 mutex_spin_exit(&sc->sc_lock); 2046 2047 /* Wake up the poller. */ 2048 softint_schedule(sc->sc_si); 2049 2050 #if NRND > 0 && defined(RND_COM) 2051 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2052 #endif 2053 2054 return (1); 2055 } 2056 2057 /* 2058 * The following functions are polled getc and putc routines, shared 2059 * by the console and kgdb glue. 2060 * 2061 * The read-ahead code is so that you can detect pending in-band 2062 * cn_magic in polled mode while doing output rather than having to 2063 * wait until the kernel decides it needs input. 2064 */ 2065 2066 #define MAX_READAHEAD 20 2067 static int com_readahead[MAX_READAHEAD]; 2068 static int com_readaheadcount = 0; 2069 2070 int 2071 com_common_getc(dev_t dev, struct com_regs *regsp) 2072 { 2073 int s = splserial(); 2074 u_char stat, c; 2075 2076 /* got a character from reading things earlier */ 2077 if (com_readaheadcount > 0) { 2078 int i; 2079 2080 c = com_readahead[0]; 2081 for (i = 1; i < com_readaheadcount; i++) { 2082 com_readahead[i-1] = com_readahead[i]; 2083 } 2084 com_readaheadcount--; 2085 splx(s); 2086 return (c); 2087 } 2088 2089 /* block until a character becomes available */ 2090 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2091 ; 2092 2093 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2094 stat = CSR_READ_1(regsp, COM_REG_IIR); 2095 { 2096 int cn_trapped = 0; /* unused */ 2097 #ifdef DDB 2098 extern int db_active; 2099 if (!db_active) 2100 #endif 2101 cn_check_magic(dev, c, com_cnm_state); 2102 } 2103 splx(s); 2104 return (c); 2105 } 2106 2107 void 2108 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2109 { 2110 int s = splserial(); 2111 int cin, stat, timo; 2112 2113 if (com_readaheadcount < MAX_READAHEAD 2114 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2115 int cn_trapped = 0; 2116 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2117 stat = CSR_READ_1(regsp, COM_REG_IIR); 2118 cn_check_magic(dev, cin, com_cnm_state); 2119 com_readahead[com_readaheadcount++] = cin; 2120 } 2121 2122 /* wait for any pending transmission to finish */ 2123 timo = 150000; 2124 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2125 continue; 2126 2127 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2128 COM_BARRIER(regsp, BR | BW); 2129 2130 splx(s); 2131 } 2132 2133 /* 2134 * Initialize UART for use as console or KGDB line. 2135 */ 2136 int 2137 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2138 tcflag_t cflag) 2139 { 2140 2141 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2142 ®sp->cr_ioh)) 2143 return (ENOMEM); /* ??? */ 2144 2145 if (type == COM_TYPE_OMAP) { 2146 /* disable before changing settings */ 2147 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2148 } 2149 2150 rate = comspeed(rate, frequency, type); 2151 if (type != COM_TYPE_AU1x00) { 2152 /* no EFR on alchemy */ 2153 if (type != COM_TYPE_16550_NOERS) { 2154 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2155 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2156 } 2157 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2158 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2159 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2160 } else { 2161 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2162 } 2163 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2164 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2165 CSR_WRITE_1(regsp, COM_REG_FIFO, 2166 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2167 2168 if (type == COM_TYPE_OMAP) { 2169 /* setup the fifos. the FCR value is not used as long 2170 as SCR[6] and SCR[7] are 0, which they are at reset 2171 and we never touch the SCR register */ 2172 uint8_t rx_fifo_trig = 40; 2173 uint8_t tx_fifo_trig = 60; 2174 uint8_t rx_start = 8; 2175 uint8_t rx_halt = 60; 2176 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2177 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2178 2179 /* enable access to TCR & TLR */ 2180 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2181 2182 /* write tcr and tlr values */ 2183 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2184 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2185 2186 /* disable access to TCR & TLR */ 2187 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2188 2189 /* enable again, but mode is based on speed */ 2190 if (rate > 230400) { 2191 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2192 } else { 2193 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2194 } 2195 } 2196 2197 #ifdef COM_PXA2X0 2198 if (type == COM_TYPE_PXA2x0) 2199 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2200 else 2201 #endif 2202 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2203 2204 return (0); 2205 } 2206 2207 /* 2208 * Following are all routines needed for COM to act as console 2209 */ 2210 struct consdev comcons = { 2211 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 2212 NODEV, CN_NORMAL 2213 }; 2214 2215 2216 int 2217 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2218 tcflag_t cflag) 2219 { 2220 int res; 2221 2222 comconsregs = *regsp; 2223 2224 res = cominit(&comconsregs, rate, frequency, type, cflag); 2225 if (res) 2226 return (res); 2227 2228 cn_tab = &comcons; 2229 cn_init_magic(&com_cnm_state); 2230 cn_set_magic("\047\001"); /* default magic is BREAK */ 2231 2232 comconsrate = rate; 2233 comconscflag = cflag; 2234 2235 return (0); 2236 } 2237 2238 int 2239 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2240 int type, tcflag_t cflag) 2241 { 2242 struct com_regs regs; 2243 2244 memset(®s, 0, sizeof regs); 2245 regs.cr_iot = iot; 2246 regs.cr_iobase = iobase; 2247 regs.cr_nports = COM_NPORTS; 2248 #ifdef COM_REGMAP 2249 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2250 #endif 2251 2252 return comcnattach1(®s, rate, frequency, type, cflag); 2253 } 2254 2255 int 2256 comcngetc(dev_t dev) 2257 { 2258 2259 return (com_common_getc(dev, &comconsregs)); 2260 } 2261 2262 /* 2263 * Console kernel output character routine. 2264 */ 2265 void 2266 comcnputc(dev_t dev, int c) 2267 { 2268 2269 com_common_putc(dev, &comconsregs, c); 2270 } 2271 2272 void 2273 comcnpollc(dev_t dev, int on) 2274 { 2275 2276 } 2277 2278 #ifdef KGDB 2279 int 2280 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2281 tcflag_t cflag) 2282 { 2283 int res; 2284 2285 if (regsp->cr_iot == comconsregs.cr_iot && 2286 regsp->cr_iobase == comconsregs.cr_iobase) { 2287 #if !defined(DDB) 2288 return (EBUSY); /* cannot share with console */ 2289 #else 2290 comkgdbregs = *regsp; 2291 comkgdbregs.cr_ioh = comconsregs.cr_ioh; 2292 #endif 2293 } else { 2294 comkgdbregs = *regsp; 2295 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2296 if (res) 2297 return (res); 2298 2299 /* 2300 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2301 * expects this to be initialized 2302 */ 2303 cn_init_magic(&com_cnm_state); 2304 cn_set_magic("\047\001"); 2305 } 2306 2307 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2308 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2309 2310 return (0); 2311 } 2312 2313 int 2314 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2315 int frequency, int type, tcflag_t cflag) 2316 { 2317 struct com_regs regs; 2318 2319 regs.cr_iot = iot; 2320 regs.cr_nports = COM_NPORTS; 2321 regs.cr_iobase = iobase; 2322 #ifdef COM_REGMAP 2323 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2324 #endif 2325 2326 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2327 } 2328 2329 /* ARGSUSED */ 2330 int 2331 com_kgdb_getc(void *arg) 2332 { 2333 2334 return (com_common_getc(NODEV, &comkgdbregs)); 2335 } 2336 2337 /* ARGSUSED */ 2338 void 2339 com_kgdb_putc(void *arg, int c) 2340 { 2341 2342 com_common_putc(NODEV, &comkgdbregs, c); 2343 } 2344 #endif /* KGDB */ 2345 2346 /* helper function to identify the com ports used by 2347 console or KGDB (and not yet autoconf attached) */ 2348 int 2349 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2350 { 2351 bus_space_handle_t help; 2352 2353 if (!comconsattached && 2354 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase) 2355 help = comconsregs.cr_ioh; 2356 #ifdef KGDB 2357 else if (!com_kgdb_attached && 2358 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2359 help = comkgdbregs.cr_ioh; 2360 #endif 2361 else 2362 return (0); 2363 2364 if (ioh) 2365 *ioh = help; 2366 return (1); 2367 } 2368 2369 /* 2370 * this routine exists to serve as a shutdown hook for systems that 2371 * have firmware which doesn't interact properly with a com device in 2372 * FIFO mode. 2373 */ 2374 bool 2375 com_cleanup(device_t self, int how) 2376 { 2377 struct com_softc *sc = device_private(self); 2378 2379 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2380 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2381 2382 return true; 2383 } 2384 2385 bool 2386 com_suspend(device_t self PMF_FN_ARGS) 2387 { 2388 struct com_softc *sc = device_private(self); 2389 2390 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2391 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2392 2393 return true; 2394 } 2395 2396 bool 2397 com_resume(device_t self PMF_FN_ARGS) 2398 { 2399 struct com_softc *sc = device_private(self); 2400 2401 mutex_spin_enter(&sc->sc_lock); 2402 com_loadchannelregs(sc); 2403 mutex_spin_exit(&sc->sc_lock); 2404 2405 return true; 2406 } 2407
Indexes created Wed Oct 22 00:09:40 GMT 2025