com.c revision 1.289
1 /* $NetBSD: com.c,v 1.289 2009/11/12 20:37:09 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.289 2009/11/12 20:37:09 dyoung Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 #if NRND > 0 && defined(RND_COM) 80 #include <sys/rnd.h> 81 #endif 82 83 /* The COM16650 option was renamed to COM_16650. */ 84 #ifdef COM16650 85 #error Obsolete COM16650 option; use COM_16650 instead. 86 #endif 87 88 /* 89 * Override cnmagic(9) macro before including <sys/systm.h>. 90 * We need to know if cn_check_magic triggered debugger, so set a flag. 91 * Callers of cn_check_magic must declare int cn_trapped = 0; 92 * XXX: this is *ugly*! 93 */ 94 #define cn_trap() \ 95 do { \ 96 console_debugger(); \ 97 cn_trapped = 1; \ 98 } while (/* CONSTCOND */ 0) 99 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/ioctl.h> 103 #include <sys/select.h> 104 #include <sys/poll.h> 105 #include <sys/tty.h> 106 #include <sys/proc.h> 107 #include <sys/user.h> 108 #include <sys/conf.h> 109 #include <sys/file.h> 110 #include <sys/uio.h> 111 #include <sys/kernel.h> 112 #include <sys/syslog.h> 113 #include <sys/device.h> 114 #include <sys/malloc.h> 115 #include <sys/timepps.h> 116 #include <sys/vnode.h> 117 #include <sys/kauth.h> 118 #include <sys/intr.h> 119 120 #include <sys/bus.h> 121 122 #include <dev/ic/comreg.h> 123 #include <dev/ic/comvar.h> 124 #include <dev/ic/ns16550reg.h> 125 #include <dev/ic/st16650reg.h> 126 #ifdef COM_HAYESP 127 #include <dev/ic/hayespreg.h> 128 #endif 129 #define com_lcr com_cfcr 130 #include <dev/cons.h> 131 132 #ifdef COM_REGMAP 133 #define CSR_WRITE_1(r, o, v) \ 134 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 135 #define CSR_READ_1(r, o) \ 136 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 137 #define CSR_WRITE_2(r, o, v) \ 138 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 139 #define CSR_READ_2(r, o) \ 140 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 141 #define CSR_WRITE_MULTI(r, o, p, n) \ 142 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 143 #else 144 #define CSR_WRITE_1(r, o, v) \ 145 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 146 #define CSR_READ_1(r, o) \ 147 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 148 #define CSR_WRITE_2(r, o, v) \ 149 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 150 #define CSR_READ_2(r, o) \ 151 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 152 #define CSR_WRITE_MULTI(r, o, p, n) \ 153 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 154 #endif 155 156 157 static void com_enable_debugport(struct com_softc *); 158 159 void com_config(struct com_softc *); 160 void com_shutdown(struct com_softc *); 161 int comspeed(long, long, int); 162 static u_char cflag2lcr(tcflag_t); 163 int comparam(struct tty *, struct termios *); 164 void comstart(struct tty *); 165 int comhwiflow(struct tty *, int); 166 167 void com_loadchannelregs(struct com_softc *); 168 void com_hwiflow(struct com_softc *); 169 void com_break(struct com_softc *, int); 170 void com_modem(struct com_softc *, int); 171 void tiocm_to_com(struct com_softc *, u_long, int); 172 int com_to_tiocm(struct com_softc *); 173 void com_iflush(struct com_softc *); 174 175 int com_common_getc(dev_t, struct com_regs *); 176 static void com_common_putc(dev_t, struct com_regs *, int); 177 178 int cominit(struct com_regs *, int, int, int, tcflag_t); 179 180 #if 0 181 static int comcngetc_detached(dev_t); 182 static void comcnputc_detached(dev_t, int); 183 #endif 184 185 static int comcnreattach(void); 186 187 int comcngetc(dev_t); 188 void comcnputc(dev_t, int); 189 void comcnpollc(dev_t, int); 190 191 #define integrate static inline 192 void comsoft(void *); 193 integrate void com_rxsoft(struct com_softc *, struct tty *); 194 integrate void com_txsoft(struct com_softc *, struct tty *); 195 integrate void com_stsoft(struct com_softc *, struct tty *); 196 integrate void com_schedrx(struct com_softc *); 197 void comdiag(void *); 198 199 extern struct cfdriver com_cd; 200 201 dev_type_open(comopen); 202 dev_type_close(comclose); 203 dev_type_read(comread); 204 dev_type_write(comwrite); 205 dev_type_ioctl(comioctl); 206 dev_type_stop(comstop); 207 dev_type_tty(comtty); 208 dev_type_poll(compoll); 209 210 static struct comcons_info comcons_info; 211 212 #if 0 213 static struct consdev comcons_detached = { 214 NULL, NULL, comcngetc_detached, comcnputc_detached, comcnpollc, 215 NULL, NULL, NULL, NODEV, CN_NULL 216 }; 217 #endif 218 219 /* 220 * Following are all routines needed for COM to act as console 221 */ 222 static struct consdev comcons = { 223 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 224 NODEV, CN_NORMAL 225 }; 226 227 228 const struct cdevsw com_cdevsw = { 229 comopen, comclose, comread, comwrite, comioctl, 230 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 231 }; 232 233 /* 234 * Make this an option variable one can patch. 235 * But be warned: this must be a power of 2! 236 */ 237 u_int com_rbuf_size = COM_RING_SIZE; 238 239 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 240 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 241 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 242 243 static int comconsattached; 244 static struct cnm_state com_cnm_state; 245 246 #ifdef KGDB 247 #include <sys/kgdb.h> 248 249 static struct com_regs comkgdbregs; 250 static int com_kgdb_attached; 251 252 int com_kgdb_getc(void *); 253 void com_kgdb_putc(void *, int); 254 #endif /* KGDB */ 255 256 #ifdef COM_REGMAP 257 /* initializer for typical 16550-ish hardware */ 258 #define COM_REG_16550 { \ 259 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 260 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 261 262 const bus_size_t com_std_map[16] = COM_REG_16550; 263 #endif /* COM_REGMAP */ 264 265 #define COMUNIT_MASK 0x7ffff 266 #define COMDIALOUT_MASK 0x80000 267 268 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 269 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 270 271 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 272 device_is_active((sc)->sc_dev)) 273 274 #define BR BUS_SPACE_BARRIER_READ 275 #define BW BUS_SPACE_BARRIER_WRITE 276 #define COM_BARRIER(r, f) \ 277 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 278 279 /*ARGSUSED*/ 280 int 281 comspeed(long speed, long frequency, int type) 282 { 283 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 284 285 int x, err; 286 int divisor = 16; 287 288 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 289 divisor = 13; 290 } 291 292 #if 0 293 if (speed == 0) 294 return (0); 295 #endif 296 if (speed <= 0) 297 return (-1); 298 x = divrnd(frequency / divisor, speed); 299 if (x <= 0) 300 return (-1); 301 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 302 if (err < 0) 303 err = -err; 304 if (err > COM_TOLERANCE) 305 return (-1); 306 return (x); 307 308 #undef divrnd 309 } 310 311 #ifdef COM_DEBUG 312 int com_debug = 0; 313 314 void comstatus(struct com_softc *, const char *); 315 void 316 comstatus(struct com_softc *sc, const char *str) 317 { 318 struct tty *tp = sc->sc_tty; 319 320 aprint_normal_dev(sc->sc_dev, 321 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 322 str, 323 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 324 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 325 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 326 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 327 sc->sc_tx_stopped ? '+' : '-'); 328 329 aprint_normal_dev(sc->sc_dev, 330 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 331 str, 332 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 333 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 334 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 335 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 336 sc->sc_rx_flags); 337 } 338 #endif 339 340 int 341 com_probe_subr(struct com_regs *regs) 342 { 343 344 /* force access to id reg */ 345 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 346 CSR_WRITE_1(regs, COM_REG_IIR, 0); 347 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 348 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 349 return (0); 350 351 return (1); 352 } 353 354 int 355 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 356 { 357 struct com_regs regs; 358 359 regs.cr_iot = iot; 360 regs.cr_ioh = ioh; 361 #ifdef COM_REGMAP 362 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 363 #endif 364 365 return com_probe_subr(®s); 366 } 367 368 /* 369 * No locking in this routine; it is only called during attach, 370 * or with the port already locked. 371 */ 372 static void 373 com_enable_debugport(struct com_softc *sc) 374 { 375 376 /* Turn on line break interrupt, set carrier. */ 377 sc->sc_ier = IER_ERXRDY; 378 if (sc->sc_type == COM_TYPE_PXA2x0) 379 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 380 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 381 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 382 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 383 } 384 385 void 386 com_attach_subr(struct com_softc *sc) 387 { 388 struct com_regs *regsp = &sc->sc_regs; 389 struct tty *tp; 390 #ifdef COM_16650 391 u_int8_t lcr; 392 #endif 393 const char *fifo_msg = NULL; 394 395 aprint_naive("\n"); 396 397 callout_init(&sc->sc_diag_callout, 0); 398 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 399 400 /* Disable interrupts before configuring the device. */ 401 if (sc->sc_type == COM_TYPE_PXA2x0) 402 sc->sc_ier = IER_EUART; 403 else 404 sc->sc_ier = 0; 405 406 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 407 408 if (regsp->cr_iot == comcons_info.regs.cr_iot && 409 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 410 comconsattached = 1; 411 412 if (cn_tab == NULL && comcnreattach() != 0) { 413 printf("can't re-init serial console @%zx\n", 414 (size_t)comcons_info.regs.cr_iobase); 415 } 416 417 /* Make sure the console is always "hardwired". */ 418 delay(10000); /* wait for output to finish */ 419 SET(sc->sc_hwflags, COM_HW_CONSOLE); 420 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 421 } 422 423 /* Probe for FIFO */ 424 switch (sc->sc_type) { 425 case COM_TYPE_HAYESP: 426 goto fifodone; 427 428 case COM_TYPE_AU1x00: 429 sc->sc_fifolen = 16; 430 fifo_msg = "Au1X00 UART, working fifo"; 431 SET(sc->sc_hwflags, COM_HW_FIFO); 432 goto fifodelay; 433 434 case COM_TYPE_16550_NOERS: 435 sc->sc_fifolen = 16; 436 fifo_msg = "ns16650, no ERS, working fifo"; 437 SET(sc->sc_hwflags, COM_HW_FIFO); 438 goto fifodelay; 439 440 case COM_TYPE_OMAP: 441 sc->sc_fifolen = 64; 442 fifo_msg = "OMAP UART, working fifo"; 443 SET(sc->sc_hwflags, COM_HW_FIFO); 444 goto fifodelay; 445 } 446 447 sc->sc_fifolen = 1; 448 /* look for a NS 16550AF UART with FIFOs */ 449 CSR_WRITE_1(regsp, COM_REG_FIFO, 450 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 451 delay(100); 452 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 453 == IIR_FIFO_MASK) 454 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 455 == FIFO_TRIGGER_14) { 456 SET(sc->sc_hwflags, COM_HW_FIFO); 457 458 #ifdef COM_16650 459 /* 460 * IIR changes into the EFR if LCR is set to LCR_EERS 461 * on 16650s. We also know IIR != 0 at this point. 462 * Write 0 into the EFR, and read it. If the result 463 * is 0, we have a 16650. 464 * 465 * Older 16650s were broken; the test to detect them 466 * is taken from the Linux driver. Apparently 467 * setting DLAB enable gives access to the EFR on 468 * these chips. 469 */ 470 lcr = CSR_READ_1(regsp, COM_REG_LCR); 471 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 472 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 473 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 474 CSR_WRITE_1(regsp, COM_REG_LCR, 475 lcr | LCR_DLAB); 476 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 477 CLR(sc->sc_hwflags, COM_HW_FIFO); 478 sc->sc_fifolen = 0; 479 } else { 480 SET(sc->sc_hwflags, COM_HW_FLOW); 481 sc->sc_fifolen = 32; 482 } 483 } else 484 #endif 485 sc->sc_fifolen = 16; 486 487 #ifdef COM_16650 488 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 489 if (sc->sc_fifolen == 0) 490 fifo_msg = "st16650, broken fifo"; 491 else if (sc->sc_fifolen == 32) 492 fifo_msg = "st16650a, working fifo"; 493 else 494 #endif 495 fifo_msg = "ns16550a, working fifo"; 496 } else 497 fifo_msg = "ns16550, broken fifo"; 498 else 499 fifo_msg = "ns8250 or ns16450, no fifo"; 500 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 501 fifodelay: 502 /* 503 * Some chips will clear down both Tx and Rx FIFOs when zero is 504 * written to com_fifo. If this chip is the console, writing zero 505 * results in some of the chip/FIFO description being lost, so delay 506 * printing it until now. 507 */ 508 delay(10); 509 aprint_normal(": %s\n", fifo_msg); 510 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 511 sc->sc_fifolen = 1; 512 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 513 } 514 515 fifodone: 516 517 tp = ttymalloc(); 518 tp->t_oproc = comstart; 519 tp->t_param = comparam; 520 tp->t_hwiflow = comhwiflow; 521 522 sc->sc_tty = tp; 523 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 524 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 525 sc->sc_rbavail = com_rbuf_size; 526 if (sc->sc_rbuf == NULL) { 527 aprint_error_dev(sc->sc_dev, 528 "unable to allocate ring buffer\n"); 529 return; 530 } 531 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 532 533 tty_attach(tp); 534 535 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 536 SET(sc->sc_mcr, MCR_IENABLE); 537 538 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 539 int maj; 540 541 /* locate the major number */ 542 maj = cdevsw_lookup_major(&com_cdevsw); 543 544 tp->t_dev = cn_tab->cn_dev = makedev(maj, 545 device_unit(sc->sc_dev)); 546 547 aprint_normal_dev(sc->sc_dev, "console\n"); 548 } 549 550 #ifdef KGDB 551 /* 552 * Allow kgdb to "take over" this port. If this is 553 * not the console and is the kgdb device, it has 554 * exclusive use. If it's the console _and_ the 555 * kgdb device, it doesn't. 556 */ 557 if (regsp->cr_iot == comkgdbregs.cr_iot && 558 regsp->cr_iobase == comkgdbregs.cr_iobase) { 559 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 560 com_kgdb_attached = 1; 561 562 SET(sc->sc_hwflags, COM_HW_KGDB); 563 } 564 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 565 } 566 #endif 567 568 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 569 570 #if NRND > 0 && defined(RND_COM) 571 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 572 RND_TYPE_TTY, 0); 573 #endif 574 575 /* if there are no enable/disable functions, assume the device 576 is always enabled */ 577 if (!sc->enable) 578 sc->enabled = 1; 579 580 com_config(sc); 581 582 SET(sc->sc_hwflags, COM_HW_DEV_OK); 583 } 584 585 void 586 com_config(struct com_softc *sc) 587 { 588 struct com_regs *regsp = &sc->sc_regs; 589 590 /* Disable interrupts before configuring the device. */ 591 if (sc->sc_type == COM_TYPE_PXA2x0) 592 sc->sc_ier = IER_EUART; 593 else 594 sc->sc_ier = 0; 595 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 596 (void) CSR_READ_1(regsp, COM_REG_IIR); 597 598 #ifdef COM_HAYESP 599 /* Look for a Hayes ESP board. */ 600 if (sc->sc_type == COM_TYPE_HAYESP) { 601 602 /* Set 16550 compatibility mode */ 603 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 604 HAYESP_SETMODE); 605 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 606 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 607 HAYESP_MODE_SCALE); 608 609 /* Set RTS/CTS flow control */ 610 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 611 HAYESP_SETFLOWTYPE); 612 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 613 HAYESP_FLOW_RTS); 614 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 615 HAYESP_FLOW_CTS); 616 617 /* Set flow control levels */ 618 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 619 HAYESP_SETRXFLOW); 620 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 621 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 622 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 623 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 624 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 625 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 626 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 627 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 628 } 629 #endif 630 631 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 632 com_enable_debugport(sc); 633 } 634 635 #if 0 636 static int 637 comcngetc_detached(dev_t dev) 638 { 639 return 0; 640 } 641 642 static void 643 comcnputc_detached(dev_t dev, int c) 644 { 645 } 646 #endif 647 648 int 649 com_detach(device_t self, int flags) 650 { 651 struct com_softc *sc = device_private(self); 652 int maj, mn; 653 654 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 655 return EBUSY; 656 657 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 658 (flags & DETACH_SHUTDOWN) != 0) 659 return EBUSY; 660 661 if (sc->disable != NULL && sc->enabled != 0) { 662 (*sc->disable)(sc); 663 sc->enabled = 0; 664 } 665 666 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 667 comconsattached = 0; 668 cn_tab = NULL; 669 } 670 671 /* locate the major number */ 672 maj = cdevsw_lookup_major(&com_cdevsw); 673 674 /* Nuke the vnodes for any open instances. */ 675 mn = device_unit(self); 676 vdevgone(maj, mn, mn, VCHR); 677 678 mn |= COMDIALOUT_MASK; 679 vdevgone(maj, mn, mn, VCHR); 680 681 if (sc->sc_rbuf == NULL) { 682 /* 683 * Ring buffer allocation failed in the com_attach_subr, 684 * only the tty is allocated, and nothing else. 685 */ 686 ttyfree(sc->sc_tty); 687 return 0; 688 } 689 690 /* Free the receive buffer. */ 691 free(sc->sc_rbuf, M_DEVBUF); 692 693 /* Detach and free the tty. */ 694 tty_detach(sc->sc_tty); 695 ttyfree(sc->sc_tty); 696 697 /* Unhook the soft interrupt handler. */ 698 softint_disestablish(sc->sc_si); 699 700 #if NRND > 0 && defined(RND_COM) 701 /* Unhook the entropy source. */ 702 rnd_detach_source(&sc->rnd_source); 703 #endif 704 callout_destroy(&sc->sc_diag_callout); 705 706 /* Destroy the lock. */ 707 mutex_destroy(&sc->sc_lock); 708 709 return (0); 710 } 711 712 void 713 com_shutdown(struct com_softc *sc) 714 { 715 struct tty *tp = sc->sc_tty; 716 717 mutex_spin_enter(&sc->sc_lock); 718 719 /* If we were asserting flow control, then deassert it. */ 720 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 721 com_hwiflow(sc); 722 723 /* Clear any break condition set with TIOCSBRK. */ 724 com_break(sc, 0); 725 726 /* 727 * Hang up if necessary. Wait a bit, so the other side has time to 728 * notice even if we immediately open the port again. 729 * Avoid tsleeping above splhigh(). 730 */ 731 if (ISSET(tp->t_cflag, HUPCL)) { 732 com_modem(sc, 0); 733 mutex_spin_exit(&sc->sc_lock); 734 /* XXX will only timeout */ 735 (void) kpause(ttclos, false, hz, NULL); 736 mutex_spin_enter(&sc->sc_lock); 737 } 738 739 /* Turn off interrupts. */ 740 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 741 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 742 if (sc->sc_type == COM_TYPE_PXA2x0) 743 sc->sc_ier |= IER_ERXTOUT; 744 } else 745 sc->sc_ier = 0; 746 747 if (sc->sc_type == COM_TYPE_PXA2x0) 748 sc->sc_ier |= IER_EUART; 749 750 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 751 752 mutex_spin_exit(&sc->sc_lock); 753 754 if (sc->disable) { 755 #ifdef DIAGNOSTIC 756 if (!sc->enabled) 757 panic("com_shutdown: not enabled?"); 758 #endif 759 (*sc->disable)(sc); 760 sc->enabled = 0; 761 } 762 } 763 764 int 765 comopen(dev_t dev, int flag, int mode, struct lwp *l) 766 { 767 struct com_softc *sc; 768 struct tty *tp; 769 int s; 770 int error; 771 772 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 773 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 774 sc->sc_rbuf == NULL) 775 return (ENXIO); 776 777 if (!device_is_active(sc->sc_dev)) 778 return (ENXIO); 779 780 #ifdef KGDB 781 /* 782 * If this is the kgdb port, no other use is permitted. 783 */ 784 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 785 return (EBUSY); 786 #endif 787 788 tp = sc->sc_tty; 789 790 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 791 return (EBUSY); 792 793 s = spltty(); 794 795 /* 796 * Do the following iff this is a first open. 797 */ 798 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 799 struct termios t; 800 801 tp->t_dev = dev; 802 803 804 if (sc->enable) { 805 if ((*sc->enable)(sc)) { 806 splx(s); 807 aprint_error_dev(sc->sc_dev, 808 "device enable failed\n"); 809 return (EIO); 810 } 811 mutex_spin_enter(&sc->sc_lock); 812 sc->enabled = 1; 813 com_config(sc); 814 } else { 815 mutex_spin_enter(&sc->sc_lock); 816 } 817 818 /* Turn on interrupts. */ 819 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 820 if (sc->sc_type == COM_TYPE_PXA2x0) 821 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 822 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 823 824 /* Fetch the current modem control status, needed later. */ 825 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 826 827 /* Clear PPS capture state on first open. */ 828 mutex_spin_enter(&timecounter_lock); 829 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 830 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 831 pps_init(&sc->sc_pps_state); 832 mutex_spin_exit(&timecounter_lock); 833 834 mutex_spin_exit(&sc->sc_lock); 835 836 /* 837 * Initialize the termios status to the defaults. Add in the 838 * sticky bits from TIOCSFLAGS. 839 */ 840 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 841 t.c_ospeed = comcons_info.rate; 842 t.c_cflag = comcons_info.cflag; 843 } else { 844 t.c_ospeed = TTYDEF_SPEED; 845 t.c_cflag = TTYDEF_CFLAG; 846 } 847 t.c_ispeed = t.c_ospeed; 848 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 849 SET(t.c_cflag, CLOCAL); 850 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 851 SET(t.c_cflag, CRTSCTS); 852 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 853 SET(t.c_cflag, MDMBUF); 854 /* Make sure comparam() will do something. */ 855 tp->t_ospeed = 0; 856 (void) comparam(tp, &t); 857 tp->t_iflag = TTYDEF_IFLAG; 858 tp->t_oflag = TTYDEF_OFLAG; 859 tp->t_lflag = TTYDEF_LFLAG; 860 ttychars(tp); 861 ttsetwater(tp); 862 863 mutex_spin_enter(&sc->sc_lock); 864 865 /* 866 * Turn on DTR. We must always do this, even if carrier is not 867 * present, because otherwise we'd have to use TIOCSDTR 868 * immediately after setting CLOCAL, which applications do not 869 * expect. We always assert DTR while the device is open 870 * unless explicitly requested to deassert it. 871 */ 872 com_modem(sc, 1); 873 874 /* Clear the input ring, and unblock. */ 875 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 876 sc->sc_rbavail = com_rbuf_size; 877 com_iflush(sc); 878 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 879 com_hwiflow(sc); 880 881 #ifdef COM_DEBUG 882 if (com_debug) 883 comstatus(sc, "comopen "); 884 #endif 885 886 mutex_spin_exit(&sc->sc_lock); 887 } 888 889 splx(s); 890 891 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 892 if (error) 893 goto bad; 894 895 error = (*tp->t_linesw->l_open)(dev, tp); 896 if (error) 897 goto bad; 898 899 return (0); 900 901 bad: 902 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 903 /* 904 * We failed to open the device, and nobody else had it opened. 905 * Clean up the state as appropriate. 906 */ 907 com_shutdown(sc); 908 } 909 910 return (error); 911 } 912 913 int 914 comclose(dev_t dev, int flag, int mode, struct lwp *l) 915 { 916 struct com_softc *sc = 917 device_lookup_private(&com_cd, COMUNIT(dev)); 918 struct tty *tp = sc->sc_tty; 919 920 /* XXX This is for cons.c. */ 921 if (!ISSET(tp->t_state, TS_ISOPEN)) 922 return (0); 923 924 (*tp->t_linesw->l_close)(tp, flag); 925 ttyclose(tp); 926 927 if (COM_ISALIVE(sc) == 0) 928 return (0); 929 930 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 931 /* 932 * Although we got a last close, the device may still be in 933 * use; e.g. if this was the dialout node, and there are still 934 * processes waiting for carrier on the non-dialout node. 935 */ 936 com_shutdown(sc); 937 } 938 939 return (0); 940 } 941 942 int 943 comread(dev_t dev, struct uio *uio, int flag) 944 { 945 struct com_softc *sc = 946 device_lookup_private(&com_cd, COMUNIT(dev)); 947 struct tty *tp = sc->sc_tty; 948 949 if (COM_ISALIVE(sc) == 0) 950 return (EIO); 951 952 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 953 } 954 955 int 956 comwrite(dev_t dev, struct uio *uio, int flag) 957 { 958 struct com_softc *sc = 959 device_lookup_private(&com_cd, COMUNIT(dev)); 960 struct tty *tp = sc->sc_tty; 961 962 if (COM_ISALIVE(sc) == 0) 963 return (EIO); 964 965 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 966 } 967 968 int 969 compoll(dev_t dev, int events, struct lwp *l) 970 { 971 struct com_softc *sc = 972 device_lookup_private(&com_cd, COMUNIT(dev)); 973 struct tty *tp = sc->sc_tty; 974 975 if (COM_ISALIVE(sc) == 0) 976 return (POLLHUP); 977 978 return ((*tp->t_linesw->l_poll)(tp, events, l)); 979 } 980 981 struct tty * 982 comtty(dev_t dev) 983 { 984 struct com_softc *sc = 985 device_lookup_private(&com_cd, COMUNIT(dev)); 986 struct tty *tp = sc->sc_tty; 987 988 return (tp); 989 } 990 991 int 992 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 993 { 994 struct com_softc *sc; 995 struct tty *tp; 996 int error; 997 998 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 999 if (sc == NULL) 1000 return ENXIO; 1001 if (COM_ISALIVE(sc) == 0) 1002 return (EIO); 1003 1004 tp = sc->sc_tty; 1005 1006 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1007 if (error != EPASSTHROUGH) 1008 return (error); 1009 1010 error = ttioctl(tp, cmd, data, flag, l); 1011 if (error != EPASSTHROUGH) 1012 return (error); 1013 1014 error = 0; 1015 switch (cmd) { 1016 case TIOCSFLAGS: 1017 error = kauth_authorize_device_tty(l->l_cred, 1018 KAUTH_DEVICE_TTY_PRIVSET, tp); 1019 break; 1020 default: 1021 /* nothing */ 1022 break; 1023 } 1024 if (error) { 1025 return error; 1026 } 1027 1028 mutex_spin_enter(&sc->sc_lock); 1029 1030 switch (cmd) { 1031 case TIOCSBRK: 1032 com_break(sc, 1); 1033 break; 1034 1035 case TIOCCBRK: 1036 com_break(sc, 0); 1037 break; 1038 1039 case TIOCSDTR: 1040 com_modem(sc, 1); 1041 break; 1042 1043 case TIOCCDTR: 1044 com_modem(sc, 0); 1045 break; 1046 1047 case TIOCGFLAGS: 1048 *(int *)data = sc->sc_swflags; 1049 break; 1050 1051 case TIOCSFLAGS: 1052 sc->sc_swflags = *(int *)data; 1053 break; 1054 1055 case TIOCMSET: 1056 case TIOCMBIS: 1057 case TIOCMBIC: 1058 tiocm_to_com(sc, cmd, *(int *)data); 1059 break; 1060 1061 case TIOCMGET: 1062 *(int *)data = com_to_tiocm(sc); 1063 break; 1064 1065 case PPS_IOC_CREATE: 1066 case PPS_IOC_DESTROY: 1067 case PPS_IOC_GETPARAMS: 1068 case PPS_IOC_SETPARAMS: 1069 case PPS_IOC_GETCAP: 1070 case PPS_IOC_FETCH: 1071 #ifdef PPS_SYNC 1072 case PPS_IOC_KCBIND: 1073 #endif 1074 mutex_spin_enter(&timecounter_lock); 1075 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1076 mutex_spin_exit(&timecounter_lock); 1077 break; 1078 1079 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1080 mutex_spin_enter(&timecounter_lock); 1081 #ifndef PPS_TRAILING_EDGE 1082 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1083 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1084 #else 1085 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1086 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1087 #endif 1088 mutex_spin_exit(&timecounter_lock); 1089 break; 1090 1091 default: 1092 error = EPASSTHROUGH; 1093 break; 1094 } 1095 1096 mutex_spin_exit(&sc->sc_lock); 1097 1098 #ifdef COM_DEBUG 1099 if (com_debug) 1100 comstatus(sc, "comioctl "); 1101 #endif 1102 1103 return (error); 1104 } 1105 1106 integrate void 1107 com_schedrx(struct com_softc *sc) 1108 { 1109 1110 sc->sc_rx_ready = 1; 1111 1112 /* Wake up the poller. */ 1113 softint_schedule(sc->sc_si); 1114 } 1115 1116 void 1117 com_break(struct com_softc *sc, int onoff) 1118 { 1119 1120 if (onoff) 1121 SET(sc->sc_lcr, LCR_SBREAK); 1122 else 1123 CLR(sc->sc_lcr, LCR_SBREAK); 1124 1125 if (!sc->sc_heldchange) { 1126 if (sc->sc_tx_busy) { 1127 sc->sc_heldtbc = sc->sc_tbc; 1128 sc->sc_tbc = 0; 1129 sc->sc_heldchange = 1; 1130 } else 1131 com_loadchannelregs(sc); 1132 } 1133 } 1134 1135 void 1136 com_modem(struct com_softc *sc, int onoff) 1137 { 1138 1139 if (sc->sc_mcr_dtr == 0) 1140 return; 1141 1142 if (onoff) 1143 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1144 else 1145 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1146 1147 if (!sc->sc_heldchange) { 1148 if (sc->sc_tx_busy) { 1149 sc->sc_heldtbc = sc->sc_tbc; 1150 sc->sc_tbc = 0; 1151 sc->sc_heldchange = 1; 1152 } else 1153 com_loadchannelregs(sc); 1154 } 1155 } 1156 1157 void 1158 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1159 { 1160 u_char combits; 1161 1162 combits = 0; 1163 if (ISSET(ttybits, TIOCM_DTR)) 1164 SET(combits, MCR_DTR); 1165 if (ISSET(ttybits, TIOCM_RTS)) 1166 SET(combits, MCR_RTS); 1167 1168 switch (how) { 1169 case TIOCMBIC: 1170 CLR(sc->sc_mcr, combits); 1171 break; 1172 1173 case TIOCMBIS: 1174 SET(sc->sc_mcr, combits); 1175 break; 1176 1177 case TIOCMSET: 1178 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1179 SET(sc->sc_mcr, combits); 1180 break; 1181 } 1182 1183 if (!sc->sc_heldchange) { 1184 if (sc->sc_tx_busy) { 1185 sc->sc_heldtbc = sc->sc_tbc; 1186 sc->sc_tbc = 0; 1187 sc->sc_heldchange = 1; 1188 } else 1189 com_loadchannelregs(sc); 1190 } 1191 } 1192 1193 int 1194 com_to_tiocm(struct com_softc *sc) 1195 { 1196 u_char combits; 1197 int ttybits = 0; 1198 1199 combits = sc->sc_mcr; 1200 if (ISSET(combits, MCR_DTR)) 1201 SET(ttybits, TIOCM_DTR); 1202 if (ISSET(combits, MCR_RTS)) 1203 SET(ttybits, TIOCM_RTS); 1204 1205 combits = sc->sc_msr; 1206 if (ISSET(combits, MSR_DCD)) 1207 SET(ttybits, TIOCM_CD); 1208 if (ISSET(combits, MSR_CTS)) 1209 SET(ttybits, TIOCM_CTS); 1210 if (ISSET(combits, MSR_DSR)) 1211 SET(ttybits, TIOCM_DSR); 1212 if (ISSET(combits, MSR_RI | MSR_TERI)) 1213 SET(ttybits, TIOCM_RI); 1214 1215 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1216 SET(ttybits, TIOCM_LE); 1217 1218 return (ttybits); 1219 } 1220 1221 static u_char 1222 cflag2lcr(tcflag_t cflag) 1223 { 1224 u_char lcr = 0; 1225 1226 switch (ISSET(cflag, CSIZE)) { 1227 case CS5: 1228 SET(lcr, LCR_5BITS); 1229 break; 1230 case CS6: 1231 SET(lcr, LCR_6BITS); 1232 break; 1233 case CS7: 1234 SET(lcr, LCR_7BITS); 1235 break; 1236 case CS8: 1237 SET(lcr, LCR_8BITS); 1238 break; 1239 } 1240 if (ISSET(cflag, PARENB)) { 1241 SET(lcr, LCR_PENAB); 1242 if (!ISSET(cflag, PARODD)) 1243 SET(lcr, LCR_PEVEN); 1244 } 1245 if (ISSET(cflag, CSTOPB)) 1246 SET(lcr, LCR_STOPB); 1247 1248 return (lcr); 1249 } 1250 1251 int 1252 comparam(struct tty *tp, struct termios *t) 1253 { 1254 struct com_softc *sc = 1255 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1256 int ospeed; 1257 u_char lcr; 1258 1259 if (COM_ISALIVE(sc) == 0) 1260 return (EIO); 1261 1262 #ifdef COM_HAYESP 1263 if (sc->sc_type == COM_TYPE_HAYESP) { 1264 int prescaler, speed; 1265 1266 /* 1267 * Calculate UART clock prescaler. It should be in 1268 * range of 0 .. 3. 1269 */ 1270 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1271 prescaler++, speed /= 2) 1272 if ((ospeed = comspeed(speed, sc->sc_frequency, 1273 sc->sc_type)) > 0) 1274 break; 1275 1276 if (prescaler == 4) 1277 return (EINVAL); 1278 sc->sc_prescaler = prescaler; 1279 } else 1280 #endif 1281 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1282 1283 /* Check requested parameters. */ 1284 if (ospeed < 0) 1285 return (EINVAL); 1286 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1287 return (EINVAL); 1288 1289 /* 1290 * For the console, always force CLOCAL and !HUPCL, so that the port 1291 * is always active. 1292 */ 1293 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1294 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1295 SET(t->c_cflag, CLOCAL); 1296 CLR(t->c_cflag, HUPCL); 1297 } 1298 1299 /* 1300 * If there were no changes, don't do anything. This avoids dropping 1301 * input and improves performance when all we did was frob things like 1302 * VMIN and VTIME. 1303 */ 1304 if (tp->t_ospeed == t->c_ospeed && 1305 tp->t_cflag == t->c_cflag) 1306 return (0); 1307 1308 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1309 1310 mutex_spin_enter(&sc->sc_lock); 1311 1312 sc->sc_lcr = lcr; 1313 1314 /* 1315 * If we're not in a mode that assumes a connection is present, then 1316 * ignore carrier changes. 1317 */ 1318 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1319 sc->sc_msr_dcd = 0; 1320 else 1321 sc->sc_msr_dcd = MSR_DCD; 1322 /* 1323 * Set the flow control pins depending on the current flow control 1324 * mode. 1325 */ 1326 if (ISSET(t->c_cflag, CRTSCTS)) { 1327 sc->sc_mcr_dtr = MCR_DTR; 1328 sc->sc_mcr_rts = MCR_RTS; 1329 sc->sc_msr_cts = MSR_CTS; 1330 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1331 } else if (ISSET(t->c_cflag, MDMBUF)) { 1332 /* 1333 * For DTR/DCD flow control, make sure we don't toggle DTR for 1334 * carrier detection. 1335 */ 1336 sc->sc_mcr_dtr = 0; 1337 sc->sc_mcr_rts = MCR_DTR; 1338 sc->sc_msr_cts = MSR_DCD; 1339 sc->sc_efr = 0; 1340 } else { 1341 /* 1342 * If no flow control, then always set RTS. This will make 1343 * the other side happy if it mistakenly thinks we're doing 1344 * RTS/CTS flow control. 1345 */ 1346 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1347 sc->sc_mcr_rts = 0; 1348 sc->sc_msr_cts = 0; 1349 sc->sc_efr = 0; 1350 if (ISSET(sc->sc_mcr, MCR_DTR)) 1351 SET(sc->sc_mcr, MCR_RTS); 1352 else 1353 CLR(sc->sc_mcr, MCR_RTS); 1354 } 1355 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1356 1357 #if 0 1358 if (ospeed == 0) 1359 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1360 else 1361 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1362 #endif 1363 1364 sc->sc_dlbl = ospeed; 1365 sc->sc_dlbh = ospeed >> 8; 1366 1367 /* 1368 * Set the FIFO threshold based on the receive speed. 1369 * 1370 * * If it's a low speed, it's probably a mouse or some other 1371 * interactive device, so set the threshold low. 1372 * * If it's a high speed, trim the trigger level down to prevent 1373 * overflows. 1374 * * Otherwise set it a bit higher. 1375 */ 1376 if (sc->sc_type == COM_TYPE_HAYESP) 1377 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1378 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1379 if (t->c_ospeed <= 1200) 1380 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1381 else if (t->c_ospeed <= 38400) 1382 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1383 else 1384 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1385 } else 1386 sc->sc_fifo = 0; 1387 1388 /* And copy to tty. */ 1389 tp->t_ispeed = t->c_ospeed; 1390 tp->t_ospeed = t->c_ospeed; 1391 tp->t_cflag = t->c_cflag; 1392 1393 if (!sc->sc_heldchange) { 1394 if (sc->sc_tx_busy) { 1395 sc->sc_heldtbc = sc->sc_tbc; 1396 sc->sc_tbc = 0; 1397 sc->sc_heldchange = 1; 1398 } else 1399 com_loadchannelregs(sc); 1400 } 1401 1402 if (!ISSET(t->c_cflag, CHWFLOW)) { 1403 /* Disable the high water mark. */ 1404 sc->sc_r_hiwat = 0; 1405 sc->sc_r_lowat = 0; 1406 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1407 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1408 com_schedrx(sc); 1409 } 1410 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1411 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1412 com_hwiflow(sc); 1413 } 1414 } else { 1415 sc->sc_r_hiwat = com_rbuf_hiwat; 1416 sc->sc_r_lowat = com_rbuf_lowat; 1417 } 1418 1419 mutex_spin_exit(&sc->sc_lock); 1420 1421 /* 1422 * Update the tty layer's idea of the carrier bit, in case we changed 1423 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1424 * explicit request. 1425 */ 1426 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1427 1428 #ifdef COM_DEBUG 1429 if (com_debug) 1430 comstatus(sc, "comparam "); 1431 #endif 1432 1433 if (!ISSET(t->c_cflag, CHWFLOW)) { 1434 if (sc->sc_tx_stopped) { 1435 sc->sc_tx_stopped = 0; 1436 comstart(tp); 1437 } 1438 } 1439 1440 return (0); 1441 } 1442 1443 void 1444 com_iflush(struct com_softc *sc) 1445 { 1446 struct com_regs *regsp = &sc->sc_regs; 1447 #ifdef DIAGNOSTIC 1448 int reg; 1449 #endif 1450 int timo; 1451 1452 #ifdef DIAGNOSTIC 1453 reg = 0xffff; 1454 #endif 1455 timo = 50000; 1456 /* flush any pending I/O */ 1457 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1458 && --timo) 1459 #ifdef DIAGNOSTIC 1460 reg = 1461 #else 1462 (void) 1463 #endif 1464 CSR_READ_1(regsp, COM_REG_RXDATA); 1465 #ifdef DIAGNOSTIC 1466 if (!timo) 1467 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1468 #endif 1469 } 1470 1471 void 1472 com_loadchannelregs(struct com_softc *sc) 1473 { 1474 struct com_regs *regsp = &sc->sc_regs; 1475 1476 /* XXXXX necessary? */ 1477 com_iflush(sc); 1478 1479 if (sc->sc_type == COM_TYPE_PXA2x0) 1480 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1481 else 1482 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1483 1484 if (sc->sc_type == COM_TYPE_OMAP) { 1485 /* disable before changing settings */ 1486 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1487 } 1488 1489 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1490 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1491 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1492 /* no EFR on alchemy */ 1493 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1494 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1495 } 1496 if (sc->sc_type == COM_TYPE_AU1x00) { 1497 /* alchemy has single separate 16-bit clock divisor register */ 1498 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1499 (sc->sc_dlbh << 8)); 1500 } else { 1501 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1502 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1503 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1504 } 1505 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1506 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1507 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1508 #ifdef COM_HAYESP 1509 if (sc->sc_type == COM_TYPE_HAYESP) { 1510 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1511 HAYESP_SETPRESCALER); 1512 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1513 sc->sc_prescaler); 1514 } 1515 #endif 1516 if (sc->sc_type == COM_TYPE_OMAP) { 1517 /* setup the fifos. the FCR value is not used as long 1518 as SCR[6] and SCR[7] are 0, which they are at reset 1519 and we never touch the SCR register */ 1520 uint8_t rx_fifo_trig = 40; 1521 uint8_t tx_fifo_trig = 60; 1522 uint8_t rx_start = 8; 1523 uint8_t rx_halt = 60; 1524 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1525 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1526 1527 /* enable access to TCR & TLR */ 1528 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1529 1530 /* write tcr and tlr values */ 1531 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1532 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1533 1534 /* disable access to TCR & TLR */ 1535 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1536 1537 /* enable again, but mode is based on speed */ 1538 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1539 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1540 } else { 1541 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1542 } 1543 } 1544 1545 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1546 } 1547 1548 int 1549 comhwiflow(struct tty *tp, int block) 1550 { 1551 struct com_softc *sc = 1552 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1553 1554 if (COM_ISALIVE(sc) == 0) 1555 return (0); 1556 1557 if (sc->sc_mcr_rts == 0) 1558 return (0); 1559 1560 mutex_spin_enter(&sc->sc_lock); 1561 1562 if (block) { 1563 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1564 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1565 com_hwiflow(sc); 1566 } 1567 } else { 1568 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1569 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1570 com_schedrx(sc); 1571 } 1572 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1573 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1574 com_hwiflow(sc); 1575 } 1576 } 1577 1578 mutex_spin_exit(&sc->sc_lock); 1579 return (1); 1580 } 1581 1582 /* 1583 * (un)block input via hw flowcontrol 1584 */ 1585 void 1586 com_hwiflow(struct com_softc *sc) 1587 { 1588 struct com_regs *regsp= &sc->sc_regs; 1589 1590 if (sc->sc_mcr_rts == 0) 1591 return; 1592 1593 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1594 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1595 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1596 } else { 1597 SET(sc->sc_mcr, sc->sc_mcr_rts); 1598 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1599 } 1600 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1601 } 1602 1603 1604 void 1605 comstart(struct tty *tp) 1606 { 1607 struct com_softc *sc = 1608 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1609 struct com_regs *regsp = &sc->sc_regs; 1610 int s; 1611 1612 if (COM_ISALIVE(sc) == 0) 1613 return; 1614 1615 s = spltty(); 1616 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1617 goto out; 1618 if (sc->sc_tx_stopped) 1619 goto out; 1620 if (!ttypull(tp)) 1621 goto out; 1622 1623 /* Grab the first contiguous region of buffer space. */ 1624 { 1625 u_char *tba; 1626 int tbc; 1627 1628 tba = tp->t_outq.c_cf; 1629 tbc = ndqb(&tp->t_outq, 0); 1630 1631 mutex_spin_enter(&sc->sc_lock); 1632 1633 sc->sc_tba = tba; 1634 sc->sc_tbc = tbc; 1635 } 1636 1637 SET(tp->t_state, TS_BUSY); 1638 sc->sc_tx_busy = 1; 1639 1640 /* Enable transmit completion interrupts if necessary. */ 1641 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1642 SET(sc->sc_ier, IER_ETXRDY); 1643 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1644 } 1645 1646 /* Output the first chunk of the contiguous buffer. */ 1647 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1648 u_int n; 1649 1650 n = sc->sc_tbc; 1651 if (n > sc->sc_fifolen) 1652 n = sc->sc_fifolen; 1653 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1654 sc->sc_tbc -= n; 1655 sc->sc_tba += n; 1656 } 1657 1658 mutex_spin_exit(&sc->sc_lock); 1659 out: 1660 splx(s); 1661 return; 1662 } 1663 1664 /* 1665 * Stop output on a line. 1666 */ 1667 void 1668 comstop(struct tty *tp, int flag) 1669 { 1670 struct com_softc *sc = 1671 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1672 1673 mutex_spin_enter(&sc->sc_lock); 1674 if (ISSET(tp->t_state, TS_BUSY)) { 1675 /* Stop transmitting at the next chunk. */ 1676 sc->sc_tbc = 0; 1677 sc->sc_heldtbc = 0; 1678 if (!ISSET(tp->t_state, TS_TTSTOP)) 1679 SET(tp->t_state, TS_FLUSH); 1680 } 1681 mutex_spin_exit(&sc->sc_lock); 1682 } 1683 1684 void 1685 comdiag(void *arg) 1686 { 1687 struct com_softc *sc = arg; 1688 int overflows, floods; 1689 1690 mutex_spin_enter(&sc->sc_lock); 1691 overflows = sc->sc_overflows; 1692 sc->sc_overflows = 0; 1693 floods = sc->sc_floods; 1694 sc->sc_floods = 0; 1695 sc->sc_errors = 0; 1696 mutex_spin_exit(&sc->sc_lock); 1697 1698 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1699 device_xname(sc->sc_dev), 1700 overflows, overflows == 1 ? "" : "s", 1701 floods, floods == 1 ? "" : "s"); 1702 } 1703 1704 integrate void 1705 com_rxsoft(struct com_softc *sc, struct tty *tp) 1706 { 1707 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1708 u_char *get, *end; 1709 u_int cc, scc; 1710 u_char lsr; 1711 int code; 1712 1713 end = sc->sc_ebuf; 1714 get = sc->sc_rbget; 1715 scc = cc = com_rbuf_size - sc->sc_rbavail; 1716 1717 if (cc == com_rbuf_size) { 1718 sc->sc_floods++; 1719 if (sc->sc_errors++ == 0) 1720 callout_reset(&sc->sc_diag_callout, 60 * hz, 1721 comdiag, sc); 1722 } 1723 1724 /* If not yet open, drop the entire buffer content here */ 1725 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1726 get += cc << 1; 1727 if (get >= end) 1728 get -= com_rbuf_size << 1; 1729 cc = 0; 1730 } 1731 while (cc) { 1732 code = get[0]; 1733 lsr = get[1]; 1734 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1735 if (ISSET(lsr, LSR_OE)) { 1736 sc->sc_overflows++; 1737 if (sc->sc_errors++ == 0) 1738 callout_reset(&sc->sc_diag_callout, 1739 60 * hz, comdiag, sc); 1740 } 1741 if (ISSET(lsr, LSR_BI | LSR_FE)) 1742 SET(code, TTY_FE); 1743 if (ISSET(lsr, LSR_PE)) 1744 SET(code, TTY_PE); 1745 } 1746 if ((*rint)(code, tp) == -1) { 1747 /* 1748 * The line discipline's buffer is out of space. 1749 */ 1750 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1751 /* 1752 * We're either not using flow control, or the 1753 * line discipline didn't tell us to block for 1754 * some reason. Either way, we have no way to 1755 * know when there's more space available, so 1756 * just drop the rest of the data. 1757 */ 1758 get += cc << 1; 1759 if (get >= end) 1760 get -= com_rbuf_size << 1; 1761 cc = 0; 1762 } else { 1763 /* 1764 * Don't schedule any more receive processing 1765 * until the line discipline tells us there's 1766 * space available (through comhwiflow()). 1767 * Leave the rest of the data in the input 1768 * buffer. 1769 */ 1770 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1771 } 1772 break; 1773 } 1774 get += 2; 1775 if (get >= end) 1776 get = sc->sc_rbuf; 1777 cc--; 1778 } 1779 1780 if (cc != scc) { 1781 sc->sc_rbget = get; 1782 mutex_spin_enter(&sc->sc_lock); 1783 1784 cc = sc->sc_rbavail += scc - cc; 1785 /* Buffers should be ok again, release possible block. */ 1786 if (cc >= sc->sc_r_lowat) { 1787 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1788 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1789 SET(sc->sc_ier, IER_ERXRDY); 1790 #ifdef COM_PXA2X0 1791 if (sc->sc_type == COM_TYPE_PXA2x0) 1792 SET(sc->sc_ier, IER_ERXTOUT); 1793 #endif 1794 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1795 } 1796 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1797 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1798 com_hwiflow(sc); 1799 } 1800 } 1801 mutex_spin_exit(&sc->sc_lock); 1802 } 1803 } 1804 1805 integrate void 1806 com_txsoft(struct com_softc *sc, struct tty *tp) 1807 { 1808 1809 CLR(tp->t_state, TS_BUSY); 1810 if (ISSET(tp->t_state, TS_FLUSH)) 1811 CLR(tp->t_state, TS_FLUSH); 1812 else 1813 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1814 (*tp->t_linesw->l_start)(tp); 1815 } 1816 1817 integrate void 1818 com_stsoft(struct com_softc *sc, struct tty *tp) 1819 { 1820 u_char msr, delta; 1821 1822 mutex_spin_enter(&sc->sc_lock); 1823 msr = sc->sc_msr; 1824 delta = sc->sc_msr_delta; 1825 sc->sc_msr_delta = 0; 1826 mutex_spin_exit(&sc->sc_lock); 1827 1828 if (ISSET(delta, sc->sc_msr_dcd)) { 1829 /* 1830 * Inform the tty layer that carrier detect changed. 1831 */ 1832 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1833 } 1834 1835 if (ISSET(delta, sc->sc_msr_cts)) { 1836 /* Block or unblock output according to flow control. */ 1837 if (ISSET(msr, sc->sc_msr_cts)) { 1838 sc->sc_tx_stopped = 0; 1839 (*tp->t_linesw->l_start)(tp); 1840 } else { 1841 sc->sc_tx_stopped = 1; 1842 } 1843 } 1844 1845 #ifdef COM_DEBUG 1846 if (com_debug) 1847 comstatus(sc, "com_stsoft"); 1848 #endif 1849 } 1850 1851 void 1852 comsoft(void *arg) 1853 { 1854 struct com_softc *sc = arg; 1855 struct tty *tp; 1856 1857 if (COM_ISALIVE(sc) == 0) 1858 return; 1859 1860 tp = sc->sc_tty; 1861 1862 if (sc->sc_rx_ready) { 1863 sc->sc_rx_ready = 0; 1864 com_rxsoft(sc, tp); 1865 } 1866 1867 if (sc->sc_st_check) { 1868 sc->sc_st_check = 0; 1869 com_stsoft(sc, tp); 1870 } 1871 1872 if (sc->sc_tx_done) { 1873 sc->sc_tx_done = 0; 1874 com_txsoft(sc, tp); 1875 } 1876 } 1877 1878 int 1879 comintr(void *arg) 1880 { 1881 struct com_softc *sc = arg; 1882 struct com_regs *regsp = &sc->sc_regs; 1883 1884 u_char *put, *end; 1885 u_int cc; 1886 u_char lsr, iir; 1887 1888 if (COM_ISALIVE(sc) == 0) 1889 return (0); 1890 1891 KASSERT(regsp != NULL); 1892 1893 mutex_spin_enter(&sc->sc_lock); 1894 iir = CSR_READ_1(regsp, COM_REG_IIR); 1895 if (ISSET(iir, IIR_NOPEND)) { 1896 mutex_spin_exit(&sc->sc_lock); 1897 return (0); 1898 } 1899 1900 end = sc->sc_ebuf; 1901 put = sc->sc_rbput; 1902 cc = sc->sc_rbavail; 1903 1904 again: do { 1905 u_char msr, delta; 1906 1907 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1908 if (ISSET(lsr, LSR_BI)) { 1909 int cn_trapped = 0; 1910 1911 cn_check_magic(sc->sc_tty->t_dev, 1912 CNC_BREAK, com_cnm_state); 1913 if (cn_trapped) 1914 continue; 1915 #if defined(KGDB) && !defined(DDB) 1916 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1917 kgdb_connect(1); 1918 continue; 1919 } 1920 #endif 1921 } 1922 1923 if (ISSET(lsr, LSR_RCV_MASK) && 1924 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1925 while (cc > 0) { 1926 int cn_trapped = 0; 1927 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1928 put[1] = lsr; 1929 cn_check_magic(sc->sc_tty->t_dev, 1930 put[0], com_cnm_state); 1931 if (cn_trapped) 1932 goto next; 1933 put += 2; 1934 if (put >= end) 1935 put = sc->sc_rbuf; 1936 cc--; 1937 next: 1938 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1939 if (!ISSET(lsr, LSR_RCV_MASK)) 1940 break; 1941 } 1942 1943 /* 1944 * Current string of incoming characters ended because 1945 * no more data was available or we ran out of space. 1946 * Schedule a receive event if any data was received. 1947 * If we're out of space, turn off receive interrupts. 1948 */ 1949 sc->sc_rbput = put; 1950 sc->sc_rbavail = cc; 1951 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1952 sc->sc_rx_ready = 1; 1953 1954 /* 1955 * See if we are in danger of overflowing a buffer. If 1956 * so, use hardware flow control to ease the pressure. 1957 */ 1958 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1959 cc < sc->sc_r_hiwat) { 1960 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1961 com_hwiflow(sc); 1962 } 1963 1964 /* 1965 * If we're out of space, disable receive interrupts 1966 * until the queue has drained a bit. 1967 */ 1968 if (!cc) { 1969 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1970 #ifdef COM_PXA2X0 1971 if (sc->sc_type == COM_TYPE_PXA2x0) 1972 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 1973 else 1974 #endif 1975 CLR(sc->sc_ier, IER_ERXRDY); 1976 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1977 } 1978 } else { 1979 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 1980 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 1981 continue; 1982 } 1983 } 1984 1985 msr = CSR_READ_1(regsp, COM_REG_MSR); 1986 delta = msr ^ sc->sc_msr; 1987 sc->sc_msr = msr; 1988 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1989 (delta & MSR_DCD)) { 1990 mutex_spin_enter(&timecounter_lock); 1991 pps_capture(&sc->sc_pps_state); 1992 pps_event(&sc->sc_pps_state, 1993 (msr & MSR_DCD) ? 1994 PPS_CAPTUREASSERT : 1995 PPS_CAPTURECLEAR); 1996 mutex_spin_exit(&timecounter_lock); 1997 } 1998 1999 /* 2000 * Process normal status changes 2001 */ 2002 if (ISSET(delta, sc->sc_msr_mask)) { 2003 SET(sc->sc_msr_delta, delta); 2004 2005 /* 2006 * Stop output immediately if we lose the output 2007 * flow control signal or carrier detect. 2008 */ 2009 if (ISSET(~msr, sc->sc_msr_mask)) { 2010 sc->sc_tbc = 0; 2011 sc->sc_heldtbc = 0; 2012 #ifdef COM_DEBUG 2013 if (com_debug) 2014 comstatus(sc, "comintr "); 2015 #endif 2016 } 2017 2018 sc->sc_st_check = 1; 2019 } 2020 } while (!ISSET((iir = 2021 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2022 /* 2023 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2024 * by IIR read, so we can't do this way: `process all interrupts, 2025 * then do TX if possble'. 2026 */ 2027 (iir & IIR_IMASK) != IIR_TXRDY); 2028 2029 /* 2030 * Read LSR again, since there may be an interrupt between 2031 * the last LSR read and IIR read above. 2032 */ 2033 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2034 2035 /* 2036 * See if data can be transmitted as well. 2037 * Schedule tx done event if no data left 2038 * and tty was marked busy. 2039 */ 2040 if (ISSET(lsr, LSR_TXRDY)) { 2041 /* 2042 * If we've delayed a parameter change, do it now, and restart 2043 * output. 2044 */ 2045 if (sc->sc_heldchange) { 2046 com_loadchannelregs(sc); 2047 sc->sc_heldchange = 0; 2048 sc->sc_tbc = sc->sc_heldtbc; 2049 sc->sc_heldtbc = 0; 2050 } 2051 2052 /* Output the next chunk of the contiguous buffer, if any. */ 2053 if (sc->sc_tbc > 0) { 2054 u_int n; 2055 2056 n = sc->sc_tbc; 2057 if (n > sc->sc_fifolen) 2058 n = sc->sc_fifolen; 2059 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2060 sc->sc_tbc -= n; 2061 sc->sc_tba += n; 2062 } else { 2063 /* Disable transmit completion interrupts if necessary. */ 2064 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2065 CLR(sc->sc_ier, IER_ETXRDY); 2066 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2067 } 2068 if (sc->sc_tx_busy) { 2069 sc->sc_tx_busy = 0; 2070 sc->sc_tx_done = 1; 2071 } 2072 } 2073 } 2074 2075 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2076 goto again; 2077 2078 mutex_spin_exit(&sc->sc_lock); 2079 2080 /* Wake up the poller. */ 2081 softint_schedule(sc->sc_si); 2082 2083 #if NRND > 0 && defined(RND_COM) 2084 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2085 #endif 2086 2087 return (1); 2088 } 2089 2090 /* 2091 * The following functions are polled getc and putc routines, shared 2092 * by the console and kgdb glue. 2093 * 2094 * The read-ahead code is so that you can detect pending in-band 2095 * cn_magic in polled mode while doing output rather than having to 2096 * wait until the kernel decides it needs input. 2097 */ 2098 2099 #define MAX_READAHEAD 20 2100 static int com_readahead[MAX_READAHEAD]; 2101 static int com_readaheadcount = 0; 2102 2103 int 2104 com_common_getc(dev_t dev, struct com_regs *regsp) 2105 { 2106 int s = splserial(); 2107 u_char stat, c; 2108 2109 /* got a character from reading things earlier */ 2110 if (com_readaheadcount > 0) { 2111 int i; 2112 2113 c = com_readahead[0]; 2114 for (i = 1; i < com_readaheadcount; i++) { 2115 com_readahead[i-1] = com_readahead[i]; 2116 } 2117 com_readaheadcount--; 2118 splx(s); 2119 return (c); 2120 } 2121 2122 /* block until a character becomes available */ 2123 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2124 ; 2125 2126 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2127 stat = CSR_READ_1(regsp, COM_REG_IIR); 2128 { 2129 int cn_trapped = 0; /* unused */ 2130 #ifdef DDB 2131 extern int db_active; 2132 if (!db_active) 2133 #endif 2134 cn_check_magic(dev, c, com_cnm_state); 2135 } 2136 splx(s); 2137 return (c); 2138 } 2139 2140 static void 2141 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2142 { 2143 int s = splserial(); 2144 int cin, stat, timo; 2145 2146 if (com_readaheadcount < MAX_READAHEAD 2147 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2148 int cn_trapped = 0; 2149 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2150 stat = CSR_READ_1(regsp, COM_REG_IIR); 2151 cn_check_magic(dev, cin, com_cnm_state); 2152 com_readahead[com_readaheadcount++] = cin; 2153 } 2154 2155 /* wait for any pending transmission to finish */ 2156 timo = 150000; 2157 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2158 continue; 2159 2160 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2161 COM_BARRIER(regsp, BR | BW); 2162 2163 splx(s); 2164 } 2165 2166 /* 2167 * Initialize UART for use as console or KGDB line. 2168 */ 2169 int 2170 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2171 tcflag_t cflag) 2172 { 2173 2174 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2175 ®sp->cr_ioh)) 2176 return (ENOMEM); /* ??? */ 2177 2178 if (type == COM_TYPE_OMAP) { 2179 /* disable before changing settings */ 2180 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2181 } 2182 2183 rate = comspeed(rate, frequency, type); 2184 if (type != COM_TYPE_AU1x00) { 2185 /* no EFR on alchemy */ 2186 if (type != COM_TYPE_16550_NOERS) { 2187 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2188 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2189 } 2190 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2191 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2192 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2193 } else { 2194 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2195 } 2196 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2197 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2198 CSR_WRITE_1(regsp, COM_REG_FIFO, 2199 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2200 2201 if (type == COM_TYPE_OMAP) { 2202 /* setup the fifos. the FCR value is not used as long 2203 as SCR[6] and SCR[7] are 0, which they are at reset 2204 and we never touch the SCR register */ 2205 uint8_t rx_fifo_trig = 40; 2206 uint8_t tx_fifo_trig = 60; 2207 uint8_t rx_start = 8; 2208 uint8_t rx_halt = 60; 2209 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2210 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2211 2212 /* enable access to TCR & TLR */ 2213 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2214 2215 /* write tcr and tlr values */ 2216 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2217 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2218 2219 /* disable access to TCR & TLR */ 2220 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2221 2222 /* enable again, but mode is based on speed */ 2223 if (rate > 230400) { 2224 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2225 } else { 2226 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2227 } 2228 } 2229 2230 #ifdef COM_PXA2X0 2231 if (type == COM_TYPE_PXA2x0) 2232 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2233 else 2234 #endif 2235 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2236 2237 return (0); 2238 } 2239 2240 int 2241 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2242 tcflag_t cflag) 2243 { 2244 int res; 2245 2246 comcons_info.regs = *regsp; 2247 2248 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2249 if (res) 2250 return (res); 2251 2252 cn_tab = &comcons; 2253 cn_init_magic(&com_cnm_state); 2254 cn_set_magic("\047\001"); /* default magic is BREAK */ 2255 2256 comcons_info.frequency = frequency; 2257 comcons_info.type = type; 2258 comcons_info.rate = rate; 2259 comcons_info.cflag = cflag; 2260 2261 return (0); 2262 } 2263 2264 int 2265 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2266 int type, tcflag_t cflag) 2267 { 2268 struct com_regs regs; 2269 2270 memset(®s, 0, sizeof regs); 2271 regs.cr_iot = iot; 2272 regs.cr_iobase = iobase; 2273 regs.cr_nports = COM_NPORTS; 2274 #ifdef COM_REGMAP 2275 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2276 #endif 2277 2278 return comcnattach1(®s, rate, frequency, type, cflag); 2279 } 2280 2281 static int 2282 comcnreattach(void) 2283 { 2284 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2285 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2286 } 2287 2288 int 2289 comcngetc(dev_t dev) 2290 { 2291 2292 return (com_common_getc(dev, &comcons_info.regs)); 2293 } 2294 2295 /* 2296 * Console kernel output character routine. 2297 */ 2298 void 2299 comcnputc(dev_t dev, int c) 2300 { 2301 2302 com_common_putc(dev, &comcons_info.regs, c); 2303 } 2304 2305 void 2306 comcnpollc(dev_t dev, int on) 2307 { 2308 2309 } 2310 2311 #ifdef KGDB 2312 int 2313 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2314 tcflag_t cflag) 2315 { 2316 int res; 2317 2318 if (regsp->cr_iot == comcons_info.regs.cr_iot && 2319 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2320 #if !defined(DDB) 2321 return (EBUSY); /* cannot share with console */ 2322 #else 2323 comkgdbregs = *regsp; 2324 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2325 #endif 2326 } else { 2327 comkgdbregs = *regsp; 2328 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2329 if (res) 2330 return (res); 2331 2332 /* 2333 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2334 * expects this to be initialized 2335 */ 2336 cn_init_magic(&com_cnm_state); 2337 cn_set_magic("\047\001"); 2338 } 2339 2340 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2341 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2342 2343 return (0); 2344 } 2345 2346 int 2347 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2348 int frequency, int type, tcflag_t cflag) 2349 { 2350 struct com_regs regs; 2351 2352 regs.cr_iot = iot; 2353 regs.cr_nports = COM_NPORTS; 2354 regs.cr_iobase = iobase; 2355 #ifdef COM_REGMAP 2356 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2357 #endif 2358 2359 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2360 } 2361 2362 /* ARGSUSED */ 2363 int 2364 com_kgdb_getc(void *arg) 2365 { 2366 2367 return (com_common_getc(NODEV, &comkgdbregs)); 2368 } 2369 2370 /* ARGSUSED */ 2371 void 2372 com_kgdb_putc(void *arg, int c) 2373 { 2374 2375 com_common_putc(NODEV, &comkgdbregs, c); 2376 } 2377 #endif /* KGDB */ 2378 2379 /* helper function to identify the com ports used by 2380 console or KGDB (and not yet autoconf attached) */ 2381 int 2382 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2383 { 2384 bus_space_handle_t help; 2385 2386 if (!comconsattached && 2387 iot == comcons_info.regs.cr_iot && 2388 iobase == comcons_info.regs.cr_iobase) 2389 help = comcons_info.regs.cr_ioh; 2390 #ifdef KGDB 2391 else if (!com_kgdb_attached && 2392 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase) 2393 help = comkgdbregs.cr_ioh; 2394 #endif 2395 else 2396 return (0); 2397 2398 if (ioh) 2399 *ioh = help; 2400 return (1); 2401 } 2402 2403 /* 2404 * this routine exists to serve as a shutdown hook for systems that 2405 * have firmware which doesn't interact properly with a com device in 2406 * FIFO mode. 2407 */ 2408 bool 2409 com_cleanup(device_t self, int how) 2410 { 2411 struct com_softc *sc = device_private(self); 2412 2413 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2414 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2415 2416 return true; 2417 } 2418 2419 bool 2420 com_suspend(device_t self PMF_FN_ARGS) 2421 { 2422 struct com_softc *sc = device_private(self); 2423 2424 #if 0 2425 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2426 cn_tab = &comcons_suspend; 2427 #endif 2428 2429 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2430 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2431 2432 return true; 2433 } 2434 2435 bool 2436 com_resume(device_t self PMF_FN_ARGS) 2437 { 2438 struct com_softc *sc = device_private(self); 2439 2440 mutex_spin_enter(&sc->sc_lock); 2441 com_loadchannelregs(sc); 2442 mutex_spin_exit(&sc->sc_lock); 2443 2444 return true; 2445 } 2446
Indexes created Fri Sep 26 08:10:20 GMT 2025