com.c revision 1.294.2.2
1 /* $NetBSD: com.c,v 1.294.2.2 2010/08/17 06:46:09 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.294.2.2 2010/08/17 06:46:09 uebayasi Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 #if NRND > 0 && defined(RND_COM) 80 #include <sys/rnd.h> 81 #endif 82 83 /* The COM16650 option was renamed to COM_16650. */ 84 #ifdef COM16650 85 #error Obsolete COM16650 option; use COM_16650 instead. 86 #endif 87 88 /* 89 * Override cnmagic(9) macro before including <sys/systm.h>. 90 * We need to know if cn_check_magic triggered debugger, so set a flag. 91 * Callers of cn_check_magic must declare int cn_trapped = 0; 92 * XXX: this is *ugly*! 93 */ 94 #define cn_trap() \ 95 do { \ 96 console_debugger(); \ 97 cn_trapped = 1; \ 98 } while (/* CONSTCOND */ 0) 99 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/ioctl.h> 103 #include <sys/select.h> 104 #include <sys/poll.h> 105 #include <sys/tty.h> 106 #include <sys/proc.h> 107 #include <sys/conf.h> 108 #include <sys/file.h> 109 #include <sys/uio.h> 110 #include <sys/kernel.h> 111 #include <sys/syslog.h> 112 #include <sys/device.h> 113 #include <sys/malloc.h> 114 #include <sys/timepps.h> 115 #include <sys/vnode.h> 116 #include <sys/kauth.h> 117 #include <sys/intr.h> 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #ifdef COM_HAYESP 126 #include <dev/ic/hayespreg.h> 127 #endif 128 #define com_lcr com_cfcr 129 #include <dev/cons.h> 130 131 #ifdef COM_REGMAP 132 #define CSR_WRITE_1(r, o, v) \ 133 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 134 #define CSR_READ_1(r, o) \ 135 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 136 #define CSR_WRITE_2(r, o, v) \ 137 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 138 #define CSR_READ_2(r, o) \ 139 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 140 #define CSR_WRITE_MULTI(r, o, p, n) \ 141 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 142 #else 143 #define CSR_WRITE_1(r, o, v) \ 144 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 145 #define CSR_READ_1(r, o) \ 146 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 147 #define CSR_WRITE_2(r, o, v) \ 148 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 149 #define CSR_READ_2(r, o) \ 150 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 151 #define CSR_WRITE_MULTI(r, o, p, n) \ 152 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 153 #endif 154 155 156 static void com_enable_debugport(struct com_softc *); 157 158 void com_config(struct com_softc *); 159 void com_shutdown(struct com_softc *); 160 int comspeed(long, long, int); 161 static u_char cflag2lcr(tcflag_t); 162 int comparam(struct tty *, struct termios *); 163 void comstart(struct tty *); 164 int comhwiflow(struct tty *, int); 165 166 void com_loadchannelregs(struct com_softc *); 167 void com_hwiflow(struct com_softc *); 168 void com_break(struct com_softc *, int); 169 void com_modem(struct com_softc *, int); 170 void tiocm_to_com(struct com_softc *, u_long, int); 171 int com_to_tiocm(struct com_softc *); 172 void com_iflush(struct com_softc *); 173 174 int com_common_getc(dev_t, struct com_regs *); 175 static void com_common_putc(dev_t, struct com_regs *, int); 176 177 int cominit(struct com_regs *, int, int, int, tcflag_t); 178 179 static int comcnreattach(void); 180 181 int comcngetc(dev_t); 182 void comcnputc(dev_t, int); 183 void comcnpollc(dev_t, int); 184 185 #define integrate static inline 186 void comsoft(void *); 187 integrate void com_rxsoft(struct com_softc *, struct tty *); 188 integrate void com_txsoft(struct com_softc *, struct tty *); 189 integrate void com_stsoft(struct com_softc *, struct tty *); 190 integrate void com_schedrx(struct com_softc *); 191 void comdiag(void *); 192 193 extern struct cfdriver com_cd; 194 195 dev_type_open(comopen); 196 dev_type_close(comclose); 197 dev_type_read(comread); 198 dev_type_write(comwrite); 199 dev_type_ioctl(comioctl); 200 dev_type_stop(comstop); 201 dev_type_tty(comtty); 202 dev_type_poll(compoll); 203 204 static struct comcons_info comcons_info; 205 206 /* 207 * Following are all routines needed for COM to act as console 208 */ 209 static struct consdev comcons = { 210 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 211 NODEV, CN_NORMAL 212 }; 213 214 215 const struct cdevsw com_cdevsw = { 216 comopen, comclose, comread, comwrite, comioctl, 217 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 218 }; 219 220 /* 221 * Make this an option variable one can patch. 222 * But be warned: this must be a power of 2! 223 */ 224 u_int com_rbuf_size = COM_RING_SIZE; 225 226 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 227 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 228 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 229 230 static int comconsattached; 231 static struct cnm_state com_cnm_state; 232 233 #ifdef KGDB 234 #include <sys/kgdb.h> 235 236 static struct com_regs comkgdbregs; 237 static int com_kgdb_attached; 238 239 int com_kgdb_getc(void *); 240 void com_kgdb_putc(void *, int); 241 #endif /* KGDB */ 242 243 #ifdef COM_REGMAP 244 /* initializer for typical 16550-ish hardware */ 245 #define COM_REG_16550 { \ 246 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 247 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 248 249 const bus_size_t com_std_map[16] = COM_REG_16550; 250 #endif /* COM_REGMAP */ 251 252 #define COMUNIT_MASK 0x7ffff 253 #define COMDIALOUT_MASK 0x80000 254 255 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 256 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 257 258 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 259 device_is_active((sc)->sc_dev)) 260 261 #define BR BUS_SPACE_BARRIER_READ 262 #define BW BUS_SPACE_BARRIER_WRITE 263 #define COM_BARRIER(r, f) \ 264 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 265 266 /*ARGSUSED*/ 267 int 268 comspeed(long speed, long frequency, int type) 269 { 270 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 271 272 int x, err; 273 int divisor = 16; 274 275 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 276 divisor = 13; 277 } 278 279 #if 0 280 if (speed == 0) 281 return (0); 282 #endif 283 if (speed <= 0) 284 return (-1); 285 x = divrnd(frequency / divisor, speed); 286 if (x <= 0) 287 return (-1); 288 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 289 if (err < 0) 290 err = -err; 291 if (err > COM_TOLERANCE) 292 return (-1); 293 return (x); 294 295 #undef divrnd 296 } 297 298 #ifdef COM_DEBUG 299 int com_debug = 0; 300 301 void comstatus(struct com_softc *, const char *); 302 void 303 comstatus(struct com_softc *sc, const char *str) 304 { 305 struct tty *tp = sc->sc_tty; 306 307 aprint_normal_dev(sc->sc_dev, 308 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 309 str, 310 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 311 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 312 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 313 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 314 sc->sc_tx_stopped ? '+' : '-'); 315 316 aprint_normal_dev(sc->sc_dev, 317 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 318 str, 319 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 320 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 321 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 322 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 323 sc->sc_rx_flags); 324 } 325 #endif 326 327 int 328 com_probe_subr(struct com_regs *regs) 329 { 330 331 /* force access to id reg */ 332 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 333 CSR_WRITE_1(regs, COM_REG_IIR, 0); 334 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 335 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 336 return (0); 337 338 return (1); 339 } 340 341 int 342 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 343 { 344 struct com_regs regs; 345 346 regs.cr_iot = iot; 347 regs.cr_ioh = ioh; 348 #ifdef COM_REGMAP 349 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 350 #endif 351 352 return com_probe_subr(®s); 353 } 354 355 /* 356 * No locking in this routine; it is only called during attach, 357 * or with the port already locked. 358 */ 359 static void 360 com_enable_debugport(struct com_softc *sc) 361 { 362 363 /* Turn on line break interrupt, set carrier. */ 364 sc->sc_ier = IER_ERXRDY; 365 if (sc->sc_type == COM_TYPE_PXA2x0) 366 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 367 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 368 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 369 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 370 } 371 372 void 373 com_attach_subr(struct com_softc *sc) 374 { 375 struct com_regs *regsp = &sc->sc_regs; 376 struct tty *tp; 377 #ifdef COM_16650 378 u_int8_t lcr; 379 #endif 380 const char *fifo_msg = NULL; 381 382 aprint_naive("\n"); 383 384 callout_init(&sc->sc_diag_callout, 0); 385 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 386 387 /* Disable interrupts before configuring the device. */ 388 if (sc->sc_type == COM_TYPE_PXA2x0) 389 sc->sc_ier = IER_EUART; 390 else 391 sc->sc_ier = 0; 392 393 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 394 395 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 396 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 397 comconsattached = 1; 398 399 if (cn_tab == NULL && comcnreattach() != 0) { 400 printf("can't re-init serial console @%lx\n", 401 (u_long)comcons_info.regs.cr_iobase); 402 } 403 404 /* Make sure the console is always "hardwired". */ 405 delay(10000); /* wait for output to finish */ 406 SET(sc->sc_hwflags, COM_HW_CONSOLE); 407 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 408 } 409 410 /* Probe for FIFO */ 411 switch (sc->sc_type) { 412 case COM_TYPE_HAYESP: 413 goto fifodone; 414 415 case COM_TYPE_AU1x00: 416 sc->sc_fifolen = 16; 417 fifo_msg = "Au1X00 UART, working fifo"; 418 SET(sc->sc_hwflags, COM_HW_FIFO); 419 goto fifodelay; 420 421 case COM_TYPE_16550_NOERS: 422 sc->sc_fifolen = 16; 423 fifo_msg = "ns16650, no ERS, working fifo"; 424 SET(sc->sc_hwflags, COM_HW_FIFO); 425 goto fifodelay; 426 427 case COM_TYPE_OMAP: 428 sc->sc_fifolen = 64; 429 fifo_msg = "OMAP UART, working fifo"; 430 SET(sc->sc_hwflags, COM_HW_FIFO); 431 goto fifodelay; 432 } 433 434 sc->sc_fifolen = 1; 435 /* look for a NS 16550AF UART with FIFOs */ 436 CSR_WRITE_1(regsp, COM_REG_FIFO, 437 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 438 delay(100); 439 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 440 == IIR_FIFO_MASK) 441 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 442 == FIFO_TRIGGER_14) { 443 SET(sc->sc_hwflags, COM_HW_FIFO); 444 445 #ifdef COM_16650 446 /* 447 * IIR changes into the EFR if LCR is set to LCR_EERS 448 * on 16650s. We also know IIR != 0 at this point. 449 * Write 0 into the EFR, and read it. If the result 450 * is 0, we have a 16650. 451 * 452 * Older 16650s were broken; the test to detect them 453 * is taken from the Linux driver. Apparently 454 * setting DLAB enable gives access to the EFR on 455 * these chips. 456 */ 457 lcr = CSR_READ_1(regsp, COM_REG_LCR); 458 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 459 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 460 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 461 CSR_WRITE_1(regsp, COM_REG_LCR, 462 lcr | LCR_DLAB); 463 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 464 CLR(sc->sc_hwflags, COM_HW_FIFO); 465 sc->sc_fifolen = 0; 466 } else { 467 SET(sc->sc_hwflags, COM_HW_FLOW); 468 SET(sc->sc_mcr, MCR_PRESCALE); 469 sc->sc_frequency /= 4; 470 sc->sc_fifolen = 32; 471 } 472 } else 473 #endif 474 sc->sc_fifolen = 16; 475 476 #ifdef COM_16650 477 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 478 if (sc->sc_fifolen == 0) 479 fifo_msg = "st16650, broken fifo"; 480 else if (sc->sc_fifolen == 32) 481 fifo_msg = "st16650a, working fifo"; 482 else 483 #endif 484 fifo_msg = "ns16550a, working fifo"; 485 } else 486 fifo_msg = "ns16550, broken fifo"; 487 else 488 fifo_msg = "ns8250 or ns16450, no fifo"; 489 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 490 fifodelay: 491 /* 492 * Some chips will clear down both Tx and Rx FIFOs when zero is 493 * written to com_fifo. If this chip is the console, writing zero 494 * results in some of the chip/FIFO description being lost, so delay 495 * printing it until now. 496 */ 497 delay(10); 498 aprint_normal(": %s\n", fifo_msg); 499 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 500 sc->sc_fifolen = 1; 501 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 502 } 503 504 fifodone: 505 506 tp = ttymalloc(); 507 tp->t_oproc = comstart; 508 tp->t_param = comparam; 509 tp->t_hwiflow = comhwiflow; 510 511 sc->sc_tty = tp; 512 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 513 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 514 sc->sc_rbavail = com_rbuf_size; 515 if (sc->sc_rbuf == NULL) { 516 aprint_error_dev(sc->sc_dev, 517 "unable to allocate ring buffer\n"); 518 return; 519 } 520 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 521 522 tty_attach(tp); 523 524 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 525 SET(sc->sc_mcr, MCR_IENABLE); 526 527 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 528 int maj; 529 530 /* locate the major number */ 531 maj = cdevsw_lookup_major(&com_cdevsw); 532 533 tp->t_dev = cn_tab->cn_dev = makedev(maj, 534 device_unit(sc->sc_dev)); 535 536 aprint_normal_dev(sc->sc_dev, "console\n"); 537 } 538 539 #ifdef KGDB 540 /* 541 * Allow kgdb to "take over" this port. If this is 542 * not the console and is the kgdb device, it has 543 * exclusive use. If it's the console _and_ the 544 * kgdb device, it doesn't. 545 */ 546 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 547 regsp->cr_iobase == comkgdbregs.cr_iobase) { 548 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 549 com_kgdb_attached = 1; 550 551 SET(sc->sc_hwflags, COM_HW_KGDB); 552 } 553 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 554 } 555 #endif 556 557 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 558 559 #if NRND > 0 && defined(RND_COM) 560 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 561 RND_TYPE_TTY, 0); 562 #endif 563 564 /* if there are no enable/disable functions, assume the device 565 is always enabled */ 566 if (!sc->enable) 567 sc->enabled = 1; 568 569 com_config(sc); 570 571 SET(sc->sc_hwflags, COM_HW_DEV_OK); 572 } 573 574 void 575 com_config(struct com_softc *sc) 576 { 577 struct com_regs *regsp = &sc->sc_regs; 578 579 /* Disable interrupts before configuring the device. */ 580 if (sc->sc_type == COM_TYPE_PXA2x0) 581 sc->sc_ier = IER_EUART; 582 else 583 sc->sc_ier = 0; 584 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 585 (void) CSR_READ_1(regsp, COM_REG_IIR); 586 587 #ifdef COM_HAYESP 588 /* Look for a Hayes ESP board. */ 589 if (sc->sc_type == COM_TYPE_HAYESP) { 590 591 /* Set 16550 compatibility mode */ 592 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 593 HAYESP_SETMODE); 594 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 595 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 596 HAYESP_MODE_SCALE); 597 598 /* Set RTS/CTS flow control */ 599 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 600 HAYESP_SETFLOWTYPE); 601 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 602 HAYESP_FLOW_RTS); 603 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 604 HAYESP_FLOW_CTS); 605 606 /* Set flow control levels */ 607 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 608 HAYESP_SETRXFLOW); 609 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 610 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 611 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 612 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 613 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 614 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 615 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 616 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 617 } 618 #endif 619 620 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 621 com_enable_debugport(sc); 622 } 623 624 #if 0 625 static int 626 comcngetc_detached(dev_t dev) 627 { 628 return 0; 629 } 630 631 static void 632 comcnputc_detached(dev_t dev, int c) 633 { 634 } 635 #endif 636 637 int 638 com_detach(device_t self, int flags) 639 { 640 struct com_softc *sc = device_private(self); 641 int maj, mn; 642 643 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 644 return EBUSY; 645 646 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 647 (flags & DETACH_SHUTDOWN) != 0) 648 return EBUSY; 649 650 if (sc->disable != NULL && sc->enabled != 0) { 651 (*sc->disable)(sc); 652 sc->enabled = 0; 653 } 654 655 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 656 comconsattached = 0; 657 cn_tab = NULL; 658 } 659 660 /* locate the major number */ 661 maj = cdevsw_lookup_major(&com_cdevsw); 662 663 /* Nuke the vnodes for any open instances. */ 664 mn = device_unit(self); 665 vdevgone(maj, mn, mn, VCHR); 666 667 mn |= COMDIALOUT_MASK; 668 vdevgone(maj, mn, mn, VCHR); 669 670 if (sc->sc_rbuf == NULL) { 671 /* 672 * Ring buffer allocation failed in the com_attach_subr, 673 * only the tty is allocated, and nothing else. 674 */ 675 ttyfree(sc->sc_tty); 676 return 0; 677 } 678 679 /* Free the receive buffer. */ 680 free(sc->sc_rbuf, M_DEVBUF); 681 682 /* Detach and free the tty. */ 683 tty_detach(sc->sc_tty); 684 ttyfree(sc->sc_tty); 685 686 /* Unhook the soft interrupt handler. */ 687 softint_disestablish(sc->sc_si); 688 689 #if NRND > 0 && defined(RND_COM) 690 /* Unhook the entropy source. */ 691 rnd_detach_source(&sc->rnd_source); 692 #endif 693 callout_destroy(&sc->sc_diag_callout); 694 695 /* Destroy the lock. */ 696 mutex_destroy(&sc->sc_lock); 697 698 return (0); 699 } 700 701 void 702 com_shutdown(struct com_softc *sc) 703 { 704 struct tty *tp = sc->sc_tty; 705 706 mutex_spin_enter(&sc->sc_lock); 707 708 /* If we were asserting flow control, then deassert it. */ 709 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 710 com_hwiflow(sc); 711 712 /* Clear any break condition set with TIOCSBRK. */ 713 com_break(sc, 0); 714 715 /* 716 * Hang up if necessary. Wait a bit, so the other side has time to 717 * notice even if we immediately open the port again. 718 * Avoid tsleeping above splhigh(). 719 */ 720 if (ISSET(tp->t_cflag, HUPCL)) { 721 com_modem(sc, 0); 722 mutex_spin_exit(&sc->sc_lock); 723 /* XXX will only timeout */ 724 (void) kpause(ttclos, false, hz, NULL); 725 mutex_spin_enter(&sc->sc_lock); 726 } 727 728 /* Turn off interrupts. */ 729 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 730 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 731 if (sc->sc_type == COM_TYPE_PXA2x0) 732 sc->sc_ier |= IER_ERXTOUT; 733 } else 734 sc->sc_ier = 0; 735 736 if (sc->sc_type == COM_TYPE_PXA2x0) 737 sc->sc_ier |= IER_EUART; 738 739 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 740 741 mutex_spin_exit(&sc->sc_lock); 742 743 if (sc->disable) { 744 #ifdef DIAGNOSTIC 745 if (!sc->enabled) 746 panic("com_shutdown: not enabled?"); 747 #endif 748 (*sc->disable)(sc); 749 sc->enabled = 0; 750 } 751 } 752 753 int 754 comopen(dev_t dev, int flag, int mode, struct lwp *l) 755 { 756 struct com_softc *sc; 757 struct tty *tp; 758 int s; 759 int error; 760 761 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 762 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 763 sc->sc_rbuf == NULL) 764 return (ENXIO); 765 766 if (!device_is_active(sc->sc_dev)) 767 return (ENXIO); 768 769 #ifdef KGDB 770 /* 771 * If this is the kgdb port, no other use is permitted. 772 */ 773 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 774 return (EBUSY); 775 #endif 776 777 tp = sc->sc_tty; 778 779 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 780 return (EBUSY); 781 782 s = spltty(); 783 784 /* 785 * Do the following iff this is a first open. 786 */ 787 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 788 struct termios t; 789 790 tp->t_dev = dev; 791 792 793 if (sc->enable) { 794 if ((*sc->enable)(sc)) { 795 splx(s); 796 aprint_error_dev(sc->sc_dev, 797 "device enable failed\n"); 798 return (EIO); 799 } 800 mutex_spin_enter(&sc->sc_lock); 801 sc->enabled = 1; 802 com_config(sc); 803 } else { 804 mutex_spin_enter(&sc->sc_lock); 805 } 806 807 /* Turn on interrupts. */ 808 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 809 if (sc->sc_type == COM_TYPE_PXA2x0) 810 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 811 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 812 813 /* Fetch the current modem control status, needed later. */ 814 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 815 816 /* Clear PPS capture state on first open. */ 817 mutex_spin_enter(&timecounter_lock); 818 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 819 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 820 pps_init(&sc->sc_pps_state); 821 mutex_spin_exit(&timecounter_lock); 822 823 mutex_spin_exit(&sc->sc_lock); 824 825 /* 826 * Initialize the termios status to the defaults. Add in the 827 * sticky bits from TIOCSFLAGS. 828 */ 829 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 830 t.c_ospeed = comcons_info.rate; 831 t.c_cflag = comcons_info.cflag; 832 } else { 833 t.c_ospeed = TTYDEF_SPEED; 834 t.c_cflag = TTYDEF_CFLAG; 835 } 836 t.c_ispeed = t.c_ospeed; 837 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 838 SET(t.c_cflag, CLOCAL); 839 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 840 SET(t.c_cflag, CRTSCTS); 841 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 842 SET(t.c_cflag, MDMBUF); 843 /* Make sure comparam() will do something. */ 844 tp->t_ospeed = 0; 845 (void) comparam(tp, &t); 846 tp->t_iflag = TTYDEF_IFLAG; 847 tp->t_oflag = TTYDEF_OFLAG; 848 tp->t_lflag = TTYDEF_LFLAG; 849 ttychars(tp); 850 ttsetwater(tp); 851 852 mutex_spin_enter(&sc->sc_lock); 853 854 /* 855 * Turn on DTR. We must always do this, even if carrier is not 856 * present, because otherwise we'd have to use TIOCSDTR 857 * immediately after setting CLOCAL, which applications do not 858 * expect. We always assert DTR while the device is open 859 * unless explicitly requested to deassert it. 860 */ 861 com_modem(sc, 1); 862 863 /* Clear the input ring, and unblock. */ 864 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 865 sc->sc_rbavail = com_rbuf_size; 866 com_iflush(sc); 867 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 868 com_hwiflow(sc); 869 870 #ifdef COM_DEBUG 871 if (com_debug) 872 comstatus(sc, "comopen "); 873 #endif 874 875 mutex_spin_exit(&sc->sc_lock); 876 } 877 878 splx(s); 879 880 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 881 if (error) 882 goto bad; 883 884 error = (*tp->t_linesw->l_open)(dev, tp); 885 if (error) 886 goto bad; 887 888 return (0); 889 890 bad: 891 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 892 /* 893 * We failed to open the device, and nobody else had it opened. 894 * Clean up the state as appropriate. 895 */ 896 com_shutdown(sc); 897 } 898 899 return (error); 900 } 901 902 int 903 comclose(dev_t dev, int flag, int mode, struct lwp *l) 904 { 905 struct com_softc *sc = 906 device_lookup_private(&com_cd, COMUNIT(dev)); 907 struct tty *tp = sc->sc_tty; 908 909 /* XXX This is for cons.c. */ 910 if (!ISSET(tp->t_state, TS_ISOPEN)) 911 return (0); 912 913 (*tp->t_linesw->l_close)(tp, flag); 914 ttyclose(tp); 915 916 if (COM_ISALIVE(sc) == 0) 917 return (0); 918 919 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 920 /* 921 * Although we got a last close, the device may still be in 922 * use; e.g. if this was the dialout node, and there are still 923 * processes waiting for carrier on the non-dialout node. 924 */ 925 com_shutdown(sc); 926 } 927 928 return (0); 929 } 930 931 int 932 comread(dev_t dev, struct uio *uio, int flag) 933 { 934 struct com_softc *sc = 935 device_lookup_private(&com_cd, COMUNIT(dev)); 936 struct tty *tp = sc->sc_tty; 937 938 if (COM_ISALIVE(sc) == 0) 939 return (EIO); 940 941 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 942 } 943 944 int 945 comwrite(dev_t dev, struct uio *uio, int flag) 946 { 947 struct com_softc *sc = 948 device_lookup_private(&com_cd, COMUNIT(dev)); 949 struct tty *tp = sc->sc_tty; 950 951 if (COM_ISALIVE(sc) == 0) 952 return (EIO); 953 954 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 955 } 956 957 int 958 compoll(dev_t dev, int events, struct lwp *l) 959 { 960 struct com_softc *sc = 961 device_lookup_private(&com_cd, COMUNIT(dev)); 962 struct tty *tp = sc->sc_tty; 963 964 if (COM_ISALIVE(sc) == 0) 965 return (POLLHUP); 966 967 return ((*tp->t_linesw->l_poll)(tp, events, l)); 968 } 969 970 struct tty * 971 comtty(dev_t dev) 972 { 973 struct com_softc *sc = 974 device_lookup_private(&com_cd, COMUNIT(dev)); 975 struct tty *tp = sc->sc_tty; 976 977 return (tp); 978 } 979 980 int 981 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 982 { 983 struct com_softc *sc; 984 struct tty *tp; 985 int error; 986 987 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 988 if (sc == NULL) 989 return ENXIO; 990 if (COM_ISALIVE(sc) == 0) 991 return (EIO); 992 993 tp = sc->sc_tty; 994 995 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 996 if (error != EPASSTHROUGH) 997 return (error); 998 999 error = ttioctl(tp, cmd, data, flag, l); 1000 if (error != EPASSTHROUGH) 1001 return (error); 1002 1003 error = 0; 1004 switch (cmd) { 1005 case TIOCSFLAGS: 1006 error = kauth_authorize_device_tty(l->l_cred, 1007 KAUTH_DEVICE_TTY_PRIVSET, tp); 1008 break; 1009 default: 1010 /* nothing */ 1011 break; 1012 } 1013 if (error) { 1014 return error; 1015 } 1016 1017 mutex_spin_enter(&sc->sc_lock); 1018 1019 switch (cmd) { 1020 case TIOCSBRK: 1021 com_break(sc, 1); 1022 break; 1023 1024 case TIOCCBRK: 1025 com_break(sc, 0); 1026 break; 1027 1028 case TIOCSDTR: 1029 com_modem(sc, 1); 1030 break; 1031 1032 case TIOCCDTR: 1033 com_modem(sc, 0); 1034 break; 1035 1036 case TIOCGFLAGS: 1037 *(int *)data = sc->sc_swflags; 1038 break; 1039 1040 case TIOCSFLAGS: 1041 sc->sc_swflags = *(int *)data; 1042 break; 1043 1044 case TIOCMSET: 1045 case TIOCMBIS: 1046 case TIOCMBIC: 1047 tiocm_to_com(sc, cmd, *(int *)data); 1048 break; 1049 1050 case TIOCMGET: 1051 *(int *)data = com_to_tiocm(sc); 1052 break; 1053 1054 case PPS_IOC_CREATE: 1055 case PPS_IOC_DESTROY: 1056 case PPS_IOC_GETPARAMS: 1057 case PPS_IOC_SETPARAMS: 1058 case PPS_IOC_GETCAP: 1059 case PPS_IOC_FETCH: 1060 #ifdef PPS_SYNC 1061 case PPS_IOC_KCBIND: 1062 #endif 1063 mutex_spin_enter(&timecounter_lock); 1064 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1065 mutex_spin_exit(&timecounter_lock); 1066 break; 1067 1068 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1069 mutex_spin_enter(&timecounter_lock); 1070 #ifndef PPS_TRAILING_EDGE 1071 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1072 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1073 #else 1074 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1075 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1076 #endif 1077 mutex_spin_exit(&timecounter_lock); 1078 break; 1079 1080 default: 1081 error = EPASSTHROUGH; 1082 break; 1083 } 1084 1085 mutex_spin_exit(&sc->sc_lock); 1086 1087 #ifdef COM_DEBUG 1088 if (com_debug) 1089 comstatus(sc, "comioctl "); 1090 #endif 1091 1092 return (error); 1093 } 1094 1095 integrate void 1096 com_schedrx(struct com_softc *sc) 1097 { 1098 1099 sc->sc_rx_ready = 1; 1100 1101 /* Wake up the poller. */ 1102 softint_schedule(sc->sc_si); 1103 } 1104 1105 void 1106 com_break(struct com_softc *sc, int onoff) 1107 { 1108 1109 if (onoff) 1110 SET(sc->sc_lcr, LCR_SBREAK); 1111 else 1112 CLR(sc->sc_lcr, LCR_SBREAK); 1113 1114 if (!sc->sc_heldchange) { 1115 if (sc->sc_tx_busy) { 1116 sc->sc_heldtbc = sc->sc_tbc; 1117 sc->sc_tbc = 0; 1118 sc->sc_heldchange = 1; 1119 } else 1120 com_loadchannelregs(sc); 1121 } 1122 } 1123 1124 void 1125 com_modem(struct com_softc *sc, int onoff) 1126 { 1127 1128 if (sc->sc_mcr_dtr == 0) 1129 return; 1130 1131 if (onoff) 1132 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1133 else 1134 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1135 1136 if (!sc->sc_heldchange) { 1137 if (sc->sc_tx_busy) { 1138 sc->sc_heldtbc = sc->sc_tbc; 1139 sc->sc_tbc = 0; 1140 sc->sc_heldchange = 1; 1141 } else 1142 com_loadchannelregs(sc); 1143 } 1144 } 1145 1146 void 1147 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1148 { 1149 u_char combits; 1150 1151 combits = 0; 1152 if (ISSET(ttybits, TIOCM_DTR)) 1153 SET(combits, MCR_DTR); 1154 if (ISSET(ttybits, TIOCM_RTS)) 1155 SET(combits, MCR_RTS); 1156 1157 switch (how) { 1158 case TIOCMBIC: 1159 CLR(sc->sc_mcr, combits); 1160 break; 1161 1162 case TIOCMBIS: 1163 SET(sc->sc_mcr, combits); 1164 break; 1165 1166 case TIOCMSET: 1167 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1168 SET(sc->sc_mcr, combits); 1169 break; 1170 } 1171 1172 if (!sc->sc_heldchange) { 1173 if (sc->sc_tx_busy) { 1174 sc->sc_heldtbc = sc->sc_tbc; 1175 sc->sc_tbc = 0; 1176 sc->sc_heldchange = 1; 1177 } else 1178 com_loadchannelregs(sc); 1179 } 1180 } 1181 1182 int 1183 com_to_tiocm(struct com_softc *sc) 1184 { 1185 u_char combits; 1186 int ttybits = 0; 1187 1188 combits = sc->sc_mcr; 1189 if (ISSET(combits, MCR_DTR)) 1190 SET(ttybits, TIOCM_DTR); 1191 if (ISSET(combits, MCR_RTS)) 1192 SET(ttybits, TIOCM_RTS); 1193 1194 combits = sc->sc_msr; 1195 if (ISSET(combits, MSR_DCD)) 1196 SET(ttybits, TIOCM_CD); 1197 if (ISSET(combits, MSR_CTS)) 1198 SET(ttybits, TIOCM_CTS); 1199 if (ISSET(combits, MSR_DSR)) 1200 SET(ttybits, TIOCM_DSR); 1201 if (ISSET(combits, MSR_RI | MSR_TERI)) 1202 SET(ttybits, TIOCM_RI); 1203 1204 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1205 SET(ttybits, TIOCM_LE); 1206 1207 return (ttybits); 1208 } 1209 1210 static u_char 1211 cflag2lcr(tcflag_t cflag) 1212 { 1213 u_char lcr = 0; 1214 1215 switch (ISSET(cflag, CSIZE)) { 1216 case CS5: 1217 SET(lcr, LCR_5BITS); 1218 break; 1219 case CS6: 1220 SET(lcr, LCR_6BITS); 1221 break; 1222 case CS7: 1223 SET(lcr, LCR_7BITS); 1224 break; 1225 case CS8: 1226 SET(lcr, LCR_8BITS); 1227 break; 1228 } 1229 if (ISSET(cflag, PARENB)) { 1230 SET(lcr, LCR_PENAB); 1231 if (!ISSET(cflag, PARODD)) 1232 SET(lcr, LCR_PEVEN); 1233 } 1234 if (ISSET(cflag, CSTOPB)) 1235 SET(lcr, LCR_STOPB); 1236 1237 return (lcr); 1238 } 1239 1240 int 1241 comparam(struct tty *tp, struct termios *t) 1242 { 1243 struct com_softc *sc = 1244 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1245 int ospeed; 1246 u_char lcr; 1247 1248 if (COM_ISALIVE(sc) == 0) 1249 return (EIO); 1250 1251 #ifdef COM_HAYESP 1252 if (sc->sc_type == COM_TYPE_HAYESP) { 1253 int prescaler, speed; 1254 1255 /* 1256 * Calculate UART clock prescaler. It should be in 1257 * range of 0 .. 3. 1258 */ 1259 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1260 prescaler++, speed /= 2) 1261 if ((ospeed = comspeed(speed, sc->sc_frequency, 1262 sc->sc_type)) > 0) 1263 break; 1264 1265 if (prescaler == 4) 1266 return (EINVAL); 1267 sc->sc_prescaler = prescaler; 1268 } else 1269 #endif 1270 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1271 1272 /* Check requested parameters. */ 1273 if (ospeed < 0) 1274 return (EINVAL); 1275 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1276 return (EINVAL); 1277 1278 /* 1279 * For the console, always force CLOCAL and !HUPCL, so that the port 1280 * is always active. 1281 */ 1282 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1283 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1284 SET(t->c_cflag, CLOCAL); 1285 CLR(t->c_cflag, HUPCL); 1286 } 1287 1288 /* 1289 * If there were no changes, don't do anything. This avoids dropping 1290 * input and improves performance when all we did was frob things like 1291 * VMIN and VTIME. 1292 */ 1293 if (tp->t_ospeed == t->c_ospeed && 1294 tp->t_cflag == t->c_cflag) 1295 return (0); 1296 1297 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1298 1299 mutex_spin_enter(&sc->sc_lock); 1300 1301 sc->sc_lcr = lcr; 1302 1303 /* 1304 * If we're not in a mode that assumes a connection is present, then 1305 * ignore carrier changes. 1306 */ 1307 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1308 sc->sc_msr_dcd = 0; 1309 else 1310 sc->sc_msr_dcd = MSR_DCD; 1311 /* 1312 * Set the flow control pins depending on the current flow control 1313 * mode. 1314 */ 1315 if (ISSET(t->c_cflag, CRTSCTS)) { 1316 sc->sc_mcr_dtr = MCR_DTR; 1317 sc->sc_mcr_rts = MCR_RTS; 1318 sc->sc_msr_cts = MSR_CTS; 1319 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1320 } else if (ISSET(t->c_cflag, MDMBUF)) { 1321 /* 1322 * For DTR/DCD flow control, make sure we don't toggle DTR for 1323 * carrier detection. 1324 */ 1325 sc->sc_mcr_dtr = 0; 1326 sc->sc_mcr_rts = MCR_DTR; 1327 sc->sc_msr_cts = MSR_DCD; 1328 sc->sc_efr = 0; 1329 } else { 1330 /* 1331 * If no flow control, then always set RTS. This will make 1332 * the other side happy if it mistakenly thinks we're doing 1333 * RTS/CTS flow control. 1334 */ 1335 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1336 sc->sc_mcr_rts = 0; 1337 sc->sc_msr_cts = 0; 1338 sc->sc_efr = 0; 1339 if (ISSET(sc->sc_mcr, MCR_DTR)) 1340 SET(sc->sc_mcr, MCR_RTS); 1341 else 1342 CLR(sc->sc_mcr, MCR_RTS); 1343 } 1344 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1345 1346 #if 0 1347 if (ospeed == 0) 1348 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1349 else 1350 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1351 #endif 1352 1353 sc->sc_dlbl = ospeed; 1354 sc->sc_dlbh = ospeed >> 8; 1355 1356 /* 1357 * Set the FIFO threshold based on the receive speed. 1358 * 1359 * * If it's a low speed, it's probably a mouse or some other 1360 * interactive device, so set the threshold low. 1361 * * If it's a high speed, trim the trigger level down to prevent 1362 * overflows. 1363 * * Otherwise set it a bit higher. 1364 */ 1365 if (sc->sc_type == COM_TYPE_HAYESP) 1366 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1367 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1368 if (t->c_ospeed <= 1200) 1369 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1370 else if (t->c_ospeed <= 38400) 1371 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1372 else 1373 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1374 } else 1375 sc->sc_fifo = 0; 1376 1377 /* And copy to tty. */ 1378 tp->t_ispeed = t->c_ospeed; 1379 tp->t_ospeed = t->c_ospeed; 1380 tp->t_cflag = t->c_cflag; 1381 1382 if (!sc->sc_heldchange) { 1383 if (sc->sc_tx_busy) { 1384 sc->sc_heldtbc = sc->sc_tbc; 1385 sc->sc_tbc = 0; 1386 sc->sc_heldchange = 1; 1387 } else 1388 com_loadchannelregs(sc); 1389 } 1390 1391 if (!ISSET(t->c_cflag, CHWFLOW)) { 1392 /* Disable the high water mark. */ 1393 sc->sc_r_hiwat = 0; 1394 sc->sc_r_lowat = 0; 1395 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1396 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1397 com_schedrx(sc); 1398 } 1399 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1400 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1401 com_hwiflow(sc); 1402 } 1403 } else { 1404 sc->sc_r_hiwat = com_rbuf_hiwat; 1405 sc->sc_r_lowat = com_rbuf_lowat; 1406 } 1407 1408 mutex_spin_exit(&sc->sc_lock); 1409 1410 /* 1411 * Update the tty layer's idea of the carrier bit, in case we changed 1412 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1413 * explicit request. 1414 */ 1415 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1416 1417 #ifdef COM_DEBUG 1418 if (com_debug) 1419 comstatus(sc, "comparam "); 1420 #endif 1421 1422 if (!ISSET(t->c_cflag, CHWFLOW)) { 1423 if (sc->sc_tx_stopped) { 1424 sc->sc_tx_stopped = 0; 1425 comstart(tp); 1426 } 1427 } 1428 1429 return (0); 1430 } 1431 1432 void 1433 com_iflush(struct com_softc *sc) 1434 { 1435 struct com_regs *regsp = &sc->sc_regs; 1436 #ifdef DIAGNOSTIC 1437 int reg; 1438 #endif 1439 int timo; 1440 1441 #ifdef DIAGNOSTIC 1442 reg = 0xffff; 1443 #endif 1444 timo = 50000; 1445 /* flush any pending I/O */ 1446 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1447 && --timo) 1448 #ifdef DIAGNOSTIC 1449 reg = 1450 #else 1451 (void) 1452 #endif 1453 CSR_READ_1(regsp, COM_REG_RXDATA); 1454 #ifdef DIAGNOSTIC 1455 if (!timo) 1456 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1457 #endif 1458 } 1459 1460 void 1461 com_loadchannelregs(struct com_softc *sc) 1462 { 1463 struct com_regs *regsp = &sc->sc_regs; 1464 1465 /* XXXXX necessary? */ 1466 com_iflush(sc); 1467 1468 if (sc->sc_type == COM_TYPE_PXA2x0) 1469 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1470 else 1471 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1472 1473 if (sc->sc_type == COM_TYPE_OMAP) { 1474 /* disable before changing settings */ 1475 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1476 } 1477 1478 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1479 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1480 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1481 /* no EFR on alchemy */ 1482 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1483 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1484 } 1485 if (sc->sc_type == COM_TYPE_AU1x00) { 1486 /* alchemy has single separate 16-bit clock divisor register */ 1487 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1488 (sc->sc_dlbh << 8)); 1489 } else { 1490 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1491 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1492 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1493 } 1494 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1495 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1496 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1497 #ifdef COM_HAYESP 1498 if (sc->sc_type == COM_TYPE_HAYESP) { 1499 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1500 HAYESP_SETPRESCALER); 1501 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1502 sc->sc_prescaler); 1503 } 1504 #endif 1505 if (sc->sc_type == COM_TYPE_OMAP) { 1506 /* setup the fifos. the FCR value is not used as long 1507 as SCR[6] and SCR[7] are 0, which they are at reset 1508 and we never touch the SCR register */ 1509 uint8_t rx_fifo_trig = 40; 1510 uint8_t tx_fifo_trig = 60; 1511 uint8_t rx_start = 8; 1512 uint8_t rx_halt = 60; 1513 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1514 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1515 1516 /* enable access to TCR & TLR */ 1517 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1518 1519 /* write tcr and tlr values */ 1520 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1521 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1522 1523 /* disable access to TCR & TLR */ 1524 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1525 1526 /* enable again, but mode is based on speed */ 1527 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1528 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1529 } else { 1530 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1531 } 1532 } 1533 1534 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1535 } 1536 1537 int 1538 comhwiflow(struct tty *tp, int block) 1539 { 1540 struct com_softc *sc = 1541 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1542 1543 if (COM_ISALIVE(sc) == 0) 1544 return (0); 1545 1546 if (sc->sc_mcr_rts == 0) 1547 return (0); 1548 1549 mutex_spin_enter(&sc->sc_lock); 1550 1551 if (block) { 1552 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1553 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1554 com_hwiflow(sc); 1555 } 1556 } else { 1557 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1558 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1559 com_schedrx(sc); 1560 } 1561 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1562 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1563 com_hwiflow(sc); 1564 } 1565 } 1566 1567 mutex_spin_exit(&sc->sc_lock); 1568 return (1); 1569 } 1570 1571 /* 1572 * (un)block input via hw flowcontrol 1573 */ 1574 void 1575 com_hwiflow(struct com_softc *sc) 1576 { 1577 struct com_regs *regsp= &sc->sc_regs; 1578 1579 if (sc->sc_mcr_rts == 0) 1580 return; 1581 1582 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1583 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1584 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1585 } else { 1586 SET(sc->sc_mcr, sc->sc_mcr_rts); 1587 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1588 } 1589 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1590 } 1591 1592 1593 void 1594 comstart(struct tty *tp) 1595 { 1596 struct com_softc *sc = 1597 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1598 struct com_regs *regsp = &sc->sc_regs; 1599 int s; 1600 1601 if (COM_ISALIVE(sc) == 0) 1602 return; 1603 1604 s = spltty(); 1605 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1606 goto out; 1607 if (sc->sc_tx_stopped) 1608 goto out; 1609 if (!ttypull(tp)) 1610 goto out; 1611 1612 /* Grab the first contiguous region of buffer space. */ 1613 { 1614 u_char *tba; 1615 int tbc; 1616 1617 tba = tp->t_outq.c_cf; 1618 tbc = ndqb(&tp->t_outq, 0); 1619 1620 mutex_spin_enter(&sc->sc_lock); 1621 1622 sc->sc_tba = tba; 1623 sc->sc_tbc = tbc; 1624 } 1625 1626 SET(tp->t_state, TS_BUSY); 1627 sc->sc_tx_busy = 1; 1628 1629 /* Enable transmit completion interrupts if necessary. */ 1630 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1631 SET(sc->sc_ier, IER_ETXRDY); 1632 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1633 } 1634 1635 /* Output the first chunk of the contiguous buffer. */ 1636 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1637 u_int n; 1638 1639 n = sc->sc_tbc; 1640 if (n > sc->sc_fifolen) 1641 n = sc->sc_fifolen; 1642 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1643 sc->sc_tbc -= n; 1644 sc->sc_tba += n; 1645 } 1646 1647 mutex_spin_exit(&sc->sc_lock); 1648 out: 1649 splx(s); 1650 return; 1651 } 1652 1653 /* 1654 * Stop output on a line. 1655 */ 1656 void 1657 comstop(struct tty *tp, int flag) 1658 { 1659 struct com_softc *sc = 1660 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1661 1662 mutex_spin_enter(&sc->sc_lock); 1663 if (ISSET(tp->t_state, TS_BUSY)) { 1664 /* Stop transmitting at the next chunk. */ 1665 sc->sc_tbc = 0; 1666 sc->sc_heldtbc = 0; 1667 if (!ISSET(tp->t_state, TS_TTSTOP)) 1668 SET(tp->t_state, TS_FLUSH); 1669 } 1670 mutex_spin_exit(&sc->sc_lock); 1671 } 1672 1673 void 1674 comdiag(void *arg) 1675 { 1676 struct com_softc *sc = arg; 1677 int overflows, floods; 1678 1679 mutex_spin_enter(&sc->sc_lock); 1680 overflows = sc->sc_overflows; 1681 sc->sc_overflows = 0; 1682 floods = sc->sc_floods; 1683 sc->sc_floods = 0; 1684 sc->sc_errors = 0; 1685 mutex_spin_exit(&sc->sc_lock); 1686 1687 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1688 device_xname(sc->sc_dev), 1689 overflows, overflows == 1 ? "" : "s", 1690 floods, floods == 1 ? "" : "s"); 1691 } 1692 1693 integrate void 1694 com_rxsoft(struct com_softc *sc, struct tty *tp) 1695 { 1696 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1697 u_char *get, *end; 1698 u_int cc, scc; 1699 u_char lsr; 1700 int code; 1701 1702 end = sc->sc_ebuf; 1703 get = sc->sc_rbget; 1704 scc = cc = com_rbuf_size - sc->sc_rbavail; 1705 1706 if (cc == com_rbuf_size) { 1707 sc->sc_floods++; 1708 if (sc->sc_errors++ == 0) 1709 callout_reset(&sc->sc_diag_callout, 60 * hz, 1710 comdiag, sc); 1711 } 1712 1713 /* If not yet open, drop the entire buffer content here */ 1714 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1715 get += cc << 1; 1716 if (get >= end) 1717 get -= com_rbuf_size << 1; 1718 cc = 0; 1719 } 1720 while (cc) { 1721 code = get[0]; 1722 lsr = get[1]; 1723 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1724 if (ISSET(lsr, LSR_OE)) { 1725 sc->sc_overflows++; 1726 if (sc->sc_errors++ == 0) 1727 callout_reset(&sc->sc_diag_callout, 1728 60 * hz, comdiag, sc); 1729 } 1730 if (ISSET(lsr, LSR_BI | LSR_FE)) 1731 SET(code, TTY_FE); 1732 if (ISSET(lsr, LSR_PE)) 1733 SET(code, TTY_PE); 1734 } 1735 if ((*rint)(code, tp) == -1) { 1736 /* 1737 * The line discipline's buffer is out of space. 1738 */ 1739 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1740 /* 1741 * We're either not using flow control, or the 1742 * line discipline didn't tell us to block for 1743 * some reason. Either way, we have no way to 1744 * know when there's more space available, so 1745 * just drop the rest of the data. 1746 */ 1747 get += cc << 1; 1748 if (get >= end) 1749 get -= com_rbuf_size << 1; 1750 cc = 0; 1751 } else { 1752 /* 1753 * Don't schedule any more receive processing 1754 * until the line discipline tells us there's 1755 * space available (through comhwiflow()). 1756 * Leave the rest of the data in the input 1757 * buffer. 1758 */ 1759 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1760 } 1761 break; 1762 } 1763 get += 2; 1764 if (get >= end) 1765 get = sc->sc_rbuf; 1766 cc--; 1767 } 1768 1769 if (cc != scc) { 1770 sc->sc_rbget = get; 1771 mutex_spin_enter(&sc->sc_lock); 1772 1773 cc = sc->sc_rbavail += scc - cc; 1774 /* Buffers should be ok again, release possible block. */ 1775 if (cc >= sc->sc_r_lowat) { 1776 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1777 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1778 SET(sc->sc_ier, IER_ERXRDY); 1779 #ifdef COM_PXA2X0 1780 if (sc->sc_type == COM_TYPE_PXA2x0) 1781 SET(sc->sc_ier, IER_ERXTOUT); 1782 #endif 1783 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1784 } 1785 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1786 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1787 com_hwiflow(sc); 1788 } 1789 } 1790 mutex_spin_exit(&sc->sc_lock); 1791 } 1792 } 1793 1794 integrate void 1795 com_txsoft(struct com_softc *sc, struct tty *tp) 1796 { 1797 1798 CLR(tp->t_state, TS_BUSY); 1799 if (ISSET(tp->t_state, TS_FLUSH)) 1800 CLR(tp->t_state, TS_FLUSH); 1801 else 1802 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1803 (*tp->t_linesw->l_start)(tp); 1804 } 1805 1806 integrate void 1807 com_stsoft(struct com_softc *sc, struct tty *tp) 1808 { 1809 u_char msr, delta; 1810 1811 mutex_spin_enter(&sc->sc_lock); 1812 msr = sc->sc_msr; 1813 delta = sc->sc_msr_delta; 1814 sc->sc_msr_delta = 0; 1815 mutex_spin_exit(&sc->sc_lock); 1816 1817 if (ISSET(delta, sc->sc_msr_dcd)) { 1818 /* 1819 * Inform the tty layer that carrier detect changed. 1820 */ 1821 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1822 } 1823 1824 if (ISSET(delta, sc->sc_msr_cts)) { 1825 /* Block or unblock output according to flow control. */ 1826 if (ISSET(msr, sc->sc_msr_cts)) { 1827 sc->sc_tx_stopped = 0; 1828 (*tp->t_linesw->l_start)(tp); 1829 } else { 1830 sc->sc_tx_stopped = 1; 1831 } 1832 } 1833 1834 #ifdef COM_DEBUG 1835 if (com_debug) 1836 comstatus(sc, "com_stsoft"); 1837 #endif 1838 } 1839 1840 void 1841 comsoft(void *arg) 1842 { 1843 struct com_softc *sc = arg; 1844 struct tty *tp; 1845 1846 if (COM_ISALIVE(sc) == 0) 1847 return; 1848 1849 tp = sc->sc_tty; 1850 1851 if (sc->sc_rx_ready) { 1852 sc->sc_rx_ready = 0; 1853 com_rxsoft(sc, tp); 1854 } 1855 1856 if (sc->sc_st_check) { 1857 sc->sc_st_check = 0; 1858 com_stsoft(sc, tp); 1859 } 1860 1861 if (sc->sc_tx_done) { 1862 sc->sc_tx_done = 0; 1863 com_txsoft(sc, tp); 1864 } 1865 } 1866 1867 int 1868 comintr(void *arg) 1869 { 1870 struct com_softc *sc = arg; 1871 struct com_regs *regsp = &sc->sc_regs; 1872 1873 u_char *put, *end; 1874 u_int cc; 1875 u_char lsr, iir; 1876 1877 if (COM_ISALIVE(sc) == 0) 1878 return (0); 1879 1880 KASSERT(regsp != NULL); 1881 1882 mutex_spin_enter(&sc->sc_lock); 1883 iir = CSR_READ_1(regsp, COM_REG_IIR); 1884 if (ISSET(iir, IIR_NOPEND)) { 1885 mutex_spin_exit(&sc->sc_lock); 1886 return (0); 1887 } 1888 1889 end = sc->sc_ebuf; 1890 put = sc->sc_rbput; 1891 cc = sc->sc_rbavail; 1892 1893 again: do { 1894 u_char msr, delta; 1895 1896 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1897 if (ISSET(lsr, LSR_BI)) { 1898 int cn_trapped = 0; 1899 1900 cn_check_magic(sc->sc_tty->t_dev, 1901 CNC_BREAK, com_cnm_state); 1902 if (cn_trapped) 1903 continue; 1904 #if defined(KGDB) && !defined(DDB) 1905 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1906 kgdb_connect(1); 1907 continue; 1908 } 1909 #endif 1910 } 1911 1912 if (ISSET(lsr, LSR_RCV_MASK) && 1913 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1914 while (cc > 0) { 1915 int cn_trapped = 0; 1916 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1917 put[1] = lsr; 1918 cn_check_magic(sc->sc_tty->t_dev, 1919 put[0], com_cnm_state); 1920 if (cn_trapped) 1921 goto next; 1922 put += 2; 1923 if (put >= end) 1924 put = sc->sc_rbuf; 1925 cc--; 1926 next: 1927 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1928 if (!ISSET(lsr, LSR_RCV_MASK)) 1929 break; 1930 } 1931 1932 /* 1933 * Current string of incoming characters ended because 1934 * no more data was available or we ran out of space. 1935 * Schedule a receive event if any data was received. 1936 * If we're out of space, turn off receive interrupts. 1937 */ 1938 sc->sc_rbput = put; 1939 sc->sc_rbavail = cc; 1940 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1941 sc->sc_rx_ready = 1; 1942 1943 /* 1944 * See if we are in danger of overflowing a buffer. If 1945 * so, use hardware flow control to ease the pressure. 1946 */ 1947 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1948 cc < sc->sc_r_hiwat) { 1949 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1950 com_hwiflow(sc); 1951 } 1952 1953 /* 1954 * If we're out of space, disable receive interrupts 1955 * until the queue has drained a bit. 1956 */ 1957 if (!cc) { 1958 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1959 #ifdef COM_PXA2X0 1960 if (sc->sc_type == COM_TYPE_PXA2x0) 1961 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 1962 else 1963 #endif 1964 CLR(sc->sc_ier, IER_ERXRDY); 1965 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1966 } 1967 } else { 1968 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 1969 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 1970 continue; 1971 } 1972 } 1973 1974 msr = CSR_READ_1(regsp, COM_REG_MSR); 1975 delta = msr ^ sc->sc_msr; 1976 sc->sc_msr = msr; 1977 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1978 (delta & MSR_DCD)) { 1979 mutex_spin_enter(&timecounter_lock); 1980 pps_capture(&sc->sc_pps_state); 1981 pps_event(&sc->sc_pps_state, 1982 (msr & MSR_DCD) ? 1983 PPS_CAPTUREASSERT : 1984 PPS_CAPTURECLEAR); 1985 mutex_spin_exit(&timecounter_lock); 1986 } 1987 1988 /* 1989 * Process normal status changes 1990 */ 1991 if (ISSET(delta, sc->sc_msr_mask)) { 1992 SET(sc->sc_msr_delta, delta); 1993 1994 /* 1995 * Stop output immediately if we lose the output 1996 * flow control signal or carrier detect. 1997 */ 1998 if (ISSET(~msr, sc->sc_msr_mask)) { 1999 sc->sc_tbc = 0; 2000 sc->sc_heldtbc = 0; 2001 #ifdef COM_DEBUG 2002 if (com_debug) 2003 comstatus(sc, "comintr "); 2004 #endif 2005 } 2006 2007 sc->sc_st_check = 1; 2008 } 2009 } while (!ISSET((iir = 2010 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2011 /* 2012 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2013 * by IIR read, so we can't do this way: `process all interrupts, 2014 * then do TX if possble'. 2015 */ 2016 (iir & IIR_IMASK) != IIR_TXRDY); 2017 2018 /* 2019 * Read LSR again, since there may be an interrupt between 2020 * the last LSR read and IIR read above. 2021 */ 2022 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2023 2024 /* 2025 * See if data can be transmitted as well. 2026 * Schedule tx done event if no data left 2027 * and tty was marked busy. 2028 */ 2029 if (ISSET(lsr, LSR_TXRDY)) { 2030 /* 2031 * If we've delayed a parameter change, do it now, and restart 2032 * output. 2033 */ 2034 if (sc->sc_heldchange) { 2035 com_loadchannelregs(sc); 2036 sc->sc_heldchange = 0; 2037 sc->sc_tbc = sc->sc_heldtbc; 2038 sc->sc_heldtbc = 0; 2039 } 2040 2041 /* Output the next chunk of the contiguous buffer, if any. */ 2042 if (sc->sc_tbc > 0) { 2043 u_int n; 2044 2045 n = sc->sc_tbc; 2046 if (n > sc->sc_fifolen) 2047 n = sc->sc_fifolen; 2048 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2049 sc->sc_tbc -= n; 2050 sc->sc_tba += n; 2051 } else { 2052 /* Disable transmit completion interrupts if necessary. */ 2053 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2054 CLR(sc->sc_ier, IER_ETXRDY); 2055 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2056 } 2057 if (sc->sc_tx_busy) { 2058 sc->sc_tx_busy = 0; 2059 sc->sc_tx_done = 1; 2060 } 2061 } 2062 } 2063 2064 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2065 goto again; 2066 2067 mutex_spin_exit(&sc->sc_lock); 2068 2069 /* Wake up the poller. */ 2070 softint_schedule(sc->sc_si); 2071 2072 #if NRND > 0 && defined(RND_COM) 2073 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2074 #endif 2075 2076 return (1); 2077 } 2078 2079 /* 2080 * The following functions are polled getc and putc routines, shared 2081 * by the console and kgdb glue. 2082 * 2083 * The read-ahead code is so that you can detect pending in-band 2084 * cn_magic in polled mode while doing output rather than having to 2085 * wait until the kernel decides it needs input. 2086 */ 2087 2088 #define MAX_READAHEAD 20 2089 static int com_readahead[MAX_READAHEAD]; 2090 static int com_readaheadcount = 0; 2091 2092 int 2093 com_common_getc(dev_t dev, struct com_regs *regsp) 2094 { 2095 int s = splserial(); 2096 u_char stat, c; 2097 2098 /* got a character from reading things earlier */ 2099 if (com_readaheadcount > 0) { 2100 int i; 2101 2102 c = com_readahead[0]; 2103 for (i = 1; i < com_readaheadcount; i++) { 2104 com_readahead[i-1] = com_readahead[i]; 2105 } 2106 com_readaheadcount--; 2107 splx(s); 2108 return (c); 2109 } 2110 2111 /* block until a character becomes available */ 2112 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2113 ; 2114 2115 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2116 stat = CSR_READ_1(regsp, COM_REG_IIR); 2117 { 2118 int cn_trapped = 0; /* unused */ 2119 #ifdef DDB 2120 extern int db_active; 2121 if (!db_active) 2122 #endif 2123 cn_check_magic(dev, c, com_cnm_state); 2124 } 2125 splx(s); 2126 return (c); 2127 } 2128 2129 static void 2130 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2131 { 2132 int s = splserial(); 2133 int cin, stat, timo; 2134 2135 if (com_readaheadcount < MAX_READAHEAD 2136 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2137 int cn_trapped = 0; 2138 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2139 stat = CSR_READ_1(regsp, COM_REG_IIR); 2140 cn_check_magic(dev, cin, com_cnm_state); 2141 com_readahead[com_readaheadcount++] = cin; 2142 } 2143 2144 /* wait for any pending transmission to finish */ 2145 timo = 150000; 2146 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2147 continue; 2148 2149 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2150 COM_BARRIER(regsp, BR | BW); 2151 2152 splx(s); 2153 } 2154 2155 /* 2156 * Initialize UART for use as console or KGDB line. 2157 */ 2158 int 2159 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2160 tcflag_t cflag) 2161 { 2162 2163 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2164 ®sp->cr_ioh)) 2165 return (ENOMEM); /* ??? */ 2166 2167 if (type == COM_TYPE_OMAP) { 2168 /* disable before changing settings */ 2169 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2170 } 2171 2172 rate = comspeed(rate, frequency, type); 2173 if (type != COM_TYPE_AU1x00) { 2174 /* no EFR on alchemy */ 2175 if (type != COM_TYPE_16550_NOERS) { 2176 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2177 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2178 } 2179 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2180 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2181 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2182 } else { 2183 CSR_WRITE_1(regsp, COM_REG_DLBL, rate); 2184 } 2185 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2186 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2187 CSR_WRITE_1(regsp, COM_REG_FIFO, 2188 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2189 2190 if (type == COM_TYPE_OMAP) { 2191 /* setup the fifos. the FCR value is not used as long 2192 as SCR[6] and SCR[7] are 0, which they are at reset 2193 and we never touch the SCR register */ 2194 uint8_t rx_fifo_trig = 40; 2195 uint8_t tx_fifo_trig = 60; 2196 uint8_t rx_start = 8; 2197 uint8_t rx_halt = 60; 2198 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2199 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2200 2201 /* enable access to TCR & TLR */ 2202 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2203 2204 /* write tcr and tlr values */ 2205 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2206 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2207 2208 /* disable access to TCR & TLR */ 2209 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2210 2211 /* enable again, but mode is based on speed */ 2212 if (rate > 230400) { 2213 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2214 } else { 2215 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2216 } 2217 } 2218 2219 #ifdef COM_PXA2X0 2220 if (type == COM_TYPE_PXA2x0) 2221 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2222 else 2223 #endif 2224 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2225 2226 return (0); 2227 } 2228 2229 int 2230 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2231 tcflag_t cflag) 2232 { 2233 int res; 2234 2235 comcons_info.regs = *regsp; 2236 2237 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2238 if (res) 2239 return (res); 2240 2241 cn_tab = &comcons; 2242 cn_init_magic(&com_cnm_state); 2243 cn_set_magic("\047\001"); /* default magic is BREAK */ 2244 2245 comcons_info.frequency = frequency; 2246 comcons_info.type = type; 2247 comcons_info.rate = rate; 2248 comcons_info.cflag = cflag; 2249 2250 return (0); 2251 } 2252 2253 int 2254 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2255 int type, tcflag_t cflag) 2256 { 2257 struct com_regs regs; 2258 2259 memset(®s, 0, sizeof regs); 2260 regs.cr_iot = iot; 2261 regs.cr_iobase = iobase; 2262 regs.cr_nports = COM_NPORTS; 2263 #ifdef COM_REGMAP 2264 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2265 #endif 2266 2267 return comcnattach1(®s, rate, frequency, type, cflag); 2268 } 2269 2270 static int 2271 comcnreattach(void) 2272 { 2273 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2274 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2275 } 2276 2277 int 2278 comcngetc(dev_t dev) 2279 { 2280 2281 return (com_common_getc(dev, &comcons_info.regs)); 2282 } 2283 2284 /* 2285 * Console kernel output character routine. 2286 */ 2287 void 2288 comcnputc(dev_t dev, int c) 2289 { 2290 2291 com_common_putc(dev, &comcons_info.regs, c); 2292 } 2293 2294 void 2295 comcnpollc(dev_t dev, int on) 2296 { 2297 2298 } 2299 2300 #ifdef KGDB 2301 int 2302 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2303 tcflag_t cflag) 2304 { 2305 int res; 2306 2307 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2308 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2309 #if !defined(DDB) 2310 return (EBUSY); /* cannot share with console */ 2311 #else 2312 comkgdbregs = *regsp; 2313 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2314 #endif 2315 } else { 2316 comkgdbregs = *regsp; 2317 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2318 if (res) 2319 return (res); 2320 2321 /* 2322 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2323 * expects this to be initialized 2324 */ 2325 cn_init_magic(&com_cnm_state); 2326 cn_set_magic("\047\001"); 2327 } 2328 2329 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2330 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2331 2332 return (0); 2333 } 2334 2335 int 2336 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2337 int frequency, int type, tcflag_t cflag) 2338 { 2339 struct com_regs regs; 2340 2341 regs.cr_iot = iot; 2342 regs.cr_nports = COM_NPORTS; 2343 regs.cr_iobase = iobase; 2344 #ifdef COM_REGMAP 2345 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2346 #endif 2347 2348 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2349 } 2350 2351 /* ARGSUSED */ 2352 int 2353 com_kgdb_getc(void *arg) 2354 { 2355 2356 return (com_common_getc(NODEV, &comkgdbregs)); 2357 } 2358 2359 /* ARGSUSED */ 2360 void 2361 com_kgdb_putc(void *arg, int c) 2362 { 2363 2364 com_common_putc(NODEV, &comkgdbregs, c); 2365 } 2366 #endif /* KGDB */ 2367 2368 /* helper function to identify the com ports used by 2369 console or KGDB (and not yet autoconf attached) */ 2370 int 2371 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2372 { 2373 bus_space_handle_t help; 2374 2375 if (!comconsattached && 2376 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2377 iobase == comcons_info.regs.cr_iobase) 2378 help = comcons_info.regs.cr_ioh; 2379 #ifdef KGDB 2380 else if (!com_kgdb_attached && 2381 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2382 iobase == comkgdbregs.cr_iobase) 2383 help = comkgdbregs.cr_ioh; 2384 #endif 2385 else 2386 return (0); 2387 2388 if (ioh) 2389 *ioh = help; 2390 return (1); 2391 } 2392 2393 /* 2394 * this routine exists to serve as a shutdown hook for systems that 2395 * have firmware which doesn't interact properly with a com device in 2396 * FIFO mode. 2397 */ 2398 bool 2399 com_cleanup(device_t self, int how) 2400 { 2401 struct com_softc *sc = device_private(self); 2402 2403 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2404 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2405 2406 return true; 2407 } 2408 2409 bool 2410 com_suspend(device_t self, const pmf_qual_t *qual) 2411 { 2412 struct com_softc *sc = device_private(self); 2413 2414 #if 0 2415 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2416 cn_tab = &comcons_suspend; 2417 #endif 2418 2419 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2420 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2421 2422 return true; 2423 } 2424 2425 bool 2426 com_resume(device_t self, const pmf_qual_t *qual) 2427 { 2428 struct com_softc *sc = device_private(self); 2429 2430 mutex_spin_enter(&sc->sc_lock); 2431 com_loadchannelregs(sc); 2432 mutex_spin_exit(&sc->sc_lock); 2433 2434 return true; 2435 } 2436
Indexes created Mon Oct 20 11:09:49 GMT 2025