com.c revision 1.305
1 /* $NetBSD: com.c,v 1.305 2012/04/22 16:00:45 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.305 2012/04/22 16:00:45 christos Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 } while (/* CONSTCOND */ 0) 96 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/ioctl.h> 100 #include <sys/select.h> 101 #include <sys/poll.h> 102 #include <sys/tty.h> 103 #include <sys/proc.h> 104 #include <sys/conf.h> 105 #include <sys/file.h> 106 #include <sys/uio.h> 107 #include <sys/kernel.h> 108 #include <sys/syslog.h> 109 #include <sys/device.h> 110 #include <sys/malloc.h> 111 #include <sys/timepps.h> 112 #include <sys/vnode.h> 113 #include <sys/kauth.h> 114 #include <sys/intr.h> 115 #ifdef RND_COM 116 #include <sys/rnd.h> 117 #endif 118 119 120 #include <sys/bus.h> 121 122 #include <dev/ic/comreg.h> 123 #include <dev/ic/comvar.h> 124 #include <dev/ic/ns16550reg.h> 125 #include <dev/ic/st16650reg.h> 126 #ifdef COM_HAYESP 127 #include <dev/ic/hayespreg.h> 128 #endif 129 #define com_lcr com_cfcr 130 #include <dev/cons.h> 131 132 #ifdef COM_REGMAP 133 #define CSR_WRITE_1(r, o, v) \ 134 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 135 #define CSR_READ_1(r, o) \ 136 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 137 #define CSR_WRITE_2(r, o, v) \ 138 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 139 #define CSR_READ_2(r, o) \ 140 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 141 #define CSR_WRITE_MULTI(r, o, p, n) \ 142 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 143 #else 144 #define CSR_WRITE_1(r, o, v) \ 145 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 146 #define CSR_READ_1(r, o) \ 147 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 148 #define CSR_WRITE_2(r, o, v) \ 149 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 150 #define CSR_READ_2(r, o) \ 151 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 152 #define CSR_WRITE_MULTI(r, o, p, n) \ 153 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 154 #endif 155 156 157 static void com_enable_debugport(struct com_softc *); 158 159 void com_config(struct com_softc *); 160 void com_shutdown(struct com_softc *); 161 int comspeed(long, long, int); 162 static u_char cflag2lcr(tcflag_t); 163 int comparam(struct tty *, struct termios *); 164 void comstart(struct tty *); 165 int comhwiflow(struct tty *, int); 166 167 void com_loadchannelregs(struct com_softc *); 168 void com_hwiflow(struct com_softc *); 169 void com_break(struct com_softc *, int); 170 void com_modem(struct com_softc *, int); 171 void tiocm_to_com(struct com_softc *, u_long, int); 172 int com_to_tiocm(struct com_softc *); 173 void com_iflush(struct com_softc *); 174 175 int com_common_getc(dev_t, struct com_regs *); 176 static void com_common_putc(dev_t, struct com_regs *, int); 177 178 int cominit(struct com_regs *, int, int, int, tcflag_t); 179 180 static int comcnreattach(void); 181 182 int comcngetc(dev_t); 183 void comcnputc(dev_t, int); 184 void comcnpollc(dev_t, int); 185 186 #define integrate static inline 187 void comsoft(void *); 188 integrate void com_rxsoft(struct com_softc *, struct tty *); 189 integrate void com_txsoft(struct com_softc *, struct tty *); 190 integrate void com_stsoft(struct com_softc *, struct tty *); 191 integrate void com_schedrx(struct com_softc *); 192 void comdiag(void *); 193 194 extern struct cfdriver com_cd; 195 196 dev_type_open(comopen); 197 dev_type_close(comclose); 198 dev_type_read(comread); 199 dev_type_write(comwrite); 200 dev_type_ioctl(comioctl); 201 dev_type_stop(comstop); 202 dev_type_tty(comtty); 203 dev_type_poll(compoll); 204 205 static struct comcons_info comcons_info; 206 207 /* 208 * Following are all routines needed for COM to act as console 209 */ 210 static struct consdev comcons = { 211 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 212 NODEV, CN_NORMAL 213 }; 214 215 216 const struct cdevsw com_cdevsw = { 217 comopen, comclose, comread, comwrite, comioctl, 218 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 219 }; 220 221 /* 222 * Make this an option variable one can patch. 223 * But be warned: this must be a power of 2! 224 */ 225 u_int com_rbuf_size = COM_RING_SIZE; 226 227 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 228 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 229 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 230 231 static int comconsattached; 232 static struct cnm_state com_cnm_state; 233 234 #ifdef KGDB 235 #include <sys/kgdb.h> 236 237 static struct com_regs comkgdbregs; 238 static int com_kgdb_attached; 239 240 int com_kgdb_getc(void *); 241 void com_kgdb_putc(void *, int); 242 #endif /* KGDB */ 243 244 #ifdef COM_REGMAP 245 /* initializer for typical 16550-ish hardware */ 246 #define COM_REG_16550 { \ 247 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 248 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 249 250 const bus_size_t com_std_map[16] = COM_REG_16550; 251 #endif /* COM_REGMAP */ 252 253 #define COMUNIT_MASK 0x7ffff 254 #define COMDIALOUT_MASK 0x80000 255 256 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 257 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 258 259 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 260 device_is_active((sc)->sc_dev)) 261 262 #define BR BUS_SPACE_BARRIER_READ 263 #define BW BUS_SPACE_BARRIER_WRITE 264 #define COM_BARRIER(r, f) \ 265 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 266 267 /*ARGSUSED*/ 268 int 269 comspeed(long speed, long frequency, int type) 270 { 271 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 272 273 int x, err; 274 int divisor = 16; 275 276 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 277 divisor = 13; 278 } 279 280 #if 0 281 if (speed == 0) 282 return (0); 283 #endif 284 if (speed <= 0) 285 return (-1); 286 x = divrnd(frequency / divisor, speed); 287 if (x <= 0) 288 return (-1); 289 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 290 if (err < 0) 291 err = -err; 292 if (err > COM_TOLERANCE) 293 return (-1); 294 return (x); 295 296 #undef divrnd 297 } 298 299 #ifdef COM_DEBUG 300 int com_debug = 0; 301 302 void comstatus(struct com_softc *, const char *); 303 void 304 comstatus(struct com_softc *sc, const char *str) 305 { 306 struct tty *tp = sc->sc_tty; 307 308 aprint_normal_dev(sc->sc_dev, 309 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 310 str, 311 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 312 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 313 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 314 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 315 sc->sc_tx_stopped ? '+' : '-'); 316 317 aprint_normal_dev(sc->sc_dev, 318 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 319 str, 320 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 321 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 322 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 323 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 324 sc->sc_rx_flags); 325 } 326 #endif 327 328 int 329 com_probe_subr(struct com_regs *regs) 330 { 331 332 /* force access to id reg */ 333 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 334 CSR_WRITE_1(regs, COM_REG_IIR, 0); 335 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 336 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 337 return (0); 338 339 return (1); 340 } 341 342 int 343 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 344 { 345 struct com_regs regs; 346 347 regs.cr_iot = iot; 348 regs.cr_ioh = ioh; 349 #ifdef COM_REGMAP 350 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 351 #endif 352 353 return com_probe_subr(®s); 354 } 355 356 /* 357 * No locking in this routine; it is only called during attach, 358 * or with the port already locked. 359 */ 360 static void 361 com_enable_debugport(struct com_softc *sc) 362 { 363 364 /* Turn on line break interrupt, set carrier. */ 365 sc->sc_ier = IER_ERXRDY; 366 if (sc->sc_type == COM_TYPE_PXA2x0) 367 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 368 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 369 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 370 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 371 } 372 373 void 374 com_attach_subr(struct com_softc *sc) 375 { 376 struct com_regs *regsp = &sc->sc_regs; 377 struct tty *tp; 378 #ifdef COM_16650 379 u_int8_t lcr; 380 #endif 381 const char *fifo_msg = NULL; 382 383 aprint_naive("\n"); 384 385 callout_init(&sc->sc_diag_callout, 0); 386 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 387 388 /* Disable interrupts before configuring the device. */ 389 if (sc->sc_type == COM_TYPE_PXA2x0) 390 sc->sc_ier = IER_EUART; 391 else 392 sc->sc_ier = 0; 393 394 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 395 396 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 397 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 398 comconsattached = 1; 399 400 if (cn_tab == NULL && comcnreattach() != 0) { 401 printf("can't re-init serial console @%lx\n", 402 (u_long)comcons_info.regs.cr_iobase); 403 } 404 405 /* Make sure the console is always "hardwired". */ 406 delay(10000); /* wait for output to finish */ 407 SET(sc->sc_hwflags, COM_HW_CONSOLE); 408 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 409 } 410 411 /* Probe for FIFO */ 412 switch (sc->sc_type) { 413 case COM_TYPE_HAYESP: 414 goto fifodone; 415 416 case COM_TYPE_AU1x00: 417 sc->sc_fifolen = 16; 418 fifo_msg = "Au1X00 UART, working fifo"; 419 SET(sc->sc_hwflags, COM_HW_FIFO); 420 goto fifodelay; 421 422 case COM_TYPE_16550_NOERS: 423 sc->sc_fifolen = 16; 424 fifo_msg = "ns16650, no ERS, working fifo"; 425 SET(sc->sc_hwflags, COM_HW_FIFO); 426 goto fifodelay; 427 428 case COM_TYPE_OMAP: 429 sc->sc_fifolen = 64; 430 fifo_msg = "OMAP UART, working fifo"; 431 SET(sc->sc_hwflags, COM_HW_FIFO); 432 goto fifodelay; 433 } 434 435 sc->sc_fifolen = 1; 436 /* look for a NS 16550AF UART with FIFOs */ 437 CSR_WRITE_1(regsp, COM_REG_FIFO, 438 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 439 delay(100); 440 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 441 == IIR_FIFO_MASK) 442 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 443 == FIFO_TRIGGER_14) { 444 SET(sc->sc_hwflags, COM_HW_FIFO); 445 446 #ifdef COM_16650 447 /* 448 * IIR changes into the EFR if LCR is set to LCR_EERS 449 * on 16650s. We also know IIR != 0 at this point. 450 * Write 0 into the EFR, and read it. If the result 451 * is 0, we have a 16650. 452 * 453 * Older 16650s were broken; the test to detect them 454 * is taken from the Linux driver. Apparently 455 * setting DLAB enable gives access to the EFR on 456 * these chips. 457 */ 458 lcr = CSR_READ_1(regsp, COM_REG_LCR); 459 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 460 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 461 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 462 CSR_WRITE_1(regsp, COM_REG_LCR, 463 lcr | LCR_DLAB); 464 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 465 CLR(sc->sc_hwflags, COM_HW_FIFO); 466 sc->sc_fifolen = 0; 467 } else { 468 SET(sc->sc_hwflags, COM_HW_FLOW); 469 sc->sc_fifolen = 32; 470 } 471 } else 472 #endif 473 sc->sc_fifolen = 16; 474 475 #ifdef COM_16650 476 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 477 if (sc->sc_fifolen == 0) 478 fifo_msg = "st16650, broken fifo"; 479 else if (sc->sc_fifolen == 32) 480 fifo_msg = "st16650a, working fifo"; 481 else 482 #endif 483 fifo_msg = "ns16550a, working fifo"; 484 } else 485 fifo_msg = "ns16550, broken fifo"; 486 else 487 fifo_msg = "ns8250 or ns16450, no fifo"; 488 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 489 fifodelay: 490 /* 491 * Some chips will clear down both Tx and Rx FIFOs when zero is 492 * written to com_fifo. If this chip is the console, writing zero 493 * results in some of the chip/FIFO description being lost, so delay 494 * printing it until now. 495 */ 496 delay(10); 497 aprint_normal(": %s\n", fifo_msg); 498 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 499 sc->sc_fifolen = 1; 500 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 501 } 502 503 fifodone: 504 505 tp = tty_alloc(); 506 tp->t_oproc = comstart; 507 tp->t_param = comparam; 508 tp->t_hwiflow = comhwiflow; 509 510 sc->sc_tty = tp; 511 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 512 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 513 sc->sc_rbavail = com_rbuf_size; 514 if (sc->sc_rbuf == NULL) { 515 aprint_error_dev(sc->sc_dev, 516 "unable to allocate ring buffer\n"); 517 return; 518 } 519 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 520 521 tty_attach(tp); 522 523 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 524 SET(sc->sc_mcr, MCR_IENABLE); 525 526 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 527 int maj; 528 529 /* locate the major number */ 530 maj = cdevsw_lookup_major(&com_cdevsw); 531 532 tp->t_dev = cn_tab->cn_dev = makedev(maj, 533 device_unit(sc->sc_dev)); 534 535 aprint_normal_dev(sc->sc_dev, "console\n"); 536 } 537 538 #ifdef KGDB 539 /* 540 * Allow kgdb to "take over" this port. If this is 541 * not the console and is the kgdb device, it has 542 * exclusive use. If it's the console _and_ the 543 * kgdb device, it doesn't. 544 */ 545 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 546 regsp->cr_iobase == comkgdbregs.cr_iobase) { 547 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 548 com_kgdb_attached = 1; 549 550 SET(sc->sc_hwflags, COM_HW_KGDB); 551 } 552 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 553 } 554 #endif 555 556 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 557 558 #ifdef RND_COM 559 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 560 RND_TYPE_TTY, 0); 561 #endif 562 563 /* if there are no enable/disable functions, assume the device 564 is always enabled */ 565 if (!sc->enable) 566 sc->enabled = 1; 567 568 com_config(sc); 569 570 SET(sc->sc_hwflags, COM_HW_DEV_OK); 571 } 572 573 void 574 com_config(struct com_softc *sc) 575 { 576 struct com_regs *regsp = &sc->sc_regs; 577 578 /* Disable interrupts before configuring the device. */ 579 if (sc->sc_type == COM_TYPE_PXA2x0) 580 sc->sc_ier = IER_EUART; 581 else 582 sc->sc_ier = 0; 583 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 584 (void) CSR_READ_1(regsp, COM_REG_IIR); 585 586 #ifdef COM_HAYESP 587 /* Look for a Hayes ESP board. */ 588 if (sc->sc_type == COM_TYPE_HAYESP) { 589 590 /* Set 16550 compatibility mode */ 591 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 592 HAYESP_SETMODE); 593 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 594 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 595 HAYESP_MODE_SCALE); 596 597 /* Set RTS/CTS flow control */ 598 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 599 HAYESP_SETFLOWTYPE); 600 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 601 HAYESP_FLOW_RTS); 602 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 603 HAYESP_FLOW_CTS); 604 605 /* Set flow control levels */ 606 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 607 HAYESP_SETRXFLOW); 608 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 609 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 610 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 611 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 612 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 613 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 614 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 615 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 616 } 617 #endif 618 619 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 620 com_enable_debugport(sc); 621 } 622 623 #if 0 624 static int 625 comcngetc_detached(dev_t dev) 626 { 627 return 0; 628 } 629 630 static void 631 comcnputc_detached(dev_t dev, int c) 632 { 633 } 634 #endif 635 636 int 637 com_detach(device_t self, int flags) 638 { 639 struct com_softc *sc = device_private(self); 640 int maj, mn; 641 642 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 643 return EBUSY; 644 645 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 646 (flags & DETACH_SHUTDOWN) != 0) 647 return EBUSY; 648 649 if (sc->disable != NULL && sc->enabled != 0) { 650 (*sc->disable)(sc); 651 sc->enabled = 0; 652 } 653 654 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 655 comconsattached = 0; 656 cn_tab = NULL; 657 } 658 659 /* locate the major number */ 660 maj = cdevsw_lookup_major(&com_cdevsw); 661 662 /* Nuke the vnodes for any open instances. */ 663 mn = device_unit(self); 664 vdevgone(maj, mn, mn, VCHR); 665 666 mn |= COMDIALOUT_MASK; 667 vdevgone(maj, mn, mn, VCHR); 668 669 if (sc->sc_rbuf == NULL) { 670 /* 671 * Ring buffer allocation failed in the com_attach_subr, 672 * only the tty is allocated, and nothing else. 673 */ 674 tty_free(sc->sc_tty); 675 return 0; 676 } 677 678 /* Free the receive buffer. */ 679 free(sc->sc_rbuf, M_DEVBUF); 680 681 /* Detach and free the tty. */ 682 tty_detach(sc->sc_tty); 683 tty_free(sc->sc_tty); 684 685 /* Unhook the soft interrupt handler. */ 686 softint_disestablish(sc->sc_si); 687 688 #ifdef RND_COM 689 /* Unhook the entropy source. */ 690 rnd_detach_source(&sc->rnd_source); 691 #endif 692 callout_destroy(&sc->sc_diag_callout); 693 694 /* Destroy the lock. */ 695 mutex_destroy(&sc->sc_lock); 696 697 return (0); 698 } 699 700 void 701 com_shutdown(struct com_softc *sc) 702 { 703 struct tty *tp = sc->sc_tty; 704 705 mutex_spin_enter(&sc->sc_lock); 706 707 /* If we were asserting flow control, then deassert it. */ 708 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 709 com_hwiflow(sc); 710 711 /* Clear any break condition set with TIOCSBRK. */ 712 com_break(sc, 0); 713 714 /* 715 * Hang up if necessary. Wait a bit, so the other side has time to 716 * notice even if we immediately open the port again. 717 * Avoid tsleeping above splhigh(). 718 */ 719 if (ISSET(tp->t_cflag, HUPCL)) { 720 com_modem(sc, 0); 721 mutex_spin_exit(&sc->sc_lock); 722 /* XXX will only timeout */ 723 (void) kpause(ttclos, false, hz, NULL); 724 mutex_spin_enter(&sc->sc_lock); 725 } 726 727 /* Turn off interrupts. */ 728 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 729 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 730 if (sc->sc_type == COM_TYPE_PXA2x0) 731 sc->sc_ier |= IER_ERXTOUT; 732 } else 733 sc->sc_ier = 0; 734 735 if (sc->sc_type == COM_TYPE_PXA2x0) 736 sc->sc_ier |= IER_EUART; 737 738 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 739 740 mutex_spin_exit(&sc->sc_lock); 741 742 if (sc->disable) { 743 #ifdef DIAGNOSTIC 744 if (!sc->enabled) 745 panic("com_shutdown: not enabled?"); 746 #endif 747 (*sc->disable)(sc); 748 sc->enabled = 0; 749 } 750 } 751 752 int 753 comopen(dev_t dev, int flag, int mode, struct lwp *l) 754 { 755 struct com_softc *sc; 756 struct tty *tp; 757 int s; 758 int error; 759 760 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 761 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 762 sc->sc_rbuf == NULL) 763 return (ENXIO); 764 765 if (!device_is_active(sc->sc_dev)) 766 return (ENXIO); 767 768 #ifdef KGDB 769 /* 770 * If this is the kgdb port, no other use is permitted. 771 */ 772 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 773 return (EBUSY); 774 #endif 775 776 tp = sc->sc_tty; 777 778 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 779 return (EBUSY); 780 781 s = spltty(); 782 783 /* 784 * Do the following iff this is a first open. 785 */ 786 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 787 struct termios t; 788 789 tp->t_dev = dev; 790 791 792 if (sc->enable) { 793 if ((*sc->enable)(sc)) { 794 splx(s); 795 aprint_error_dev(sc->sc_dev, 796 "device enable failed\n"); 797 return (EIO); 798 } 799 mutex_spin_enter(&sc->sc_lock); 800 sc->enabled = 1; 801 com_config(sc); 802 } else { 803 mutex_spin_enter(&sc->sc_lock); 804 } 805 806 /* Turn on interrupts. */ 807 sc->sc_ier = IER_ERXRDY | IER_ERLS; 808 if (!ISSET(tp->t_cflag, CLOCAL)) 809 sc->sc_ier |= IER_EMSC; 810 811 if (sc->sc_type == COM_TYPE_PXA2x0) 812 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 813 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 814 815 /* Fetch the current modem control status, needed later. */ 816 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 817 818 /* Clear PPS capture state on first open. */ 819 mutex_spin_enter(&timecounter_lock); 820 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 821 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 822 pps_init(&sc->sc_pps_state); 823 mutex_spin_exit(&timecounter_lock); 824 825 mutex_spin_exit(&sc->sc_lock); 826 827 /* 828 * Initialize the termios status to the defaults. Add in the 829 * sticky bits from TIOCSFLAGS. 830 */ 831 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 832 t.c_ospeed = comcons_info.rate; 833 t.c_cflag = comcons_info.cflag; 834 } else { 835 t.c_ospeed = TTYDEF_SPEED; 836 t.c_cflag = TTYDEF_CFLAG; 837 } 838 t.c_ispeed = t.c_ospeed; 839 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 840 SET(t.c_cflag, CLOCAL); 841 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 842 SET(t.c_cflag, CRTSCTS); 843 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 844 SET(t.c_cflag, MDMBUF); 845 /* Make sure comparam() will do something. */ 846 tp->t_ospeed = 0; 847 (void) comparam(tp, &t); 848 tp->t_iflag = TTYDEF_IFLAG; 849 tp->t_oflag = TTYDEF_OFLAG; 850 tp->t_lflag = TTYDEF_LFLAG; 851 ttychars(tp); 852 ttsetwater(tp); 853 854 mutex_spin_enter(&sc->sc_lock); 855 856 /* 857 * Turn on DTR. We must always do this, even if carrier is not 858 * present, because otherwise we'd have to use TIOCSDTR 859 * immediately after setting CLOCAL, which applications do not 860 * expect. We always assert DTR while the device is open 861 * unless explicitly requested to deassert it. 862 */ 863 com_modem(sc, 1); 864 865 /* Clear the input ring, and unblock. */ 866 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 867 sc->sc_rbavail = com_rbuf_size; 868 com_iflush(sc); 869 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 870 com_hwiflow(sc); 871 872 #ifdef COM_DEBUG 873 if (com_debug) 874 comstatus(sc, "comopen "); 875 #endif 876 877 mutex_spin_exit(&sc->sc_lock); 878 } 879 880 splx(s); 881 882 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 883 if (error) 884 goto bad; 885 886 error = (*tp->t_linesw->l_open)(dev, tp); 887 if (error) 888 goto bad; 889 890 return (0); 891 892 bad: 893 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 894 /* 895 * We failed to open the device, and nobody else had it opened. 896 * Clean up the state as appropriate. 897 */ 898 com_shutdown(sc); 899 } 900 901 return (error); 902 } 903 904 int 905 comclose(dev_t dev, int flag, int mode, struct lwp *l) 906 { 907 struct com_softc *sc = 908 device_lookup_private(&com_cd, COMUNIT(dev)); 909 struct tty *tp = sc->sc_tty; 910 911 /* XXX This is for cons.c. */ 912 if (!ISSET(tp->t_state, TS_ISOPEN)) 913 return (0); 914 915 (*tp->t_linesw->l_close)(tp, flag); 916 ttyclose(tp); 917 918 if (COM_ISALIVE(sc) == 0) 919 return (0); 920 921 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 922 /* 923 * Although we got a last close, the device may still be in 924 * use; e.g. if this was the dialout node, and there are still 925 * processes waiting for carrier on the non-dialout node. 926 */ 927 com_shutdown(sc); 928 } 929 930 return (0); 931 } 932 933 int 934 comread(dev_t dev, struct uio *uio, int flag) 935 { 936 struct com_softc *sc = 937 device_lookup_private(&com_cd, COMUNIT(dev)); 938 struct tty *tp = sc->sc_tty; 939 940 if (COM_ISALIVE(sc) == 0) 941 return (EIO); 942 943 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 944 } 945 946 int 947 comwrite(dev_t dev, struct uio *uio, int flag) 948 { 949 struct com_softc *sc = 950 device_lookup_private(&com_cd, COMUNIT(dev)); 951 struct tty *tp = sc->sc_tty; 952 953 if (COM_ISALIVE(sc) == 0) 954 return (EIO); 955 956 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 957 } 958 959 int 960 compoll(dev_t dev, int events, struct lwp *l) 961 { 962 struct com_softc *sc = 963 device_lookup_private(&com_cd, COMUNIT(dev)); 964 struct tty *tp = sc->sc_tty; 965 966 if (COM_ISALIVE(sc) == 0) 967 return (POLLHUP); 968 969 return ((*tp->t_linesw->l_poll)(tp, events, l)); 970 } 971 972 struct tty * 973 comtty(dev_t dev) 974 { 975 struct com_softc *sc = 976 device_lookup_private(&com_cd, COMUNIT(dev)); 977 struct tty *tp = sc->sc_tty; 978 979 return (tp); 980 } 981 982 int 983 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 984 { 985 struct com_softc *sc; 986 struct tty *tp; 987 int error; 988 989 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 990 if (sc == NULL) 991 return ENXIO; 992 if (COM_ISALIVE(sc) == 0) 993 return (EIO); 994 995 tp = sc->sc_tty; 996 997 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 998 if (error != EPASSTHROUGH) 999 return (error); 1000 1001 error = ttioctl(tp, cmd, data, flag, l); 1002 if (error != EPASSTHROUGH) 1003 return (error); 1004 1005 error = 0; 1006 switch (cmd) { 1007 case TIOCSFLAGS: 1008 error = kauth_authorize_device_tty(l->l_cred, 1009 KAUTH_DEVICE_TTY_PRIVSET, tp); 1010 break; 1011 default: 1012 /* nothing */ 1013 break; 1014 } 1015 if (error) { 1016 return error; 1017 } 1018 1019 mutex_spin_enter(&sc->sc_lock); 1020 1021 switch (cmd) { 1022 case TIOCSBRK: 1023 com_break(sc, 1); 1024 break; 1025 1026 case TIOCCBRK: 1027 com_break(sc, 0); 1028 break; 1029 1030 case TIOCSDTR: 1031 com_modem(sc, 1); 1032 break; 1033 1034 case TIOCCDTR: 1035 com_modem(sc, 0); 1036 break; 1037 1038 case TIOCGFLAGS: 1039 *(int *)data = sc->sc_swflags; 1040 break; 1041 1042 case TIOCSFLAGS: 1043 sc->sc_swflags = *(int *)data; 1044 break; 1045 1046 case TIOCMSET: 1047 case TIOCMBIS: 1048 case TIOCMBIC: 1049 tiocm_to_com(sc, cmd, *(int *)data); 1050 break; 1051 1052 case TIOCMGET: 1053 *(int *)data = com_to_tiocm(sc); 1054 break; 1055 1056 case PPS_IOC_CREATE: 1057 case PPS_IOC_DESTROY: 1058 case PPS_IOC_GETPARAMS: 1059 case PPS_IOC_SETPARAMS: 1060 case PPS_IOC_GETCAP: 1061 case PPS_IOC_FETCH: 1062 #ifdef PPS_SYNC 1063 case PPS_IOC_KCBIND: 1064 #endif 1065 mutex_spin_enter(&timecounter_lock); 1066 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1067 mutex_spin_exit(&timecounter_lock); 1068 break; 1069 1070 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1071 mutex_spin_enter(&timecounter_lock); 1072 #ifndef PPS_TRAILING_EDGE 1073 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1074 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1075 #else 1076 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1077 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1078 #endif 1079 mutex_spin_exit(&timecounter_lock); 1080 break; 1081 1082 default: 1083 error = EPASSTHROUGH; 1084 break; 1085 } 1086 1087 mutex_spin_exit(&sc->sc_lock); 1088 1089 #ifdef COM_DEBUG 1090 if (com_debug) 1091 comstatus(sc, "comioctl "); 1092 #endif 1093 1094 return (error); 1095 } 1096 1097 integrate void 1098 com_schedrx(struct com_softc *sc) 1099 { 1100 1101 sc->sc_rx_ready = 1; 1102 1103 /* Wake up the poller. */ 1104 softint_schedule(sc->sc_si); 1105 } 1106 1107 void 1108 com_break(struct com_softc *sc, int onoff) 1109 { 1110 1111 if (onoff) 1112 SET(sc->sc_lcr, LCR_SBREAK); 1113 else 1114 CLR(sc->sc_lcr, LCR_SBREAK); 1115 1116 if (!sc->sc_heldchange) { 1117 if (sc->sc_tx_busy) { 1118 sc->sc_heldtbc = sc->sc_tbc; 1119 sc->sc_tbc = 0; 1120 sc->sc_heldchange = 1; 1121 } else 1122 com_loadchannelregs(sc); 1123 } 1124 } 1125 1126 void 1127 com_modem(struct com_softc *sc, int onoff) 1128 { 1129 1130 if (sc->sc_mcr_dtr == 0) 1131 return; 1132 1133 if (onoff) 1134 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1135 else 1136 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1137 1138 if (!sc->sc_heldchange) { 1139 if (sc->sc_tx_busy) { 1140 sc->sc_heldtbc = sc->sc_tbc; 1141 sc->sc_tbc = 0; 1142 sc->sc_heldchange = 1; 1143 } else 1144 com_loadchannelregs(sc); 1145 } 1146 } 1147 1148 void 1149 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1150 { 1151 u_char combits; 1152 1153 combits = 0; 1154 if (ISSET(ttybits, TIOCM_DTR)) 1155 SET(combits, MCR_DTR); 1156 if (ISSET(ttybits, TIOCM_RTS)) 1157 SET(combits, MCR_RTS); 1158 1159 switch (how) { 1160 case TIOCMBIC: 1161 CLR(sc->sc_mcr, combits); 1162 break; 1163 1164 case TIOCMBIS: 1165 SET(sc->sc_mcr, combits); 1166 break; 1167 1168 case TIOCMSET: 1169 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1170 SET(sc->sc_mcr, combits); 1171 break; 1172 } 1173 1174 if (!sc->sc_heldchange) { 1175 if (sc->sc_tx_busy) { 1176 sc->sc_heldtbc = sc->sc_tbc; 1177 sc->sc_tbc = 0; 1178 sc->sc_heldchange = 1; 1179 } else 1180 com_loadchannelregs(sc); 1181 } 1182 } 1183 1184 int 1185 com_to_tiocm(struct com_softc *sc) 1186 { 1187 u_char combits; 1188 int ttybits = 0; 1189 1190 combits = sc->sc_mcr; 1191 if (ISSET(combits, MCR_DTR)) 1192 SET(ttybits, TIOCM_DTR); 1193 if (ISSET(combits, MCR_RTS)) 1194 SET(ttybits, TIOCM_RTS); 1195 1196 combits = sc->sc_msr; 1197 if (ISSET(combits, MSR_DCD)) 1198 SET(ttybits, TIOCM_CD); 1199 if (ISSET(combits, MSR_CTS)) 1200 SET(ttybits, TIOCM_CTS); 1201 if (ISSET(combits, MSR_DSR)) 1202 SET(ttybits, TIOCM_DSR); 1203 if (ISSET(combits, MSR_RI | MSR_TERI)) 1204 SET(ttybits, TIOCM_RI); 1205 1206 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1207 SET(ttybits, TIOCM_LE); 1208 1209 return (ttybits); 1210 } 1211 1212 static u_char 1213 cflag2lcr(tcflag_t cflag) 1214 { 1215 u_char lcr = 0; 1216 1217 switch (ISSET(cflag, CSIZE)) { 1218 case CS5: 1219 SET(lcr, LCR_5BITS); 1220 break; 1221 case CS6: 1222 SET(lcr, LCR_6BITS); 1223 break; 1224 case CS7: 1225 SET(lcr, LCR_7BITS); 1226 break; 1227 case CS8: 1228 SET(lcr, LCR_8BITS); 1229 break; 1230 } 1231 if (ISSET(cflag, PARENB)) { 1232 SET(lcr, LCR_PENAB); 1233 if (!ISSET(cflag, PARODD)) 1234 SET(lcr, LCR_PEVEN); 1235 } 1236 if (ISSET(cflag, CSTOPB)) 1237 SET(lcr, LCR_STOPB); 1238 1239 return (lcr); 1240 } 1241 1242 int 1243 comparam(struct tty *tp, struct termios *t) 1244 { 1245 struct com_softc *sc = 1246 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1247 int ospeed; 1248 u_char lcr; 1249 1250 if (COM_ISALIVE(sc) == 0) 1251 return (EIO); 1252 1253 #ifdef COM_HAYESP 1254 if (sc->sc_type == COM_TYPE_HAYESP) { 1255 int prescaler, speed; 1256 1257 /* 1258 * Calculate UART clock prescaler. It should be in 1259 * range of 0 .. 3. 1260 */ 1261 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1262 prescaler++, speed /= 2) 1263 if ((ospeed = comspeed(speed, sc->sc_frequency, 1264 sc->sc_type)) > 0) 1265 break; 1266 1267 if (prescaler == 4) 1268 return (EINVAL); 1269 sc->sc_prescaler = prescaler; 1270 } else 1271 #endif 1272 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1273 1274 /* Check requested parameters. */ 1275 if (ospeed < 0) 1276 return (EINVAL); 1277 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1278 return (EINVAL); 1279 1280 /* 1281 * For the console, always force CLOCAL and !HUPCL, so that the port 1282 * is always active. 1283 */ 1284 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1285 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1286 SET(t->c_cflag, CLOCAL); 1287 CLR(t->c_cflag, HUPCL); 1288 } 1289 1290 /* 1291 * If there were no changes, don't do anything. This avoids dropping 1292 * input and improves performance when all we did was frob things like 1293 * VMIN and VTIME. 1294 */ 1295 if (tp->t_ospeed == t->c_ospeed && 1296 tp->t_cflag == t->c_cflag) 1297 return (0); 1298 1299 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1300 1301 mutex_spin_enter(&sc->sc_lock); 1302 1303 sc->sc_lcr = lcr; 1304 1305 /* 1306 * If we're not in a mode that assumes a connection is present, then 1307 * ignore carrier changes. 1308 */ 1309 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1310 sc->sc_msr_dcd = 0; 1311 else 1312 sc->sc_msr_dcd = MSR_DCD; 1313 /* 1314 * Set the flow control pins depending on the current flow control 1315 * mode. 1316 */ 1317 if (ISSET(t->c_cflag, CRTSCTS)) { 1318 sc->sc_mcr_dtr = MCR_DTR; 1319 sc->sc_mcr_rts = MCR_RTS; 1320 sc->sc_msr_cts = MSR_CTS; 1321 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1322 } else if (ISSET(t->c_cflag, MDMBUF)) { 1323 /* 1324 * For DTR/DCD flow control, make sure we don't toggle DTR for 1325 * carrier detection. 1326 */ 1327 sc->sc_mcr_dtr = 0; 1328 sc->sc_mcr_rts = MCR_DTR; 1329 sc->sc_msr_cts = MSR_DCD; 1330 sc->sc_efr = 0; 1331 } else { 1332 /* 1333 * If no flow control, then always set RTS. This will make 1334 * the other side happy if it mistakenly thinks we're doing 1335 * RTS/CTS flow control. 1336 */ 1337 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1338 sc->sc_mcr_rts = 0; 1339 sc->sc_msr_cts = 0; 1340 sc->sc_efr = 0; 1341 if (ISSET(sc->sc_mcr, MCR_DTR)) 1342 SET(sc->sc_mcr, MCR_RTS); 1343 else 1344 CLR(sc->sc_mcr, MCR_RTS); 1345 } 1346 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1347 1348 #if 0 1349 if (ospeed == 0) 1350 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1351 else 1352 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1353 #endif 1354 1355 sc->sc_dlbl = ospeed; 1356 sc->sc_dlbh = ospeed >> 8; 1357 1358 /* 1359 * Set the FIFO threshold based on the receive speed. 1360 * 1361 * * If it's a low speed, it's probably a mouse or some other 1362 * interactive device, so set the threshold low. 1363 * * If it's a high speed, trim the trigger level down to prevent 1364 * overflows. 1365 * * Otherwise set it a bit higher. 1366 */ 1367 if (sc->sc_type == COM_TYPE_HAYESP) 1368 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1369 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1370 if (t->c_ospeed <= 1200) 1371 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1372 else if (t->c_ospeed <= 38400) 1373 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1374 else 1375 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1376 } else 1377 sc->sc_fifo = 0; 1378 1379 /* And copy to tty. */ 1380 tp->t_ispeed = t->c_ospeed; 1381 tp->t_ospeed = t->c_ospeed; 1382 tp->t_cflag = t->c_cflag; 1383 1384 if (!sc->sc_heldchange) { 1385 if (sc->sc_tx_busy) { 1386 sc->sc_heldtbc = sc->sc_tbc; 1387 sc->sc_tbc = 0; 1388 sc->sc_heldchange = 1; 1389 } else 1390 com_loadchannelregs(sc); 1391 } 1392 1393 if (!ISSET(t->c_cflag, CHWFLOW)) { 1394 /* Disable the high water mark. */ 1395 sc->sc_r_hiwat = 0; 1396 sc->sc_r_lowat = 0; 1397 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1398 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1399 com_schedrx(sc); 1400 } 1401 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1402 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1403 com_hwiflow(sc); 1404 } 1405 } else { 1406 sc->sc_r_hiwat = com_rbuf_hiwat; 1407 sc->sc_r_lowat = com_rbuf_lowat; 1408 } 1409 1410 mutex_spin_exit(&sc->sc_lock); 1411 1412 /* 1413 * Update the tty layer's idea of the carrier bit, in case we changed 1414 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1415 * explicit request. 1416 */ 1417 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1418 1419 #ifdef COM_DEBUG 1420 if (com_debug) 1421 comstatus(sc, "comparam "); 1422 #endif 1423 1424 if (!ISSET(t->c_cflag, CHWFLOW)) { 1425 if (sc->sc_tx_stopped) { 1426 sc->sc_tx_stopped = 0; 1427 comstart(tp); 1428 } 1429 } 1430 1431 return (0); 1432 } 1433 1434 void 1435 com_iflush(struct com_softc *sc) 1436 { 1437 struct com_regs *regsp = &sc->sc_regs; 1438 #ifdef DIAGNOSTIC 1439 int reg; 1440 #endif 1441 int timo; 1442 1443 #ifdef DIAGNOSTIC 1444 reg = 0xffff; 1445 #endif 1446 timo = 50000; 1447 /* flush any pending I/O */ 1448 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1449 && --timo) 1450 #ifdef DIAGNOSTIC 1451 reg = 1452 #else 1453 (void) 1454 #endif 1455 CSR_READ_1(regsp, COM_REG_RXDATA); 1456 #ifdef DIAGNOSTIC 1457 if (!timo) 1458 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1459 #endif 1460 } 1461 1462 void 1463 com_loadchannelregs(struct com_softc *sc) 1464 { 1465 struct com_regs *regsp = &sc->sc_regs; 1466 1467 /* XXXXX necessary? */ 1468 com_iflush(sc); 1469 1470 if (sc->sc_type == COM_TYPE_PXA2x0) 1471 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1472 else 1473 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1474 1475 if (sc->sc_type == COM_TYPE_OMAP) { 1476 /* disable before changing settings */ 1477 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1478 } 1479 1480 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1481 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1482 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1483 /* no EFR on alchemy */ 1484 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1485 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1486 } 1487 if (sc->sc_type == COM_TYPE_AU1x00) { 1488 /* alchemy has single separate 16-bit clock divisor register */ 1489 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1490 (sc->sc_dlbh << 8)); 1491 } else { 1492 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1493 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1494 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1495 } 1496 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1497 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1498 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1499 #ifdef COM_HAYESP 1500 if (sc->sc_type == COM_TYPE_HAYESP) { 1501 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1502 HAYESP_SETPRESCALER); 1503 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1504 sc->sc_prescaler); 1505 } 1506 #endif 1507 if (sc->sc_type == COM_TYPE_OMAP) { 1508 /* setup the fifos. the FCR value is not used as long 1509 as SCR[6] and SCR[7] are 0, which they are at reset 1510 and we never touch the SCR register */ 1511 uint8_t rx_fifo_trig = 40; 1512 uint8_t tx_fifo_trig = 60; 1513 uint8_t rx_start = 8; 1514 uint8_t rx_halt = 60; 1515 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1516 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1517 1518 /* enable access to TCR & TLR */ 1519 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1520 1521 /* write tcr and tlr values */ 1522 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1523 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1524 1525 /* disable access to TCR & TLR */ 1526 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1527 1528 /* enable again, but mode is based on speed */ 1529 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1530 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1531 } else { 1532 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1533 } 1534 } 1535 1536 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1537 } 1538 1539 int 1540 comhwiflow(struct tty *tp, int block) 1541 { 1542 struct com_softc *sc = 1543 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1544 1545 if (COM_ISALIVE(sc) == 0) 1546 return (0); 1547 1548 if (sc->sc_mcr_rts == 0) 1549 return (0); 1550 1551 mutex_spin_enter(&sc->sc_lock); 1552 1553 if (block) { 1554 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1555 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1556 com_hwiflow(sc); 1557 } 1558 } else { 1559 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1560 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1561 com_schedrx(sc); 1562 } 1563 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1564 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1565 com_hwiflow(sc); 1566 } 1567 } 1568 1569 mutex_spin_exit(&sc->sc_lock); 1570 return (1); 1571 } 1572 1573 /* 1574 * (un)block input via hw flowcontrol 1575 */ 1576 void 1577 com_hwiflow(struct com_softc *sc) 1578 { 1579 struct com_regs *regsp= &sc->sc_regs; 1580 1581 if (sc->sc_mcr_rts == 0) 1582 return; 1583 1584 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1585 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1586 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1587 } else { 1588 SET(sc->sc_mcr, sc->sc_mcr_rts); 1589 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1590 } 1591 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1592 } 1593 1594 1595 void 1596 comstart(struct tty *tp) 1597 { 1598 struct com_softc *sc = 1599 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1600 struct com_regs *regsp = &sc->sc_regs; 1601 int s; 1602 1603 if (COM_ISALIVE(sc) == 0) 1604 return; 1605 1606 s = spltty(); 1607 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1608 goto out; 1609 if (sc->sc_tx_stopped) 1610 goto out; 1611 if (!ttypull(tp)) 1612 goto out; 1613 1614 /* Grab the first contiguous region of buffer space. */ 1615 { 1616 u_char *tba; 1617 int tbc; 1618 1619 tba = tp->t_outq.c_cf; 1620 tbc = ndqb(&tp->t_outq, 0); 1621 1622 mutex_spin_enter(&sc->sc_lock); 1623 1624 sc->sc_tba = tba; 1625 sc->sc_tbc = tbc; 1626 } 1627 1628 SET(tp->t_state, TS_BUSY); 1629 sc->sc_tx_busy = 1; 1630 1631 /* Enable transmit completion interrupts if necessary. */ 1632 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1633 SET(sc->sc_ier, IER_ETXRDY); 1634 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1635 } 1636 1637 /* Output the first chunk of the contiguous buffer. */ 1638 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1639 u_int n; 1640 1641 n = sc->sc_tbc; 1642 if (n > sc->sc_fifolen) 1643 n = sc->sc_fifolen; 1644 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1645 sc->sc_tbc -= n; 1646 sc->sc_tba += n; 1647 } 1648 1649 mutex_spin_exit(&sc->sc_lock); 1650 out: 1651 splx(s); 1652 return; 1653 } 1654 1655 /* 1656 * Stop output on a line. 1657 */ 1658 void 1659 comstop(struct tty *tp, int flag) 1660 { 1661 struct com_softc *sc = 1662 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1663 1664 mutex_spin_enter(&sc->sc_lock); 1665 if (ISSET(tp->t_state, TS_BUSY)) { 1666 /* Stop transmitting at the next chunk. */ 1667 sc->sc_tbc = 0; 1668 sc->sc_heldtbc = 0; 1669 if (!ISSET(tp->t_state, TS_TTSTOP)) 1670 SET(tp->t_state, TS_FLUSH); 1671 } 1672 mutex_spin_exit(&sc->sc_lock); 1673 } 1674 1675 void 1676 comdiag(void *arg) 1677 { 1678 struct com_softc *sc = arg; 1679 int overflows, floods; 1680 1681 mutex_spin_enter(&sc->sc_lock); 1682 overflows = sc->sc_overflows; 1683 sc->sc_overflows = 0; 1684 floods = sc->sc_floods; 1685 sc->sc_floods = 0; 1686 sc->sc_errors = 0; 1687 mutex_spin_exit(&sc->sc_lock); 1688 1689 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1690 device_xname(sc->sc_dev), 1691 overflows, overflows == 1 ? "" : "s", 1692 floods, floods == 1 ? "" : "s"); 1693 } 1694 1695 integrate void 1696 com_rxsoft(struct com_softc *sc, struct tty *tp) 1697 { 1698 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1699 u_char *get, *end; 1700 u_int cc, scc; 1701 u_char lsr; 1702 int code; 1703 1704 end = sc->sc_ebuf; 1705 get = sc->sc_rbget; 1706 scc = cc = com_rbuf_size - sc->sc_rbavail; 1707 1708 if (cc == com_rbuf_size) { 1709 sc->sc_floods++; 1710 if (sc->sc_errors++ == 0) 1711 callout_reset(&sc->sc_diag_callout, 60 * hz, 1712 comdiag, sc); 1713 } 1714 1715 /* If not yet open, drop the entire buffer content here */ 1716 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1717 get += cc << 1; 1718 if (get >= end) 1719 get -= com_rbuf_size << 1; 1720 cc = 0; 1721 } 1722 while (cc) { 1723 code = get[0]; 1724 lsr = get[1]; 1725 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1726 if (ISSET(lsr, LSR_OE)) { 1727 sc->sc_overflows++; 1728 if (sc->sc_errors++ == 0) 1729 callout_reset(&sc->sc_diag_callout, 1730 60 * hz, comdiag, sc); 1731 } 1732 if (ISSET(lsr, LSR_BI | LSR_FE)) 1733 SET(code, TTY_FE); 1734 if (ISSET(lsr, LSR_PE)) 1735 SET(code, TTY_PE); 1736 } 1737 if ((*rint)(code, tp) == -1) { 1738 /* 1739 * The line discipline's buffer is out of space. 1740 */ 1741 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1742 /* 1743 * We're either not using flow control, or the 1744 * line discipline didn't tell us to block for 1745 * some reason. Either way, we have no way to 1746 * know when there's more space available, so 1747 * just drop the rest of the data. 1748 */ 1749 get += cc << 1; 1750 if (get >= end) 1751 get -= com_rbuf_size << 1; 1752 cc = 0; 1753 } else { 1754 /* 1755 * Don't schedule any more receive processing 1756 * until the line discipline tells us there's 1757 * space available (through comhwiflow()). 1758 * Leave the rest of the data in the input 1759 * buffer. 1760 */ 1761 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1762 } 1763 break; 1764 } 1765 get += 2; 1766 if (get >= end) 1767 get = sc->sc_rbuf; 1768 cc--; 1769 } 1770 1771 if (cc != scc) { 1772 sc->sc_rbget = get; 1773 mutex_spin_enter(&sc->sc_lock); 1774 1775 cc = sc->sc_rbavail += scc - cc; 1776 /* Buffers should be ok again, release possible block. */ 1777 if (cc >= sc->sc_r_lowat) { 1778 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1779 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1780 SET(sc->sc_ier, IER_ERXRDY); 1781 #ifdef COM_PXA2X0 1782 if (sc->sc_type == COM_TYPE_PXA2x0) 1783 SET(sc->sc_ier, IER_ERXTOUT); 1784 #endif 1785 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1786 } 1787 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1788 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1789 com_hwiflow(sc); 1790 } 1791 } 1792 mutex_spin_exit(&sc->sc_lock); 1793 } 1794 } 1795 1796 integrate void 1797 com_txsoft(struct com_softc *sc, struct tty *tp) 1798 { 1799 1800 CLR(tp->t_state, TS_BUSY); 1801 if (ISSET(tp->t_state, TS_FLUSH)) 1802 CLR(tp->t_state, TS_FLUSH); 1803 else 1804 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1805 (*tp->t_linesw->l_start)(tp); 1806 } 1807 1808 integrate void 1809 com_stsoft(struct com_softc *sc, struct tty *tp) 1810 { 1811 u_char msr, delta; 1812 1813 mutex_spin_enter(&sc->sc_lock); 1814 msr = sc->sc_msr; 1815 delta = sc->sc_msr_delta; 1816 sc->sc_msr_delta = 0; 1817 mutex_spin_exit(&sc->sc_lock); 1818 1819 if (ISSET(delta, sc->sc_msr_dcd)) { 1820 /* 1821 * Inform the tty layer that carrier detect changed. 1822 */ 1823 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1824 } 1825 1826 if (ISSET(delta, sc->sc_msr_cts)) { 1827 /* Block or unblock output according to flow control. */ 1828 if (ISSET(msr, sc->sc_msr_cts)) { 1829 sc->sc_tx_stopped = 0; 1830 (*tp->t_linesw->l_start)(tp); 1831 } else { 1832 sc->sc_tx_stopped = 1; 1833 } 1834 } 1835 1836 #ifdef COM_DEBUG 1837 if (com_debug) 1838 comstatus(sc, "com_stsoft"); 1839 #endif 1840 } 1841 1842 void 1843 comsoft(void *arg) 1844 { 1845 struct com_softc *sc = arg; 1846 struct tty *tp; 1847 1848 if (COM_ISALIVE(sc) == 0) 1849 return; 1850 1851 tp = sc->sc_tty; 1852 1853 if (sc->sc_rx_ready) { 1854 sc->sc_rx_ready = 0; 1855 com_rxsoft(sc, tp); 1856 } 1857 1858 if (sc->sc_st_check) { 1859 sc->sc_st_check = 0; 1860 com_stsoft(sc, tp); 1861 } 1862 1863 if (sc->sc_tx_done) { 1864 sc->sc_tx_done = 0; 1865 com_txsoft(sc, tp); 1866 } 1867 } 1868 1869 int 1870 comintr(void *arg) 1871 { 1872 struct com_softc *sc = arg; 1873 struct com_regs *regsp = &sc->sc_regs; 1874 1875 u_char *put, *end; 1876 u_int cc; 1877 u_char lsr, iir; 1878 1879 if (COM_ISALIVE(sc) == 0) 1880 return (0); 1881 1882 KASSERT(regsp != NULL); 1883 1884 mutex_spin_enter(&sc->sc_lock); 1885 iir = CSR_READ_1(regsp, COM_REG_IIR); 1886 if (ISSET(iir, IIR_NOPEND)) { 1887 mutex_spin_exit(&sc->sc_lock); 1888 return (0); 1889 } 1890 1891 end = sc->sc_ebuf; 1892 put = sc->sc_rbput; 1893 cc = sc->sc_rbavail; 1894 1895 again: do { 1896 u_char msr, delta; 1897 1898 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1899 if (ISSET(lsr, LSR_BI)) { 1900 int cn_trapped = 0; 1901 1902 cn_check_magic(sc->sc_tty->t_dev, 1903 CNC_BREAK, com_cnm_state); 1904 if (cn_trapped) 1905 continue; 1906 #if defined(KGDB) && !defined(DDB) 1907 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1908 kgdb_connect(1); 1909 continue; 1910 } 1911 #endif 1912 } 1913 1914 if (ISSET(lsr, LSR_RCV_MASK) && 1915 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1916 while (cc > 0) { 1917 int cn_trapped = 0; 1918 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1919 put[1] = lsr; 1920 cn_check_magic(sc->sc_tty->t_dev, 1921 put[0], com_cnm_state); 1922 if (cn_trapped) 1923 goto next; 1924 put += 2; 1925 if (put >= end) 1926 put = sc->sc_rbuf; 1927 cc--; 1928 next: 1929 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1930 if (!ISSET(lsr, LSR_RCV_MASK)) 1931 break; 1932 } 1933 1934 /* 1935 * Current string of incoming characters ended because 1936 * no more data was available or we ran out of space. 1937 * Schedule a receive event if any data was received. 1938 * If we're out of space, turn off receive interrupts. 1939 */ 1940 sc->sc_rbput = put; 1941 sc->sc_rbavail = cc; 1942 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1943 sc->sc_rx_ready = 1; 1944 1945 /* 1946 * See if we are in danger of overflowing a buffer. If 1947 * so, use hardware flow control to ease the pressure. 1948 */ 1949 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1950 cc < sc->sc_r_hiwat) { 1951 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1952 com_hwiflow(sc); 1953 } 1954 1955 /* 1956 * If we're out of space, disable receive interrupts 1957 * until the queue has drained a bit. 1958 */ 1959 if (!cc) { 1960 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1961 #ifdef COM_PXA2X0 1962 if (sc->sc_type == COM_TYPE_PXA2x0) 1963 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 1964 else 1965 #endif 1966 CLR(sc->sc_ier, IER_ERXRDY); 1967 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1968 } 1969 } else { 1970 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 1971 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 1972 continue; 1973 } 1974 } 1975 1976 msr = CSR_READ_1(regsp, COM_REG_MSR); 1977 delta = msr ^ sc->sc_msr; 1978 sc->sc_msr = msr; 1979 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1980 (delta & MSR_DCD)) { 1981 mutex_spin_enter(&timecounter_lock); 1982 pps_capture(&sc->sc_pps_state); 1983 pps_event(&sc->sc_pps_state, 1984 (msr & MSR_DCD) ? 1985 PPS_CAPTUREASSERT : 1986 PPS_CAPTURECLEAR); 1987 mutex_spin_exit(&timecounter_lock); 1988 } 1989 1990 /* 1991 * Process normal status changes 1992 */ 1993 if (ISSET(delta, sc->sc_msr_mask)) { 1994 SET(sc->sc_msr_delta, delta); 1995 1996 /* 1997 * Stop output immediately if we lose the output 1998 * flow control signal or carrier detect. 1999 */ 2000 if (ISSET(~msr, sc->sc_msr_mask)) { 2001 sc->sc_tbc = 0; 2002 sc->sc_heldtbc = 0; 2003 #ifdef COM_DEBUG 2004 if (com_debug) 2005 comstatus(sc, "comintr "); 2006 #endif 2007 } 2008 2009 sc->sc_st_check = 1; 2010 } 2011 } while (!ISSET((iir = 2012 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2013 /* 2014 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2015 * by IIR read, so we can't do this way: `process all interrupts, 2016 * then do TX if possible'. 2017 */ 2018 (iir & IIR_IMASK) != IIR_TXRDY); 2019 2020 /* 2021 * Read LSR again, since there may be an interrupt between 2022 * the last LSR read and IIR read above. 2023 */ 2024 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2025 2026 /* 2027 * See if data can be transmitted as well. 2028 * Schedule tx done event if no data left 2029 * and tty was marked busy. 2030 */ 2031 if (ISSET(lsr, LSR_TXRDY)) { 2032 /* 2033 * If we've delayed a parameter change, do it now, and restart 2034 * output. 2035 */ 2036 if (sc->sc_heldchange) { 2037 com_loadchannelregs(sc); 2038 sc->sc_heldchange = 0; 2039 sc->sc_tbc = sc->sc_heldtbc; 2040 sc->sc_heldtbc = 0; 2041 } 2042 2043 /* Output the next chunk of the contiguous buffer, if any. */ 2044 if (sc->sc_tbc > 0) { 2045 u_int n; 2046 2047 n = sc->sc_tbc; 2048 if (n > sc->sc_fifolen) 2049 n = sc->sc_fifolen; 2050 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2051 sc->sc_tbc -= n; 2052 sc->sc_tba += n; 2053 } else { 2054 /* Disable transmit completion interrupts if necessary. */ 2055 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2056 CLR(sc->sc_ier, IER_ETXRDY); 2057 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2058 } 2059 if (sc->sc_tx_busy) { 2060 sc->sc_tx_busy = 0; 2061 sc->sc_tx_done = 1; 2062 } 2063 } 2064 } 2065 2066 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2067 goto again; 2068 2069 mutex_spin_exit(&sc->sc_lock); 2070 2071 /* Wake up the poller. */ 2072 softint_schedule(sc->sc_si); 2073 2074 #ifdef RND_COM 2075 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2076 #endif 2077 2078 return (1); 2079 } 2080 2081 /* 2082 * The following functions are polled getc and putc routines, shared 2083 * by the console and kgdb glue. 2084 * 2085 * The read-ahead code is so that you can detect pending in-band 2086 * cn_magic in polled mode while doing output rather than having to 2087 * wait until the kernel decides it needs input. 2088 */ 2089 2090 #define MAX_READAHEAD 20 2091 static int com_readahead[MAX_READAHEAD]; 2092 static int com_readaheadcount = 0; 2093 2094 int 2095 com_common_getc(dev_t dev, struct com_regs *regsp) 2096 { 2097 int s = splserial(); 2098 u_char stat, c; 2099 2100 /* got a character from reading things earlier */ 2101 if (com_readaheadcount > 0) { 2102 int i; 2103 2104 c = com_readahead[0]; 2105 for (i = 1; i < com_readaheadcount; i++) { 2106 com_readahead[i-1] = com_readahead[i]; 2107 } 2108 com_readaheadcount--; 2109 splx(s); 2110 return (c); 2111 } 2112 2113 /* block until a character becomes available */ 2114 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2115 ; 2116 2117 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2118 stat = CSR_READ_1(regsp, COM_REG_IIR); 2119 { 2120 int cn_trapped = 0; /* unused */ 2121 #ifdef DDB 2122 extern int db_active; 2123 if (!db_active) 2124 #endif 2125 cn_check_magic(dev, c, com_cnm_state); 2126 } 2127 splx(s); 2128 return (c); 2129 } 2130 2131 static void 2132 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2133 { 2134 int s = splserial(); 2135 int cin, stat, timo; 2136 2137 if (com_readaheadcount < MAX_READAHEAD 2138 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2139 int cn_trapped = 0; 2140 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2141 stat = CSR_READ_1(regsp, COM_REG_IIR); 2142 cn_check_magic(dev, cin, com_cnm_state); 2143 com_readahead[com_readaheadcount++] = cin; 2144 } 2145 2146 /* wait for any pending transmission to finish */ 2147 timo = 150000; 2148 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2149 continue; 2150 2151 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2152 COM_BARRIER(regsp, BR | BW); 2153 2154 splx(s); 2155 } 2156 2157 /* 2158 * Initialize UART for use as console or KGDB line. 2159 */ 2160 int 2161 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2162 tcflag_t cflag) 2163 { 2164 2165 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2166 ®sp->cr_ioh)) 2167 return (ENOMEM); /* ??? */ 2168 2169 if (type == COM_TYPE_OMAP) { 2170 /* disable before changing settings */ 2171 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2172 } 2173 2174 rate = comspeed(rate, frequency, type); 2175 if (__predict_true(rate != -1)) { 2176 if (type == COM_TYPE_AU1x00) { 2177 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2178 } else { 2179 /* no EFR on alchemy */ 2180 if (type != COM_TYPE_16550_NOERS) { 2181 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2182 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2183 } 2184 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2185 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2186 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2187 } 2188 } 2189 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2190 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2191 CSR_WRITE_1(regsp, COM_REG_FIFO, 2192 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2193 2194 if (type == COM_TYPE_OMAP) { 2195 /* setup the fifos. the FCR value is not used as long 2196 as SCR[6] and SCR[7] are 0, which they are at reset 2197 and we never touch the SCR register */ 2198 uint8_t rx_fifo_trig = 40; 2199 uint8_t tx_fifo_trig = 60; 2200 uint8_t rx_start = 8; 2201 uint8_t rx_halt = 60; 2202 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2203 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2204 2205 /* enable access to TCR & TLR */ 2206 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2207 2208 /* write tcr and tlr values */ 2209 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2210 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2211 2212 /* disable access to TCR & TLR */ 2213 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2214 2215 /* enable again, but mode is based on speed */ 2216 if (rate > 230400) { 2217 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2218 } else { 2219 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2220 } 2221 } 2222 2223 #ifdef COM_PXA2X0 2224 if (type == COM_TYPE_PXA2x0) 2225 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2226 else 2227 #endif 2228 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2229 2230 return (0); 2231 } 2232 2233 int 2234 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2235 tcflag_t cflag) 2236 { 2237 int res; 2238 2239 comcons_info.regs = *regsp; 2240 2241 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2242 if (res) 2243 return (res); 2244 2245 cn_tab = &comcons; 2246 cn_init_magic(&com_cnm_state); 2247 cn_set_magic("\047\001"); /* default magic is BREAK */ 2248 2249 comcons_info.frequency = frequency; 2250 comcons_info.type = type; 2251 comcons_info.rate = rate; 2252 comcons_info.cflag = cflag; 2253 2254 return (0); 2255 } 2256 2257 int 2258 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2259 int type, tcflag_t cflag) 2260 { 2261 struct com_regs regs; 2262 2263 memset(®s, 0, sizeof regs); 2264 regs.cr_iot = iot; 2265 regs.cr_iobase = iobase; 2266 regs.cr_nports = COM_NPORTS; 2267 #ifdef COM_REGMAP 2268 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2269 #endif 2270 2271 return comcnattach1(®s, rate, frequency, type, cflag); 2272 } 2273 2274 static int 2275 comcnreattach(void) 2276 { 2277 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2278 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2279 } 2280 2281 int 2282 comcngetc(dev_t dev) 2283 { 2284 2285 return (com_common_getc(dev, &comcons_info.regs)); 2286 } 2287 2288 /* 2289 * Console kernel output character routine. 2290 */ 2291 void 2292 comcnputc(dev_t dev, int c) 2293 { 2294 2295 com_common_putc(dev, &comcons_info.regs, c); 2296 } 2297 2298 void 2299 comcnpollc(dev_t dev, int on) 2300 { 2301 2302 } 2303 2304 #ifdef KGDB 2305 int 2306 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2307 tcflag_t cflag) 2308 { 2309 int res; 2310 2311 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2312 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2313 #if !defined(DDB) 2314 return (EBUSY); /* cannot share with console */ 2315 #else 2316 comkgdbregs = *regsp; 2317 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2318 #endif 2319 } else { 2320 comkgdbregs = *regsp; 2321 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2322 if (res) 2323 return (res); 2324 2325 /* 2326 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2327 * expects this to be initialized 2328 */ 2329 cn_init_magic(&com_cnm_state); 2330 cn_set_magic("\047\001"); 2331 } 2332 2333 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2334 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2335 2336 return (0); 2337 } 2338 2339 int 2340 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2341 int frequency, int type, tcflag_t cflag) 2342 { 2343 struct com_regs regs; 2344 2345 regs.cr_iot = iot; 2346 regs.cr_nports = COM_NPORTS; 2347 regs.cr_iobase = iobase; 2348 #ifdef COM_REGMAP 2349 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2350 #endif 2351 2352 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2353 } 2354 2355 /* ARGSUSED */ 2356 int 2357 com_kgdb_getc(void *arg) 2358 { 2359 2360 return (com_common_getc(NODEV, &comkgdbregs)); 2361 } 2362 2363 /* ARGSUSED */ 2364 void 2365 com_kgdb_putc(void *arg, int c) 2366 { 2367 2368 com_common_putc(NODEV, &comkgdbregs, c); 2369 } 2370 #endif /* KGDB */ 2371 2372 /* helper function to identify the com ports used by 2373 console or KGDB (and not yet autoconf attached) */ 2374 int 2375 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2376 { 2377 bus_space_handle_t help; 2378 2379 if (!comconsattached && 2380 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2381 iobase == comcons_info.regs.cr_iobase) 2382 help = comcons_info.regs.cr_ioh; 2383 #ifdef KGDB 2384 else if (!com_kgdb_attached && 2385 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2386 iobase == comkgdbregs.cr_iobase) 2387 help = comkgdbregs.cr_ioh; 2388 #endif 2389 else 2390 return (0); 2391 2392 if (ioh) 2393 *ioh = help; 2394 return (1); 2395 } 2396 2397 /* 2398 * this routine exists to serve as a shutdown hook for systems that 2399 * have firmware which doesn't interact properly with a com device in 2400 * FIFO mode. 2401 */ 2402 bool 2403 com_cleanup(device_t self, int how) 2404 { 2405 struct com_softc *sc = device_private(self); 2406 2407 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2408 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2409 2410 return true; 2411 } 2412 2413 bool 2414 com_suspend(device_t self, const pmf_qual_t *qual) 2415 { 2416 struct com_softc *sc = device_private(self); 2417 2418 #if 0 2419 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2420 cn_tab = &comcons_suspend; 2421 #endif 2422 2423 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2424 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2425 2426 return true; 2427 } 2428 2429 bool 2430 com_resume(device_t self, const pmf_qual_t *qual) 2431 { 2432 struct com_softc *sc = device_private(self); 2433 2434 mutex_spin_enter(&sc->sc_lock); 2435 com_loadchannelregs(sc); 2436 mutex_spin_exit(&sc->sc_lock); 2437 2438 return true; 2439 } 2440
Indexes created Thu Sep 25 16:09:42 GMT 2025