com.c revision 1.306
1 /* $NetBSD: com.c,v 1.306 2012/05/21 20:51:46 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.306 2012/05/21 20:51:46 skrll Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 } while (/* CONSTCOND */ 0) 96 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/ioctl.h> 100 #include <sys/select.h> 101 #include <sys/poll.h> 102 #include <sys/tty.h> 103 #include <sys/proc.h> 104 #include <sys/conf.h> 105 #include <sys/file.h> 106 #include <sys/uio.h> 107 #include <sys/kernel.h> 108 #include <sys/syslog.h> 109 #include <sys/device.h> 110 #include <sys/malloc.h> 111 #include <sys/timepps.h> 112 #include <sys/vnode.h> 113 #include <sys/kauth.h> 114 #include <sys/intr.h> 115 #ifdef RND_COM 116 #include <sys/rnd.h> 117 #endif 118 119 120 #include <sys/bus.h> 121 122 #include <dev/ic/comreg.h> 123 #include <dev/ic/comvar.h> 124 #include <dev/ic/ns16550reg.h> 125 #include <dev/ic/st16650reg.h> 126 #ifdef COM_HAYESP 127 #include <dev/ic/hayespreg.h> 128 #endif 129 #define com_lcr com_cfcr 130 #include <dev/cons.h> 131 132 #ifdef COM_REGMAP 133 #define CSR_WRITE_1(r, o, v) \ 134 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 135 #define CSR_READ_1(r, o) \ 136 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 137 #define CSR_WRITE_2(r, o, v) \ 138 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 139 #define CSR_READ_2(r, o) \ 140 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 141 #define CSR_WRITE_MULTI(r, o, p, n) \ 142 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 143 #else 144 #define CSR_WRITE_1(r, o, v) \ 145 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 146 #define CSR_READ_1(r, o) \ 147 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 148 #define CSR_WRITE_2(r, o, v) \ 149 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 150 #define CSR_READ_2(r, o) \ 151 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 152 #define CSR_WRITE_MULTI(r, o, p, n) \ 153 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 154 #endif 155 156 157 static void com_enable_debugport(struct com_softc *); 158 159 void com_config(struct com_softc *); 160 void com_shutdown(struct com_softc *); 161 int comspeed(long, long, int); 162 static u_char cflag2lcr(tcflag_t); 163 int comparam(struct tty *, struct termios *); 164 void comstart(struct tty *); 165 int comhwiflow(struct tty *, int); 166 167 void com_loadchannelregs(struct com_softc *); 168 void com_hwiflow(struct com_softc *); 169 void com_break(struct com_softc *, int); 170 void com_modem(struct com_softc *, int); 171 void tiocm_to_com(struct com_softc *, u_long, int); 172 int com_to_tiocm(struct com_softc *); 173 void com_iflush(struct com_softc *); 174 175 int com_common_getc(dev_t, struct com_regs *); 176 static void com_common_putc(dev_t, struct com_regs *, int); 177 178 int cominit(struct com_regs *, int, int, int, tcflag_t); 179 180 static int comcnreattach(void); 181 182 int comcngetc(dev_t); 183 void comcnputc(dev_t, int); 184 void comcnpollc(dev_t, int); 185 186 #define integrate static inline 187 void comsoft(void *); 188 integrate void com_rxsoft(struct com_softc *, struct tty *); 189 integrate void com_txsoft(struct com_softc *, struct tty *); 190 integrate void com_stsoft(struct com_softc *, struct tty *); 191 integrate void com_schedrx(struct com_softc *); 192 void comdiag(void *); 193 194 extern struct cfdriver com_cd; 195 196 dev_type_open(comopen); 197 dev_type_close(comclose); 198 dev_type_read(comread); 199 dev_type_write(comwrite); 200 dev_type_ioctl(comioctl); 201 dev_type_stop(comstop); 202 dev_type_tty(comtty); 203 dev_type_poll(compoll); 204 205 static struct comcons_info comcons_info; 206 207 /* 208 * Following are all routines needed for COM to act as console 209 */ 210 static struct consdev comcons = { 211 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 212 NODEV, CN_NORMAL 213 }; 214 215 216 const struct cdevsw com_cdevsw = { 217 comopen, comclose, comread, comwrite, comioctl, 218 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 219 }; 220 221 /* 222 * Make this an option variable one can patch. 223 * But be warned: this must be a power of 2! 224 */ 225 u_int com_rbuf_size = COM_RING_SIZE; 226 227 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 228 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 229 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 230 231 static int comconsattached; 232 static struct cnm_state com_cnm_state; 233 234 #ifdef KGDB 235 #include <sys/kgdb.h> 236 237 static struct com_regs comkgdbregs; 238 static int com_kgdb_attached; 239 240 int com_kgdb_getc(void *); 241 void com_kgdb_putc(void *, int); 242 #endif /* KGDB */ 243 244 #ifdef COM_REGMAP 245 /* initializer for typical 16550-ish hardware */ 246 #define COM_REG_16550 { \ 247 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 248 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 249 250 const bus_size_t com_std_map[16] = COM_REG_16550; 251 #endif /* COM_REGMAP */ 252 253 #define COMUNIT_MASK 0x7ffff 254 #define COMDIALOUT_MASK 0x80000 255 256 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 257 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 258 259 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 260 device_is_active((sc)->sc_dev)) 261 262 #define BR BUS_SPACE_BARRIER_READ 263 #define BW BUS_SPACE_BARRIER_WRITE 264 #define COM_BARRIER(r, f) \ 265 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 266 267 /*ARGSUSED*/ 268 int 269 comspeed(long speed, long frequency, int type) 270 { 271 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 272 273 int x, err; 274 int divisor = 16; 275 276 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 277 divisor = 13; 278 } 279 280 #if 0 281 if (speed == 0) 282 return (0); 283 #endif 284 if (speed <= 0) 285 return (-1); 286 x = divrnd(frequency / divisor, speed); 287 if (x <= 0) 288 return (-1); 289 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 290 if (err < 0) 291 err = -err; 292 if (err > COM_TOLERANCE) 293 return (-1); 294 return (x); 295 296 #undef divrnd 297 } 298 299 #ifdef COM_DEBUG 300 int com_debug = 0; 301 302 void comstatus(struct com_softc *, const char *); 303 void 304 comstatus(struct com_softc *sc, const char *str) 305 { 306 struct tty *tp = sc->sc_tty; 307 308 aprint_normal_dev(sc->sc_dev, 309 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 310 str, 311 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 312 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 313 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 314 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 315 sc->sc_tx_stopped ? '+' : '-'); 316 317 aprint_normal_dev(sc->sc_dev, 318 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 319 str, 320 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 321 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 322 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 323 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 324 sc->sc_rx_flags); 325 } 326 #endif 327 328 int 329 com_probe_subr(struct com_regs *regs) 330 { 331 332 /* force access to id reg */ 333 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 334 CSR_WRITE_1(regs, COM_REG_IIR, 0); 335 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 336 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 337 return (0); 338 339 return (1); 340 } 341 342 int 343 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 344 { 345 struct com_regs regs; 346 347 regs.cr_iot = iot; 348 regs.cr_ioh = ioh; 349 #ifdef COM_REGMAP 350 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 351 #endif 352 353 return com_probe_subr(®s); 354 } 355 356 /* 357 * No locking in this routine; it is only called during attach, 358 * or with the port already locked. 359 */ 360 static void 361 com_enable_debugport(struct com_softc *sc) 362 { 363 364 /* Turn on line break interrupt, set carrier. */ 365 sc->sc_ier = IER_ERXRDY; 366 if (sc->sc_type == COM_TYPE_PXA2x0) 367 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 368 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 369 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 370 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 371 } 372 373 void 374 com_attach_subr(struct com_softc *sc) 375 { 376 struct com_regs *regsp = &sc->sc_regs; 377 struct tty *tp; 378 #ifdef COM_16650 379 u_int8_t lcr; 380 #endif 381 const char *fifo_msg = NULL; 382 383 aprint_naive("\n"); 384 385 callout_init(&sc->sc_diag_callout, 0); 386 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 387 388 /* Disable interrupts before configuring the device. */ 389 if (sc->sc_type == COM_TYPE_PXA2x0) 390 sc->sc_ier = IER_EUART; 391 else 392 sc->sc_ier = 0; 393 394 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 395 396 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 397 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 398 comconsattached = 1; 399 400 if (cn_tab == NULL && comcnreattach() != 0) { 401 printf("can't re-init serial console @%lx\n", 402 (u_long)comcons_info.regs.cr_iobase); 403 } 404 405 /* Make sure the console is always "hardwired". */ 406 delay(10000); /* wait for output to finish */ 407 SET(sc->sc_hwflags, COM_HW_CONSOLE); 408 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 409 } 410 411 /* Probe for FIFO */ 412 switch (sc->sc_type) { 413 case COM_TYPE_HAYESP: 414 goto fifodone; 415 416 case COM_TYPE_AU1x00: 417 sc->sc_fifolen = 16; 418 fifo_msg = "Au1X00 UART, working fifo"; 419 SET(sc->sc_hwflags, COM_HW_FIFO); 420 goto fifodelay; 421 422 case COM_TYPE_16550_NOERS: 423 sc->sc_fifolen = 16; 424 fifo_msg = "ns16650, no ERS, working fifo"; 425 SET(sc->sc_hwflags, COM_HW_FIFO); 426 goto fifodelay; 427 428 case COM_TYPE_OMAP: 429 sc->sc_fifolen = 64; 430 fifo_msg = "OMAP UART, working fifo"; 431 SET(sc->sc_hwflags, COM_HW_FIFO); 432 goto fifodelay; 433 } 434 435 sc->sc_fifolen = 1; 436 /* look for a NS 16550AF UART with FIFOs */ 437 CSR_WRITE_1(regsp, COM_REG_FIFO, 438 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 439 delay(100); 440 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 441 == IIR_FIFO_MASK) 442 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 443 == FIFO_TRIGGER_14) { 444 SET(sc->sc_hwflags, COM_HW_FIFO); 445 446 #ifdef COM_16650 447 /* 448 * IIR changes into the EFR if LCR is set to LCR_EERS 449 * on 16650s. We also know IIR != 0 at this point. 450 * Write 0 into the EFR, and read it. If the result 451 * is 0, we have a 16650. 452 * 453 * Older 16650s were broken; the test to detect them 454 * is taken from the Linux driver. Apparently 455 * setting DLAB enable gives access to the EFR on 456 * these chips. 457 */ 458 lcr = CSR_READ_1(regsp, COM_REG_LCR); 459 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 460 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 461 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 462 CSR_WRITE_1(regsp, COM_REG_LCR, 463 lcr | LCR_DLAB); 464 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 465 CLR(sc->sc_hwflags, COM_HW_FIFO); 466 sc->sc_fifolen = 0; 467 } else { 468 SET(sc->sc_hwflags, COM_HW_FLOW); 469 sc->sc_fifolen = 32; 470 } 471 } else 472 #endif 473 sc->sc_fifolen = 16; 474 475 #ifdef COM_16650 476 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 477 if (sc->sc_fifolen == 0) 478 fifo_msg = "st16650, broken fifo"; 479 else if (sc->sc_fifolen == 32) 480 fifo_msg = "st16650a, working fifo"; 481 else 482 #endif 483 fifo_msg = "ns16550a, working fifo"; 484 } else 485 fifo_msg = "ns16550, broken fifo"; 486 else 487 fifo_msg = "ns8250 or ns16450, no fifo"; 488 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 489 fifodelay: 490 /* 491 * Some chips will clear down both Tx and Rx FIFOs when zero is 492 * written to com_fifo. If this chip is the console, writing zero 493 * results in some of the chip/FIFO description being lost, so delay 494 * printing it until now. 495 */ 496 delay(10); 497 aprint_normal(": %s\n", fifo_msg); 498 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 499 sc->sc_fifolen = 1; 500 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 501 } 502 503 fifodone: 504 505 tp = tty_alloc(); 506 tp->t_oproc = comstart; 507 tp->t_param = comparam; 508 tp->t_hwiflow = comhwiflow; 509 510 sc->sc_tty = tp; 511 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 512 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 513 sc->sc_rbavail = com_rbuf_size; 514 if (sc->sc_rbuf == NULL) { 515 aprint_error_dev(sc->sc_dev, 516 "unable to allocate ring buffer\n"); 517 return; 518 } 519 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 520 521 tty_attach(tp); 522 523 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 524 SET(sc->sc_mcr, MCR_IENABLE); 525 526 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 527 int maj; 528 529 /* locate the major number */ 530 maj = cdevsw_lookup_major(&com_cdevsw); 531 532 tp->t_dev = cn_tab->cn_dev = makedev(maj, 533 device_unit(sc->sc_dev)); 534 535 aprint_normal_dev(sc->sc_dev, "console\n"); 536 } 537 538 #ifdef KGDB 539 /* 540 * Allow kgdb to "take over" this port. If this is 541 * not the console and is the kgdb device, it has 542 * exclusive use. If it's the console _and_ the 543 * kgdb device, it doesn't. 544 */ 545 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 546 regsp->cr_iobase == comkgdbregs.cr_iobase) { 547 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 548 com_kgdb_attached = 1; 549 550 SET(sc->sc_hwflags, COM_HW_KGDB); 551 } 552 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 553 } 554 #endif 555 556 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 557 558 #ifdef RND_COM 559 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 560 RND_TYPE_TTY, 0); 561 #endif 562 563 /* if there are no enable/disable functions, assume the device 564 is always enabled */ 565 if (!sc->enable) 566 sc->enabled = 1; 567 568 com_config(sc); 569 570 SET(sc->sc_hwflags, COM_HW_DEV_OK); 571 } 572 573 void 574 com_config(struct com_softc *sc) 575 { 576 struct com_regs *regsp = &sc->sc_regs; 577 578 /* Disable interrupts before configuring the device. */ 579 if (sc->sc_type == COM_TYPE_PXA2x0) 580 sc->sc_ier = IER_EUART; 581 else 582 sc->sc_ier = 0; 583 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 584 (void) CSR_READ_1(regsp, COM_REG_IIR); 585 586 #ifdef COM_HAYESP 587 /* Look for a Hayes ESP board. */ 588 if (sc->sc_type == COM_TYPE_HAYESP) { 589 590 /* Set 16550 compatibility mode */ 591 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 592 HAYESP_SETMODE); 593 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 594 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 595 HAYESP_MODE_SCALE); 596 597 /* Set RTS/CTS flow control */ 598 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 599 HAYESP_SETFLOWTYPE); 600 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 601 HAYESP_FLOW_RTS); 602 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 603 HAYESP_FLOW_CTS); 604 605 /* Set flow control levels */ 606 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 607 HAYESP_SETRXFLOW); 608 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 609 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 610 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 611 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 612 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 613 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 614 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 615 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 616 } 617 #endif 618 619 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 620 com_enable_debugport(sc); 621 } 622 623 #if 0 624 static int 625 comcngetc_detached(dev_t dev) 626 { 627 return 0; 628 } 629 630 static void 631 comcnputc_detached(dev_t dev, int c) 632 { 633 } 634 #endif 635 636 int 637 com_detach(device_t self, int flags) 638 { 639 struct com_softc *sc = device_private(self); 640 int maj, mn; 641 642 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 643 return EBUSY; 644 645 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 646 (flags & DETACH_SHUTDOWN) != 0) 647 return EBUSY; 648 649 if (sc->disable != NULL && sc->enabled != 0) { 650 (*sc->disable)(sc); 651 sc->enabled = 0; 652 } 653 654 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 655 comconsattached = 0; 656 cn_tab = NULL; 657 } 658 659 /* locate the major number */ 660 maj = cdevsw_lookup_major(&com_cdevsw); 661 662 /* Nuke the vnodes for any open instances. */ 663 mn = device_unit(self); 664 vdevgone(maj, mn, mn, VCHR); 665 666 mn |= COMDIALOUT_MASK; 667 vdevgone(maj, mn, mn, VCHR); 668 669 if (sc->sc_rbuf == NULL) { 670 /* 671 * Ring buffer allocation failed in the com_attach_subr, 672 * only the tty is allocated, and nothing else. 673 */ 674 tty_free(sc->sc_tty); 675 return 0; 676 } 677 678 /* Free the receive buffer. */ 679 free(sc->sc_rbuf, M_DEVBUF); 680 681 /* Detach and free the tty. */ 682 tty_detach(sc->sc_tty); 683 tty_free(sc->sc_tty); 684 685 /* Unhook the soft interrupt handler. */ 686 softint_disestablish(sc->sc_si); 687 688 #ifdef RND_COM 689 /* Unhook the entropy source. */ 690 rnd_detach_source(&sc->rnd_source); 691 #endif 692 callout_destroy(&sc->sc_diag_callout); 693 694 /* Destroy the lock. */ 695 mutex_destroy(&sc->sc_lock); 696 697 return (0); 698 } 699 700 void 701 com_shutdown(struct com_softc *sc) 702 { 703 struct tty *tp = sc->sc_tty; 704 705 mutex_spin_enter(&sc->sc_lock); 706 707 /* If we were asserting flow control, then deassert it. */ 708 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 709 com_hwiflow(sc); 710 711 /* Clear any break condition set with TIOCSBRK. */ 712 com_break(sc, 0); 713 714 /* 715 * Hang up if necessary. Wait a bit, so the other side has time to 716 * notice even if we immediately open the port again. 717 * Avoid tsleeping above splhigh(). 718 */ 719 if (ISSET(tp->t_cflag, HUPCL)) { 720 com_modem(sc, 0); 721 mutex_spin_exit(&sc->sc_lock); 722 /* XXX will only timeout */ 723 (void) kpause(ttclos, false, hz, NULL); 724 mutex_spin_enter(&sc->sc_lock); 725 } 726 727 /* Turn off interrupts. */ 728 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 729 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 730 if (sc->sc_type == COM_TYPE_PXA2x0) 731 sc->sc_ier |= IER_ERXTOUT; 732 } else 733 sc->sc_ier = 0; 734 735 if (sc->sc_type == COM_TYPE_PXA2x0) 736 sc->sc_ier |= IER_EUART; 737 738 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 739 740 mutex_spin_exit(&sc->sc_lock); 741 742 if (sc->disable) { 743 #ifdef DIAGNOSTIC 744 if (!sc->enabled) 745 panic("com_shutdown: not enabled?"); 746 #endif 747 (*sc->disable)(sc); 748 sc->enabled = 0; 749 } 750 } 751 752 int 753 comopen(dev_t dev, int flag, int mode, struct lwp *l) 754 { 755 struct com_softc *sc; 756 struct tty *tp; 757 int s; 758 int error; 759 760 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 761 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 762 sc->sc_rbuf == NULL) 763 return (ENXIO); 764 765 if (!device_is_active(sc->sc_dev)) 766 return (ENXIO); 767 768 #ifdef KGDB 769 /* 770 * If this is the kgdb port, no other use is permitted. 771 */ 772 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 773 return (EBUSY); 774 #endif 775 776 tp = sc->sc_tty; 777 778 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 779 return (EBUSY); 780 781 s = spltty(); 782 783 /* 784 * Do the following iff this is a first open. 785 */ 786 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 787 struct termios t; 788 789 tp->t_dev = dev; 790 791 if (sc->enable) { 792 if ((*sc->enable)(sc)) { 793 splx(s); 794 aprint_error_dev(sc->sc_dev, 795 "device enable failed\n"); 796 return (EIO); 797 } 798 mutex_spin_enter(&sc->sc_lock); 799 sc->enabled = 1; 800 com_config(sc); 801 } else { 802 mutex_spin_enter(&sc->sc_lock); 803 } 804 805 /* Turn on interrupts. */ 806 sc->sc_ier = IER_ERXRDY | IER_ERLS; 807 if (!ISSET(tp->t_cflag, CLOCAL)) 808 sc->sc_ier |= IER_EMSC; 809 810 if (sc->sc_type == COM_TYPE_PXA2x0) 811 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 812 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 813 814 /* Fetch the current modem control status, needed later. */ 815 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 816 817 /* Clear PPS capture state on first open. */ 818 mutex_spin_enter(&timecounter_lock); 819 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 820 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 821 pps_init(&sc->sc_pps_state); 822 mutex_spin_exit(&timecounter_lock); 823 824 mutex_spin_exit(&sc->sc_lock); 825 826 /* 827 * Initialize the termios status to the defaults. Add in the 828 * sticky bits from TIOCSFLAGS. 829 */ 830 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 831 t.c_ospeed = comcons_info.rate; 832 t.c_cflag = comcons_info.cflag; 833 } else { 834 t.c_ospeed = TTYDEF_SPEED; 835 t.c_cflag = TTYDEF_CFLAG; 836 } 837 t.c_ispeed = t.c_ospeed; 838 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 839 SET(t.c_cflag, CLOCAL); 840 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 841 SET(t.c_cflag, CRTSCTS); 842 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 843 SET(t.c_cflag, MDMBUF); 844 /* Make sure comparam() will do something. */ 845 tp->t_ospeed = 0; 846 (void) comparam(tp, &t); 847 tp->t_iflag = TTYDEF_IFLAG; 848 tp->t_oflag = TTYDEF_OFLAG; 849 tp->t_lflag = TTYDEF_LFLAG; 850 ttychars(tp); 851 ttsetwater(tp); 852 853 mutex_spin_enter(&sc->sc_lock); 854 855 /* 856 * Turn on DTR. We must always do this, even if carrier is not 857 * present, because otherwise we'd have to use TIOCSDTR 858 * immediately after setting CLOCAL, which applications do not 859 * expect. We always assert DTR while the device is open 860 * unless explicitly requested to deassert it. 861 */ 862 com_modem(sc, 1); 863 864 /* Clear the input ring, and unblock. */ 865 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 866 sc->sc_rbavail = com_rbuf_size; 867 com_iflush(sc); 868 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 869 com_hwiflow(sc); 870 871 #ifdef COM_DEBUG 872 if (com_debug) 873 comstatus(sc, "comopen "); 874 #endif 875 876 mutex_spin_exit(&sc->sc_lock); 877 } 878 879 splx(s); 880 881 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 882 if (error) 883 goto bad; 884 885 error = (*tp->t_linesw->l_open)(dev, tp); 886 if (error) 887 goto bad; 888 889 return (0); 890 891 bad: 892 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 893 /* 894 * We failed to open the device, and nobody else had it opened. 895 * Clean up the state as appropriate. 896 */ 897 com_shutdown(sc); 898 } 899 900 return (error); 901 } 902 903 int 904 comclose(dev_t dev, int flag, int mode, struct lwp *l) 905 { 906 struct com_softc *sc = 907 device_lookup_private(&com_cd, COMUNIT(dev)); 908 struct tty *tp = sc->sc_tty; 909 910 /* XXX This is for cons.c. */ 911 if (!ISSET(tp->t_state, TS_ISOPEN)) 912 return (0); 913 914 (*tp->t_linesw->l_close)(tp, flag); 915 ttyclose(tp); 916 917 if (COM_ISALIVE(sc) == 0) 918 return (0); 919 920 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 921 /* 922 * Although we got a last close, the device may still be in 923 * use; e.g. if this was the dialout node, and there are still 924 * processes waiting for carrier on the non-dialout node. 925 */ 926 com_shutdown(sc); 927 } 928 929 return (0); 930 } 931 932 int 933 comread(dev_t dev, struct uio *uio, int flag) 934 { 935 struct com_softc *sc = 936 device_lookup_private(&com_cd, COMUNIT(dev)); 937 struct tty *tp = sc->sc_tty; 938 939 if (COM_ISALIVE(sc) == 0) 940 return (EIO); 941 942 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 943 } 944 945 int 946 comwrite(dev_t dev, struct uio *uio, int flag) 947 { 948 struct com_softc *sc = 949 device_lookup_private(&com_cd, COMUNIT(dev)); 950 struct tty *tp = sc->sc_tty; 951 952 if (COM_ISALIVE(sc) == 0) 953 return (EIO); 954 955 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 956 } 957 958 int 959 compoll(dev_t dev, int events, struct lwp *l) 960 { 961 struct com_softc *sc = 962 device_lookup_private(&com_cd, COMUNIT(dev)); 963 struct tty *tp = sc->sc_tty; 964 965 if (COM_ISALIVE(sc) == 0) 966 return (POLLHUP); 967 968 return ((*tp->t_linesw->l_poll)(tp, events, l)); 969 } 970 971 struct tty * 972 comtty(dev_t dev) 973 { 974 struct com_softc *sc = 975 device_lookup_private(&com_cd, COMUNIT(dev)); 976 struct tty *tp = sc->sc_tty; 977 978 return (tp); 979 } 980 981 int 982 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 983 { 984 struct com_softc *sc; 985 struct tty *tp; 986 int error; 987 988 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 989 if (sc == NULL) 990 return ENXIO; 991 if (COM_ISALIVE(sc) == 0) 992 return (EIO); 993 994 tp = sc->sc_tty; 995 996 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 997 if (error != EPASSTHROUGH) 998 return (error); 999 1000 error = ttioctl(tp, cmd, data, flag, l); 1001 if (error != EPASSTHROUGH) 1002 return (error); 1003 1004 error = 0; 1005 switch (cmd) { 1006 case TIOCSFLAGS: 1007 error = kauth_authorize_device_tty(l->l_cred, 1008 KAUTH_DEVICE_TTY_PRIVSET, tp); 1009 break; 1010 default: 1011 /* nothing */ 1012 break; 1013 } 1014 if (error) { 1015 return error; 1016 } 1017 1018 mutex_spin_enter(&sc->sc_lock); 1019 1020 switch (cmd) { 1021 case TIOCSBRK: 1022 com_break(sc, 1); 1023 break; 1024 1025 case TIOCCBRK: 1026 com_break(sc, 0); 1027 break; 1028 1029 case TIOCSDTR: 1030 com_modem(sc, 1); 1031 break; 1032 1033 case TIOCCDTR: 1034 com_modem(sc, 0); 1035 break; 1036 1037 case TIOCGFLAGS: 1038 *(int *)data = sc->sc_swflags; 1039 break; 1040 1041 case TIOCSFLAGS: 1042 sc->sc_swflags = *(int *)data; 1043 break; 1044 1045 case TIOCMSET: 1046 case TIOCMBIS: 1047 case TIOCMBIC: 1048 tiocm_to_com(sc, cmd, *(int *)data); 1049 break; 1050 1051 case TIOCMGET: 1052 *(int *)data = com_to_tiocm(sc); 1053 break; 1054 1055 case PPS_IOC_CREATE: 1056 case PPS_IOC_DESTROY: 1057 case PPS_IOC_GETPARAMS: 1058 case PPS_IOC_SETPARAMS: 1059 case PPS_IOC_GETCAP: 1060 case PPS_IOC_FETCH: 1061 #ifdef PPS_SYNC 1062 case PPS_IOC_KCBIND: 1063 #endif 1064 mutex_spin_enter(&timecounter_lock); 1065 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1066 mutex_spin_exit(&timecounter_lock); 1067 break; 1068 1069 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1070 mutex_spin_enter(&timecounter_lock); 1071 #ifndef PPS_TRAILING_EDGE 1072 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1073 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1074 #else 1075 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1076 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1077 #endif 1078 mutex_spin_exit(&timecounter_lock); 1079 break; 1080 1081 default: 1082 error = EPASSTHROUGH; 1083 break; 1084 } 1085 1086 mutex_spin_exit(&sc->sc_lock); 1087 1088 #ifdef COM_DEBUG 1089 if (com_debug) 1090 comstatus(sc, "comioctl "); 1091 #endif 1092 1093 return (error); 1094 } 1095 1096 integrate void 1097 com_schedrx(struct com_softc *sc) 1098 { 1099 1100 sc->sc_rx_ready = 1; 1101 1102 /* Wake up the poller. */ 1103 softint_schedule(sc->sc_si); 1104 } 1105 1106 void 1107 com_break(struct com_softc *sc, int onoff) 1108 { 1109 1110 if (onoff) 1111 SET(sc->sc_lcr, LCR_SBREAK); 1112 else 1113 CLR(sc->sc_lcr, LCR_SBREAK); 1114 1115 if (!sc->sc_heldchange) { 1116 if (sc->sc_tx_busy) { 1117 sc->sc_heldtbc = sc->sc_tbc; 1118 sc->sc_tbc = 0; 1119 sc->sc_heldchange = 1; 1120 } else 1121 com_loadchannelregs(sc); 1122 } 1123 } 1124 1125 void 1126 com_modem(struct com_softc *sc, int onoff) 1127 { 1128 1129 if (sc->sc_mcr_dtr == 0) 1130 return; 1131 1132 if (onoff) 1133 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1134 else 1135 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1136 1137 if (!sc->sc_heldchange) { 1138 if (sc->sc_tx_busy) { 1139 sc->sc_heldtbc = sc->sc_tbc; 1140 sc->sc_tbc = 0; 1141 sc->sc_heldchange = 1; 1142 } else 1143 com_loadchannelregs(sc); 1144 } 1145 } 1146 1147 void 1148 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1149 { 1150 u_char combits; 1151 1152 combits = 0; 1153 if (ISSET(ttybits, TIOCM_DTR)) 1154 SET(combits, MCR_DTR); 1155 if (ISSET(ttybits, TIOCM_RTS)) 1156 SET(combits, MCR_RTS); 1157 1158 switch (how) { 1159 case TIOCMBIC: 1160 CLR(sc->sc_mcr, combits); 1161 break; 1162 1163 case TIOCMBIS: 1164 SET(sc->sc_mcr, combits); 1165 break; 1166 1167 case TIOCMSET: 1168 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1169 SET(sc->sc_mcr, combits); 1170 break; 1171 } 1172 1173 if (!sc->sc_heldchange) { 1174 if (sc->sc_tx_busy) { 1175 sc->sc_heldtbc = sc->sc_tbc; 1176 sc->sc_tbc = 0; 1177 sc->sc_heldchange = 1; 1178 } else 1179 com_loadchannelregs(sc); 1180 } 1181 } 1182 1183 int 1184 com_to_tiocm(struct com_softc *sc) 1185 { 1186 u_char combits; 1187 int ttybits = 0; 1188 1189 combits = sc->sc_mcr; 1190 if (ISSET(combits, MCR_DTR)) 1191 SET(ttybits, TIOCM_DTR); 1192 if (ISSET(combits, MCR_RTS)) 1193 SET(ttybits, TIOCM_RTS); 1194 1195 combits = sc->sc_msr; 1196 if (ISSET(combits, MSR_DCD)) 1197 SET(ttybits, TIOCM_CD); 1198 if (ISSET(combits, MSR_CTS)) 1199 SET(ttybits, TIOCM_CTS); 1200 if (ISSET(combits, MSR_DSR)) 1201 SET(ttybits, TIOCM_DSR); 1202 if (ISSET(combits, MSR_RI | MSR_TERI)) 1203 SET(ttybits, TIOCM_RI); 1204 1205 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1206 SET(ttybits, TIOCM_LE); 1207 1208 return (ttybits); 1209 } 1210 1211 static u_char 1212 cflag2lcr(tcflag_t cflag) 1213 { 1214 u_char lcr = 0; 1215 1216 switch (ISSET(cflag, CSIZE)) { 1217 case CS5: 1218 SET(lcr, LCR_5BITS); 1219 break; 1220 case CS6: 1221 SET(lcr, LCR_6BITS); 1222 break; 1223 case CS7: 1224 SET(lcr, LCR_7BITS); 1225 break; 1226 case CS8: 1227 SET(lcr, LCR_8BITS); 1228 break; 1229 } 1230 if (ISSET(cflag, PARENB)) { 1231 SET(lcr, LCR_PENAB); 1232 if (!ISSET(cflag, PARODD)) 1233 SET(lcr, LCR_PEVEN); 1234 } 1235 if (ISSET(cflag, CSTOPB)) 1236 SET(lcr, LCR_STOPB); 1237 1238 return (lcr); 1239 } 1240 1241 int 1242 comparam(struct tty *tp, struct termios *t) 1243 { 1244 struct com_softc *sc = 1245 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1246 int ospeed; 1247 u_char lcr; 1248 1249 if (COM_ISALIVE(sc) == 0) 1250 return (EIO); 1251 1252 #ifdef COM_HAYESP 1253 if (sc->sc_type == COM_TYPE_HAYESP) { 1254 int prescaler, speed; 1255 1256 /* 1257 * Calculate UART clock prescaler. It should be in 1258 * range of 0 .. 3. 1259 */ 1260 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1261 prescaler++, speed /= 2) 1262 if ((ospeed = comspeed(speed, sc->sc_frequency, 1263 sc->sc_type)) > 0) 1264 break; 1265 1266 if (prescaler == 4) 1267 return (EINVAL); 1268 sc->sc_prescaler = prescaler; 1269 } else 1270 #endif 1271 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1272 1273 /* Check requested parameters. */ 1274 if (ospeed < 0) 1275 return (EINVAL); 1276 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1277 return (EINVAL); 1278 1279 /* 1280 * For the console, always force CLOCAL and !HUPCL, so that the port 1281 * is always active. 1282 */ 1283 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1284 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1285 SET(t->c_cflag, CLOCAL); 1286 CLR(t->c_cflag, HUPCL); 1287 } 1288 1289 /* 1290 * If there were no changes, don't do anything. This avoids dropping 1291 * input and improves performance when all we did was frob things like 1292 * VMIN and VTIME. 1293 */ 1294 if (tp->t_ospeed == t->c_ospeed && 1295 tp->t_cflag == t->c_cflag) 1296 return (0); 1297 1298 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1299 1300 mutex_spin_enter(&sc->sc_lock); 1301 1302 sc->sc_lcr = lcr; 1303 1304 /* 1305 * If we're not in a mode that assumes a connection is present, then 1306 * ignore carrier changes. 1307 */ 1308 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1309 sc->sc_msr_dcd = 0; 1310 else 1311 sc->sc_msr_dcd = MSR_DCD; 1312 /* 1313 * Set the flow control pins depending on the current flow control 1314 * mode. 1315 */ 1316 if (ISSET(t->c_cflag, CRTSCTS)) { 1317 sc->sc_mcr_dtr = MCR_DTR; 1318 sc->sc_mcr_rts = MCR_RTS; 1319 sc->sc_msr_cts = MSR_CTS; 1320 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1321 } else if (ISSET(t->c_cflag, MDMBUF)) { 1322 /* 1323 * For DTR/DCD flow control, make sure we don't toggle DTR for 1324 * carrier detection. 1325 */ 1326 sc->sc_mcr_dtr = 0; 1327 sc->sc_mcr_rts = MCR_DTR; 1328 sc->sc_msr_cts = MSR_DCD; 1329 sc->sc_efr = 0; 1330 } else { 1331 /* 1332 * If no flow control, then always set RTS. This will make 1333 * the other side happy if it mistakenly thinks we're doing 1334 * RTS/CTS flow control. 1335 */ 1336 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1337 sc->sc_mcr_rts = 0; 1338 sc->sc_msr_cts = 0; 1339 sc->sc_efr = 0; 1340 if (ISSET(sc->sc_mcr, MCR_DTR)) 1341 SET(sc->sc_mcr, MCR_RTS); 1342 else 1343 CLR(sc->sc_mcr, MCR_RTS); 1344 } 1345 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1346 1347 #if 0 1348 if (ospeed == 0) 1349 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1350 else 1351 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1352 #endif 1353 1354 sc->sc_dlbl = ospeed; 1355 sc->sc_dlbh = ospeed >> 8; 1356 1357 /* 1358 * Set the FIFO threshold based on the receive speed. 1359 * 1360 * * If it's a low speed, it's probably a mouse or some other 1361 * interactive device, so set the threshold low. 1362 * * If it's a high speed, trim the trigger level down to prevent 1363 * overflows. 1364 * * Otherwise set it a bit higher. 1365 */ 1366 if (sc->sc_type == COM_TYPE_HAYESP) 1367 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1368 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1369 if (t->c_ospeed <= 1200) 1370 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1371 else if (t->c_ospeed <= 38400) 1372 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1373 else 1374 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1375 } else 1376 sc->sc_fifo = 0; 1377 1378 /* And copy to tty. */ 1379 tp->t_ispeed = t->c_ospeed; 1380 tp->t_ospeed = t->c_ospeed; 1381 tp->t_cflag = t->c_cflag; 1382 1383 if (!sc->sc_heldchange) { 1384 if (sc->sc_tx_busy) { 1385 sc->sc_heldtbc = sc->sc_tbc; 1386 sc->sc_tbc = 0; 1387 sc->sc_heldchange = 1; 1388 } else 1389 com_loadchannelregs(sc); 1390 } 1391 1392 if (!ISSET(t->c_cflag, CHWFLOW)) { 1393 /* Disable the high water mark. */ 1394 sc->sc_r_hiwat = 0; 1395 sc->sc_r_lowat = 0; 1396 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1397 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1398 com_schedrx(sc); 1399 } 1400 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1401 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1402 com_hwiflow(sc); 1403 } 1404 } else { 1405 sc->sc_r_hiwat = com_rbuf_hiwat; 1406 sc->sc_r_lowat = com_rbuf_lowat; 1407 } 1408 1409 mutex_spin_exit(&sc->sc_lock); 1410 1411 /* 1412 * Update the tty layer's idea of the carrier bit, in case we changed 1413 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1414 * explicit request. 1415 */ 1416 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1417 1418 #ifdef COM_DEBUG 1419 if (com_debug) 1420 comstatus(sc, "comparam "); 1421 #endif 1422 1423 if (!ISSET(t->c_cflag, CHWFLOW)) { 1424 if (sc->sc_tx_stopped) { 1425 sc->sc_tx_stopped = 0; 1426 comstart(tp); 1427 } 1428 } 1429 1430 return (0); 1431 } 1432 1433 void 1434 com_iflush(struct com_softc *sc) 1435 { 1436 struct com_regs *regsp = &sc->sc_regs; 1437 #ifdef DIAGNOSTIC 1438 int reg; 1439 #endif 1440 int timo; 1441 1442 #ifdef DIAGNOSTIC 1443 reg = 0xffff; 1444 #endif 1445 timo = 50000; 1446 /* flush any pending I/O */ 1447 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1448 && --timo) 1449 #ifdef DIAGNOSTIC 1450 reg = 1451 #else 1452 (void) 1453 #endif 1454 CSR_READ_1(regsp, COM_REG_RXDATA); 1455 #ifdef DIAGNOSTIC 1456 if (!timo) 1457 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1458 #endif 1459 } 1460 1461 void 1462 com_loadchannelregs(struct com_softc *sc) 1463 { 1464 struct com_regs *regsp = &sc->sc_regs; 1465 1466 /* XXXXX necessary? */ 1467 com_iflush(sc); 1468 1469 if (sc->sc_type == COM_TYPE_PXA2x0) 1470 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1471 else 1472 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1473 1474 if (sc->sc_type == COM_TYPE_OMAP) { 1475 /* disable before changing settings */ 1476 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1477 } 1478 1479 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1480 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1481 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1482 /* no EFR on alchemy */ 1483 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1484 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1485 } 1486 if (sc->sc_type == COM_TYPE_AU1x00) { 1487 /* alchemy has single separate 16-bit clock divisor register */ 1488 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1489 (sc->sc_dlbh << 8)); 1490 } else { 1491 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1492 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1493 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1494 } 1495 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1496 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1497 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1498 #ifdef COM_HAYESP 1499 if (sc->sc_type == COM_TYPE_HAYESP) { 1500 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1501 HAYESP_SETPRESCALER); 1502 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1503 sc->sc_prescaler); 1504 } 1505 #endif 1506 if (sc->sc_type == COM_TYPE_OMAP) { 1507 /* setup the fifos. the FCR value is not used as long 1508 as SCR[6] and SCR[7] are 0, which they are at reset 1509 and we never touch the SCR register */ 1510 uint8_t rx_fifo_trig = 40; 1511 uint8_t tx_fifo_trig = 60; 1512 uint8_t rx_start = 8; 1513 uint8_t rx_halt = 60; 1514 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1515 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1516 1517 /* enable access to TCR & TLR */ 1518 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1519 1520 /* write tcr and tlr values */ 1521 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1522 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1523 1524 /* disable access to TCR & TLR */ 1525 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1526 1527 /* enable again, but mode is based on speed */ 1528 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1529 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1530 } else { 1531 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1532 } 1533 } 1534 1535 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1536 } 1537 1538 int 1539 comhwiflow(struct tty *tp, int block) 1540 { 1541 struct com_softc *sc = 1542 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1543 1544 if (COM_ISALIVE(sc) == 0) 1545 return (0); 1546 1547 if (sc->sc_mcr_rts == 0) 1548 return (0); 1549 1550 mutex_spin_enter(&sc->sc_lock); 1551 1552 if (block) { 1553 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1554 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1555 com_hwiflow(sc); 1556 } 1557 } else { 1558 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1559 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1560 com_schedrx(sc); 1561 } 1562 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1563 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1564 com_hwiflow(sc); 1565 } 1566 } 1567 1568 mutex_spin_exit(&sc->sc_lock); 1569 return (1); 1570 } 1571 1572 /* 1573 * (un)block input via hw flowcontrol 1574 */ 1575 void 1576 com_hwiflow(struct com_softc *sc) 1577 { 1578 struct com_regs *regsp= &sc->sc_regs; 1579 1580 if (sc->sc_mcr_rts == 0) 1581 return; 1582 1583 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1584 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1585 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1586 } else { 1587 SET(sc->sc_mcr, sc->sc_mcr_rts); 1588 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1589 } 1590 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1591 } 1592 1593 1594 void 1595 comstart(struct tty *tp) 1596 { 1597 struct com_softc *sc = 1598 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1599 struct com_regs *regsp = &sc->sc_regs; 1600 int s; 1601 1602 if (COM_ISALIVE(sc) == 0) 1603 return; 1604 1605 s = spltty(); 1606 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1607 goto out; 1608 if (sc->sc_tx_stopped) 1609 goto out; 1610 if (!ttypull(tp)) 1611 goto out; 1612 1613 /* Grab the first contiguous region of buffer space. */ 1614 { 1615 u_char *tba; 1616 int tbc; 1617 1618 tba = tp->t_outq.c_cf; 1619 tbc = ndqb(&tp->t_outq, 0); 1620 1621 mutex_spin_enter(&sc->sc_lock); 1622 1623 sc->sc_tba = tba; 1624 sc->sc_tbc = tbc; 1625 } 1626 1627 SET(tp->t_state, TS_BUSY); 1628 sc->sc_tx_busy = 1; 1629 1630 /* Enable transmit completion interrupts if necessary. */ 1631 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1632 SET(sc->sc_ier, IER_ETXRDY); 1633 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1634 } 1635 1636 /* Output the first chunk of the contiguous buffer. */ 1637 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1638 u_int n; 1639 1640 n = sc->sc_tbc; 1641 if (n > sc->sc_fifolen) 1642 n = sc->sc_fifolen; 1643 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1644 sc->sc_tbc -= n; 1645 sc->sc_tba += n; 1646 } 1647 1648 mutex_spin_exit(&sc->sc_lock); 1649 out: 1650 splx(s); 1651 return; 1652 } 1653 1654 /* 1655 * Stop output on a line. 1656 */ 1657 void 1658 comstop(struct tty *tp, int flag) 1659 { 1660 struct com_softc *sc = 1661 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1662 1663 mutex_spin_enter(&sc->sc_lock); 1664 if (ISSET(tp->t_state, TS_BUSY)) { 1665 /* Stop transmitting at the next chunk. */ 1666 sc->sc_tbc = 0; 1667 sc->sc_heldtbc = 0; 1668 if (!ISSET(tp->t_state, TS_TTSTOP)) 1669 SET(tp->t_state, TS_FLUSH); 1670 } 1671 mutex_spin_exit(&sc->sc_lock); 1672 } 1673 1674 void 1675 comdiag(void *arg) 1676 { 1677 struct com_softc *sc = arg; 1678 int overflows, floods; 1679 1680 mutex_spin_enter(&sc->sc_lock); 1681 overflows = sc->sc_overflows; 1682 sc->sc_overflows = 0; 1683 floods = sc->sc_floods; 1684 sc->sc_floods = 0; 1685 sc->sc_errors = 0; 1686 mutex_spin_exit(&sc->sc_lock); 1687 1688 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1689 device_xname(sc->sc_dev), 1690 overflows, overflows == 1 ? "" : "s", 1691 floods, floods == 1 ? "" : "s"); 1692 } 1693 1694 integrate void 1695 com_rxsoft(struct com_softc *sc, struct tty *tp) 1696 { 1697 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1698 u_char *get, *end; 1699 u_int cc, scc; 1700 u_char lsr; 1701 int code; 1702 1703 end = sc->sc_ebuf; 1704 get = sc->sc_rbget; 1705 scc = cc = com_rbuf_size - sc->sc_rbavail; 1706 1707 if (cc == com_rbuf_size) { 1708 sc->sc_floods++; 1709 if (sc->sc_errors++ == 0) 1710 callout_reset(&sc->sc_diag_callout, 60 * hz, 1711 comdiag, sc); 1712 } 1713 1714 /* If not yet open, drop the entire buffer content here */ 1715 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1716 get += cc << 1; 1717 if (get >= end) 1718 get -= com_rbuf_size << 1; 1719 cc = 0; 1720 } 1721 while (cc) { 1722 code = get[0]; 1723 lsr = get[1]; 1724 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1725 if (ISSET(lsr, LSR_OE)) { 1726 sc->sc_overflows++; 1727 if (sc->sc_errors++ == 0) 1728 callout_reset(&sc->sc_diag_callout, 1729 60 * hz, comdiag, sc); 1730 } 1731 if (ISSET(lsr, LSR_BI | LSR_FE)) 1732 SET(code, TTY_FE); 1733 if (ISSET(lsr, LSR_PE)) 1734 SET(code, TTY_PE); 1735 } 1736 if ((*rint)(code, tp) == -1) { 1737 /* 1738 * The line discipline's buffer is out of space. 1739 */ 1740 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1741 /* 1742 * We're either not using flow control, or the 1743 * line discipline didn't tell us to block for 1744 * some reason. Either way, we have no way to 1745 * know when there's more space available, so 1746 * just drop the rest of the data. 1747 */ 1748 get += cc << 1; 1749 if (get >= end) 1750 get -= com_rbuf_size << 1; 1751 cc = 0; 1752 } else { 1753 /* 1754 * Don't schedule any more receive processing 1755 * until the line discipline tells us there's 1756 * space available (through comhwiflow()). 1757 * Leave the rest of the data in the input 1758 * buffer. 1759 */ 1760 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1761 } 1762 break; 1763 } 1764 get += 2; 1765 if (get >= end) 1766 get = sc->sc_rbuf; 1767 cc--; 1768 } 1769 1770 if (cc != scc) { 1771 sc->sc_rbget = get; 1772 mutex_spin_enter(&sc->sc_lock); 1773 1774 cc = sc->sc_rbavail += scc - cc; 1775 /* Buffers should be ok again, release possible block. */ 1776 if (cc >= sc->sc_r_lowat) { 1777 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1778 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1779 SET(sc->sc_ier, IER_ERXRDY); 1780 #ifdef COM_PXA2X0 1781 if (sc->sc_type == COM_TYPE_PXA2x0) 1782 SET(sc->sc_ier, IER_ERXTOUT); 1783 #endif 1784 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1785 } 1786 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1787 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1788 com_hwiflow(sc); 1789 } 1790 } 1791 mutex_spin_exit(&sc->sc_lock); 1792 } 1793 } 1794 1795 integrate void 1796 com_txsoft(struct com_softc *sc, struct tty *tp) 1797 { 1798 1799 CLR(tp->t_state, TS_BUSY); 1800 if (ISSET(tp->t_state, TS_FLUSH)) 1801 CLR(tp->t_state, TS_FLUSH); 1802 else 1803 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1804 (*tp->t_linesw->l_start)(tp); 1805 } 1806 1807 integrate void 1808 com_stsoft(struct com_softc *sc, struct tty *tp) 1809 { 1810 u_char msr, delta; 1811 1812 mutex_spin_enter(&sc->sc_lock); 1813 msr = sc->sc_msr; 1814 delta = sc->sc_msr_delta; 1815 sc->sc_msr_delta = 0; 1816 mutex_spin_exit(&sc->sc_lock); 1817 1818 if (ISSET(delta, sc->sc_msr_dcd)) { 1819 /* 1820 * Inform the tty layer that carrier detect changed. 1821 */ 1822 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1823 } 1824 1825 if (ISSET(delta, sc->sc_msr_cts)) { 1826 /* Block or unblock output according to flow control. */ 1827 if (ISSET(msr, sc->sc_msr_cts)) { 1828 sc->sc_tx_stopped = 0; 1829 (*tp->t_linesw->l_start)(tp); 1830 } else { 1831 sc->sc_tx_stopped = 1; 1832 } 1833 } 1834 1835 #ifdef COM_DEBUG 1836 if (com_debug) 1837 comstatus(sc, "com_stsoft"); 1838 #endif 1839 } 1840 1841 void 1842 comsoft(void *arg) 1843 { 1844 struct com_softc *sc = arg; 1845 struct tty *tp; 1846 1847 if (COM_ISALIVE(sc) == 0) 1848 return; 1849 1850 tp = sc->sc_tty; 1851 1852 if (sc->sc_rx_ready) { 1853 sc->sc_rx_ready = 0; 1854 com_rxsoft(sc, tp); 1855 } 1856 1857 if (sc->sc_st_check) { 1858 sc->sc_st_check = 0; 1859 com_stsoft(sc, tp); 1860 } 1861 1862 if (sc->sc_tx_done) { 1863 sc->sc_tx_done = 0; 1864 com_txsoft(sc, tp); 1865 } 1866 } 1867 1868 int 1869 comintr(void *arg) 1870 { 1871 struct com_softc *sc = arg; 1872 struct com_regs *regsp = &sc->sc_regs; 1873 1874 u_char *put, *end; 1875 u_int cc; 1876 u_char lsr, iir; 1877 1878 if (COM_ISALIVE(sc) == 0) 1879 return (0); 1880 1881 KASSERT(regsp != NULL); 1882 1883 mutex_spin_enter(&sc->sc_lock); 1884 iir = CSR_READ_1(regsp, COM_REG_IIR); 1885 if (ISSET(iir, IIR_NOPEND)) { 1886 mutex_spin_exit(&sc->sc_lock); 1887 return (0); 1888 } 1889 1890 end = sc->sc_ebuf; 1891 put = sc->sc_rbput; 1892 cc = sc->sc_rbavail; 1893 1894 again: do { 1895 u_char msr, delta; 1896 1897 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1898 if (ISSET(lsr, LSR_BI)) { 1899 int cn_trapped = 0; 1900 1901 cn_check_magic(sc->sc_tty->t_dev, 1902 CNC_BREAK, com_cnm_state); 1903 if (cn_trapped) 1904 continue; 1905 #if defined(KGDB) && !defined(DDB) 1906 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1907 kgdb_connect(1); 1908 continue; 1909 } 1910 #endif 1911 } 1912 1913 if (ISSET(lsr, LSR_RCV_MASK) && 1914 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1915 while (cc > 0) { 1916 int cn_trapped = 0; 1917 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1918 put[1] = lsr; 1919 cn_check_magic(sc->sc_tty->t_dev, 1920 put[0], com_cnm_state); 1921 if (cn_trapped) 1922 goto next; 1923 put += 2; 1924 if (put >= end) 1925 put = sc->sc_rbuf; 1926 cc--; 1927 next: 1928 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1929 if (!ISSET(lsr, LSR_RCV_MASK)) 1930 break; 1931 } 1932 1933 /* 1934 * Current string of incoming characters ended because 1935 * no more data was available or we ran out of space. 1936 * Schedule a receive event if any data was received. 1937 * If we're out of space, turn off receive interrupts. 1938 */ 1939 sc->sc_rbput = put; 1940 sc->sc_rbavail = cc; 1941 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1942 sc->sc_rx_ready = 1; 1943 1944 /* 1945 * See if we are in danger of overflowing a buffer. If 1946 * so, use hardware flow control to ease the pressure. 1947 */ 1948 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1949 cc < sc->sc_r_hiwat) { 1950 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1951 com_hwiflow(sc); 1952 } 1953 1954 /* 1955 * If we're out of space, disable receive interrupts 1956 * until the queue has drained a bit. 1957 */ 1958 if (!cc) { 1959 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1960 #ifdef COM_PXA2X0 1961 if (sc->sc_type == COM_TYPE_PXA2x0) 1962 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 1963 else 1964 #endif 1965 CLR(sc->sc_ier, IER_ERXRDY); 1966 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1967 } 1968 } else { 1969 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 1970 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 1971 continue; 1972 } 1973 } 1974 1975 msr = CSR_READ_1(regsp, COM_REG_MSR); 1976 delta = msr ^ sc->sc_msr; 1977 sc->sc_msr = msr; 1978 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1979 (delta & MSR_DCD)) { 1980 mutex_spin_enter(&timecounter_lock); 1981 pps_capture(&sc->sc_pps_state); 1982 pps_event(&sc->sc_pps_state, 1983 (msr & MSR_DCD) ? 1984 PPS_CAPTUREASSERT : 1985 PPS_CAPTURECLEAR); 1986 mutex_spin_exit(&timecounter_lock); 1987 } 1988 1989 /* 1990 * Process normal status changes 1991 */ 1992 if (ISSET(delta, sc->sc_msr_mask)) { 1993 SET(sc->sc_msr_delta, delta); 1994 1995 /* 1996 * Stop output immediately if we lose the output 1997 * flow control signal or carrier detect. 1998 */ 1999 if (ISSET(~msr, sc->sc_msr_mask)) { 2000 sc->sc_tbc = 0; 2001 sc->sc_heldtbc = 0; 2002 #ifdef COM_DEBUG 2003 if (com_debug) 2004 comstatus(sc, "comintr "); 2005 #endif 2006 } 2007 2008 sc->sc_st_check = 1; 2009 } 2010 } while (!ISSET((iir = 2011 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2012 /* 2013 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2014 * by IIR read, so we can't do this way: `process all interrupts, 2015 * then do TX if possible'. 2016 */ 2017 (iir & IIR_IMASK) != IIR_TXRDY); 2018 2019 /* 2020 * Read LSR again, since there may be an interrupt between 2021 * the last LSR read and IIR read above. 2022 */ 2023 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2024 2025 /* 2026 * See if data can be transmitted as well. 2027 * Schedule tx done event if no data left 2028 * and tty was marked busy. 2029 */ 2030 if (ISSET(lsr, LSR_TXRDY)) { 2031 /* 2032 * If we've delayed a parameter change, do it now, and restart 2033 * output. 2034 */ 2035 if (sc->sc_heldchange) { 2036 com_loadchannelregs(sc); 2037 sc->sc_heldchange = 0; 2038 sc->sc_tbc = sc->sc_heldtbc; 2039 sc->sc_heldtbc = 0; 2040 } 2041 2042 /* Output the next chunk of the contiguous buffer, if any. */ 2043 if (sc->sc_tbc > 0) { 2044 u_int n; 2045 2046 n = sc->sc_tbc; 2047 if (n > sc->sc_fifolen) 2048 n = sc->sc_fifolen; 2049 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2050 sc->sc_tbc -= n; 2051 sc->sc_tba += n; 2052 } else { 2053 /* Disable transmit completion interrupts if necessary. */ 2054 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2055 CLR(sc->sc_ier, IER_ETXRDY); 2056 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2057 } 2058 if (sc->sc_tx_busy) { 2059 sc->sc_tx_busy = 0; 2060 sc->sc_tx_done = 1; 2061 } 2062 } 2063 } 2064 2065 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2066 goto again; 2067 2068 mutex_spin_exit(&sc->sc_lock); 2069 2070 /* Wake up the poller. */ 2071 softint_schedule(sc->sc_si); 2072 2073 #ifdef RND_COM 2074 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2075 #endif 2076 2077 return (1); 2078 } 2079 2080 /* 2081 * The following functions are polled getc and putc routines, shared 2082 * by the console and kgdb glue. 2083 * 2084 * The read-ahead code is so that you can detect pending in-band 2085 * cn_magic in polled mode while doing output rather than having to 2086 * wait until the kernel decides it needs input. 2087 */ 2088 2089 #define MAX_READAHEAD 20 2090 static int com_readahead[MAX_READAHEAD]; 2091 static int com_readaheadcount = 0; 2092 2093 int 2094 com_common_getc(dev_t dev, struct com_regs *regsp) 2095 { 2096 int s = splserial(); 2097 u_char stat, c; 2098 2099 /* got a character from reading things earlier */ 2100 if (com_readaheadcount > 0) { 2101 int i; 2102 2103 c = com_readahead[0]; 2104 for (i = 1; i < com_readaheadcount; i++) { 2105 com_readahead[i-1] = com_readahead[i]; 2106 } 2107 com_readaheadcount--; 2108 splx(s); 2109 return (c); 2110 } 2111 2112 /* block until a character becomes available */ 2113 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2114 ; 2115 2116 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2117 stat = CSR_READ_1(regsp, COM_REG_IIR); 2118 { 2119 int cn_trapped = 0; /* unused */ 2120 #ifdef DDB 2121 extern int db_active; 2122 if (!db_active) 2123 #endif 2124 cn_check_magic(dev, c, com_cnm_state); 2125 } 2126 splx(s); 2127 return (c); 2128 } 2129 2130 static void 2131 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2132 { 2133 int s = splserial(); 2134 int cin, stat, timo; 2135 2136 if (com_readaheadcount < MAX_READAHEAD 2137 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2138 int cn_trapped = 0; 2139 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2140 stat = CSR_READ_1(regsp, COM_REG_IIR); 2141 cn_check_magic(dev, cin, com_cnm_state); 2142 com_readahead[com_readaheadcount++] = cin; 2143 } 2144 2145 /* wait for any pending transmission to finish */ 2146 timo = 150000; 2147 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2148 continue; 2149 2150 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2151 COM_BARRIER(regsp, BR | BW); 2152 2153 splx(s); 2154 } 2155 2156 /* 2157 * Initialize UART for use as console or KGDB line. 2158 */ 2159 int 2160 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2161 tcflag_t cflag) 2162 { 2163 2164 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2165 ®sp->cr_ioh)) 2166 return (ENOMEM); /* ??? */ 2167 2168 if (type == COM_TYPE_OMAP) { 2169 /* disable before changing settings */ 2170 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2171 } 2172 2173 rate = comspeed(rate, frequency, type); 2174 if (__predict_true(rate != -1)) { 2175 if (type == COM_TYPE_AU1x00) { 2176 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2177 } else { 2178 /* no EFR on alchemy */ 2179 if (type != COM_TYPE_16550_NOERS) { 2180 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2181 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2182 } 2183 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2184 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2185 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2186 } 2187 } 2188 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2189 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2190 CSR_WRITE_1(regsp, COM_REG_FIFO, 2191 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2192 2193 if (type == COM_TYPE_OMAP) { 2194 /* setup the fifos. the FCR value is not used as long 2195 as SCR[6] and SCR[7] are 0, which they are at reset 2196 and we never touch the SCR register */ 2197 uint8_t rx_fifo_trig = 40; 2198 uint8_t tx_fifo_trig = 60; 2199 uint8_t rx_start = 8; 2200 uint8_t rx_halt = 60; 2201 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2202 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2203 2204 /* enable access to TCR & TLR */ 2205 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2206 2207 /* write tcr and tlr values */ 2208 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2209 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2210 2211 /* disable access to TCR & TLR */ 2212 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2213 2214 /* enable again, but mode is based on speed */ 2215 if (rate > 230400) { 2216 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2217 } else { 2218 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2219 } 2220 } 2221 2222 #ifdef COM_PXA2X0 2223 if (type == COM_TYPE_PXA2x0) 2224 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2225 else 2226 #endif 2227 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2228 2229 return (0); 2230 } 2231 2232 int 2233 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2234 tcflag_t cflag) 2235 { 2236 int res; 2237 2238 comcons_info.regs = *regsp; 2239 2240 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2241 if (res) 2242 return (res); 2243 2244 cn_tab = &comcons; 2245 cn_init_magic(&com_cnm_state); 2246 cn_set_magic("\047\001"); /* default magic is BREAK */ 2247 2248 comcons_info.frequency = frequency; 2249 comcons_info.type = type; 2250 comcons_info.rate = rate; 2251 comcons_info.cflag = cflag; 2252 2253 return (0); 2254 } 2255 2256 int 2257 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2258 int type, tcflag_t cflag) 2259 { 2260 struct com_regs regs; 2261 2262 memset(®s, 0, sizeof regs); 2263 regs.cr_iot = iot; 2264 regs.cr_iobase = iobase; 2265 regs.cr_nports = COM_NPORTS; 2266 #ifdef COM_REGMAP 2267 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2268 #endif 2269 2270 return comcnattach1(®s, rate, frequency, type, cflag); 2271 } 2272 2273 static int 2274 comcnreattach(void) 2275 { 2276 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2277 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2278 } 2279 2280 int 2281 comcngetc(dev_t dev) 2282 { 2283 2284 return (com_common_getc(dev, &comcons_info.regs)); 2285 } 2286 2287 /* 2288 * Console kernel output character routine. 2289 */ 2290 void 2291 comcnputc(dev_t dev, int c) 2292 { 2293 2294 com_common_putc(dev, &comcons_info.regs, c); 2295 } 2296 2297 void 2298 comcnpollc(dev_t dev, int on) 2299 { 2300 2301 } 2302 2303 #ifdef KGDB 2304 int 2305 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2306 tcflag_t cflag) 2307 { 2308 int res; 2309 2310 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2311 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2312 #if !defined(DDB) 2313 return (EBUSY); /* cannot share with console */ 2314 #else 2315 comkgdbregs = *regsp; 2316 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2317 #endif 2318 } else { 2319 comkgdbregs = *regsp; 2320 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2321 if (res) 2322 return (res); 2323 2324 /* 2325 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2326 * expects this to be initialized 2327 */ 2328 cn_init_magic(&com_cnm_state); 2329 cn_set_magic("\047\001"); 2330 } 2331 2332 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2333 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2334 2335 return (0); 2336 } 2337 2338 int 2339 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2340 int frequency, int type, tcflag_t cflag) 2341 { 2342 struct com_regs regs; 2343 2344 regs.cr_iot = iot; 2345 regs.cr_nports = COM_NPORTS; 2346 regs.cr_iobase = iobase; 2347 #ifdef COM_REGMAP 2348 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2349 #endif 2350 2351 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2352 } 2353 2354 /* ARGSUSED */ 2355 int 2356 com_kgdb_getc(void *arg) 2357 { 2358 2359 return (com_common_getc(NODEV, &comkgdbregs)); 2360 } 2361 2362 /* ARGSUSED */ 2363 void 2364 com_kgdb_putc(void *arg, int c) 2365 { 2366 2367 com_common_putc(NODEV, &comkgdbregs, c); 2368 } 2369 #endif /* KGDB */ 2370 2371 /* helper function to identify the com ports used by 2372 console or KGDB (and not yet autoconf attached) */ 2373 int 2374 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2375 { 2376 bus_space_handle_t help; 2377 2378 if (!comconsattached && 2379 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2380 iobase == comcons_info.regs.cr_iobase) 2381 help = comcons_info.regs.cr_ioh; 2382 #ifdef KGDB 2383 else if (!com_kgdb_attached && 2384 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2385 iobase == comkgdbregs.cr_iobase) 2386 help = comkgdbregs.cr_ioh; 2387 #endif 2388 else 2389 return (0); 2390 2391 if (ioh) 2392 *ioh = help; 2393 return (1); 2394 } 2395 2396 /* 2397 * this routine exists to serve as a shutdown hook for systems that 2398 * have firmware which doesn't interact properly with a com device in 2399 * FIFO mode. 2400 */ 2401 bool 2402 com_cleanup(device_t self, int how) 2403 { 2404 struct com_softc *sc = device_private(self); 2405 2406 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2407 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2408 2409 return true; 2410 } 2411 2412 bool 2413 com_suspend(device_t self, const pmf_qual_t *qual) 2414 { 2415 struct com_softc *sc = device_private(self); 2416 2417 #if 0 2418 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2419 cn_tab = &comcons_suspend; 2420 #endif 2421 2422 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2423 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2424 2425 return true; 2426 } 2427 2428 bool 2429 com_resume(device_t self, const pmf_qual_t *qual) 2430 { 2431 struct com_softc *sc = device_private(self); 2432 2433 mutex_spin_enter(&sc->sc_lock); 2434 com_loadchannelregs(sc); 2435 mutex_spin_exit(&sc->sc_lock); 2436 2437 return true; 2438 } 2439
Indexes created Mon Oct 20 10:10:01 GMT 2025