com.c revision 1.307
1 /* $NetBSD: com.c,v 1.307 2013/01/10 17:38:10 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.307 2013/01/10 17:38:10 macallan Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 } while (/* CONSTCOND */ 0) 96 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/ioctl.h> 100 #include <sys/select.h> 101 #include <sys/poll.h> 102 #include <sys/tty.h> 103 #include <sys/proc.h> 104 #include <sys/conf.h> 105 #include <sys/file.h> 106 #include <sys/uio.h> 107 #include <sys/kernel.h> 108 #include <sys/syslog.h> 109 #include <sys/device.h> 110 #include <sys/malloc.h> 111 #include <sys/timepps.h> 112 #include <sys/vnode.h> 113 #include <sys/kauth.h> 114 #include <sys/intr.h> 115 #ifdef RND_COM 116 #include <sys/rnd.h> 117 #endif 118 119 120 #include <sys/bus.h> 121 122 #include <dev/ic/comreg.h> 123 #include <dev/ic/comvar.h> 124 #include <dev/ic/ns16550reg.h> 125 #include <dev/ic/st16650reg.h> 126 #ifdef COM_HAYESP 127 #include <dev/ic/hayespreg.h> 128 #endif 129 #define com_lcr com_cfcr 130 #include <dev/cons.h> 131 132 #ifdef COM_REGMAP 133 #define CSR_WRITE_1(r, o, v) \ 134 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 135 #define CSR_READ_1(r, o) \ 136 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 137 #define CSR_WRITE_2(r, o, v) \ 138 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 139 #define CSR_READ_2(r, o) \ 140 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 141 #define CSR_WRITE_MULTI(r, o, p, n) \ 142 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 143 #else 144 #define CSR_WRITE_1(r, o, v) \ 145 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 146 #define CSR_READ_1(r, o) \ 147 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 148 #define CSR_WRITE_2(r, o, v) \ 149 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 150 #define CSR_READ_2(r, o) \ 151 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 152 #define CSR_WRITE_MULTI(r, o, p, n) \ 153 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 154 #endif 155 156 157 static void com_enable_debugport(struct com_softc *); 158 159 void com_config(struct com_softc *); 160 void com_shutdown(struct com_softc *); 161 int comspeed(long, long, int); 162 static u_char cflag2lcr(tcflag_t); 163 int comparam(struct tty *, struct termios *); 164 void comstart(struct tty *); 165 int comhwiflow(struct tty *, int); 166 167 void com_loadchannelregs(struct com_softc *); 168 void com_hwiflow(struct com_softc *); 169 void com_break(struct com_softc *, int); 170 void com_modem(struct com_softc *, int); 171 void tiocm_to_com(struct com_softc *, u_long, int); 172 int com_to_tiocm(struct com_softc *); 173 void com_iflush(struct com_softc *); 174 175 int com_common_getc(dev_t, struct com_regs *); 176 static void com_common_putc(dev_t, struct com_regs *, int); 177 178 int cominit(struct com_regs *, int, int, int, tcflag_t); 179 180 static int comcnreattach(void); 181 182 int comcngetc(dev_t); 183 void comcnputc(dev_t, int); 184 void comcnpollc(dev_t, int); 185 186 #define integrate static inline 187 void comsoft(void *); 188 integrate void com_rxsoft(struct com_softc *, struct tty *); 189 integrate void com_txsoft(struct com_softc *, struct tty *); 190 integrate void com_stsoft(struct com_softc *, struct tty *); 191 integrate void com_schedrx(struct com_softc *); 192 void comdiag(void *); 193 194 extern struct cfdriver com_cd; 195 196 dev_type_open(comopen); 197 dev_type_close(comclose); 198 dev_type_read(comread); 199 dev_type_write(comwrite); 200 dev_type_ioctl(comioctl); 201 dev_type_stop(comstop); 202 dev_type_tty(comtty); 203 dev_type_poll(compoll); 204 205 static struct comcons_info comcons_info; 206 207 /* 208 * Following are all routines needed for COM to act as console 209 */ 210 static struct consdev comcons = { 211 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 212 NODEV, CN_NORMAL 213 }; 214 215 216 const struct cdevsw com_cdevsw = { 217 comopen, comclose, comread, comwrite, comioctl, 218 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 219 }; 220 221 /* 222 * Make this an option variable one can patch. 223 * But be warned: this must be a power of 2! 224 */ 225 u_int com_rbuf_size = COM_RING_SIZE; 226 227 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 228 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 229 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 230 231 static int comconsattached; 232 static struct cnm_state com_cnm_state; 233 234 #ifdef KGDB 235 #include <sys/kgdb.h> 236 237 static struct com_regs comkgdbregs; 238 static int com_kgdb_attached; 239 240 int com_kgdb_getc(void *); 241 void com_kgdb_putc(void *, int); 242 #endif /* KGDB */ 243 244 #ifdef COM_REGMAP 245 /* initializer for typical 16550-ish hardware */ 246 #define COM_REG_16550 { \ 247 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 248 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 249 250 const bus_size_t com_std_map[16] = COM_REG_16550; 251 #endif /* COM_REGMAP */ 252 253 #define COMUNIT_MASK 0x7ffff 254 #define COMDIALOUT_MASK 0x80000 255 256 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 257 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 258 259 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 260 device_is_active((sc)->sc_dev)) 261 262 #define BR BUS_SPACE_BARRIER_READ 263 #define BW BUS_SPACE_BARRIER_WRITE 264 #define COM_BARRIER(r, f) \ 265 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 266 267 /*ARGSUSED*/ 268 int 269 comspeed(long speed, long frequency, int type) 270 { 271 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 272 273 int x, err; 274 int divisor = 16; 275 276 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 277 divisor = 13; 278 } 279 280 #if 0 281 if (speed == 0) 282 return (0); 283 #endif 284 if (speed <= 0) 285 return (-1); 286 x = divrnd(frequency / divisor, speed); 287 if (x <= 0) 288 return (-1); 289 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 290 if (err < 0) 291 err = -err; 292 if (err > COM_TOLERANCE) 293 return (-1); 294 return (x); 295 296 #undef divrnd 297 } 298 299 #ifdef COM_DEBUG 300 int com_debug = 0; 301 302 void comstatus(struct com_softc *, const char *); 303 void 304 comstatus(struct com_softc *sc, const char *str) 305 { 306 struct tty *tp = sc->sc_tty; 307 308 aprint_normal_dev(sc->sc_dev, 309 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 310 str, 311 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 312 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 313 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 314 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 315 sc->sc_tx_stopped ? '+' : '-'); 316 317 aprint_normal_dev(sc->sc_dev, 318 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 319 str, 320 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 321 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 322 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 323 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 324 sc->sc_rx_flags); 325 } 326 #endif 327 328 int 329 com_probe_subr(struct com_regs *regs) 330 { 331 332 /* force access to id reg */ 333 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 334 CSR_WRITE_1(regs, COM_REG_IIR, 0); 335 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 336 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 337 return (0); 338 339 return (1); 340 } 341 342 int 343 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 344 { 345 struct com_regs regs; 346 347 regs.cr_iot = iot; 348 regs.cr_ioh = ioh; 349 #ifdef COM_REGMAP 350 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 351 #endif 352 353 return com_probe_subr(®s); 354 } 355 356 /* 357 * No locking in this routine; it is only called during attach, 358 * or with the port already locked. 359 */ 360 static void 361 com_enable_debugport(struct com_softc *sc) 362 { 363 364 /* Turn on line break interrupt, set carrier. */ 365 sc->sc_ier = IER_ERXRDY; 366 if (sc->sc_type == COM_TYPE_PXA2x0) 367 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 368 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 369 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 370 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 371 } 372 373 void 374 com_attach_subr(struct com_softc *sc) 375 { 376 struct com_regs *regsp = &sc->sc_regs; 377 struct tty *tp; 378 #ifdef COM_16650 379 u_int8_t lcr; 380 #endif 381 const char *fifo_msg = NULL; 382 prop_dictionary_t dict; 383 bool is_console = true; 384 385 aprint_naive("\n"); 386 387 dict = device_properties(sc->sc_dev); 388 prop_dictionary_get_bool(dict, "is_console", &is_console); 389 390 callout_init(&sc->sc_diag_callout, 0); 391 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 392 393 /* Disable interrupts before configuring the device. */ 394 if (sc->sc_type == COM_TYPE_PXA2x0) 395 sc->sc_ier = IER_EUART; 396 else 397 sc->sc_ier = 0; 398 399 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 400 401 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 402 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 403 comconsattached = 1; 404 405 if (cn_tab == NULL && comcnreattach() != 0) { 406 printf("can't re-init serial console @%lx\n", 407 (u_long)comcons_info.regs.cr_iobase); 408 } 409 410 411 /* Make sure the console is always "hardwired". */ 412 delay(10000); /* wait for output to finish */ 413 if (is_console) { 414 SET(sc->sc_hwflags, COM_HW_CONSOLE); 415 } 416 417 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 418 } 419 420 /* Probe for FIFO */ 421 switch (sc->sc_type) { 422 case COM_TYPE_HAYESP: 423 goto fifodone; 424 425 case COM_TYPE_AU1x00: 426 sc->sc_fifolen = 16; 427 fifo_msg = "Au1X00 UART, working fifo"; 428 SET(sc->sc_hwflags, COM_HW_FIFO); 429 goto fifodelay; 430 431 case COM_TYPE_16550_NOERS: 432 sc->sc_fifolen = 16; 433 fifo_msg = "ns16650, no ERS, working fifo"; 434 SET(sc->sc_hwflags, COM_HW_FIFO); 435 goto fifodelay; 436 437 case COM_TYPE_OMAP: 438 sc->sc_fifolen = 64; 439 fifo_msg = "OMAP UART, working fifo"; 440 SET(sc->sc_hwflags, COM_HW_FIFO); 441 goto fifodelay; 442 } 443 444 sc->sc_fifolen = 1; 445 /* look for a NS 16550AF UART with FIFOs */ 446 CSR_WRITE_1(regsp, COM_REG_FIFO, 447 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 448 delay(100); 449 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 450 == IIR_FIFO_MASK) 451 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 452 == FIFO_TRIGGER_14) { 453 SET(sc->sc_hwflags, COM_HW_FIFO); 454 455 #ifdef COM_16650 456 /* 457 * IIR changes into the EFR if LCR is set to LCR_EERS 458 * on 16650s. We also know IIR != 0 at this point. 459 * Write 0 into the EFR, and read it. If the result 460 * is 0, we have a 16650. 461 * 462 * Older 16650s were broken; the test to detect them 463 * is taken from the Linux driver. Apparently 464 * setting DLAB enable gives access to the EFR on 465 * these chips. 466 */ 467 lcr = CSR_READ_1(regsp, COM_REG_LCR); 468 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 469 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 470 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 471 CSR_WRITE_1(regsp, COM_REG_LCR, 472 lcr | LCR_DLAB); 473 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 474 CLR(sc->sc_hwflags, COM_HW_FIFO); 475 sc->sc_fifolen = 0; 476 } else { 477 SET(sc->sc_hwflags, COM_HW_FLOW); 478 sc->sc_fifolen = 32; 479 } 480 } else 481 #endif 482 sc->sc_fifolen = 16; 483 484 #ifdef COM_16650 485 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 486 if (sc->sc_fifolen == 0) 487 fifo_msg = "st16650, broken fifo"; 488 else if (sc->sc_fifolen == 32) 489 fifo_msg = "st16650a, working fifo"; 490 else 491 #endif 492 fifo_msg = "ns16550a, working fifo"; 493 } else 494 fifo_msg = "ns16550, broken fifo"; 495 else 496 fifo_msg = "ns8250 or ns16450, no fifo"; 497 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 498 fifodelay: 499 /* 500 * Some chips will clear down both Tx and Rx FIFOs when zero is 501 * written to com_fifo. If this chip is the console, writing zero 502 * results in some of the chip/FIFO description being lost, so delay 503 * printing it until now. 504 */ 505 delay(10); 506 aprint_normal(": %s\n", fifo_msg); 507 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 508 sc->sc_fifolen = 1; 509 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 510 } 511 512 fifodone: 513 514 tp = tty_alloc(); 515 tp->t_oproc = comstart; 516 tp->t_param = comparam; 517 tp->t_hwiflow = comhwiflow; 518 519 sc->sc_tty = tp; 520 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 521 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 522 sc->sc_rbavail = com_rbuf_size; 523 if (sc->sc_rbuf == NULL) { 524 aprint_error_dev(sc->sc_dev, 525 "unable to allocate ring buffer\n"); 526 return; 527 } 528 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 529 530 tty_attach(tp); 531 532 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 533 SET(sc->sc_mcr, MCR_IENABLE); 534 535 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 536 int maj; 537 538 /* locate the major number */ 539 maj = cdevsw_lookup_major(&com_cdevsw); 540 541 tp->t_dev = cn_tab->cn_dev = makedev(maj, 542 device_unit(sc->sc_dev)); 543 544 aprint_normal_dev(sc->sc_dev, "console\n"); 545 } 546 547 #ifdef KGDB 548 /* 549 * Allow kgdb to "take over" this port. If this is 550 * not the console and is the kgdb device, it has 551 * exclusive use. If it's the console _and_ the 552 * kgdb device, it doesn't. 553 */ 554 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 555 regsp->cr_iobase == comkgdbregs.cr_iobase) { 556 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 557 com_kgdb_attached = 1; 558 559 SET(sc->sc_hwflags, COM_HW_KGDB); 560 } 561 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 562 } 563 #endif 564 565 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 566 567 #ifdef RND_COM 568 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 569 RND_TYPE_TTY, 0); 570 #endif 571 572 /* if there are no enable/disable functions, assume the device 573 is always enabled */ 574 if (!sc->enable) 575 sc->enabled = 1; 576 577 com_config(sc); 578 579 SET(sc->sc_hwflags, COM_HW_DEV_OK); 580 } 581 582 void 583 com_config(struct com_softc *sc) 584 { 585 struct com_regs *regsp = &sc->sc_regs; 586 587 /* Disable interrupts before configuring the device. */ 588 if (sc->sc_type == COM_TYPE_PXA2x0) 589 sc->sc_ier = IER_EUART; 590 else 591 sc->sc_ier = 0; 592 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 593 (void) CSR_READ_1(regsp, COM_REG_IIR); 594 595 #ifdef COM_HAYESP 596 /* Look for a Hayes ESP board. */ 597 if (sc->sc_type == COM_TYPE_HAYESP) { 598 599 /* Set 16550 compatibility mode */ 600 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 601 HAYESP_SETMODE); 602 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 603 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 604 HAYESP_MODE_SCALE); 605 606 /* Set RTS/CTS flow control */ 607 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 608 HAYESP_SETFLOWTYPE); 609 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 610 HAYESP_FLOW_RTS); 611 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 612 HAYESP_FLOW_CTS); 613 614 /* Set flow control levels */ 615 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 616 HAYESP_SETRXFLOW); 617 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 618 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 619 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 620 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 621 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 622 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 623 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 624 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 625 } 626 #endif 627 628 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 629 com_enable_debugport(sc); 630 } 631 632 #if 0 633 static int 634 comcngetc_detached(dev_t dev) 635 { 636 return 0; 637 } 638 639 static void 640 comcnputc_detached(dev_t dev, int c) 641 { 642 } 643 #endif 644 645 int 646 com_detach(device_t self, int flags) 647 { 648 struct com_softc *sc = device_private(self); 649 int maj, mn; 650 651 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 652 return EBUSY; 653 654 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 655 (flags & DETACH_SHUTDOWN) != 0) 656 return EBUSY; 657 658 if (sc->disable != NULL && sc->enabled != 0) { 659 (*sc->disable)(sc); 660 sc->enabled = 0; 661 } 662 663 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 664 comconsattached = 0; 665 cn_tab = NULL; 666 } 667 668 /* locate the major number */ 669 maj = cdevsw_lookup_major(&com_cdevsw); 670 671 /* Nuke the vnodes for any open instances. */ 672 mn = device_unit(self); 673 vdevgone(maj, mn, mn, VCHR); 674 675 mn |= COMDIALOUT_MASK; 676 vdevgone(maj, mn, mn, VCHR); 677 678 if (sc->sc_rbuf == NULL) { 679 /* 680 * Ring buffer allocation failed in the com_attach_subr, 681 * only the tty is allocated, and nothing else. 682 */ 683 tty_free(sc->sc_tty); 684 return 0; 685 } 686 687 /* Free the receive buffer. */ 688 free(sc->sc_rbuf, M_DEVBUF); 689 690 /* Detach and free the tty. */ 691 tty_detach(sc->sc_tty); 692 tty_free(sc->sc_tty); 693 694 /* Unhook the soft interrupt handler. */ 695 softint_disestablish(sc->sc_si); 696 697 #ifdef RND_COM 698 /* Unhook the entropy source. */ 699 rnd_detach_source(&sc->rnd_source); 700 #endif 701 callout_destroy(&sc->sc_diag_callout); 702 703 /* Destroy the lock. */ 704 mutex_destroy(&sc->sc_lock); 705 706 return (0); 707 } 708 709 void 710 com_shutdown(struct com_softc *sc) 711 { 712 struct tty *tp = sc->sc_tty; 713 714 mutex_spin_enter(&sc->sc_lock); 715 716 /* If we were asserting flow control, then deassert it. */ 717 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 718 com_hwiflow(sc); 719 720 /* Clear any break condition set with TIOCSBRK. */ 721 com_break(sc, 0); 722 723 /* 724 * Hang up if necessary. Wait a bit, so the other side has time to 725 * notice even if we immediately open the port again. 726 * Avoid tsleeping above splhigh(). 727 */ 728 if (ISSET(tp->t_cflag, HUPCL)) { 729 com_modem(sc, 0); 730 mutex_spin_exit(&sc->sc_lock); 731 /* XXX will only timeout */ 732 (void) kpause(ttclos, false, hz, NULL); 733 mutex_spin_enter(&sc->sc_lock); 734 } 735 736 /* Turn off interrupts. */ 737 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 738 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 739 if (sc->sc_type == COM_TYPE_PXA2x0) 740 sc->sc_ier |= IER_ERXTOUT; 741 } else 742 sc->sc_ier = 0; 743 744 if (sc->sc_type == COM_TYPE_PXA2x0) 745 sc->sc_ier |= IER_EUART; 746 747 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 748 749 mutex_spin_exit(&sc->sc_lock); 750 751 if (sc->disable) { 752 #ifdef DIAGNOSTIC 753 if (!sc->enabled) 754 panic("com_shutdown: not enabled?"); 755 #endif 756 (*sc->disable)(sc); 757 sc->enabled = 0; 758 } 759 } 760 761 int 762 comopen(dev_t dev, int flag, int mode, struct lwp *l) 763 { 764 struct com_softc *sc; 765 struct tty *tp; 766 int s; 767 int error; 768 769 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 770 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 771 sc->sc_rbuf == NULL) 772 return (ENXIO); 773 774 if (!device_is_active(sc->sc_dev)) 775 return (ENXIO); 776 777 #ifdef KGDB 778 /* 779 * If this is the kgdb port, no other use is permitted. 780 */ 781 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 782 return (EBUSY); 783 #endif 784 785 tp = sc->sc_tty; 786 787 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 788 return (EBUSY); 789 790 s = spltty(); 791 792 /* 793 * Do the following iff this is a first open. 794 */ 795 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 796 struct termios t; 797 798 tp->t_dev = dev; 799 800 if (sc->enable) { 801 if ((*sc->enable)(sc)) { 802 splx(s); 803 aprint_error_dev(sc->sc_dev, 804 "device enable failed\n"); 805 return (EIO); 806 } 807 mutex_spin_enter(&sc->sc_lock); 808 sc->enabled = 1; 809 com_config(sc); 810 } else { 811 mutex_spin_enter(&sc->sc_lock); 812 } 813 814 /* Turn on interrupts. */ 815 sc->sc_ier = IER_ERXRDY | IER_ERLS; 816 if (!ISSET(tp->t_cflag, CLOCAL)) 817 sc->sc_ier |= IER_EMSC; 818 819 if (sc->sc_type == COM_TYPE_PXA2x0) 820 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 821 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 822 823 /* Fetch the current modem control status, needed later. */ 824 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 825 826 /* Clear PPS capture state on first open. */ 827 mutex_spin_enter(&timecounter_lock); 828 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 829 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 830 pps_init(&sc->sc_pps_state); 831 mutex_spin_exit(&timecounter_lock); 832 833 mutex_spin_exit(&sc->sc_lock); 834 835 /* 836 * Initialize the termios status to the defaults. Add in the 837 * sticky bits from TIOCSFLAGS. 838 */ 839 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 840 t.c_ospeed = comcons_info.rate; 841 t.c_cflag = comcons_info.cflag; 842 } else { 843 t.c_ospeed = TTYDEF_SPEED; 844 t.c_cflag = TTYDEF_CFLAG; 845 } 846 t.c_ispeed = t.c_ospeed; 847 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 848 SET(t.c_cflag, CLOCAL); 849 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 850 SET(t.c_cflag, CRTSCTS); 851 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 852 SET(t.c_cflag, MDMBUF); 853 /* Make sure comparam() will do something. */ 854 tp->t_ospeed = 0; 855 (void) comparam(tp, &t); 856 tp->t_iflag = TTYDEF_IFLAG; 857 tp->t_oflag = TTYDEF_OFLAG; 858 tp->t_lflag = TTYDEF_LFLAG; 859 ttychars(tp); 860 ttsetwater(tp); 861 862 mutex_spin_enter(&sc->sc_lock); 863 864 /* 865 * Turn on DTR. We must always do this, even if carrier is not 866 * present, because otherwise we'd have to use TIOCSDTR 867 * immediately after setting CLOCAL, which applications do not 868 * expect. We always assert DTR while the device is open 869 * unless explicitly requested to deassert it. 870 */ 871 com_modem(sc, 1); 872 873 /* Clear the input ring, and unblock. */ 874 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 875 sc->sc_rbavail = com_rbuf_size; 876 com_iflush(sc); 877 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 878 com_hwiflow(sc); 879 880 #ifdef COM_DEBUG 881 if (com_debug) 882 comstatus(sc, "comopen "); 883 #endif 884 885 mutex_spin_exit(&sc->sc_lock); 886 } 887 888 splx(s); 889 890 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 891 if (error) 892 goto bad; 893 894 error = (*tp->t_linesw->l_open)(dev, tp); 895 if (error) 896 goto bad; 897 898 return (0); 899 900 bad: 901 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 902 /* 903 * We failed to open the device, and nobody else had it opened. 904 * Clean up the state as appropriate. 905 */ 906 com_shutdown(sc); 907 } 908 909 return (error); 910 } 911 912 int 913 comclose(dev_t dev, int flag, int mode, struct lwp *l) 914 { 915 struct com_softc *sc = 916 device_lookup_private(&com_cd, COMUNIT(dev)); 917 struct tty *tp = sc->sc_tty; 918 919 /* XXX This is for cons.c. */ 920 if (!ISSET(tp->t_state, TS_ISOPEN)) 921 return (0); 922 923 (*tp->t_linesw->l_close)(tp, flag); 924 ttyclose(tp); 925 926 if (COM_ISALIVE(sc) == 0) 927 return (0); 928 929 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 930 /* 931 * Although we got a last close, the device may still be in 932 * use; e.g. if this was the dialout node, and there are still 933 * processes waiting for carrier on the non-dialout node. 934 */ 935 com_shutdown(sc); 936 } 937 938 return (0); 939 } 940 941 int 942 comread(dev_t dev, struct uio *uio, int flag) 943 { 944 struct com_softc *sc = 945 device_lookup_private(&com_cd, COMUNIT(dev)); 946 struct tty *tp = sc->sc_tty; 947 948 if (COM_ISALIVE(sc) == 0) 949 return (EIO); 950 951 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 952 } 953 954 int 955 comwrite(dev_t dev, struct uio *uio, int flag) 956 { 957 struct com_softc *sc = 958 device_lookup_private(&com_cd, COMUNIT(dev)); 959 struct tty *tp = sc->sc_tty; 960 961 if (COM_ISALIVE(sc) == 0) 962 return (EIO); 963 964 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 965 } 966 967 int 968 compoll(dev_t dev, int events, struct lwp *l) 969 { 970 struct com_softc *sc = 971 device_lookup_private(&com_cd, COMUNIT(dev)); 972 struct tty *tp = sc->sc_tty; 973 974 if (COM_ISALIVE(sc) == 0) 975 return (POLLHUP); 976 977 return ((*tp->t_linesw->l_poll)(tp, events, l)); 978 } 979 980 struct tty * 981 comtty(dev_t dev) 982 { 983 struct com_softc *sc = 984 device_lookup_private(&com_cd, COMUNIT(dev)); 985 struct tty *tp = sc->sc_tty; 986 987 return (tp); 988 } 989 990 int 991 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 992 { 993 struct com_softc *sc; 994 struct tty *tp; 995 int error; 996 997 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 998 if (sc == NULL) 999 return ENXIO; 1000 if (COM_ISALIVE(sc) == 0) 1001 return (EIO); 1002 1003 tp = sc->sc_tty; 1004 1005 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1006 if (error != EPASSTHROUGH) 1007 return (error); 1008 1009 error = ttioctl(tp, cmd, data, flag, l); 1010 if (error != EPASSTHROUGH) 1011 return (error); 1012 1013 error = 0; 1014 switch (cmd) { 1015 case TIOCSFLAGS: 1016 error = kauth_authorize_device_tty(l->l_cred, 1017 KAUTH_DEVICE_TTY_PRIVSET, tp); 1018 break; 1019 default: 1020 /* nothing */ 1021 break; 1022 } 1023 if (error) { 1024 return error; 1025 } 1026 1027 mutex_spin_enter(&sc->sc_lock); 1028 1029 switch (cmd) { 1030 case TIOCSBRK: 1031 com_break(sc, 1); 1032 break; 1033 1034 case TIOCCBRK: 1035 com_break(sc, 0); 1036 break; 1037 1038 case TIOCSDTR: 1039 com_modem(sc, 1); 1040 break; 1041 1042 case TIOCCDTR: 1043 com_modem(sc, 0); 1044 break; 1045 1046 case TIOCGFLAGS: 1047 *(int *)data = sc->sc_swflags; 1048 break; 1049 1050 case TIOCSFLAGS: 1051 sc->sc_swflags = *(int *)data; 1052 break; 1053 1054 case TIOCMSET: 1055 case TIOCMBIS: 1056 case TIOCMBIC: 1057 tiocm_to_com(sc, cmd, *(int *)data); 1058 break; 1059 1060 case TIOCMGET: 1061 *(int *)data = com_to_tiocm(sc); 1062 break; 1063 1064 case PPS_IOC_CREATE: 1065 case PPS_IOC_DESTROY: 1066 case PPS_IOC_GETPARAMS: 1067 case PPS_IOC_SETPARAMS: 1068 case PPS_IOC_GETCAP: 1069 case PPS_IOC_FETCH: 1070 #ifdef PPS_SYNC 1071 case PPS_IOC_KCBIND: 1072 #endif 1073 mutex_spin_enter(&timecounter_lock); 1074 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1075 mutex_spin_exit(&timecounter_lock); 1076 break; 1077 1078 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1079 mutex_spin_enter(&timecounter_lock); 1080 #ifndef PPS_TRAILING_EDGE 1081 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1082 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1083 #else 1084 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1085 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1086 #endif 1087 mutex_spin_exit(&timecounter_lock); 1088 break; 1089 1090 default: 1091 error = EPASSTHROUGH; 1092 break; 1093 } 1094 1095 mutex_spin_exit(&sc->sc_lock); 1096 1097 #ifdef COM_DEBUG 1098 if (com_debug) 1099 comstatus(sc, "comioctl "); 1100 #endif 1101 1102 return (error); 1103 } 1104 1105 integrate void 1106 com_schedrx(struct com_softc *sc) 1107 { 1108 1109 sc->sc_rx_ready = 1; 1110 1111 /* Wake up the poller. */ 1112 softint_schedule(sc->sc_si); 1113 } 1114 1115 void 1116 com_break(struct com_softc *sc, int onoff) 1117 { 1118 1119 if (onoff) 1120 SET(sc->sc_lcr, LCR_SBREAK); 1121 else 1122 CLR(sc->sc_lcr, LCR_SBREAK); 1123 1124 if (!sc->sc_heldchange) { 1125 if (sc->sc_tx_busy) { 1126 sc->sc_heldtbc = sc->sc_tbc; 1127 sc->sc_tbc = 0; 1128 sc->sc_heldchange = 1; 1129 } else 1130 com_loadchannelregs(sc); 1131 } 1132 } 1133 1134 void 1135 com_modem(struct com_softc *sc, int onoff) 1136 { 1137 1138 if (sc->sc_mcr_dtr == 0) 1139 return; 1140 1141 if (onoff) 1142 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1143 else 1144 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1145 1146 if (!sc->sc_heldchange) { 1147 if (sc->sc_tx_busy) { 1148 sc->sc_heldtbc = sc->sc_tbc; 1149 sc->sc_tbc = 0; 1150 sc->sc_heldchange = 1; 1151 } else 1152 com_loadchannelregs(sc); 1153 } 1154 } 1155 1156 void 1157 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1158 { 1159 u_char combits; 1160 1161 combits = 0; 1162 if (ISSET(ttybits, TIOCM_DTR)) 1163 SET(combits, MCR_DTR); 1164 if (ISSET(ttybits, TIOCM_RTS)) 1165 SET(combits, MCR_RTS); 1166 1167 switch (how) { 1168 case TIOCMBIC: 1169 CLR(sc->sc_mcr, combits); 1170 break; 1171 1172 case TIOCMBIS: 1173 SET(sc->sc_mcr, combits); 1174 break; 1175 1176 case TIOCMSET: 1177 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1178 SET(sc->sc_mcr, combits); 1179 break; 1180 } 1181 1182 if (!sc->sc_heldchange) { 1183 if (sc->sc_tx_busy) { 1184 sc->sc_heldtbc = sc->sc_tbc; 1185 sc->sc_tbc = 0; 1186 sc->sc_heldchange = 1; 1187 } else 1188 com_loadchannelregs(sc); 1189 } 1190 } 1191 1192 int 1193 com_to_tiocm(struct com_softc *sc) 1194 { 1195 u_char combits; 1196 int ttybits = 0; 1197 1198 combits = sc->sc_mcr; 1199 if (ISSET(combits, MCR_DTR)) 1200 SET(ttybits, TIOCM_DTR); 1201 if (ISSET(combits, MCR_RTS)) 1202 SET(ttybits, TIOCM_RTS); 1203 1204 combits = sc->sc_msr; 1205 if (ISSET(combits, MSR_DCD)) 1206 SET(ttybits, TIOCM_CD); 1207 if (ISSET(combits, MSR_CTS)) 1208 SET(ttybits, TIOCM_CTS); 1209 if (ISSET(combits, MSR_DSR)) 1210 SET(ttybits, TIOCM_DSR); 1211 if (ISSET(combits, MSR_RI | MSR_TERI)) 1212 SET(ttybits, TIOCM_RI); 1213 1214 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1215 SET(ttybits, TIOCM_LE); 1216 1217 return (ttybits); 1218 } 1219 1220 static u_char 1221 cflag2lcr(tcflag_t cflag) 1222 { 1223 u_char lcr = 0; 1224 1225 switch (ISSET(cflag, CSIZE)) { 1226 case CS5: 1227 SET(lcr, LCR_5BITS); 1228 break; 1229 case CS6: 1230 SET(lcr, LCR_6BITS); 1231 break; 1232 case CS7: 1233 SET(lcr, LCR_7BITS); 1234 break; 1235 case CS8: 1236 SET(lcr, LCR_8BITS); 1237 break; 1238 } 1239 if (ISSET(cflag, PARENB)) { 1240 SET(lcr, LCR_PENAB); 1241 if (!ISSET(cflag, PARODD)) 1242 SET(lcr, LCR_PEVEN); 1243 } 1244 if (ISSET(cflag, CSTOPB)) 1245 SET(lcr, LCR_STOPB); 1246 1247 return (lcr); 1248 } 1249 1250 int 1251 comparam(struct tty *tp, struct termios *t) 1252 { 1253 struct com_softc *sc = 1254 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1255 int ospeed; 1256 u_char lcr; 1257 1258 if (COM_ISALIVE(sc) == 0) 1259 return (EIO); 1260 1261 #ifdef COM_HAYESP 1262 if (sc->sc_type == COM_TYPE_HAYESP) { 1263 int prescaler, speed; 1264 1265 /* 1266 * Calculate UART clock prescaler. It should be in 1267 * range of 0 .. 3. 1268 */ 1269 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1270 prescaler++, speed /= 2) 1271 if ((ospeed = comspeed(speed, sc->sc_frequency, 1272 sc->sc_type)) > 0) 1273 break; 1274 1275 if (prescaler == 4) 1276 return (EINVAL); 1277 sc->sc_prescaler = prescaler; 1278 } else 1279 #endif 1280 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1281 1282 /* Check requested parameters. */ 1283 if (ospeed < 0) 1284 return (EINVAL); 1285 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1286 return (EINVAL); 1287 1288 /* 1289 * For the console, always force CLOCAL and !HUPCL, so that the port 1290 * is always active. 1291 */ 1292 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1293 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1294 SET(t->c_cflag, CLOCAL); 1295 CLR(t->c_cflag, HUPCL); 1296 } 1297 1298 /* 1299 * If there were no changes, don't do anything. This avoids dropping 1300 * input and improves performance when all we did was frob things like 1301 * VMIN and VTIME. 1302 */ 1303 if (tp->t_ospeed == t->c_ospeed && 1304 tp->t_cflag == t->c_cflag) 1305 return (0); 1306 1307 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1308 1309 mutex_spin_enter(&sc->sc_lock); 1310 1311 sc->sc_lcr = lcr; 1312 1313 /* 1314 * If we're not in a mode that assumes a connection is present, then 1315 * ignore carrier changes. 1316 */ 1317 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1318 sc->sc_msr_dcd = 0; 1319 else 1320 sc->sc_msr_dcd = MSR_DCD; 1321 /* 1322 * Set the flow control pins depending on the current flow control 1323 * mode. 1324 */ 1325 if (ISSET(t->c_cflag, CRTSCTS)) { 1326 sc->sc_mcr_dtr = MCR_DTR; 1327 sc->sc_mcr_rts = MCR_RTS; 1328 sc->sc_msr_cts = MSR_CTS; 1329 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1330 } else if (ISSET(t->c_cflag, MDMBUF)) { 1331 /* 1332 * For DTR/DCD flow control, make sure we don't toggle DTR for 1333 * carrier detection. 1334 */ 1335 sc->sc_mcr_dtr = 0; 1336 sc->sc_mcr_rts = MCR_DTR; 1337 sc->sc_msr_cts = MSR_DCD; 1338 sc->sc_efr = 0; 1339 } else { 1340 /* 1341 * If no flow control, then always set RTS. This will make 1342 * the other side happy if it mistakenly thinks we're doing 1343 * RTS/CTS flow control. 1344 */ 1345 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1346 sc->sc_mcr_rts = 0; 1347 sc->sc_msr_cts = 0; 1348 sc->sc_efr = 0; 1349 if (ISSET(sc->sc_mcr, MCR_DTR)) 1350 SET(sc->sc_mcr, MCR_RTS); 1351 else 1352 CLR(sc->sc_mcr, MCR_RTS); 1353 } 1354 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1355 1356 #if 0 1357 if (ospeed == 0) 1358 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1359 else 1360 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1361 #endif 1362 1363 sc->sc_dlbl = ospeed; 1364 sc->sc_dlbh = ospeed >> 8; 1365 1366 /* 1367 * Set the FIFO threshold based on the receive speed. 1368 * 1369 * * If it's a low speed, it's probably a mouse or some other 1370 * interactive device, so set the threshold low. 1371 * * If it's a high speed, trim the trigger level down to prevent 1372 * overflows. 1373 * * Otherwise set it a bit higher. 1374 */ 1375 if (sc->sc_type == COM_TYPE_HAYESP) 1376 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1377 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1378 if (t->c_ospeed <= 1200) 1379 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1380 else if (t->c_ospeed <= 38400) 1381 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1382 else 1383 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1384 } else 1385 sc->sc_fifo = 0; 1386 1387 /* And copy to tty. */ 1388 tp->t_ispeed = t->c_ospeed; 1389 tp->t_ospeed = t->c_ospeed; 1390 tp->t_cflag = t->c_cflag; 1391 1392 if (!sc->sc_heldchange) { 1393 if (sc->sc_tx_busy) { 1394 sc->sc_heldtbc = sc->sc_tbc; 1395 sc->sc_tbc = 0; 1396 sc->sc_heldchange = 1; 1397 } else 1398 com_loadchannelregs(sc); 1399 } 1400 1401 if (!ISSET(t->c_cflag, CHWFLOW)) { 1402 /* Disable the high water mark. */ 1403 sc->sc_r_hiwat = 0; 1404 sc->sc_r_lowat = 0; 1405 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1406 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1407 com_schedrx(sc); 1408 } 1409 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1410 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1411 com_hwiflow(sc); 1412 } 1413 } else { 1414 sc->sc_r_hiwat = com_rbuf_hiwat; 1415 sc->sc_r_lowat = com_rbuf_lowat; 1416 } 1417 1418 mutex_spin_exit(&sc->sc_lock); 1419 1420 /* 1421 * Update the tty layer's idea of the carrier bit, in case we changed 1422 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1423 * explicit request. 1424 */ 1425 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1426 1427 #ifdef COM_DEBUG 1428 if (com_debug) 1429 comstatus(sc, "comparam "); 1430 #endif 1431 1432 if (!ISSET(t->c_cflag, CHWFLOW)) { 1433 if (sc->sc_tx_stopped) { 1434 sc->sc_tx_stopped = 0; 1435 comstart(tp); 1436 } 1437 } 1438 1439 return (0); 1440 } 1441 1442 void 1443 com_iflush(struct com_softc *sc) 1444 { 1445 struct com_regs *regsp = &sc->sc_regs; 1446 #ifdef DIAGNOSTIC 1447 int reg; 1448 #endif 1449 int timo; 1450 1451 #ifdef DIAGNOSTIC 1452 reg = 0xffff; 1453 #endif 1454 timo = 50000; 1455 /* flush any pending I/O */ 1456 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1457 && --timo) 1458 #ifdef DIAGNOSTIC 1459 reg = 1460 #else 1461 (void) 1462 #endif 1463 CSR_READ_1(regsp, COM_REG_RXDATA); 1464 #ifdef DIAGNOSTIC 1465 if (!timo) 1466 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1467 #endif 1468 } 1469 1470 void 1471 com_loadchannelregs(struct com_softc *sc) 1472 { 1473 struct com_regs *regsp = &sc->sc_regs; 1474 1475 /* XXXXX necessary? */ 1476 com_iflush(sc); 1477 1478 if (sc->sc_type == COM_TYPE_PXA2x0) 1479 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1480 else 1481 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1482 1483 if (sc->sc_type == COM_TYPE_OMAP) { 1484 /* disable before changing settings */ 1485 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1486 } 1487 1488 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1489 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1490 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1491 /* no EFR on alchemy */ 1492 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1493 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1494 } 1495 if (sc->sc_type == COM_TYPE_AU1x00) { 1496 /* alchemy has single separate 16-bit clock divisor register */ 1497 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1498 (sc->sc_dlbh << 8)); 1499 } else { 1500 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1501 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1502 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1503 } 1504 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1505 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1506 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1507 #ifdef COM_HAYESP 1508 if (sc->sc_type == COM_TYPE_HAYESP) { 1509 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1510 HAYESP_SETPRESCALER); 1511 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1512 sc->sc_prescaler); 1513 } 1514 #endif 1515 if (sc->sc_type == COM_TYPE_OMAP) { 1516 /* setup the fifos. the FCR value is not used as long 1517 as SCR[6] and SCR[7] are 0, which they are at reset 1518 and we never touch the SCR register */ 1519 uint8_t rx_fifo_trig = 40; 1520 uint8_t tx_fifo_trig = 60; 1521 uint8_t rx_start = 8; 1522 uint8_t rx_halt = 60; 1523 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1524 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1525 1526 /* enable access to TCR & TLR */ 1527 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1528 1529 /* write tcr and tlr values */ 1530 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1531 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1532 1533 /* disable access to TCR & TLR */ 1534 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1535 1536 /* enable again, but mode is based on speed */ 1537 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1538 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1539 } else { 1540 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1541 } 1542 } 1543 1544 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1545 } 1546 1547 int 1548 comhwiflow(struct tty *tp, int block) 1549 { 1550 struct com_softc *sc = 1551 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1552 1553 if (COM_ISALIVE(sc) == 0) 1554 return (0); 1555 1556 if (sc->sc_mcr_rts == 0) 1557 return (0); 1558 1559 mutex_spin_enter(&sc->sc_lock); 1560 1561 if (block) { 1562 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1563 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1564 com_hwiflow(sc); 1565 } 1566 } else { 1567 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1568 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1569 com_schedrx(sc); 1570 } 1571 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1572 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1573 com_hwiflow(sc); 1574 } 1575 } 1576 1577 mutex_spin_exit(&sc->sc_lock); 1578 return (1); 1579 } 1580 1581 /* 1582 * (un)block input via hw flowcontrol 1583 */ 1584 void 1585 com_hwiflow(struct com_softc *sc) 1586 { 1587 struct com_regs *regsp= &sc->sc_regs; 1588 1589 if (sc->sc_mcr_rts == 0) 1590 return; 1591 1592 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1593 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1594 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1595 } else { 1596 SET(sc->sc_mcr, sc->sc_mcr_rts); 1597 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1598 } 1599 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1600 } 1601 1602 1603 void 1604 comstart(struct tty *tp) 1605 { 1606 struct com_softc *sc = 1607 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1608 struct com_regs *regsp = &sc->sc_regs; 1609 int s; 1610 1611 if (COM_ISALIVE(sc) == 0) 1612 return; 1613 1614 s = spltty(); 1615 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1616 goto out; 1617 if (sc->sc_tx_stopped) 1618 goto out; 1619 if (!ttypull(tp)) 1620 goto out; 1621 1622 /* Grab the first contiguous region of buffer space. */ 1623 { 1624 u_char *tba; 1625 int tbc; 1626 1627 tba = tp->t_outq.c_cf; 1628 tbc = ndqb(&tp->t_outq, 0); 1629 1630 mutex_spin_enter(&sc->sc_lock); 1631 1632 sc->sc_tba = tba; 1633 sc->sc_tbc = tbc; 1634 } 1635 1636 SET(tp->t_state, TS_BUSY); 1637 sc->sc_tx_busy = 1; 1638 1639 /* Enable transmit completion interrupts if necessary. */ 1640 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1641 SET(sc->sc_ier, IER_ETXRDY); 1642 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1643 } 1644 1645 /* Output the first chunk of the contiguous buffer. */ 1646 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1647 u_int n; 1648 1649 n = sc->sc_tbc; 1650 if (n > sc->sc_fifolen) 1651 n = sc->sc_fifolen; 1652 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1653 sc->sc_tbc -= n; 1654 sc->sc_tba += n; 1655 } 1656 1657 mutex_spin_exit(&sc->sc_lock); 1658 out: 1659 splx(s); 1660 return; 1661 } 1662 1663 /* 1664 * Stop output on a line. 1665 */ 1666 void 1667 comstop(struct tty *tp, int flag) 1668 { 1669 struct com_softc *sc = 1670 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1671 1672 mutex_spin_enter(&sc->sc_lock); 1673 if (ISSET(tp->t_state, TS_BUSY)) { 1674 /* Stop transmitting at the next chunk. */ 1675 sc->sc_tbc = 0; 1676 sc->sc_heldtbc = 0; 1677 if (!ISSET(tp->t_state, TS_TTSTOP)) 1678 SET(tp->t_state, TS_FLUSH); 1679 } 1680 mutex_spin_exit(&sc->sc_lock); 1681 } 1682 1683 void 1684 comdiag(void *arg) 1685 { 1686 struct com_softc *sc = arg; 1687 int overflows, floods; 1688 1689 mutex_spin_enter(&sc->sc_lock); 1690 overflows = sc->sc_overflows; 1691 sc->sc_overflows = 0; 1692 floods = sc->sc_floods; 1693 sc->sc_floods = 0; 1694 sc->sc_errors = 0; 1695 mutex_spin_exit(&sc->sc_lock); 1696 1697 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1698 device_xname(sc->sc_dev), 1699 overflows, overflows == 1 ? "" : "s", 1700 floods, floods == 1 ? "" : "s"); 1701 } 1702 1703 integrate void 1704 com_rxsoft(struct com_softc *sc, struct tty *tp) 1705 { 1706 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1707 u_char *get, *end; 1708 u_int cc, scc; 1709 u_char lsr; 1710 int code; 1711 1712 end = sc->sc_ebuf; 1713 get = sc->sc_rbget; 1714 scc = cc = com_rbuf_size - sc->sc_rbavail; 1715 1716 if (cc == com_rbuf_size) { 1717 sc->sc_floods++; 1718 if (sc->sc_errors++ == 0) 1719 callout_reset(&sc->sc_diag_callout, 60 * hz, 1720 comdiag, sc); 1721 } 1722 1723 /* If not yet open, drop the entire buffer content here */ 1724 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1725 get += cc << 1; 1726 if (get >= end) 1727 get -= com_rbuf_size << 1; 1728 cc = 0; 1729 } 1730 while (cc) { 1731 code = get[0]; 1732 lsr = get[1]; 1733 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1734 if (ISSET(lsr, LSR_OE)) { 1735 sc->sc_overflows++; 1736 if (sc->sc_errors++ == 0) 1737 callout_reset(&sc->sc_diag_callout, 1738 60 * hz, comdiag, sc); 1739 } 1740 if (ISSET(lsr, LSR_BI | LSR_FE)) 1741 SET(code, TTY_FE); 1742 if (ISSET(lsr, LSR_PE)) 1743 SET(code, TTY_PE); 1744 } 1745 if ((*rint)(code, tp) == -1) { 1746 /* 1747 * The line discipline's buffer is out of space. 1748 */ 1749 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1750 /* 1751 * We're either not using flow control, or the 1752 * line discipline didn't tell us to block for 1753 * some reason. Either way, we have no way to 1754 * know when there's more space available, so 1755 * just drop the rest of the data. 1756 */ 1757 get += cc << 1; 1758 if (get >= end) 1759 get -= com_rbuf_size << 1; 1760 cc = 0; 1761 } else { 1762 /* 1763 * Don't schedule any more receive processing 1764 * until the line discipline tells us there's 1765 * space available (through comhwiflow()). 1766 * Leave the rest of the data in the input 1767 * buffer. 1768 */ 1769 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1770 } 1771 break; 1772 } 1773 get += 2; 1774 if (get >= end) 1775 get = sc->sc_rbuf; 1776 cc--; 1777 } 1778 1779 if (cc != scc) { 1780 sc->sc_rbget = get; 1781 mutex_spin_enter(&sc->sc_lock); 1782 1783 cc = sc->sc_rbavail += scc - cc; 1784 /* Buffers should be ok again, release possible block. */ 1785 if (cc >= sc->sc_r_lowat) { 1786 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1787 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1788 SET(sc->sc_ier, IER_ERXRDY); 1789 #ifdef COM_PXA2X0 1790 if (sc->sc_type == COM_TYPE_PXA2x0) 1791 SET(sc->sc_ier, IER_ERXTOUT); 1792 #endif 1793 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1794 } 1795 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1796 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1797 com_hwiflow(sc); 1798 } 1799 } 1800 mutex_spin_exit(&sc->sc_lock); 1801 } 1802 } 1803 1804 integrate void 1805 com_txsoft(struct com_softc *sc, struct tty *tp) 1806 { 1807 1808 CLR(tp->t_state, TS_BUSY); 1809 if (ISSET(tp->t_state, TS_FLUSH)) 1810 CLR(tp->t_state, TS_FLUSH); 1811 else 1812 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1813 (*tp->t_linesw->l_start)(tp); 1814 } 1815 1816 integrate void 1817 com_stsoft(struct com_softc *sc, struct tty *tp) 1818 { 1819 u_char msr, delta; 1820 1821 mutex_spin_enter(&sc->sc_lock); 1822 msr = sc->sc_msr; 1823 delta = sc->sc_msr_delta; 1824 sc->sc_msr_delta = 0; 1825 mutex_spin_exit(&sc->sc_lock); 1826 1827 if (ISSET(delta, sc->sc_msr_dcd)) { 1828 /* 1829 * Inform the tty layer that carrier detect changed. 1830 */ 1831 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1832 } 1833 1834 if (ISSET(delta, sc->sc_msr_cts)) { 1835 /* Block or unblock output according to flow control. */ 1836 if (ISSET(msr, sc->sc_msr_cts)) { 1837 sc->sc_tx_stopped = 0; 1838 (*tp->t_linesw->l_start)(tp); 1839 } else { 1840 sc->sc_tx_stopped = 1; 1841 } 1842 } 1843 1844 #ifdef COM_DEBUG 1845 if (com_debug) 1846 comstatus(sc, "com_stsoft"); 1847 #endif 1848 } 1849 1850 void 1851 comsoft(void *arg) 1852 { 1853 struct com_softc *sc = arg; 1854 struct tty *tp; 1855 1856 if (COM_ISALIVE(sc) == 0) 1857 return; 1858 1859 tp = sc->sc_tty; 1860 1861 if (sc->sc_rx_ready) { 1862 sc->sc_rx_ready = 0; 1863 com_rxsoft(sc, tp); 1864 } 1865 1866 if (sc->sc_st_check) { 1867 sc->sc_st_check = 0; 1868 com_stsoft(sc, tp); 1869 } 1870 1871 if (sc->sc_tx_done) { 1872 sc->sc_tx_done = 0; 1873 com_txsoft(sc, tp); 1874 } 1875 } 1876 1877 int 1878 comintr(void *arg) 1879 { 1880 struct com_softc *sc = arg; 1881 struct com_regs *regsp = &sc->sc_regs; 1882 1883 u_char *put, *end; 1884 u_int cc; 1885 u_char lsr, iir; 1886 1887 if (COM_ISALIVE(sc) == 0) 1888 return (0); 1889 1890 KASSERT(regsp != NULL); 1891 1892 mutex_spin_enter(&sc->sc_lock); 1893 iir = CSR_READ_1(regsp, COM_REG_IIR); 1894 if (ISSET(iir, IIR_NOPEND)) { 1895 mutex_spin_exit(&sc->sc_lock); 1896 return (0); 1897 } 1898 1899 end = sc->sc_ebuf; 1900 put = sc->sc_rbput; 1901 cc = sc->sc_rbavail; 1902 1903 again: do { 1904 u_char msr, delta; 1905 1906 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1907 if (ISSET(lsr, LSR_BI)) { 1908 int cn_trapped = 0; 1909 1910 cn_check_magic(sc->sc_tty->t_dev, 1911 CNC_BREAK, com_cnm_state); 1912 if (cn_trapped) 1913 continue; 1914 #if defined(KGDB) && !defined(DDB) 1915 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1916 kgdb_connect(1); 1917 continue; 1918 } 1919 #endif 1920 } 1921 1922 if (ISSET(lsr, LSR_RCV_MASK) && 1923 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1924 while (cc > 0) { 1925 int cn_trapped = 0; 1926 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1927 put[1] = lsr; 1928 cn_check_magic(sc->sc_tty->t_dev, 1929 put[0], com_cnm_state); 1930 if (cn_trapped) 1931 goto next; 1932 put += 2; 1933 if (put >= end) 1934 put = sc->sc_rbuf; 1935 cc--; 1936 next: 1937 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1938 if (!ISSET(lsr, LSR_RCV_MASK)) 1939 break; 1940 } 1941 1942 /* 1943 * Current string of incoming characters ended because 1944 * no more data was available or we ran out of space. 1945 * Schedule a receive event if any data was received. 1946 * If we're out of space, turn off receive interrupts. 1947 */ 1948 sc->sc_rbput = put; 1949 sc->sc_rbavail = cc; 1950 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1951 sc->sc_rx_ready = 1; 1952 1953 /* 1954 * See if we are in danger of overflowing a buffer. If 1955 * so, use hardware flow control to ease the pressure. 1956 */ 1957 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1958 cc < sc->sc_r_hiwat) { 1959 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1960 com_hwiflow(sc); 1961 } 1962 1963 /* 1964 * If we're out of space, disable receive interrupts 1965 * until the queue has drained a bit. 1966 */ 1967 if (!cc) { 1968 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1969 #ifdef COM_PXA2X0 1970 if (sc->sc_type == COM_TYPE_PXA2x0) 1971 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 1972 else 1973 #endif 1974 CLR(sc->sc_ier, IER_ERXRDY); 1975 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1976 } 1977 } else { 1978 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 1979 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 1980 continue; 1981 } 1982 } 1983 1984 msr = CSR_READ_1(regsp, COM_REG_MSR); 1985 delta = msr ^ sc->sc_msr; 1986 sc->sc_msr = msr; 1987 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 1988 (delta & MSR_DCD)) { 1989 mutex_spin_enter(&timecounter_lock); 1990 pps_capture(&sc->sc_pps_state); 1991 pps_event(&sc->sc_pps_state, 1992 (msr & MSR_DCD) ? 1993 PPS_CAPTUREASSERT : 1994 PPS_CAPTURECLEAR); 1995 mutex_spin_exit(&timecounter_lock); 1996 } 1997 1998 /* 1999 * Process normal status changes 2000 */ 2001 if (ISSET(delta, sc->sc_msr_mask)) { 2002 SET(sc->sc_msr_delta, delta); 2003 2004 /* 2005 * Stop output immediately if we lose the output 2006 * flow control signal or carrier detect. 2007 */ 2008 if (ISSET(~msr, sc->sc_msr_mask)) { 2009 sc->sc_tbc = 0; 2010 sc->sc_heldtbc = 0; 2011 #ifdef COM_DEBUG 2012 if (com_debug) 2013 comstatus(sc, "comintr "); 2014 #endif 2015 } 2016 2017 sc->sc_st_check = 1; 2018 } 2019 } while (!ISSET((iir = 2020 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2021 /* 2022 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2023 * by IIR read, so we can't do this way: `process all interrupts, 2024 * then do TX if possible'. 2025 */ 2026 (iir & IIR_IMASK) != IIR_TXRDY); 2027 2028 /* 2029 * Read LSR again, since there may be an interrupt between 2030 * the last LSR read and IIR read above. 2031 */ 2032 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2033 2034 /* 2035 * See if data can be transmitted as well. 2036 * Schedule tx done event if no data left 2037 * and tty was marked busy. 2038 */ 2039 if (ISSET(lsr, LSR_TXRDY)) { 2040 /* 2041 * If we've delayed a parameter change, do it now, and restart 2042 * output. 2043 */ 2044 if (sc->sc_heldchange) { 2045 com_loadchannelregs(sc); 2046 sc->sc_heldchange = 0; 2047 sc->sc_tbc = sc->sc_heldtbc; 2048 sc->sc_heldtbc = 0; 2049 } 2050 2051 /* Output the next chunk of the contiguous buffer, if any. */ 2052 if (sc->sc_tbc > 0) { 2053 u_int n; 2054 2055 n = sc->sc_tbc; 2056 if (n > sc->sc_fifolen) 2057 n = sc->sc_fifolen; 2058 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2059 sc->sc_tbc -= n; 2060 sc->sc_tba += n; 2061 } else { 2062 /* Disable transmit completion interrupts if necessary. */ 2063 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2064 CLR(sc->sc_ier, IER_ETXRDY); 2065 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2066 } 2067 if (sc->sc_tx_busy) { 2068 sc->sc_tx_busy = 0; 2069 sc->sc_tx_done = 1; 2070 } 2071 } 2072 } 2073 2074 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2075 goto again; 2076 2077 mutex_spin_exit(&sc->sc_lock); 2078 2079 /* Wake up the poller. */ 2080 softint_schedule(sc->sc_si); 2081 2082 #ifdef RND_COM 2083 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2084 #endif 2085 2086 return (1); 2087 } 2088 2089 /* 2090 * The following functions are polled getc and putc routines, shared 2091 * by the console and kgdb glue. 2092 * 2093 * The read-ahead code is so that you can detect pending in-band 2094 * cn_magic in polled mode while doing output rather than having to 2095 * wait until the kernel decides it needs input. 2096 */ 2097 2098 #define MAX_READAHEAD 20 2099 static int com_readahead[MAX_READAHEAD]; 2100 static int com_readaheadcount = 0; 2101 2102 int 2103 com_common_getc(dev_t dev, struct com_regs *regsp) 2104 { 2105 int s = splserial(); 2106 u_char stat, c; 2107 2108 /* got a character from reading things earlier */ 2109 if (com_readaheadcount > 0) { 2110 int i; 2111 2112 c = com_readahead[0]; 2113 for (i = 1; i < com_readaheadcount; i++) { 2114 com_readahead[i-1] = com_readahead[i]; 2115 } 2116 com_readaheadcount--; 2117 splx(s); 2118 return (c); 2119 } 2120 2121 /* block until a character becomes available */ 2122 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2123 ; 2124 2125 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2126 stat = CSR_READ_1(regsp, COM_REG_IIR); 2127 { 2128 int cn_trapped = 0; /* unused */ 2129 #ifdef DDB 2130 extern int db_active; 2131 if (!db_active) 2132 #endif 2133 cn_check_magic(dev, c, com_cnm_state); 2134 } 2135 splx(s); 2136 return (c); 2137 } 2138 2139 static void 2140 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2141 { 2142 int s = splserial(); 2143 int cin, stat, timo; 2144 2145 if (com_readaheadcount < MAX_READAHEAD 2146 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2147 int cn_trapped = 0; 2148 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2149 stat = CSR_READ_1(regsp, COM_REG_IIR); 2150 cn_check_magic(dev, cin, com_cnm_state); 2151 com_readahead[com_readaheadcount++] = cin; 2152 } 2153 2154 /* wait for any pending transmission to finish */ 2155 timo = 150000; 2156 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2157 continue; 2158 2159 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2160 COM_BARRIER(regsp, BR | BW); 2161 2162 splx(s); 2163 } 2164 2165 /* 2166 * Initialize UART for use as console or KGDB line. 2167 */ 2168 int 2169 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2170 tcflag_t cflag) 2171 { 2172 2173 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2174 ®sp->cr_ioh)) 2175 return (ENOMEM); /* ??? */ 2176 2177 if (type == COM_TYPE_OMAP) { 2178 /* disable before changing settings */ 2179 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2180 } 2181 2182 rate = comspeed(rate, frequency, type); 2183 if (__predict_true(rate != -1)) { 2184 if (type == COM_TYPE_AU1x00) { 2185 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2186 } else { 2187 /* no EFR on alchemy */ 2188 if (type != COM_TYPE_16550_NOERS) { 2189 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2190 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2191 } 2192 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2193 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2194 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2195 } 2196 } 2197 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2198 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2199 CSR_WRITE_1(regsp, COM_REG_FIFO, 2200 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2201 2202 if (type == COM_TYPE_OMAP) { 2203 /* setup the fifos. the FCR value is not used as long 2204 as SCR[6] and SCR[7] are 0, which they are at reset 2205 and we never touch the SCR register */ 2206 uint8_t rx_fifo_trig = 40; 2207 uint8_t tx_fifo_trig = 60; 2208 uint8_t rx_start = 8; 2209 uint8_t rx_halt = 60; 2210 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2211 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2212 2213 /* enable access to TCR & TLR */ 2214 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2215 2216 /* write tcr and tlr values */ 2217 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2218 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2219 2220 /* disable access to TCR & TLR */ 2221 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2222 2223 /* enable again, but mode is based on speed */ 2224 if (rate > 230400) { 2225 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2226 } else { 2227 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2228 } 2229 } 2230 2231 #ifdef COM_PXA2X0 2232 if (type == COM_TYPE_PXA2x0) 2233 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2234 else 2235 #endif 2236 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2237 2238 return (0); 2239 } 2240 2241 int 2242 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2243 tcflag_t cflag) 2244 { 2245 int res; 2246 2247 comcons_info.regs = *regsp; 2248 2249 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2250 if (res) 2251 return (res); 2252 2253 cn_tab = &comcons; 2254 cn_init_magic(&com_cnm_state); 2255 cn_set_magic("\047\001"); /* default magic is BREAK */ 2256 2257 comcons_info.frequency = frequency; 2258 comcons_info.type = type; 2259 comcons_info.rate = rate; 2260 comcons_info.cflag = cflag; 2261 2262 return (0); 2263 } 2264 2265 int 2266 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2267 int type, tcflag_t cflag) 2268 { 2269 struct com_regs regs; 2270 2271 memset(®s, 0, sizeof regs); 2272 regs.cr_iot = iot; 2273 regs.cr_iobase = iobase; 2274 regs.cr_nports = COM_NPORTS; 2275 #ifdef COM_REGMAP 2276 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2277 #endif 2278 2279 return comcnattach1(®s, rate, frequency, type, cflag); 2280 } 2281 2282 static int 2283 comcnreattach(void) 2284 { 2285 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2286 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2287 } 2288 2289 int 2290 comcngetc(dev_t dev) 2291 { 2292 2293 return (com_common_getc(dev, &comcons_info.regs)); 2294 } 2295 2296 /* 2297 * Console kernel output character routine. 2298 */ 2299 void 2300 comcnputc(dev_t dev, int c) 2301 { 2302 2303 com_common_putc(dev, &comcons_info.regs, c); 2304 } 2305 2306 void 2307 comcnpollc(dev_t dev, int on) 2308 { 2309 2310 } 2311 2312 #ifdef KGDB 2313 int 2314 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2315 tcflag_t cflag) 2316 { 2317 int res; 2318 2319 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2320 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2321 #if !defined(DDB) 2322 return (EBUSY); /* cannot share with console */ 2323 #else 2324 comkgdbregs = *regsp; 2325 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2326 #endif 2327 } else { 2328 comkgdbregs = *regsp; 2329 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2330 if (res) 2331 return (res); 2332 2333 /* 2334 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2335 * expects this to be initialized 2336 */ 2337 cn_init_magic(&com_cnm_state); 2338 cn_set_magic("\047\001"); 2339 } 2340 2341 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2342 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2343 2344 return (0); 2345 } 2346 2347 int 2348 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2349 int frequency, int type, tcflag_t cflag) 2350 { 2351 struct com_regs regs; 2352 2353 regs.cr_iot = iot; 2354 regs.cr_nports = COM_NPORTS; 2355 regs.cr_iobase = iobase; 2356 #ifdef COM_REGMAP 2357 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2358 #endif 2359 2360 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2361 } 2362 2363 /* ARGSUSED */ 2364 int 2365 com_kgdb_getc(void *arg) 2366 { 2367 2368 return (com_common_getc(NODEV, &comkgdbregs)); 2369 } 2370 2371 /* ARGSUSED */ 2372 void 2373 com_kgdb_putc(void *arg, int c) 2374 { 2375 2376 com_common_putc(NODEV, &comkgdbregs, c); 2377 } 2378 #endif /* KGDB */ 2379 2380 /* helper function to identify the com ports used by 2381 console or KGDB (and not yet autoconf attached) */ 2382 int 2383 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2384 { 2385 bus_space_handle_t help; 2386 2387 if (!comconsattached && 2388 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2389 iobase == comcons_info.regs.cr_iobase) 2390 help = comcons_info.regs.cr_ioh; 2391 #ifdef KGDB 2392 else if (!com_kgdb_attached && 2393 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2394 iobase == comkgdbregs.cr_iobase) 2395 help = comkgdbregs.cr_ioh; 2396 #endif 2397 else 2398 return (0); 2399 2400 if (ioh) 2401 *ioh = help; 2402 return (1); 2403 } 2404 2405 /* 2406 * this routine exists to serve as a shutdown hook for systems that 2407 * have firmware which doesn't interact properly with a com device in 2408 * FIFO mode. 2409 */ 2410 bool 2411 com_cleanup(device_t self, int how) 2412 { 2413 struct com_softc *sc = device_private(self); 2414 2415 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2416 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2417 2418 return true; 2419 } 2420 2421 bool 2422 com_suspend(device_t self, const pmf_qual_t *qual) 2423 { 2424 struct com_softc *sc = device_private(self); 2425 2426 #if 0 2427 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2428 cn_tab = &comcons_suspend; 2429 #endif 2430 2431 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2432 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2433 2434 return true; 2435 } 2436 2437 bool 2438 com_resume(device_t self, const pmf_qual_t *qual) 2439 { 2440 struct com_softc *sc = device_private(self); 2441 2442 mutex_spin_enter(&sc->sc_lock); 2443 com_loadchannelregs(sc); 2444 mutex_spin_exit(&sc->sc_lock); 2445 2446 return true; 2447 } 2448
Indexes created Mon Oct 20 20:10:13 GMT 2025