com.c revision 1.310
1 /* $NetBSD: com.c,v 1.310 2013/05/01 07:38:00 mlelstv Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.310 2013/05/01 07:38:00 mlelstv Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 } while (/* CONSTCOND */ 0) 96 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/ioctl.h> 100 #include <sys/select.h> 101 #include <sys/poll.h> 102 #include <sys/tty.h> 103 #include <sys/proc.h> 104 #include <sys/conf.h> 105 #include <sys/file.h> 106 #include <sys/uio.h> 107 #include <sys/kernel.h> 108 #include <sys/syslog.h> 109 #include <sys/device.h> 110 #include <sys/malloc.h> 111 #include <sys/timepps.h> 112 #include <sys/vnode.h> 113 #include <sys/kauth.h> 114 #include <sys/intr.h> 115 #ifdef RND_COM 116 #include <sys/rnd.h> 117 #endif 118 119 120 #include <sys/bus.h> 121 122 #include <dev/ic/comreg.h> 123 #include <dev/ic/comvar.h> 124 #include <dev/ic/ns16550reg.h> 125 #include <dev/ic/st16650reg.h> 126 #ifdef COM_HAYESP 127 #include <dev/ic/hayespreg.h> 128 #endif 129 #define com_lcr com_cfcr 130 #include <dev/cons.h> 131 132 #ifdef COM_REGMAP 133 #define CSR_WRITE_1(r, o, v) \ 134 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 135 #define CSR_READ_1(r, o) \ 136 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 137 #define CSR_WRITE_2(r, o, v) \ 138 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 139 #define CSR_READ_2(r, o) \ 140 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 141 #define CSR_WRITE_MULTI(r, o, p, n) \ 142 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 143 #else 144 #define CSR_WRITE_1(r, o, v) \ 145 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 146 #define CSR_READ_1(r, o) \ 147 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 148 #define CSR_WRITE_2(r, o, v) \ 149 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 150 #define CSR_READ_2(r, o) \ 151 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 152 #define CSR_WRITE_MULTI(r, o, p, n) \ 153 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 154 #endif 155 156 157 static void com_enable_debugport(struct com_softc *); 158 159 void com_config(struct com_softc *); 160 void com_shutdown(struct com_softc *); 161 int comspeed(long, long, int); 162 static u_char cflag2lcr(tcflag_t); 163 int comparam(struct tty *, struct termios *); 164 void comstart(struct tty *); 165 int comhwiflow(struct tty *, int); 166 167 void com_loadchannelregs(struct com_softc *); 168 void com_hwiflow(struct com_softc *); 169 void com_break(struct com_softc *, int); 170 void com_modem(struct com_softc *, int); 171 void tiocm_to_com(struct com_softc *, u_long, int); 172 int com_to_tiocm(struct com_softc *); 173 void com_iflush(struct com_softc *); 174 175 int com_common_getc(dev_t, struct com_regs *); 176 static void com_common_putc(dev_t, struct com_regs *, int); 177 178 int cominit(struct com_regs *, int, int, int, tcflag_t); 179 180 static int comcnreattach(void); 181 182 int comcngetc(dev_t); 183 void comcnputc(dev_t, int); 184 void comcnpollc(dev_t, int); 185 186 #define integrate static inline 187 void comsoft(void *); 188 integrate void com_rxsoft(struct com_softc *, struct tty *); 189 integrate void com_txsoft(struct com_softc *, struct tty *); 190 integrate void com_stsoft(struct com_softc *, struct tty *); 191 integrate void com_schedrx(struct com_softc *); 192 void comdiag(void *); 193 194 extern struct cfdriver com_cd; 195 196 dev_type_open(comopen); 197 dev_type_close(comclose); 198 dev_type_read(comread); 199 dev_type_write(comwrite); 200 dev_type_ioctl(comioctl); 201 dev_type_stop(comstop); 202 dev_type_tty(comtty); 203 dev_type_poll(compoll); 204 205 static struct comcons_info comcons_info; 206 207 /* 208 * Following are all routines needed for COM to act as console 209 */ 210 static struct consdev comcons = { 211 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 212 NODEV, CN_NORMAL 213 }; 214 215 216 const struct cdevsw com_cdevsw = { 217 comopen, comclose, comread, comwrite, comioctl, 218 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 219 }; 220 221 /* 222 * Make this an option variable one can patch. 223 * But be warned: this must be a power of 2! 224 */ 225 u_int com_rbuf_size = COM_RING_SIZE; 226 227 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 228 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 229 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 230 231 static int comconsattached; 232 static struct cnm_state com_cnm_state; 233 234 #ifdef KGDB 235 #include <sys/kgdb.h> 236 237 static struct com_regs comkgdbregs; 238 static int com_kgdb_attached; 239 240 int com_kgdb_getc(void *); 241 void com_kgdb_putc(void *, int); 242 #endif /* KGDB */ 243 244 #ifdef COM_REGMAP 245 /* initializer for typical 16550-ish hardware */ 246 #define COM_REG_16550 { \ 247 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 248 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 249 /* 16750-specific register set, additional UART status register */ 250 #define COM_REG_16750 { \ 251 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 252 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } 254 255 #ifdef COM_16750 256 const bus_size_t com_std_map[32] = COM_REG_16750; 257 #else 258 const bus_size_t com_std_map[16] = COM_REG_16550; 259 #endif /* COM_16750 */ 260 #endif /* COM_REGMAP */ 261 262 #define COMUNIT_MASK 0x7ffff 263 #define COMDIALOUT_MASK 0x80000 264 265 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 266 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 267 268 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 269 device_is_active((sc)->sc_dev)) 270 271 #define BR BUS_SPACE_BARRIER_READ 272 #define BW BUS_SPACE_BARRIER_WRITE 273 #define COM_BARRIER(r, f) \ 274 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 275 276 /*ARGSUSED*/ 277 int 278 comspeed(long speed, long frequency, int type) 279 { 280 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 281 282 int x, err; 283 int divisor = 16; 284 285 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 286 divisor = 13; 287 } 288 289 #if 0 290 if (speed == 0) 291 return (0); 292 #endif 293 if (speed <= 0) 294 return (-1); 295 x = divrnd(frequency / divisor, speed); 296 if (x <= 0) 297 return (-1); 298 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 299 if (err < 0) 300 err = -err; 301 if (err > COM_TOLERANCE) 302 return (-1); 303 return (x); 304 305 #undef divrnd 306 } 307 308 #ifdef COM_DEBUG 309 int com_debug = 0; 310 311 void comstatus(struct com_softc *, const char *); 312 void 313 comstatus(struct com_softc *sc, const char *str) 314 { 315 struct tty *tp = sc->sc_tty; 316 317 aprint_normal_dev(sc->sc_dev, 318 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 319 str, 320 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 321 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 322 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 323 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 324 sc->sc_tx_stopped ? '+' : '-'); 325 326 aprint_normal_dev(sc->sc_dev, 327 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 328 str, 329 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 330 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 331 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 332 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 333 sc->sc_rx_flags); 334 } 335 #endif 336 337 int 338 com_probe_subr(struct com_regs *regs) 339 { 340 341 /* force access to id reg */ 342 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 343 CSR_WRITE_1(regs, COM_REG_IIR, 0); 344 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 345 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 346 return (0); 347 348 return (1); 349 } 350 351 int 352 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 353 { 354 struct com_regs regs; 355 356 regs.cr_iot = iot; 357 regs.cr_ioh = ioh; 358 #ifdef COM_REGMAP 359 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 360 #endif 361 362 return com_probe_subr(®s); 363 } 364 365 /* 366 * No locking in this routine; it is only called during attach, 367 * or with the port already locked. 368 */ 369 static void 370 com_enable_debugport(struct com_softc *sc) 371 { 372 373 /* Turn on line break interrupt, set carrier. */ 374 sc->sc_ier = IER_ERXRDY; 375 if (sc->sc_type == COM_TYPE_PXA2x0) 376 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 377 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 378 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 379 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 380 } 381 382 void 383 com_attach_subr(struct com_softc *sc) 384 { 385 struct com_regs *regsp = &sc->sc_regs; 386 struct tty *tp; 387 #ifdef COM_16650 388 u_int8_t lcr; 389 #endif 390 const char *fifo_msg = NULL; 391 prop_dictionary_t dict; 392 bool is_console = true; 393 394 aprint_naive("\n"); 395 396 dict = device_properties(sc->sc_dev); 397 prop_dictionary_get_bool(dict, "is_console", &is_console); 398 399 callout_init(&sc->sc_diag_callout, 0); 400 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 401 402 /* Disable interrupts before configuring the device. */ 403 if (sc->sc_type == COM_TYPE_PXA2x0) 404 sc->sc_ier = IER_EUART; 405 else 406 sc->sc_ier = 0; 407 408 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 409 410 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 411 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 412 comconsattached = 1; 413 414 if (cn_tab == NULL && comcnreattach() != 0) { 415 printf("can't re-init serial console @%lx\n", 416 (u_long)comcons_info.regs.cr_iobase); 417 } 418 419 420 /* Make sure the console is always "hardwired". */ 421 delay(10000); /* wait for output to finish */ 422 if (is_console) { 423 SET(sc->sc_hwflags, COM_HW_CONSOLE); 424 } 425 426 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 427 } 428 429 /* Probe for FIFO */ 430 switch (sc->sc_type) { 431 case COM_TYPE_HAYESP: 432 goto fifodone; 433 434 case COM_TYPE_AU1x00: 435 sc->sc_fifolen = 16; 436 fifo_msg = "Au1X00 UART, working fifo"; 437 SET(sc->sc_hwflags, COM_HW_FIFO); 438 goto fifodelay; 439 440 case COM_TYPE_16550_NOERS: 441 sc->sc_fifolen = 16; 442 fifo_msg = "ns16650, no ERS, working fifo"; 443 SET(sc->sc_hwflags, COM_HW_FIFO); 444 goto fifodelay; 445 446 case COM_TYPE_OMAP: 447 sc->sc_fifolen = 64; 448 fifo_msg = "OMAP UART, working fifo"; 449 SET(sc->sc_hwflags, COM_HW_FIFO); 450 goto fifodelay; 451 } 452 453 sc->sc_fifolen = 1; 454 /* look for a NS 16550AF UART with FIFOs */ 455 CSR_WRITE_1(regsp, COM_REG_FIFO, 456 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 457 delay(100); 458 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 459 == IIR_FIFO_MASK) 460 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 461 == FIFO_TRIGGER_14) { 462 SET(sc->sc_hwflags, COM_HW_FIFO); 463 464 #ifdef COM_16650 465 /* 466 * IIR changes into the EFR if LCR is set to LCR_EERS 467 * on 16650s. We also know IIR != 0 at this point. 468 * Write 0 into the EFR, and read it. If the result 469 * is 0, we have a 16650. 470 * 471 * Older 16650s were broken; the test to detect them 472 * is taken from the Linux driver. Apparently 473 * setting DLAB enable gives access to the EFR on 474 * these chips. 475 */ 476 lcr = CSR_READ_1(regsp, COM_REG_LCR); 477 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 478 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 479 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 480 CSR_WRITE_1(regsp, COM_REG_LCR, 481 lcr | LCR_DLAB); 482 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 483 CLR(sc->sc_hwflags, COM_HW_FIFO); 484 sc->sc_fifolen = 0; 485 } else { 486 SET(sc->sc_hwflags, COM_HW_FLOW); 487 sc->sc_fifolen = 32; 488 } 489 } else 490 #endif 491 sc->sc_fifolen = 16; 492 493 #ifdef COM_16650 494 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 495 if (sc->sc_fifolen == 0) 496 fifo_msg = "st16650, broken fifo"; 497 else if (sc->sc_fifolen == 32) 498 fifo_msg = "st16650a, working fifo"; 499 else 500 #endif 501 fifo_msg = "ns16550a, working fifo"; 502 } else 503 fifo_msg = "ns16550, broken fifo"; 504 else 505 fifo_msg = "ns8250 or ns16450, no fifo"; 506 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 507 fifodelay: 508 /* 509 * Some chips will clear down both Tx and Rx FIFOs when zero is 510 * written to com_fifo. If this chip is the console, writing zero 511 * results in some of the chip/FIFO description being lost, so delay 512 * printing it until now. 513 */ 514 delay(10); 515 aprint_normal(": %s\n", fifo_msg); 516 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 517 sc->sc_fifolen = 1; 518 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 519 } 520 521 fifodone: 522 523 tp = tty_alloc(); 524 tp->t_oproc = comstart; 525 tp->t_param = comparam; 526 tp->t_hwiflow = comhwiflow; 527 tp->t_softc = sc; 528 529 sc->sc_tty = tp; 530 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 531 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 532 sc->sc_rbavail = com_rbuf_size; 533 if (sc->sc_rbuf == NULL) { 534 aprint_error_dev(sc->sc_dev, 535 "unable to allocate ring buffer\n"); 536 return; 537 } 538 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 539 540 tty_attach(tp); 541 542 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 543 SET(sc->sc_mcr, MCR_IENABLE); 544 545 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 546 int maj; 547 548 /* locate the major number */ 549 maj = cdevsw_lookup_major(&com_cdevsw); 550 551 tp->t_dev = cn_tab->cn_dev = makedev(maj, 552 device_unit(sc->sc_dev)); 553 554 aprint_normal_dev(sc->sc_dev, "console\n"); 555 } 556 557 #ifdef KGDB 558 /* 559 * Allow kgdb to "take over" this port. If this is 560 * not the console and is the kgdb device, it has 561 * exclusive use. If it's the console _and_ the 562 * kgdb device, it doesn't. 563 */ 564 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 565 regsp->cr_iobase == comkgdbregs.cr_iobase) { 566 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 567 com_kgdb_attached = 1; 568 569 SET(sc->sc_hwflags, COM_HW_KGDB); 570 } 571 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 572 } 573 #endif 574 575 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 576 577 #ifdef RND_COM 578 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 579 RND_TYPE_TTY, 0); 580 #endif 581 582 /* if there are no enable/disable functions, assume the device 583 is always enabled */ 584 if (!sc->enable) 585 sc->enabled = 1; 586 587 com_config(sc); 588 589 SET(sc->sc_hwflags, COM_HW_DEV_OK); 590 } 591 592 void 593 com_config(struct com_softc *sc) 594 { 595 struct com_regs *regsp = &sc->sc_regs; 596 597 /* Disable interrupts before configuring the device. */ 598 if (sc->sc_type == COM_TYPE_PXA2x0) 599 sc->sc_ier = IER_EUART; 600 else 601 sc->sc_ier = 0; 602 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 603 (void) CSR_READ_1(regsp, COM_REG_IIR); 604 605 #ifdef COM_HAYESP 606 /* Look for a Hayes ESP board. */ 607 if (sc->sc_type == COM_TYPE_HAYESP) { 608 609 /* Set 16550 compatibility mode */ 610 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 611 HAYESP_SETMODE); 612 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 613 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 614 HAYESP_MODE_SCALE); 615 616 /* Set RTS/CTS flow control */ 617 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 618 HAYESP_SETFLOWTYPE); 619 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 620 HAYESP_FLOW_RTS); 621 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 622 HAYESP_FLOW_CTS); 623 624 /* Set flow control levels */ 625 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 626 HAYESP_SETRXFLOW); 627 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 628 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 629 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 630 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 631 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 632 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 633 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 634 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 635 } 636 #endif 637 638 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 639 com_enable_debugport(sc); 640 } 641 642 #if 0 643 static int 644 comcngetc_detached(dev_t dev) 645 { 646 return 0; 647 } 648 649 static void 650 comcnputc_detached(dev_t dev, int c) 651 { 652 } 653 #endif 654 655 int 656 com_detach(device_t self, int flags) 657 { 658 struct com_softc *sc = device_private(self); 659 int maj, mn; 660 661 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 662 return EBUSY; 663 664 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 665 (flags & DETACH_SHUTDOWN) != 0) 666 return EBUSY; 667 668 if (sc->disable != NULL && sc->enabled != 0) { 669 (*sc->disable)(sc); 670 sc->enabled = 0; 671 } 672 673 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 674 comconsattached = 0; 675 cn_tab = NULL; 676 } 677 678 /* locate the major number */ 679 maj = cdevsw_lookup_major(&com_cdevsw); 680 681 /* Nuke the vnodes for any open instances. */ 682 mn = device_unit(self); 683 vdevgone(maj, mn, mn, VCHR); 684 685 mn |= COMDIALOUT_MASK; 686 vdevgone(maj, mn, mn, VCHR); 687 688 if (sc->sc_rbuf == NULL) { 689 /* 690 * Ring buffer allocation failed in the com_attach_subr, 691 * only the tty is allocated, and nothing else. 692 */ 693 tty_free(sc->sc_tty); 694 return 0; 695 } 696 697 /* Free the receive buffer. */ 698 free(sc->sc_rbuf, M_DEVBUF); 699 700 /* Detach and free the tty. */ 701 tty_detach(sc->sc_tty); 702 tty_free(sc->sc_tty); 703 704 /* Unhook the soft interrupt handler. */ 705 softint_disestablish(sc->sc_si); 706 707 #ifdef RND_COM 708 /* Unhook the entropy source. */ 709 rnd_detach_source(&sc->rnd_source); 710 #endif 711 callout_destroy(&sc->sc_diag_callout); 712 713 /* Destroy the lock. */ 714 mutex_destroy(&sc->sc_lock); 715 716 return (0); 717 } 718 719 void 720 com_shutdown(struct com_softc *sc) 721 { 722 struct tty *tp = sc->sc_tty; 723 724 mutex_spin_enter(&sc->sc_lock); 725 726 /* If we were asserting flow control, then deassert it. */ 727 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 728 com_hwiflow(sc); 729 730 /* Clear any break condition set with TIOCSBRK. */ 731 com_break(sc, 0); 732 733 /* 734 * Hang up if necessary. Wait a bit, so the other side has time to 735 * notice even if we immediately open the port again. 736 * Avoid tsleeping above splhigh(). 737 */ 738 if (ISSET(tp->t_cflag, HUPCL)) { 739 com_modem(sc, 0); 740 mutex_spin_exit(&sc->sc_lock); 741 /* XXX will only timeout */ 742 (void) kpause(ttclos, false, hz, NULL); 743 mutex_spin_enter(&sc->sc_lock); 744 } 745 746 /* Turn off interrupts. */ 747 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 748 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 749 if (sc->sc_type == COM_TYPE_PXA2x0) 750 sc->sc_ier |= IER_ERXTOUT; 751 } else 752 sc->sc_ier = 0; 753 754 if (sc->sc_type == COM_TYPE_PXA2x0) 755 sc->sc_ier |= IER_EUART; 756 757 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 758 759 mutex_spin_exit(&sc->sc_lock); 760 761 if (sc->disable) { 762 #ifdef DIAGNOSTIC 763 if (!sc->enabled) 764 panic("com_shutdown: not enabled?"); 765 #endif 766 (*sc->disable)(sc); 767 sc->enabled = 0; 768 } 769 } 770 771 int 772 comopen(dev_t dev, int flag, int mode, struct lwp *l) 773 { 774 struct com_softc *sc; 775 struct tty *tp; 776 int s; 777 int error; 778 779 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 780 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 781 sc->sc_rbuf == NULL) 782 return (ENXIO); 783 784 if (!device_is_active(sc->sc_dev)) 785 return (ENXIO); 786 787 #ifdef KGDB 788 /* 789 * If this is the kgdb port, no other use is permitted. 790 */ 791 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 792 return (EBUSY); 793 #endif 794 795 tp = sc->sc_tty; 796 797 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 798 return (EBUSY); 799 800 s = spltty(); 801 802 /* 803 * Do the following iff this is a first open. 804 */ 805 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 806 struct termios t; 807 808 tp->t_dev = dev; 809 810 if (sc->enable) { 811 if ((*sc->enable)(sc)) { 812 splx(s); 813 aprint_error_dev(sc->sc_dev, 814 "device enable failed\n"); 815 return (EIO); 816 } 817 mutex_spin_enter(&sc->sc_lock); 818 sc->enabled = 1; 819 com_config(sc); 820 } else { 821 mutex_spin_enter(&sc->sc_lock); 822 } 823 824 /* Turn on interrupts. */ 825 sc->sc_ier = IER_ERXRDY | IER_ERLS; 826 if (!ISSET(tp->t_cflag, CLOCAL)) 827 sc->sc_ier |= IER_EMSC; 828 829 if (sc->sc_type == COM_TYPE_PXA2x0) 830 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 831 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 832 833 /* Fetch the current modem control status, needed later. */ 834 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 835 836 /* Clear PPS capture state on first open. */ 837 mutex_spin_enter(&timecounter_lock); 838 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 839 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 840 pps_init(&sc->sc_pps_state); 841 mutex_spin_exit(&timecounter_lock); 842 843 mutex_spin_exit(&sc->sc_lock); 844 845 /* 846 * Initialize the termios status to the defaults. Add in the 847 * sticky bits from TIOCSFLAGS. 848 */ 849 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 850 t.c_ospeed = comcons_info.rate; 851 t.c_cflag = comcons_info.cflag; 852 } else { 853 t.c_ospeed = TTYDEF_SPEED; 854 t.c_cflag = TTYDEF_CFLAG; 855 } 856 t.c_ispeed = t.c_ospeed; 857 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 858 SET(t.c_cflag, CLOCAL); 859 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 860 SET(t.c_cflag, CRTSCTS); 861 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 862 SET(t.c_cflag, MDMBUF); 863 /* Make sure comparam() will do something. */ 864 tp->t_ospeed = 0; 865 (void) comparam(tp, &t); 866 tp->t_iflag = TTYDEF_IFLAG; 867 tp->t_oflag = TTYDEF_OFLAG; 868 tp->t_lflag = TTYDEF_LFLAG; 869 ttychars(tp); 870 ttsetwater(tp); 871 872 mutex_spin_enter(&sc->sc_lock); 873 874 /* 875 * Turn on DTR. We must always do this, even if carrier is not 876 * present, because otherwise we'd have to use TIOCSDTR 877 * immediately after setting CLOCAL, which applications do not 878 * expect. We always assert DTR while the device is open 879 * unless explicitly requested to deassert it. 880 */ 881 com_modem(sc, 1); 882 883 /* Clear the input ring, and unblock. */ 884 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 885 sc->sc_rbavail = com_rbuf_size; 886 com_iflush(sc); 887 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 888 com_hwiflow(sc); 889 890 #ifdef COM_DEBUG 891 if (com_debug) 892 comstatus(sc, "comopen "); 893 #endif 894 895 mutex_spin_exit(&sc->sc_lock); 896 } 897 898 splx(s); 899 900 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 901 if (error) 902 goto bad; 903 904 error = (*tp->t_linesw->l_open)(dev, tp); 905 if (error) 906 goto bad; 907 908 return (0); 909 910 bad: 911 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 912 /* 913 * We failed to open the device, and nobody else had it opened. 914 * Clean up the state as appropriate. 915 */ 916 com_shutdown(sc); 917 } 918 919 return (error); 920 } 921 922 int 923 comclose(dev_t dev, int flag, int mode, struct lwp *l) 924 { 925 struct com_softc *sc = 926 device_lookup_private(&com_cd, COMUNIT(dev)); 927 struct tty *tp = sc->sc_tty; 928 929 /* XXX This is for cons.c. */ 930 if (!ISSET(tp->t_state, TS_ISOPEN)) 931 return (0); 932 933 (*tp->t_linesw->l_close)(tp, flag); 934 ttyclose(tp); 935 936 if (COM_ISALIVE(sc) == 0) 937 return (0); 938 939 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 940 /* 941 * Although we got a last close, the device may still be in 942 * use; e.g. if this was the dialout node, and there are still 943 * processes waiting for carrier on the non-dialout node. 944 */ 945 com_shutdown(sc); 946 } 947 948 return (0); 949 } 950 951 int 952 comread(dev_t dev, struct uio *uio, int flag) 953 { 954 struct com_softc *sc = 955 device_lookup_private(&com_cd, COMUNIT(dev)); 956 struct tty *tp = sc->sc_tty; 957 958 if (COM_ISALIVE(sc) == 0) 959 return (EIO); 960 961 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 962 } 963 964 int 965 comwrite(dev_t dev, struct uio *uio, int flag) 966 { 967 struct com_softc *sc = 968 device_lookup_private(&com_cd, COMUNIT(dev)); 969 struct tty *tp = sc->sc_tty; 970 971 if (COM_ISALIVE(sc) == 0) 972 return (EIO); 973 974 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 975 } 976 977 int 978 compoll(dev_t dev, int events, struct lwp *l) 979 { 980 struct com_softc *sc = 981 device_lookup_private(&com_cd, COMUNIT(dev)); 982 struct tty *tp = sc->sc_tty; 983 984 if (COM_ISALIVE(sc) == 0) 985 return (POLLHUP); 986 987 return ((*tp->t_linesw->l_poll)(tp, events, l)); 988 } 989 990 struct tty * 991 comtty(dev_t dev) 992 { 993 struct com_softc *sc = 994 device_lookup_private(&com_cd, COMUNIT(dev)); 995 struct tty *tp = sc->sc_tty; 996 997 return (tp); 998 } 999 1000 int 1001 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1002 { 1003 struct com_softc *sc; 1004 struct tty *tp; 1005 int error; 1006 1007 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1008 if (sc == NULL) 1009 return ENXIO; 1010 if (COM_ISALIVE(sc) == 0) 1011 return (EIO); 1012 1013 tp = sc->sc_tty; 1014 1015 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1016 if (error != EPASSTHROUGH) 1017 return (error); 1018 1019 error = ttioctl(tp, cmd, data, flag, l); 1020 if (error != EPASSTHROUGH) 1021 return (error); 1022 1023 error = 0; 1024 switch (cmd) { 1025 case TIOCSFLAGS: 1026 error = kauth_authorize_device_tty(l->l_cred, 1027 KAUTH_DEVICE_TTY_PRIVSET, tp); 1028 break; 1029 default: 1030 /* nothing */ 1031 break; 1032 } 1033 if (error) { 1034 return error; 1035 } 1036 1037 mutex_spin_enter(&sc->sc_lock); 1038 1039 switch (cmd) { 1040 case TIOCSBRK: 1041 com_break(sc, 1); 1042 break; 1043 1044 case TIOCCBRK: 1045 com_break(sc, 0); 1046 break; 1047 1048 case TIOCSDTR: 1049 com_modem(sc, 1); 1050 break; 1051 1052 case TIOCCDTR: 1053 com_modem(sc, 0); 1054 break; 1055 1056 case TIOCGFLAGS: 1057 *(int *)data = sc->sc_swflags; 1058 break; 1059 1060 case TIOCSFLAGS: 1061 sc->sc_swflags = *(int *)data; 1062 break; 1063 1064 case TIOCMSET: 1065 case TIOCMBIS: 1066 case TIOCMBIC: 1067 tiocm_to_com(sc, cmd, *(int *)data); 1068 break; 1069 1070 case TIOCMGET: 1071 *(int *)data = com_to_tiocm(sc); 1072 break; 1073 1074 case PPS_IOC_CREATE: 1075 case PPS_IOC_DESTROY: 1076 case PPS_IOC_GETPARAMS: 1077 case PPS_IOC_SETPARAMS: 1078 case PPS_IOC_GETCAP: 1079 case PPS_IOC_FETCH: 1080 #ifdef PPS_SYNC 1081 case PPS_IOC_KCBIND: 1082 #endif 1083 mutex_spin_enter(&timecounter_lock); 1084 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1085 mutex_spin_exit(&timecounter_lock); 1086 break; 1087 1088 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1089 mutex_spin_enter(&timecounter_lock); 1090 #ifndef PPS_TRAILING_EDGE 1091 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1092 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1093 #else 1094 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1095 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1096 #endif 1097 mutex_spin_exit(&timecounter_lock); 1098 break; 1099 1100 default: 1101 error = EPASSTHROUGH; 1102 break; 1103 } 1104 1105 mutex_spin_exit(&sc->sc_lock); 1106 1107 #ifdef COM_DEBUG 1108 if (com_debug) 1109 comstatus(sc, "comioctl "); 1110 #endif 1111 1112 return (error); 1113 } 1114 1115 integrate void 1116 com_schedrx(struct com_softc *sc) 1117 { 1118 1119 sc->sc_rx_ready = 1; 1120 1121 /* Wake up the poller. */ 1122 softint_schedule(sc->sc_si); 1123 } 1124 1125 void 1126 com_break(struct com_softc *sc, int onoff) 1127 { 1128 1129 if (onoff) 1130 SET(sc->sc_lcr, LCR_SBREAK); 1131 else 1132 CLR(sc->sc_lcr, LCR_SBREAK); 1133 1134 if (!sc->sc_heldchange) { 1135 if (sc->sc_tx_busy) { 1136 sc->sc_heldtbc = sc->sc_tbc; 1137 sc->sc_tbc = 0; 1138 sc->sc_heldchange = 1; 1139 } else 1140 com_loadchannelregs(sc); 1141 } 1142 } 1143 1144 void 1145 com_modem(struct com_softc *sc, int onoff) 1146 { 1147 1148 if (sc->sc_mcr_dtr == 0) 1149 return; 1150 1151 if (onoff) 1152 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1153 else 1154 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1155 1156 if (!sc->sc_heldchange) { 1157 if (sc->sc_tx_busy) { 1158 sc->sc_heldtbc = sc->sc_tbc; 1159 sc->sc_tbc = 0; 1160 sc->sc_heldchange = 1; 1161 } else 1162 com_loadchannelregs(sc); 1163 } 1164 } 1165 1166 void 1167 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1168 { 1169 u_char combits; 1170 1171 combits = 0; 1172 if (ISSET(ttybits, TIOCM_DTR)) 1173 SET(combits, MCR_DTR); 1174 if (ISSET(ttybits, TIOCM_RTS)) 1175 SET(combits, MCR_RTS); 1176 1177 switch (how) { 1178 case TIOCMBIC: 1179 CLR(sc->sc_mcr, combits); 1180 break; 1181 1182 case TIOCMBIS: 1183 SET(sc->sc_mcr, combits); 1184 break; 1185 1186 case TIOCMSET: 1187 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1188 SET(sc->sc_mcr, combits); 1189 break; 1190 } 1191 1192 if (!sc->sc_heldchange) { 1193 if (sc->sc_tx_busy) { 1194 sc->sc_heldtbc = sc->sc_tbc; 1195 sc->sc_tbc = 0; 1196 sc->sc_heldchange = 1; 1197 } else 1198 com_loadchannelregs(sc); 1199 } 1200 } 1201 1202 int 1203 com_to_tiocm(struct com_softc *sc) 1204 { 1205 u_char combits; 1206 int ttybits = 0; 1207 1208 combits = sc->sc_mcr; 1209 if (ISSET(combits, MCR_DTR)) 1210 SET(ttybits, TIOCM_DTR); 1211 if (ISSET(combits, MCR_RTS)) 1212 SET(ttybits, TIOCM_RTS); 1213 1214 combits = sc->sc_msr; 1215 if (ISSET(combits, MSR_DCD)) 1216 SET(ttybits, TIOCM_CD); 1217 if (ISSET(combits, MSR_CTS)) 1218 SET(ttybits, TIOCM_CTS); 1219 if (ISSET(combits, MSR_DSR)) 1220 SET(ttybits, TIOCM_DSR); 1221 if (ISSET(combits, MSR_RI | MSR_TERI)) 1222 SET(ttybits, TIOCM_RI); 1223 1224 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1225 SET(ttybits, TIOCM_LE); 1226 1227 return (ttybits); 1228 } 1229 1230 static u_char 1231 cflag2lcr(tcflag_t cflag) 1232 { 1233 u_char lcr = 0; 1234 1235 switch (ISSET(cflag, CSIZE)) { 1236 case CS5: 1237 SET(lcr, LCR_5BITS); 1238 break; 1239 case CS6: 1240 SET(lcr, LCR_6BITS); 1241 break; 1242 case CS7: 1243 SET(lcr, LCR_7BITS); 1244 break; 1245 case CS8: 1246 SET(lcr, LCR_8BITS); 1247 break; 1248 } 1249 if (ISSET(cflag, PARENB)) { 1250 SET(lcr, LCR_PENAB); 1251 if (!ISSET(cflag, PARODD)) 1252 SET(lcr, LCR_PEVEN); 1253 } 1254 if (ISSET(cflag, CSTOPB)) 1255 SET(lcr, LCR_STOPB); 1256 1257 return (lcr); 1258 } 1259 1260 int 1261 comparam(struct tty *tp, struct termios *t) 1262 { 1263 struct com_softc *sc = 1264 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1265 int ospeed; 1266 u_char lcr; 1267 1268 if (COM_ISALIVE(sc) == 0) 1269 return (EIO); 1270 1271 #ifdef COM_HAYESP 1272 if (sc->sc_type == COM_TYPE_HAYESP) { 1273 int prescaler, speed; 1274 1275 /* 1276 * Calculate UART clock prescaler. It should be in 1277 * range of 0 .. 3. 1278 */ 1279 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1280 prescaler++, speed /= 2) 1281 if ((ospeed = comspeed(speed, sc->sc_frequency, 1282 sc->sc_type)) > 0) 1283 break; 1284 1285 if (prescaler == 4) 1286 return (EINVAL); 1287 sc->sc_prescaler = prescaler; 1288 } else 1289 #endif 1290 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1291 1292 /* Check requested parameters. */ 1293 if (ospeed < 0) 1294 return (EINVAL); 1295 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1296 return (EINVAL); 1297 1298 /* 1299 * For the console, always force CLOCAL and !HUPCL, so that the port 1300 * is always active. 1301 */ 1302 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1303 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1304 SET(t->c_cflag, CLOCAL); 1305 CLR(t->c_cflag, HUPCL); 1306 } 1307 1308 /* 1309 * If there were no changes, don't do anything. This avoids dropping 1310 * input and improves performance when all we did was frob things like 1311 * VMIN and VTIME. 1312 */ 1313 if (tp->t_ospeed == t->c_ospeed && 1314 tp->t_cflag == t->c_cflag) 1315 return (0); 1316 1317 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1318 1319 mutex_spin_enter(&sc->sc_lock); 1320 1321 sc->sc_lcr = lcr; 1322 1323 /* 1324 * If we're not in a mode that assumes a connection is present, then 1325 * ignore carrier changes. 1326 */ 1327 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1328 sc->sc_msr_dcd = 0; 1329 else 1330 sc->sc_msr_dcd = MSR_DCD; 1331 /* 1332 * Set the flow control pins depending on the current flow control 1333 * mode. 1334 */ 1335 if (ISSET(t->c_cflag, CRTSCTS)) { 1336 sc->sc_mcr_dtr = MCR_DTR; 1337 sc->sc_mcr_rts = MCR_RTS; 1338 sc->sc_msr_cts = MSR_CTS; 1339 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1340 } else if (ISSET(t->c_cflag, MDMBUF)) { 1341 /* 1342 * For DTR/DCD flow control, make sure we don't toggle DTR for 1343 * carrier detection. 1344 */ 1345 sc->sc_mcr_dtr = 0; 1346 sc->sc_mcr_rts = MCR_DTR; 1347 sc->sc_msr_cts = MSR_DCD; 1348 sc->sc_efr = 0; 1349 } else { 1350 /* 1351 * If no flow control, then always set RTS. This will make 1352 * the other side happy if it mistakenly thinks we're doing 1353 * RTS/CTS flow control. 1354 */ 1355 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1356 sc->sc_mcr_rts = 0; 1357 sc->sc_msr_cts = 0; 1358 sc->sc_efr = 0; 1359 if (ISSET(sc->sc_mcr, MCR_DTR)) 1360 SET(sc->sc_mcr, MCR_RTS); 1361 else 1362 CLR(sc->sc_mcr, MCR_RTS); 1363 } 1364 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1365 1366 #if 0 1367 if (ospeed == 0) 1368 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1369 else 1370 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1371 #endif 1372 1373 sc->sc_dlbl = ospeed; 1374 sc->sc_dlbh = ospeed >> 8; 1375 1376 /* 1377 * Set the FIFO threshold based on the receive speed. 1378 * 1379 * * If it's a low speed, it's probably a mouse or some other 1380 * interactive device, so set the threshold low. 1381 * * If it's a high speed, trim the trigger level down to prevent 1382 * overflows. 1383 * * Otherwise set it a bit higher. 1384 */ 1385 if (sc->sc_type == COM_TYPE_HAYESP) 1386 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1387 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1388 if (t->c_ospeed <= 1200) 1389 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1390 else if (t->c_ospeed <= 38400) 1391 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1392 else 1393 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1394 } else 1395 sc->sc_fifo = 0; 1396 1397 /* And copy to tty. */ 1398 tp->t_ispeed = t->c_ospeed; 1399 tp->t_ospeed = t->c_ospeed; 1400 tp->t_cflag = t->c_cflag; 1401 1402 if (!sc->sc_heldchange) { 1403 if (sc->sc_tx_busy) { 1404 sc->sc_heldtbc = sc->sc_tbc; 1405 sc->sc_tbc = 0; 1406 sc->sc_heldchange = 1; 1407 } else 1408 com_loadchannelregs(sc); 1409 } 1410 1411 if (!ISSET(t->c_cflag, CHWFLOW)) { 1412 /* Disable the high water mark. */ 1413 sc->sc_r_hiwat = 0; 1414 sc->sc_r_lowat = 0; 1415 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1416 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1417 com_schedrx(sc); 1418 } 1419 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1420 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1421 com_hwiflow(sc); 1422 } 1423 } else { 1424 sc->sc_r_hiwat = com_rbuf_hiwat; 1425 sc->sc_r_lowat = com_rbuf_lowat; 1426 } 1427 1428 mutex_spin_exit(&sc->sc_lock); 1429 1430 /* 1431 * Update the tty layer's idea of the carrier bit, in case we changed 1432 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1433 * explicit request. 1434 */ 1435 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1436 1437 #ifdef COM_DEBUG 1438 if (com_debug) 1439 comstatus(sc, "comparam "); 1440 #endif 1441 1442 if (!ISSET(t->c_cflag, CHWFLOW)) { 1443 if (sc->sc_tx_stopped) { 1444 sc->sc_tx_stopped = 0; 1445 comstart(tp); 1446 } 1447 } 1448 1449 return (0); 1450 } 1451 1452 void 1453 com_iflush(struct com_softc *sc) 1454 { 1455 struct com_regs *regsp = &sc->sc_regs; 1456 #ifdef DIAGNOSTIC 1457 int reg; 1458 #endif 1459 int timo; 1460 1461 #ifdef DIAGNOSTIC 1462 reg = 0xffff; 1463 #endif 1464 timo = 50000; 1465 /* flush any pending I/O */ 1466 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1467 && --timo) 1468 #ifdef DIAGNOSTIC 1469 reg = 1470 #else 1471 (void) 1472 #endif 1473 CSR_READ_1(regsp, COM_REG_RXDATA); 1474 #ifdef DIAGNOSTIC 1475 if (!timo) 1476 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1477 #endif 1478 1479 #ifdef COM_16750 1480 uint8_t fifo; 1481 /* 1482 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1483 * This should prevent triggering busy interrupt while 1484 * manipulating divisors. 1485 */ 1486 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1487 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1488 CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST | 1489 FIFO_XMT_RST); 1490 delay(100); 1491 #endif 1492 } 1493 1494 void 1495 com_loadchannelregs(struct com_softc *sc) 1496 { 1497 struct com_regs *regsp = &sc->sc_regs; 1498 1499 /* XXXXX necessary? */ 1500 com_iflush(sc); 1501 1502 if (sc->sc_type == COM_TYPE_PXA2x0) 1503 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1504 else 1505 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1506 1507 if (sc->sc_type == COM_TYPE_OMAP) { 1508 /* disable before changing settings */ 1509 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1510 } 1511 1512 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1513 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1514 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1515 /* no EFR on alchemy */ 1516 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1517 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1518 } 1519 if (sc->sc_type == COM_TYPE_AU1x00) { 1520 /* alchemy has single separate 16-bit clock divisor register */ 1521 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1522 (sc->sc_dlbh << 8)); 1523 } else { 1524 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1525 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1526 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1527 } 1528 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1529 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1530 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1531 #ifdef COM_HAYESP 1532 if (sc->sc_type == COM_TYPE_HAYESP) { 1533 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1534 HAYESP_SETPRESCALER); 1535 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1536 sc->sc_prescaler); 1537 } 1538 #endif 1539 if (sc->sc_type == COM_TYPE_OMAP) { 1540 /* setup the fifos. the FCR value is not used as long 1541 as SCR[6] and SCR[7] are 0, which they are at reset 1542 and we never touch the SCR register */ 1543 uint8_t rx_fifo_trig = 40; 1544 uint8_t tx_fifo_trig = 60; 1545 uint8_t rx_start = 8; 1546 uint8_t rx_halt = 60; 1547 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1548 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1549 1550 /* enable access to TCR & TLR */ 1551 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1552 1553 /* write tcr and tlr values */ 1554 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1555 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1556 1557 /* disable access to TCR & TLR */ 1558 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1559 1560 /* enable again, but mode is based on speed */ 1561 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1562 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1563 } else { 1564 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1565 } 1566 } 1567 1568 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1569 } 1570 1571 int 1572 comhwiflow(struct tty *tp, int block) 1573 { 1574 struct com_softc *sc = 1575 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1576 1577 if (COM_ISALIVE(sc) == 0) 1578 return (0); 1579 1580 if (sc->sc_mcr_rts == 0) 1581 return (0); 1582 1583 mutex_spin_enter(&sc->sc_lock); 1584 1585 if (block) { 1586 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1587 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1588 com_hwiflow(sc); 1589 } 1590 } else { 1591 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1592 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1593 com_schedrx(sc); 1594 } 1595 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1596 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1597 com_hwiflow(sc); 1598 } 1599 } 1600 1601 mutex_spin_exit(&sc->sc_lock); 1602 return (1); 1603 } 1604 1605 /* 1606 * (un)block input via hw flowcontrol 1607 */ 1608 void 1609 com_hwiflow(struct com_softc *sc) 1610 { 1611 struct com_regs *regsp= &sc->sc_regs; 1612 1613 if (sc->sc_mcr_rts == 0) 1614 return; 1615 1616 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1617 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1618 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1619 } else { 1620 SET(sc->sc_mcr, sc->sc_mcr_rts); 1621 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1622 } 1623 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1624 } 1625 1626 1627 void 1628 comstart(struct tty *tp) 1629 { 1630 struct com_softc *sc = 1631 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1632 struct com_regs *regsp = &sc->sc_regs; 1633 int s; 1634 1635 if (COM_ISALIVE(sc) == 0) 1636 return; 1637 1638 s = spltty(); 1639 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1640 goto out; 1641 if (sc->sc_tx_stopped) 1642 goto out; 1643 if (!ttypull(tp)) 1644 goto out; 1645 1646 /* Grab the first contiguous region of buffer space. */ 1647 { 1648 u_char *tba; 1649 int tbc; 1650 1651 tba = tp->t_outq.c_cf; 1652 tbc = ndqb(&tp->t_outq, 0); 1653 1654 mutex_spin_enter(&sc->sc_lock); 1655 1656 sc->sc_tba = tba; 1657 sc->sc_tbc = tbc; 1658 } 1659 1660 SET(tp->t_state, TS_BUSY); 1661 sc->sc_tx_busy = 1; 1662 1663 /* Enable transmit completion interrupts if necessary. */ 1664 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1665 SET(sc->sc_ier, IER_ETXRDY); 1666 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1667 } 1668 1669 /* Output the first chunk of the contiguous buffer. */ 1670 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1671 u_int n; 1672 1673 n = sc->sc_tbc; 1674 if (n > sc->sc_fifolen) 1675 n = sc->sc_fifolen; 1676 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1677 sc->sc_tbc -= n; 1678 sc->sc_tba += n; 1679 } 1680 1681 mutex_spin_exit(&sc->sc_lock); 1682 out: 1683 splx(s); 1684 return; 1685 } 1686 1687 /* 1688 * Stop output on a line. 1689 */ 1690 void 1691 comstop(struct tty *tp, int flag) 1692 { 1693 struct com_softc *sc = 1694 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1695 1696 mutex_spin_enter(&sc->sc_lock); 1697 if (ISSET(tp->t_state, TS_BUSY)) { 1698 /* Stop transmitting at the next chunk. */ 1699 sc->sc_tbc = 0; 1700 sc->sc_heldtbc = 0; 1701 if (!ISSET(tp->t_state, TS_TTSTOP)) 1702 SET(tp->t_state, TS_FLUSH); 1703 } 1704 mutex_spin_exit(&sc->sc_lock); 1705 } 1706 1707 void 1708 comdiag(void *arg) 1709 { 1710 struct com_softc *sc = arg; 1711 int overflows, floods; 1712 1713 mutex_spin_enter(&sc->sc_lock); 1714 overflows = sc->sc_overflows; 1715 sc->sc_overflows = 0; 1716 floods = sc->sc_floods; 1717 sc->sc_floods = 0; 1718 sc->sc_errors = 0; 1719 mutex_spin_exit(&sc->sc_lock); 1720 1721 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1722 device_xname(sc->sc_dev), 1723 overflows, overflows == 1 ? "" : "s", 1724 floods, floods == 1 ? "" : "s"); 1725 } 1726 1727 integrate void 1728 com_rxsoft(struct com_softc *sc, struct tty *tp) 1729 { 1730 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1731 u_char *get, *end; 1732 u_int cc, scc; 1733 u_char lsr; 1734 int code; 1735 1736 end = sc->sc_ebuf; 1737 get = sc->sc_rbget; 1738 scc = cc = com_rbuf_size - sc->sc_rbavail; 1739 1740 if (cc == com_rbuf_size) { 1741 sc->sc_floods++; 1742 if (sc->sc_errors++ == 0) 1743 callout_reset(&sc->sc_diag_callout, 60 * hz, 1744 comdiag, sc); 1745 } 1746 1747 /* If not yet open, drop the entire buffer content here */ 1748 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1749 get += cc << 1; 1750 if (get >= end) 1751 get -= com_rbuf_size << 1; 1752 cc = 0; 1753 } 1754 while (cc) { 1755 code = get[0]; 1756 lsr = get[1]; 1757 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1758 if (ISSET(lsr, LSR_OE)) { 1759 sc->sc_overflows++; 1760 if (sc->sc_errors++ == 0) 1761 callout_reset(&sc->sc_diag_callout, 1762 60 * hz, comdiag, sc); 1763 } 1764 if (ISSET(lsr, LSR_BI | LSR_FE)) 1765 SET(code, TTY_FE); 1766 if (ISSET(lsr, LSR_PE)) 1767 SET(code, TTY_PE); 1768 } 1769 if ((*rint)(code, tp) == -1) { 1770 /* 1771 * The line discipline's buffer is out of space. 1772 */ 1773 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1774 /* 1775 * We're either not using flow control, or the 1776 * line discipline didn't tell us to block for 1777 * some reason. Either way, we have no way to 1778 * know when there's more space available, so 1779 * just drop the rest of the data. 1780 */ 1781 get += cc << 1; 1782 if (get >= end) 1783 get -= com_rbuf_size << 1; 1784 cc = 0; 1785 } else { 1786 /* 1787 * Don't schedule any more receive processing 1788 * until the line discipline tells us there's 1789 * space available (through comhwiflow()). 1790 * Leave the rest of the data in the input 1791 * buffer. 1792 */ 1793 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1794 } 1795 break; 1796 } 1797 get += 2; 1798 if (get >= end) 1799 get = sc->sc_rbuf; 1800 cc--; 1801 } 1802 1803 if (cc != scc) { 1804 sc->sc_rbget = get; 1805 mutex_spin_enter(&sc->sc_lock); 1806 1807 cc = sc->sc_rbavail += scc - cc; 1808 /* Buffers should be ok again, release possible block. */ 1809 if (cc >= sc->sc_r_lowat) { 1810 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1811 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1812 SET(sc->sc_ier, IER_ERXRDY); 1813 #ifdef COM_PXA2X0 1814 if (sc->sc_type == COM_TYPE_PXA2x0) 1815 SET(sc->sc_ier, IER_ERXTOUT); 1816 #endif 1817 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1818 } 1819 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1820 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1821 com_hwiflow(sc); 1822 } 1823 } 1824 mutex_spin_exit(&sc->sc_lock); 1825 } 1826 } 1827 1828 integrate void 1829 com_txsoft(struct com_softc *sc, struct tty *tp) 1830 { 1831 1832 CLR(tp->t_state, TS_BUSY); 1833 if (ISSET(tp->t_state, TS_FLUSH)) 1834 CLR(tp->t_state, TS_FLUSH); 1835 else 1836 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1837 (*tp->t_linesw->l_start)(tp); 1838 } 1839 1840 integrate void 1841 com_stsoft(struct com_softc *sc, struct tty *tp) 1842 { 1843 u_char msr, delta; 1844 1845 mutex_spin_enter(&sc->sc_lock); 1846 msr = sc->sc_msr; 1847 delta = sc->sc_msr_delta; 1848 sc->sc_msr_delta = 0; 1849 mutex_spin_exit(&sc->sc_lock); 1850 1851 if (ISSET(delta, sc->sc_msr_dcd)) { 1852 /* 1853 * Inform the tty layer that carrier detect changed. 1854 */ 1855 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1856 } 1857 1858 if (ISSET(delta, sc->sc_msr_cts)) { 1859 /* Block or unblock output according to flow control. */ 1860 if (ISSET(msr, sc->sc_msr_cts)) { 1861 sc->sc_tx_stopped = 0; 1862 (*tp->t_linesw->l_start)(tp); 1863 } else { 1864 sc->sc_tx_stopped = 1; 1865 } 1866 } 1867 1868 #ifdef COM_DEBUG 1869 if (com_debug) 1870 comstatus(sc, "com_stsoft"); 1871 #endif 1872 } 1873 1874 void 1875 comsoft(void *arg) 1876 { 1877 struct com_softc *sc = arg; 1878 struct tty *tp; 1879 1880 if (COM_ISALIVE(sc) == 0) 1881 return; 1882 1883 tp = sc->sc_tty; 1884 1885 if (sc->sc_rx_ready) { 1886 sc->sc_rx_ready = 0; 1887 com_rxsoft(sc, tp); 1888 } 1889 1890 if (sc->sc_st_check) { 1891 sc->sc_st_check = 0; 1892 com_stsoft(sc, tp); 1893 } 1894 1895 if (sc->sc_tx_done) { 1896 sc->sc_tx_done = 0; 1897 com_txsoft(sc, tp); 1898 } 1899 } 1900 1901 int 1902 comintr(void *arg) 1903 { 1904 struct com_softc *sc = arg; 1905 struct com_regs *regsp = &sc->sc_regs; 1906 1907 u_char *put, *end; 1908 u_int cc; 1909 u_char lsr, iir; 1910 1911 if (COM_ISALIVE(sc) == 0) 1912 return (0); 1913 1914 KASSERT(regsp != NULL); 1915 1916 mutex_spin_enter(&sc->sc_lock); 1917 iir = CSR_READ_1(regsp, COM_REG_IIR); 1918 1919 /* Handle ns16750-specific busy interrupt. */ 1920 #ifdef COM_16750 1921 int timeout; 1922 if ((iir & IIR_BUSY) == IIR_BUSY) { 1923 for (timeout = 10000; 1924 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 1925 if (timeout <= 0) { 1926 aprint_error_dev(sc->sc_dev, 1927 "timeout while waiting for BUSY interrupt " 1928 "acknowledge\n"); 1929 mutex_spin_exit(&sc->sc_lock); 1930 return (0); 1931 } 1932 1933 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1934 iir = CSR_READ_1(regsp, COM_REG_IIR); 1935 } 1936 #endif /* COM_16750 */ 1937 1938 1939 if (ISSET(iir, IIR_NOPEND)) { 1940 mutex_spin_exit(&sc->sc_lock); 1941 return (0); 1942 } 1943 1944 end = sc->sc_ebuf; 1945 put = sc->sc_rbput; 1946 cc = sc->sc_rbavail; 1947 1948 again: do { 1949 u_char msr, delta; 1950 1951 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1952 if (ISSET(lsr, LSR_BI)) { 1953 int cn_trapped = 0; 1954 1955 cn_check_magic(sc->sc_tty->t_dev, 1956 CNC_BREAK, com_cnm_state); 1957 if (cn_trapped) 1958 continue; 1959 #if defined(KGDB) && !defined(DDB) 1960 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1961 kgdb_connect(1); 1962 continue; 1963 } 1964 #endif 1965 } 1966 1967 if (ISSET(lsr, LSR_RCV_MASK) && 1968 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1969 while (cc > 0) { 1970 int cn_trapped = 0; 1971 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1972 put[1] = lsr; 1973 cn_check_magic(sc->sc_tty->t_dev, 1974 put[0], com_cnm_state); 1975 if (cn_trapped) 1976 goto next; 1977 put += 2; 1978 if (put >= end) 1979 put = sc->sc_rbuf; 1980 cc--; 1981 next: 1982 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1983 if (!ISSET(lsr, LSR_RCV_MASK)) 1984 break; 1985 } 1986 1987 /* 1988 * Current string of incoming characters ended because 1989 * no more data was available or we ran out of space. 1990 * Schedule a receive event if any data was received. 1991 * If we're out of space, turn off receive interrupts. 1992 */ 1993 sc->sc_rbput = put; 1994 sc->sc_rbavail = cc; 1995 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1996 sc->sc_rx_ready = 1; 1997 1998 /* 1999 * See if we are in danger of overflowing a buffer. If 2000 * so, use hardware flow control to ease the pressure. 2001 */ 2002 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2003 cc < sc->sc_r_hiwat) { 2004 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2005 com_hwiflow(sc); 2006 } 2007 2008 /* 2009 * If we're out of space, disable receive interrupts 2010 * until the queue has drained a bit. 2011 */ 2012 if (!cc) { 2013 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2014 #ifdef COM_PXA2X0 2015 if (sc->sc_type == COM_TYPE_PXA2x0) 2016 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2017 else 2018 #endif 2019 CLR(sc->sc_ier, IER_ERXRDY); 2020 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2021 } 2022 } else { 2023 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2024 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2025 continue; 2026 } 2027 } 2028 2029 msr = CSR_READ_1(regsp, COM_REG_MSR); 2030 delta = msr ^ sc->sc_msr; 2031 sc->sc_msr = msr; 2032 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2033 (delta & MSR_DCD)) { 2034 mutex_spin_enter(&timecounter_lock); 2035 pps_capture(&sc->sc_pps_state); 2036 pps_event(&sc->sc_pps_state, 2037 (msr & MSR_DCD) ? 2038 PPS_CAPTUREASSERT : 2039 PPS_CAPTURECLEAR); 2040 mutex_spin_exit(&timecounter_lock); 2041 } 2042 2043 /* 2044 * Process normal status changes 2045 */ 2046 if (ISSET(delta, sc->sc_msr_mask)) { 2047 SET(sc->sc_msr_delta, delta); 2048 2049 /* 2050 * Stop output immediately if we lose the output 2051 * flow control signal or carrier detect. 2052 */ 2053 if (ISSET(~msr, sc->sc_msr_mask)) { 2054 sc->sc_tbc = 0; 2055 sc->sc_heldtbc = 0; 2056 #ifdef COM_DEBUG 2057 if (com_debug) 2058 comstatus(sc, "comintr "); 2059 #endif 2060 } 2061 2062 sc->sc_st_check = 1; 2063 } 2064 } while (!ISSET((iir = 2065 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2066 /* 2067 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2068 * by IIR read, so we can't do this way: `process all interrupts, 2069 * then do TX if possible'. 2070 */ 2071 (iir & IIR_IMASK) != IIR_TXRDY); 2072 2073 /* 2074 * Read LSR again, since there may be an interrupt between 2075 * the last LSR read and IIR read above. 2076 */ 2077 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2078 2079 /* 2080 * See if data can be transmitted as well. 2081 * Schedule tx done event if no data left 2082 * and tty was marked busy. 2083 */ 2084 if (ISSET(lsr, LSR_TXRDY)) { 2085 /* 2086 * If we've delayed a parameter change, do it now, and restart 2087 * output. 2088 */ 2089 if (sc->sc_heldchange) { 2090 com_loadchannelregs(sc); 2091 sc->sc_heldchange = 0; 2092 sc->sc_tbc = sc->sc_heldtbc; 2093 sc->sc_heldtbc = 0; 2094 } 2095 2096 /* Output the next chunk of the contiguous buffer, if any. */ 2097 if (sc->sc_tbc > 0) { 2098 u_int n; 2099 2100 n = sc->sc_tbc; 2101 if (n > sc->sc_fifolen) 2102 n = sc->sc_fifolen; 2103 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2104 sc->sc_tbc -= n; 2105 sc->sc_tba += n; 2106 } else { 2107 /* Disable transmit completion interrupts if necessary. */ 2108 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2109 CLR(sc->sc_ier, IER_ETXRDY); 2110 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2111 } 2112 if (sc->sc_tx_busy) { 2113 sc->sc_tx_busy = 0; 2114 sc->sc_tx_done = 1; 2115 } 2116 } 2117 } 2118 2119 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2120 goto again; 2121 2122 mutex_spin_exit(&sc->sc_lock); 2123 2124 /* Wake up the poller. */ 2125 softint_schedule(sc->sc_si); 2126 2127 #ifdef RND_COM 2128 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2129 #endif 2130 2131 return (1); 2132 } 2133 2134 /* 2135 * The following functions are polled getc and putc routines, shared 2136 * by the console and kgdb glue. 2137 * 2138 * The read-ahead code is so that you can detect pending in-band 2139 * cn_magic in polled mode while doing output rather than having to 2140 * wait until the kernel decides it needs input. 2141 */ 2142 2143 #define MAX_READAHEAD 20 2144 static int com_readahead[MAX_READAHEAD]; 2145 static int com_readaheadcount = 0; 2146 2147 int 2148 com_common_getc(dev_t dev, struct com_regs *regsp) 2149 { 2150 int s = splserial(); 2151 u_char stat, c; 2152 2153 /* got a character from reading things earlier */ 2154 if (com_readaheadcount > 0) { 2155 int i; 2156 2157 c = com_readahead[0]; 2158 for (i = 1; i < com_readaheadcount; i++) { 2159 com_readahead[i-1] = com_readahead[i]; 2160 } 2161 com_readaheadcount--; 2162 splx(s); 2163 return (c); 2164 } 2165 2166 /* block until a character becomes available */ 2167 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2168 ; 2169 2170 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2171 stat = CSR_READ_1(regsp, COM_REG_IIR); 2172 { 2173 int cn_trapped = 0; /* unused */ 2174 #ifdef DDB 2175 extern int db_active; 2176 if (!db_active) 2177 #endif 2178 cn_check_magic(dev, c, com_cnm_state); 2179 } 2180 splx(s); 2181 return (c); 2182 } 2183 2184 static void 2185 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2186 { 2187 int s = splserial(); 2188 int cin, stat, timo; 2189 2190 if (com_readaheadcount < MAX_READAHEAD 2191 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2192 int cn_trapped = 0; 2193 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2194 stat = CSR_READ_1(regsp, COM_REG_IIR); 2195 cn_check_magic(dev, cin, com_cnm_state); 2196 com_readahead[com_readaheadcount++] = cin; 2197 } 2198 2199 /* wait for any pending transmission to finish */ 2200 timo = 150000; 2201 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2202 continue; 2203 2204 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2205 COM_BARRIER(regsp, BR | BW); 2206 2207 splx(s); 2208 } 2209 2210 /* 2211 * Initialize UART for use as console or KGDB line. 2212 */ 2213 int 2214 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2215 tcflag_t cflag) 2216 { 2217 2218 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2219 ®sp->cr_ioh)) 2220 return (ENOMEM); /* ??? */ 2221 2222 if (type == COM_TYPE_OMAP) { 2223 /* disable before changing settings */ 2224 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2225 } 2226 2227 rate = comspeed(rate, frequency, type); 2228 if (__predict_true(rate != -1)) { 2229 if (type == COM_TYPE_AU1x00) { 2230 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2231 } else { 2232 /* no EFR on alchemy */ 2233 if (type != COM_TYPE_16550_NOERS) { 2234 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2235 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2236 } 2237 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2238 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2239 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2240 } 2241 } 2242 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2243 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2244 CSR_WRITE_1(regsp, COM_REG_FIFO, 2245 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2246 2247 if (type == COM_TYPE_OMAP) { 2248 /* setup the fifos. the FCR value is not used as long 2249 as SCR[6] and SCR[7] are 0, which they are at reset 2250 and we never touch the SCR register */ 2251 uint8_t rx_fifo_trig = 40; 2252 uint8_t tx_fifo_trig = 60; 2253 uint8_t rx_start = 8; 2254 uint8_t rx_halt = 60; 2255 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2256 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2257 2258 /* enable access to TCR & TLR */ 2259 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2260 2261 /* write tcr and tlr values */ 2262 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2263 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2264 2265 /* disable access to TCR & TLR */ 2266 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2267 2268 /* enable again, but mode is based on speed */ 2269 if (rate > 230400) { 2270 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2271 } else { 2272 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2273 } 2274 } 2275 2276 #ifdef COM_PXA2X0 2277 if (type == COM_TYPE_PXA2x0) 2278 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2279 else 2280 #endif 2281 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2282 2283 return (0); 2284 } 2285 2286 int 2287 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2288 tcflag_t cflag) 2289 { 2290 int res; 2291 2292 comcons_info.regs = *regsp; 2293 2294 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2295 if (res) 2296 return (res); 2297 2298 cn_tab = &comcons; 2299 cn_init_magic(&com_cnm_state); 2300 cn_set_magic("\047\001"); /* default magic is BREAK */ 2301 2302 comcons_info.frequency = frequency; 2303 comcons_info.type = type; 2304 comcons_info.rate = rate; 2305 comcons_info.cflag = cflag; 2306 2307 return (0); 2308 } 2309 2310 int 2311 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2312 int type, tcflag_t cflag) 2313 { 2314 struct com_regs regs; 2315 2316 memset(®s, 0, sizeof regs); 2317 regs.cr_iot = iot; 2318 regs.cr_iobase = iobase; 2319 regs.cr_nports = COM_NPORTS; 2320 #ifdef COM_REGMAP 2321 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2322 #endif 2323 2324 return comcnattach1(®s, rate, frequency, type, cflag); 2325 } 2326 2327 static int 2328 comcnreattach(void) 2329 { 2330 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2331 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2332 } 2333 2334 int 2335 comcngetc(dev_t dev) 2336 { 2337 2338 return (com_common_getc(dev, &comcons_info.regs)); 2339 } 2340 2341 /* 2342 * Console kernel output character routine. 2343 */ 2344 void 2345 comcnputc(dev_t dev, int c) 2346 { 2347 2348 com_common_putc(dev, &comcons_info.regs, c); 2349 } 2350 2351 void 2352 comcnpollc(dev_t dev, int on) 2353 { 2354 2355 com_readaheadcount = 0; 2356 } 2357 2358 #ifdef KGDB 2359 int 2360 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2361 tcflag_t cflag) 2362 { 2363 int res; 2364 2365 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2366 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2367 #if !defined(DDB) 2368 return (EBUSY); /* cannot share with console */ 2369 #else 2370 comkgdbregs = *regsp; 2371 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2372 #endif 2373 } else { 2374 comkgdbregs = *regsp; 2375 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2376 if (res) 2377 return (res); 2378 2379 /* 2380 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2381 * expects this to be initialized 2382 */ 2383 cn_init_magic(&com_cnm_state); 2384 cn_set_magic("\047\001"); 2385 } 2386 2387 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2388 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2389 2390 return (0); 2391 } 2392 2393 int 2394 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2395 int frequency, int type, tcflag_t cflag) 2396 { 2397 struct com_regs regs; 2398 2399 regs.cr_iot = iot; 2400 regs.cr_nports = COM_NPORTS; 2401 regs.cr_iobase = iobase; 2402 #ifdef COM_REGMAP 2403 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2404 #endif 2405 2406 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2407 } 2408 2409 /* ARGSUSED */ 2410 int 2411 com_kgdb_getc(void *arg) 2412 { 2413 2414 return (com_common_getc(NODEV, &comkgdbregs)); 2415 } 2416 2417 /* ARGSUSED */ 2418 void 2419 com_kgdb_putc(void *arg, int c) 2420 { 2421 2422 com_common_putc(NODEV, &comkgdbregs, c); 2423 } 2424 #endif /* KGDB */ 2425 2426 /* helper function to identify the com ports used by 2427 console or KGDB (and not yet autoconf attached) */ 2428 int 2429 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2430 { 2431 bus_space_handle_t help; 2432 2433 if (!comconsattached && 2434 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2435 iobase == comcons_info.regs.cr_iobase) 2436 help = comcons_info.regs.cr_ioh; 2437 #ifdef KGDB 2438 else if (!com_kgdb_attached && 2439 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2440 iobase == comkgdbregs.cr_iobase) 2441 help = comkgdbregs.cr_ioh; 2442 #endif 2443 else 2444 return (0); 2445 2446 if (ioh) 2447 *ioh = help; 2448 return (1); 2449 } 2450 2451 /* 2452 * this routine exists to serve as a shutdown hook for systems that 2453 * have firmware which doesn't interact properly with a com device in 2454 * FIFO mode. 2455 */ 2456 bool 2457 com_cleanup(device_t self, int how) 2458 { 2459 struct com_softc *sc = device_private(self); 2460 2461 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2462 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2463 2464 return true; 2465 } 2466 2467 bool 2468 com_suspend(device_t self, const pmf_qual_t *qual) 2469 { 2470 struct com_softc *sc = device_private(self); 2471 2472 #if 0 2473 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2474 cn_tab = &comcons_suspend; 2475 #endif 2476 2477 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2478 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2479 2480 return true; 2481 } 2482 2483 bool 2484 com_resume(device_t self, const pmf_qual_t *qual) 2485 { 2486 struct com_softc *sc = device_private(self); 2487 2488 mutex_spin_enter(&sc->sc_lock); 2489 com_loadchannelregs(sc); 2490 mutex_spin_exit(&sc->sc_lock); 2491 2492 return true; 2493 } 2494
Indexes created Fri Sep 26 08:10:20 GMT 2025