com.c revision 1.311
1 /* $NetBSD: com.c,v 1.311 2013/07/27 06:43:56 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.311 2013/07/27 06:43:56 kiyohara Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 } while (/* CONSTCOND */ 0) 96 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/ioctl.h> 100 #include <sys/select.h> 101 #include <sys/poll.h> 102 #include <sys/tty.h> 103 #include <sys/proc.h> 104 #include <sys/conf.h> 105 #include <sys/file.h> 106 #include <sys/uio.h> 107 #include <sys/kernel.h> 108 #include <sys/syslog.h> 109 #include <sys/device.h> 110 #include <sys/malloc.h> 111 #include <sys/timepps.h> 112 #include <sys/vnode.h> 113 #include <sys/kauth.h> 114 #include <sys/intr.h> 115 #ifdef RND_COM 116 #include <sys/rnd.h> 117 #endif 118 119 120 #include <sys/bus.h> 121 122 #include <dev/ic/comreg.h> 123 #include <dev/ic/comvar.h> 124 #include <dev/ic/ns16550reg.h> 125 #include <dev/ic/st16650reg.h> 126 #ifdef COM_HAYESP 127 #include <dev/ic/hayespreg.h> 128 #endif 129 #define com_lcr com_cfcr 130 #include <dev/cons.h> 131 132 #ifdef COM_REGMAP 133 #define CSR_WRITE_1(r, o, v) \ 134 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 135 #define CSR_READ_1(r, o) \ 136 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 137 #define CSR_WRITE_2(r, o, v) \ 138 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 139 #define CSR_READ_2(r, o) \ 140 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 141 #define CSR_WRITE_MULTI(r, o, p, n) \ 142 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 143 #else 144 #define CSR_WRITE_1(r, o, v) \ 145 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 146 #define CSR_READ_1(r, o) \ 147 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 148 #define CSR_WRITE_2(r, o, v) \ 149 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 150 #define CSR_READ_2(r, o) \ 151 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 152 #define CSR_WRITE_MULTI(r, o, p, n) \ 153 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 154 #endif 155 156 157 static void com_enable_debugport(struct com_softc *); 158 159 void com_config(struct com_softc *); 160 void com_shutdown(struct com_softc *); 161 int comspeed(long, long, int); 162 static u_char cflag2lcr(tcflag_t); 163 int comparam(struct tty *, struct termios *); 164 void comstart(struct tty *); 165 int comhwiflow(struct tty *, int); 166 167 void com_loadchannelregs(struct com_softc *); 168 void com_hwiflow(struct com_softc *); 169 void com_break(struct com_softc *, int); 170 void com_modem(struct com_softc *, int); 171 void tiocm_to_com(struct com_softc *, u_long, int); 172 int com_to_tiocm(struct com_softc *); 173 void com_iflush(struct com_softc *); 174 175 int com_common_getc(dev_t, struct com_regs *); 176 static void com_common_putc(dev_t, struct com_regs *, int); 177 178 int cominit(struct com_regs *, int, int, int, tcflag_t); 179 180 static int comcnreattach(void); 181 182 int comcngetc(dev_t); 183 void comcnputc(dev_t, int); 184 void comcnpollc(dev_t, int); 185 186 #define integrate static inline 187 void comsoft(void *); 188 integrate void com_rxsoft(struct com_softc *, struct tty *); 189 integrate void com_txsoft(struct com_softc *, struct tty *); 190 integrate void com_stsoft(struct com_softc *, struct tty *); 191 integrate void com_schedrx(struct com_softc *); 192 void comdiag(void *); 193 194 extern struct cfdriver com_cd; 195 196 dev_type_open(comopen); 197 dev_type_close(comclose); 198 dev_type_read(comread); 199 dev_type_write(comwrite); 200 dev_type_ioctl(comioctl); 201 dev_type_stop(comstop); 202 dev_type_tty(comtty); 203 dev_type_poll(compoll); 204 205 static struct comcons_info comcons_info; 206 207 /* 208 * Following are all routines needed for COM to act as console 209 */ 210 static struct consdev comcons = { 211 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 212 NODEV, CN_NORMAL 213 }; 214 215 216 const struct cdevsw com_cdevsw = { 217 comopen, comclose, comread, comwrite, comioctl, 218 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 219 }; 220 221 /* 222 * Make this an option variable one can patch. 223 * But be warned: this must be a power of 2! 224 */ 225 u_int com_rbuf_size = COM_RING_SIZE; 226 227 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 228 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 229 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 230 231 static int comconsattached; 232 static struct cnm_state com_cnm_state; 233 234 #ifdef KGDB 235 #include <sys/kgdb.h> 236 237 static struct com_regs comkgdbregs; 238 static int com_kgdb_attached; 239 240 int com_kgdb_getc(void *); 241 void com_kgdb_putc(void *, int); 242 #endif /* KGDB */ 243 244 #ifdef COM_REGMAP 245 /* initializer for typical 16550-ish hardware */ 246 #define COM_REG_16550 { \ 247 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 248 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 249 /* 16750-specific register set, additional UART status register */ 250 #define COM_REG_16750 { \ 251 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 252 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } 254 255 #ifdef COM_16750 256 const bus_size_t com_std_map[32] = COM_REG_16750; 257 #else 258 const bus_size_t com_std_map[16] = COM_REG_16550; 259 #endif /* COM_16750 */ 260 #endif /* COM_REGMAP */ 261 262 #define COMUNIT_MASK 0x7ffff 263 #define COMDIALOUT_MASK 0x80000 264 265 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 266 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 267 268 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 269 device_is_active((sc)->sc_dev)) 270 271 #define BR BUS_SPACE_BARRIER_READ 272 #define BW BUS_SPACE_BARRIER_WRITE 273 #define COM_BARRIER(r, f) \ 274 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 275 276 /*ARGSUSED*/ 277 int 278 comspeed(long speed, long frequency, int type) 279 { 280 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 281 282 int x, err; 283 int divisor = 16; 284 285 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 286 divisor = 13; 287 } 288 289 #if 0 290 if (speed == 0) 291 return (0); 292 #endif 293 if (speed <= 0) 294 return (-1); 295 x = divrnd(frequency / divisor, speed); 296 if (x <= 0) 297 return (-1); 298 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 299 if (err < 0) 300 err = -err; 301 if (err > COM_TOLERANCE) 302 return (-1); 303 return (x); 304 305 #undef divrnd 306 } 307 308 #ifdef COM_DEBUG 309 int com_debug = 0; 310 311 void comstatus(struct com_softc *, const char *); 312 void 313 comstatus(struct com_softc *sc, const char *str) 314 { 315 struct tty *tp = sc->sc_tty; 316 317 aprint_normal_dev(sc->sc_dev, 318 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 319 str, 320 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 321 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 322 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 323 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 324 sc->sc_tx_stopped ? '+' : '-'); 325 326 aprint_normal_dev(sc->sc_dev, 327 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 328 str, 329 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 330 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 331 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 332 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 333 sc->sc_rx_flags); 334 } 335 #endif 336 337 int 338 com_probe_subr(struct com_regs *regs) 339 { 340 341 /* force access to id reg */ 342 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 343 CSR_WRITE_1(regs, COM_REG_IIR, 0); 344 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 345 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 346 return (0); 347 348 return (1); 349 } 350 351 int 352 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 353 { 354 struct com_regs regs; 355 356 regs.cr_iot = iot; 357 regs.cr_ioh = ioh; 358 #ifdef COM_REGMAP 359 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 360 #endif 361 362 return com_probe_subr(®s); 363 } 364 365 /* 366 * No locking in this routine; it is only called during attach, 367 * or with the port already locked. 368 */ 369 static void 370 com_enable_debugport(struct com_softc *sc) 371 { 372 373 /* Turn on line break interrupt, set carrier. */ 374 sc->sc_ier = IER_ERXRDY; 375 if (sc->sc_type == COM_TYPE_PXA2x0) 376 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 377 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 378 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 379 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 380 } 381 382 void 383 com_attach_subr(struct com_softc *sc) 384 { 385 struct com_regs *regsp = &sc->sc_regs; 386 struct tty *tp; 387 #ifdef COM_16650 388 u_int8_t lcr; 389 #endif 390 const char *fifo_msg = NULL; 391 prop_dictionary_t dict; 392 bool is_console = true; 393 394 aprint_naive("\n"); 395 396 dict = device_properties(sc->sc_dev); 397 prop_dictionary_get_bool(dict, "is_console", &is_console); 398 399 callout_init(&sc->sc_diag_callout, 0); 400 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 401 402 /* Disable interrupts before configuring the device. */ 403 if (sc->sc_type == COM_TYPE_PXA2x0) 404 sc->sc_ier = IER_EUART; 405 else 406 sc->sc_ier = 0; 407 408 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 409 410 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 411 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 412 comconsattached = 1; 413 414 if (cn_tab == NULL && comcnreattach() != 0) { 415 printf("can't re-init serial console @%lx\n", 416 (u_long)comcons_info.regs.cr_iobase); 417 } 418 419 /* Make sure the console is always "hardwired". */ 420 delay(10000); /* wait for output to finish */ 421 if (is_console) { 422 SET(sc->sc_hwflags, COM_HW_CONSOLE); 423 } 424 425 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 426 } 427 428 /* Probe for FIFO */ 429 switch (sc->sc_type) { 430 case COM_TYPE_HAYESP: 431 goto fifodone; 432 433 case COM_TYPE_AU1x00: 434 sc->sc_fifolen = 16; 435 fifo_msg = "Au1X00 UART, working fifo"; 436 SET(sc->sc_hwflags, COM_HW_FIFO); 437 goto fifodelay; 438 439 case COM_TYPE_16550_NOERS: 440 sc->sc_fifolen = 16; 441 fifo_msg = "ns16650, no ERS, working fifo"; 442 SET(sc->sc_hwflags, COM_HW_FIFO); 443 goto fifodelay; 444 445 case COM_TYPE_OMAP: 446 sc->sc_fifolen = 64; 447 fifo_msg = "OMAP UART, working fifo"; 448 SET(sc->sc_hwflags, COM_HW_FIFO); 449 goto fifodelay; 450 } 451 452 sc->sc_fifolen = 1; 453 /* look for a NS 16550AF UART with FIFOs */ 454 CSR_WRITE_1(regsp, COM_REG_FIFO, 455 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 456 delay(100); 457 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 458 == IIR_FIFO_MASK) 459 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 460 == FIFO_TRIGGER_14) { 461 SET(sc->sc_hwflags, COM_HW_FIFO); 462 463 #ifdef COM_16650 464 /* 465 * IIR changes into the EFR if LCR is set to LCR_EERS 466 * on 16650s. We also know IIR != 0 at this point. 467 * Write 0 into the EFR, and read it. If the result 468 * is 0, we have a 16650. 469 * 470 * Older 16650s were broken; the test to detect them 471 * is taken from the Linux driver. Apparently 472 * setting DLAB enable gives access to the EFR on 473 * these chips. 474 */ 475 lcr = CSR_READ_1(regsp, COM_REG_LCR); 476 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 477 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 478 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 479 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 480 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 481 CLR(sc->sc_hwflags, COM_HW_FIFO); 482 sc->sc_fifolen = 0; 483 } else { 484 SET(sc->sc_hwflags, COM_HW_FLOW); 485 sc->sc_fifolen = 32; 486 } 487 } else 488 #endif 489 sc->sc_fifolen = 16; 490 491 #ifdef COM_16650 492 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 493 if (sc->sc_fifolen == 0) 494 fifo_msg = "st16650, broken fifo"; 495 else if (sc->sc_fifolen == 32) 496 fifo_msg = "st16650a, working fifo"; 497 else 498 #endif 499 fifo_msg = "ns16550a, working fifo"; 500 } else 501 fifo_msg = "ns16550, broken fifo"; 502 else 503 fifo_msg = "ns8250 or ns16450, no fifo"; 504 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 505 fifodelay: 506 /* 507 * Some chips will clear down both Tx and Rx FIFOs when zero is 508 * written to com_fifo. If this chip is the console, writing zero 509 * results in some of the chip/FIFO description being lost, so delay 510 * printing it until now. 511 */ 512 delay(10); 513 aprint_normal(": %s\n", fifo_msg); 514 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 515 sc->sc_fifolen = 1; 516 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 517 } 518 519 fifodone: 520 521 tp = tty_alloc(); 522 tp->t_oproc = comstart; 523 tp->t_param = comparam; 524 tp->t_hwiflow = comhwiflow; 525 tp->t_softc = sc; 526 527 sc->sc_tty = tp; 528 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 529 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 530 sc->sc_rbavail = com_rbuf_size; 531 if (sc->sc_rbuf == NULL) { 532 aprint_error_dev(sc->sc_dev, 533 "unable to allocate ring buffer\n"); 534 return; 535 } 536 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 537 538 tty_attach(tp); 539 540 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 541 SET(sc->sc_mcr, MCR_IENABLE); 542 543 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 544 int maj; 545 546 /* locate the major number */ 547 maj = cdevsw_lookup_major(&com_cdevsw); 548 549 tp->t_dev = cn_tab->cn_dev = makedev(maj, 550 device_unit(sc->sc_dev)); 551 552 aprint_normal_dev(sc->sc_dev, "console\n"); 553 } 554 555 #ifdef KGDB 556 /* 557 * Allow kgdb to "take over" this port. If this is 558 * not the console and is the kgdb device, it has 559 * exclusive use. If it's the console _and_ the 560 * kgdb device, it doesn't. 561 */ 562 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 563 regsp->cr_iobase == comkgdbregs.cr_iobase) { 564 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 565 com_kgdb_attached = 1; 566 567 SET(sc->sc_hwflags, COM_HW_KGDB); 568 } 569 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 570 } 571 #endif 572 573 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 574 575 #ifdef RND_COM 576 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 577 RND_TYPE_TTY, 0); 578 #endif 579 580 /* if there are no enable/disable functions, assume the device 581 is always enabled */ 582 if (!sc->enable) 583 sc->enabled = 1; 584 585 com_config(sc); 586 587 SET(sc->sc_hwflags, COM_HW_DEV_OK); 588 } 589 590 void 591 com_config(struct com_softc *sc) 592 { 593 struct com_regs *regsp = &sc->sc_regs; 594 595 /* Disable interrupts before configuring the device. */ 596 if (sc->sc_type == COM_TYPE_PXA2x0) 597 sc->sc_ier = IER_EUART; 598 else 599 sc->sc_ier = 0; 600 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 601 (void) CSR_READ_1(regsp, COM_REG_IIR); 602 603 #ifdef COM_HAYESP 604 /* Look for a Hayes ESP board. */ 605 if (sc->sc_type == COM_TYPE_HAYESP) { 606 607 /* Set 16550 compatibility mode */ 608 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 609 HAYESP_SETMODE); 610 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 611 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 612 HAYESP_MODE_SCALE); 613 614 /* Set RTS/CTS flow control */ 615 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 616 HAYESP_SETFLOWTYPE); 617 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 618 HAYESP_FLOW_RTS); 619 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 620 HAYESP_FLOW_CTS); 621 622 /* Set flow control levels */ 623 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 624 HAYESP_SETRXFLOW); 625 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 626 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 627 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 628 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 629 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 630 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 631 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 632 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 633 } 634 #endif 635 636 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 637 com_enable_debugport(sc); 638 } 639 640 #if 0 641 static int 642 comcngetc_detached(dev_t dev) 643 { 644 return 0; 645 } 646 647 static void 648 comcnputc_detached(dev_t dev, int c) 649 { 650 } 651 #endif 652 653 int 654 com_detach(device_t self, int flags) 655 { 656 struct com_softc *sc = device_private(self); 657 int maj, mn; 658 659 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 660 return EBUSY; 661 662 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 663 (flags & DETACH_SHUTDOWN) != 0) 664 return EBUSY; 665 666 if (sc->disable != NULL && sc->enabled != 0) { 667 (*sc->disable)(sc); 668 sc->enabled = 0; 669 } 670 671 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 672 comconsattached = 0; 673 cn_tab = NULL; 674 } 675 676 /* locate the major number */ 677 maj = cdevsw_lookup_major(&com_cdevsw); 678 679 /* Nuke the vnodes for any open instances. */ 680 mn = device_unit(self); 681 vdevgone(maj, mn, mn, VCHR); 682 683 mn |= COMDIALOUT_MASK; 684 vdevgone(maj, mn, mn, VCHR); 685 686 if (sc->sc_rbuf == NULL) { 687 /* 688 * Ring buffer allocation failed in the com_attach_subr, 689 * only the tty is allocated, and nothing else. 690 */ 691 tty_free(sc->sc_tty); 692 return 0; 693 } 694 695 /* Free the receive buffer. */ 696 free(sc->sc_rbuf, M_DEVBUF); 697 698 /* Detach and free the tty. */ 699 tty_detach(sc->sc_tty); 700 tty_free(sc->sc_tty); 701 702 /* Unhook the soft interrupt handler. */ 703 softint_disestablish(sc->sc_si); 704 705 #ifdef RND_COM 706 /* Unhook the entropy source. */ 707 rnd_detach_source(&sc->rnd_source); 708 #endif 709 callout_destroy(&sc->sc_diag_callout); 710 711 /* Destroy the lock. */ 712 mutex_destroy(&sc->sc_lock); 713 714 return (0); 715 } 716 717 void 718 com_shutdown(struct com_softc *sc) 719 { 720 struct tty *tp = sc->sc_tty; 721 722 mutex_spin_enter(&sc->sc_lock); 723 724 /* If we were asserting flow control, then deassert it. */ 725 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 726 com_hwiflow(sc); 727 728 /* Clear any break condition set with TIOCSBRK. */ 729 com_break(sc, 0); 730 731 /* 732 * Hang up if necessary. Wait a bit, so the other side has time to 733 * notice even if we immediately open the port again. 734 * Avoid tsleeping above splhigh(). 735 */ 736 if (ISSET(tp->t_cflag, HUPCL)) { 737 com_modem(sc, 0); 738 mutex_spin_exit(&sc->sc_lock); 739 /* XXX will only timeout */ 740 (void) kpause(ttclos, false, hz, NULL); 741 mutex_spin_enter(&sc->sc_lock); 742 } 743 744 /* Turn off interrupts. */ 745 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 746 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 747 if (sc->sc_type == COM_TYPE_PXA2x0) 748 sc->sc_ier |= IER_ERXTOUT; 749 } else 750 sc->sc_ier = 0; 751 752 if (sc->sc_type == COM_TYPE_PXA2x0) 753 sc->sc_ier |= IER_EUART; 754 755 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 756 757 mutex_spin_exit(&sc->sc_lock); 758 759 if (sc->disable) { 760 #ifdef DIAGNOSTIC 761 if (!sc->enabled) 762 panic("com_shutdown: not enabled?"); 763 #endif 764 (*sc->disable)(sc); 765 sc->enabled = 0; 766 } 767 } 768 769 int 770 comopen(dev_t dev, int flag, int mode, struct lwp *l) 771 { 772 struct com_softc *sc; 773 struct tty *tp; 774 int s; 775 int error; 776 777 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 778 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 779 sc->sc_rbuf == NULL) 780 return (ENXIO); 781 782 if (!device_is_active(sc->sc_dev)) 783 return (ENXIO); 784 785 #ifdef KGDB 786 /* 787 * If this is the kgdb port, no other use is permitted. 788 */ 789 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 790 return (EBUSY); 791 #endif 792 793 tp = sc->sc_tty; 794 795 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 796 return (EBUSY); 797 798 s = spltty(); 799 800 /* 801 * Do the following iff this is a first open. 802 */ 803 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 804 struct termios t; 805 806 tp->t_dev = dev; 807 808 if (sc->enable) { 809 if ((*sc->enable)(sc)) { 810 splx(s); 811 aprint_error_dev(sc->sc_dev, 812 "device enable failed\n"); 813 return (EIO); 814 } 815 mutex_spin_enter(&sc->sc_lock); 816 sc->enabled = 1; 817 com_config(sc); 818 } else { 819 mutex_spin_enter(&sc->sc_lock); 820 } 821 822 /* Turn on interrupts. */ 823 sc->sc_ier = IER_ERXRDY | IER_ERLS; 824 if (!ISSET(tp->t_cflag, CLOCAL)) 825 sc->sc_ier |= IER_EMSC; 826 827 if (sc->sc_type == COM_TYPE_PXA2x0) 828 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 829 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 830 831 /* Fetch the current modem control status, needed later. */ 832 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 833 834 /* Clear PPS capture state on first open. */ 835 mutex_spin_enter(&timecounter_lock); 836 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 837 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 838 pps_init(&sc->sc_pps_state); 839 mutex_spin_exit(&timecounter_lock); 840 841 mutex_spin_exit(&sc->sc_lock); 842 843 /* 844 * Initialize the termios status to the defaults. Add in the 845 * sticky bits from TIOCSFLAGS. 846 */ 847 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 848 t.c_ospeed = comcons_info.rate; 849 t.c_cflag = comcons_info.cflag; 850 } else { 851 t.c_ospeed = TTYDEF_SPEED; 852 t.c_cflag = TTYDEF_CFLAG; 853 } 854 t.c_ispeed = t.c_ospeed; 855 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 856 SET(t.c_cflag, CLOCAL); 857 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 858 SET(t.c_cflag, CRTSCTS); 859 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 860 SET(t.c_cflag, MDMBUF); 861 /* Make sure comparam() will do something. */ 862 tp->t_ospeed = 0; 863 (void) comparam(tp, &t); 864 tp->t_iflag = TTYDEF_IFLAG; 865 tp->t_oflag = TTYDEF_OFLAG; 866 tp->t_lflag = TTYDEF_LFLAG; 867 ttychars(tp); 868 ttsetwater(tp); 869 870 mutex_spin_enter(&sc->sc_lock); 871 872 /* 873 * Turn on DTR. We must always do this, even if carrier is not 874 * present, because otherwise we'd have to use TIOCSDTR 875 * immediately after setting CLOCAL, which applications do not 876 * expect. We always assert DTR while the device is open 877 * unless explicitly requested to deassert it. 878 */ 879 com_modem(sc, 1); 880 881 /* Clear the input ring, and unblock. */ 882 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 883 sc->sc_rbavail = com_rbuf_size; 884 com_iflush(sc); 885 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 886 com_hwiflow(sc); 887 888 #ifdef COM_DEBUG 889 if (com_debug) 890 comstatus(sc, "comopen "); 891 #endif 892 893 mutex_spin_exit(&sc->sc_lock); 894 } 895 896 splx(s); 897 898 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 899 if (error) 900 goto bad; 901 902 error = (*tp->t_linesw->l_open)(dev, tp); 903 if (error) 904 goto bad; 905 906 return (0); 907 908 bad: 909 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 910 /* 911 * We failed to open the device, and nobody else had it opened. 912 * Clean up the state as appropriate. 913 */ 914 com_shutdown(sc); 915 } 916 917 return (error); 918 } 919 920 int 921 comclose(dev_t dev, int flag, int mode, struct lwp *l) 922 { 923 struct com_softc *sc = 924 device_lookup_private(&com_cd, COMUNIT(dev)); 925 struct tty *tp = sc->sc_tty; 926 927 /* XXX This is for cons.c. */ 928 if (!ISSET(tp->t_state, TS_ISOPEN)) 929 return (0); 930 931 (*tp->t_linesw->l_close)(tp, flag); 932 ttyclose(tp); 933 934 if (COM_ISALIVE(sc) == 0) 935 return (0); 936 937 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 938 /* 939 * Although we got a last close, the device may still be in 940 * use; e.g. if this was the dialout node, and there are still 941 * processes waiting for carrier on the non-dialout node. 942 */ 943 com_shutdown(sc); 944 } 945 946 return (0); 947 } 948 949 int 950 comread(dev_t dev, struct uio *uio, int flag) 951 { 952 struct com_softc *sc = 953 device_lookup_private(&com_cd, COMUNIT(dev)); 954 struct tty *tp = sc->sc_tty; 955 956 if (COM_ISALIVE(sc) == 0) 957 return (EIO); 958 959 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 960 } 961 962 int 963 comwrite(dev_t dev, struct uio *uio, int flag) 964 { 965 struct com_softc *sc = 966 device_lookup_private(&com_cd, COMUNIT(dev)); 967 struct tty *tp = sc->sc_tty; 968 969 if (COM_ISALIVE(sc) == 0) 970 return (EIO); 971 972 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 973 } 974 975 int 976 compoll(dev_t dev, int events, struct lwp *l) 977 { 978 struct com_softc *sc = 979 device_lookup_private(&com_cd, COMUNIT(dev)); 980 struct tty *tp = sc->sc_tty; 981 982 if (COM_ISALIVE(sc) == 0) 983 return (POLLHUP); 984 985 return ((*tp->t_linesw->l_poll)(tp, events, l)); 986 } 987 988 struct tty * 989 comtty(dev_t dev) 990 { 991 struct com_softc *sc = 992 device_lookup_private(&com_cd, COMUNIT(dev)); 993 struct tty *tp = sc->sc_tty; 994 995 return (tp); 996 } 997 998 int 999 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1000 { 1001 struct com_softc *sc; 1002 struct tty *tp; 1003 int error; 1004 1005 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1006 if (sc == NULL) 1007 return ENXIO; 1008 if (COM_ISALIVE(sc) == 0) 1009 return (EIO); 1010 1011 tp = sc->sc_tty; 1012 1013 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1014 if (error != EPASSTHROUGH) 1015 return (error); 1016 1017 error = ttioctl(tp, cmd, data, flag, l); 1018 if (error != EPASSTHROUGH) 1019 return (error); 1020 1021 error = 0; 1022 switch (cmd) { 1023 case TIOCSFLAGS: 1024 error = kauth_authorize_device_tty(l->l_cred, 1025 KAUTH_DEVICE_TTY_PRIVSET, tp); 1026 break; 1027 default: 1028 /* nothing */ 1029 break; 1030 } 1031 if (error) { 1032 return error; 1033 } 1034 1035 mutex_spin_enter(&sc->sc_lock); 1036 1037 switch (cmd) { 1038 case TIOCSBRK: 1039 com_break(sc, 1); 1040 break; 1041 1042 case TIOCCBRK: 1043 com_break(sc, 0); 1044 break; 1045 1046 case TIOCSDTR: 1047 com_modem(sc, 1); 1048 break; 1049 1050 case TIOCCDTR: 1051 com_modem(sc, 0); 1052 break; 1053 1054 case TIOCGFLAGS: 1055 *(int *)data = sc->sc_swflags; 1056 break; 1057 1058 case TIOCSFLAGS: 1059 sc->sc_swflags = *(int *)data; 1060 break; 1061 1062 case TIOCMSET: 1063 case TIOCMBIS: 1064 case TIOCMBIC: 1065 tiocm_to_com(sc, cmd, *(int *)data); 1066 break; 1067 1068 case TIOCMGET: 1069 *(int *)data = com_to_tiocm(sc); 1070 break; 1071 1072 case PPS_IOC_CREATE: 1073 case PPS_IOC_DESTROY: 1074 case PPS_IOC_GETPARAMS: 1075 case PPS_IOC_SETPARAMS: 1076 case PPS_IOC_GETCAP: 1077 case PPS_IOC_FETCH: 1078 #ifdef PPS_SYNC 1079 case PPS_IOC_KCBIND: 1080 #endif 1081 mutex_spin_enter(&timecounter_lock); 1082 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1083 mutex_spin_exit(&timecounter_lock); 1084 break; 1085 1086 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1087 mutex_spin_enter(&timecounter_lock); 1088 #ifndef PPS_TRAILING_EDGE 1089 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1090 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1091 #else 1092 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1093 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1094 #endif 1095 mutex_spin_exit(&timecounter_lock); 1096 break; 1097 1098 default: 1099 error = EPASSTHROUGH; 1100 break; 1101 } 1102 1103 mutex_spin_exit(&sc->sc_lock); 1104 1105 #ifdef COM_DEBUG 1106 if (com_debug) 1107 comstatus(sc, "comioctl "); 1108 #endif 1109 1110 return (error); 1111 } 1112 1113 integrate void 1114 com_schedrx(struct com_softc *sc) 1115 { 1116 1117 sc->sc_rx_ready = 1; 1118 1119 /* Wake up the poller. */ 1120 softint_schedule(sc->sc_si); 1121 } 1122 1123 void 1124 com_break(struct com_softc *sc, int onoff) 1125 { 1126 1127 if (onoff) 1128 SET(sc->sc_lcr, LCR_SBREAK); 1129 else 1130 CLR(sc->sc_lcr, LCR_SBREAK); 1131 1132 if (!sc->sc_heldchange) { 1133 if (sc->sc_tx_busy) { 1134 sc->sc_heldtbc = sc->sc_tbc; 1135 sc->sc_tbc = 0; 1136 sc->sc_heldchange = 1; 1137 } else 1138 com_loadchannelregs(sc); 1139 } 1140 } 1141 1142 void 1143 com_modem(struct com_softc *sc, int onoff) 1144 { 1145 1146 if (sc->sc_mcr_dtr == 0) 1147 return; 1148 1149 if (onoff) 1150 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1151 else 1152 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1153 1154 if (!sc->sc_heldchange) { 1155 if (sc->sc_tx_busy) { 1156 sc->sc_heldtbc = sc->sc_tbc; 1157 sc->sc_tbc = 0; 1158 sc->sc_heldchange = 1; 1159 } else 1160 com_loadchannelregs(sc); 1161 } 1162 } 1163 1164 void 1165 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1166 { 1167 u_char combits; 1168 1169 combits = 0; 1170 if (ISSET(ttybits, TIOCM_DTR)) 1171 SET(combits, MCR_DTR); 1172 if (ISSET(ttybits, TIOCM_RTS)) 1173 SET(combits, MCR_RTS); 1174 1175 switch (how) { 1176 case TIOCMBIC: 1177 CLR(sc->sc_mcr, combits); 1178 break; 1179 1180 case TIOCMBIS: 1181 SET(sc->sc_mcr, combits); 1182 break; 1183 1184 case TIOCMSET: 1185 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1186 SET(sc->sc_mcr, combits); 1187 break; 1188 } 1189 1190 if (!sc->sc_heldchange) { 1191 if (sc->sc_tx_busy) { 1192 sc->sc_heldtbc = sc->sc_tbc; 1193 sc->sc_tbc = 0; 1194 sc->sc_heldchange = 1; 1195 } else 1196 com_loadchannelregs(sc); 1197 } 1198 } 1199 1200 int 1201 com_to_tiocm(struct com_softc *sc) 1202 { 1203 u_char combits; 1204 int ttybits = 0; 1205 1206 combits = sc->sc_mcr; 1207 if (ISSET(combits, MCR_DTR)) 1208 SET(ttybits, TIOCM_DTR); 1209 if (ISSET(combits, MCR_RTS)) 1210 SET(ttybits, TIOCM_RTS); 1211 1212 combits = sc->sc_msr; 1213 if (ISSET(combits, MSR_DCD)) 1214 SET(ttybits, TIOCM_CD); 1215 if (ISSET(combits, MSR_CTS)) 1216 SET(ttybits, TIOCM_CTS); 1217 if (ISSET(combits, MSR_DSR)) 1218 SET(ttybits, TIOCM_DSR); 1219 if (ISSET(combits, MSR_RI | MSR_TERI)) 1220 SET(ttybits, TIOCM_RI); 1221 1222 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1223 SET(ttybits, TIOCM_LE); 1224 1225 return (ttybits); 1226 } 1227 1228 static u_char 1229 cflag2lcr(tcflag_t cflag) 1230 { 1231 u_char lcr = 0; 1232 1233 switch (ISSET(cflag, CSIZE)) { 1234 case CS5: 1235 SET(lcr, LCR_5BITS); 1236 break; 1237 case CS6: 1238 SET(lcr, LCR_6BITS); 1239 break; 1240 case CS7: 1241 SET(lcr, LCR_7BITS); 1242 break; 1243 case CS8: 1244 SET(lcr, LCR_8BITS); 1245 break; 1246 } 1247 if (ISSET(cflag, PARENB)) { 1248 SET(lcr, LCR_PENAB); 1249 if (!ISSET(cflag, PARODD)) 1250 SET(lcr, LCR_PEVEN); 1251 } 1252 if (ISSET(cflag, CSTOPB)) 1253 SET(lcr, LCR_STOPB); 1254 1255 return (lcr); 1256 } 1257 1258 int 1259 comparam(struct tty *tp, struct termios *t) 1260 { 1261 struct com_softc *sc = 1262 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1263 int ospeed; 1264 u_char lcr; 1265 1266 if (COM_ISALIVE(sc) == 0) 1267 return (EIO); 1268 1269 #ifdef COM_HAYESP 1270 if (sc->sc_type == COM_TYPE_HAYESP) { 1271 int prescaler, speed; 1272 1273 /* 1274 * Calculate UART clock prescaler. It should be in 1275 * range of 0 .. 3. 1276 */ 1277 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1278 prescaler++, speed /= 2) 1279 if ((ospeed = comspeed(speed, sc->sc_frequency, 1280 sc->sc_type)) > 0) 1281 break; 1282 1283 if (prescaler == 4) 1284 return (EINVAL); 1285 sc->sc_prescaler = prescaler; 1286 } else 1287 #endif 1288 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1289 1290 /* Check requested parameters. */ 1291 if (ospeed < 0) 1292 return (EINVAL); 1293 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1294 return (EINVAL); 1295 1296 /* 1297 * For the console, always force CLOCAL and !HUPCL, so that the port 1298 * is always active. 1299 */ 1300 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1301 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1302 SET(t->c_cflag, CLOCAL); 1303 CLR(t->c_cflag, HUPCL); 1304 } 1305 1306 /* 1307 * If there were no changes, don't do anything. This avoids dropping 1308 * input and improves performance when all we did was frob things like 1309 * VMIN and VTIME. 1310 */ 1311 if (tp->t_ospeed == t->c_ospeed && 1312 tp->t_cflag == t->c_cflag) 1313 return (0); 1314 1315 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1316 1317 mutex_spin_enter(&sc->sc_lock); 1318 1319 sc->sc_lcr = lcr; 1320 1321 /* 1322 * If we're not in a mode that assumes a connection is present, then 1323 * ignore carrier changes. 1324 */ 1325 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1326 sc->sc_msr_dcd = 0; 1327 else 1328 sc->sc_msr_dcd = MSR_DCD; 1329 /* 1330 * Set the flow control pins depending on the current flow control 1331 * mode. 1332 */ 1333 if (ISSET(t->c_cflag, CRTSCTS)) { 1334 sc->sc_mcr_dtr = MCR_DTR; 1335 sc->sc_mcr_rts = MCR_RTS; 1336 sc->sc_msr_cts = MSR_CTS; 1337 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1338 } else if (ISSET(t->c_cflag, MDMBUF)) { 1339 /* 1340 * For DTR/DCD flow control, make sure we don't toggle DTR for 1341 * carrier detection. 1342 */ 1343 sc->sc_mcr_dtr = 0; 1344 sc->sc_mcr_rts = MCR_DTR; 1345 sc->sc_msr_cts = MSR_DCD; 1346 sc->sc_efr = 0; 1347 } else { 1348 /* 1349 * If no flow control, then always set RTS. This will make 1350 * the other side happy if it mistakenly thinks we're doing 1351 * RTS/CTS flow control. 1352 */ 1353 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1354 sc->sc_mcr_rts = 0; 1355 sc->sc_msr_cts = 0; 1356 sc->sc_efr = 0; 1357 if (ISSET(sc->sc_mcr, MCR_DTR)) 1358 SET(sc->sc_mcr, MCR_RTS); 1359 else 1360 CLR(sc->sc_mcr, MCR_RTS); 1361 } 1362 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1363 1364 #if 0 1365 if (ospeed == 0) 1366 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1367 else 1368 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1369 #endif 1370 1371 sc->sc_dlbl = ospeed; 1372 sc->sc_dlbh = ospeed >> 8; 1373 1374 /* 1375 * Set the FIFO threshold based on the receive speed. 1376 * 1377 * * If it's a low speed, it's probably a mouse or some other 1378 * interactive device, so set the threshold low. 1379 * * If it's a high speed, trim the trigger level down to prevent 1380 * overflows. 1381 * * Otherwise set it a bit higher. 1382 */ 1383 if (sc->sc_type == COM_TYPE_HAYESP) 1384 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1385 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1386 if (t->c_ospeed <= 1200) 1387 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1388 else if (t->c_ospeed <= 38400) 1389 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1390 else 1391 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1392 } else 1393 sc->sc_fifo = 0; 1394 1395 /* And copy to tty. */ 1396 tp->t_ispeed = t->c_ospeed; 1397 tp->t_ospeed = t->c_ospeed; 1398 tp->t_cflag = t->c_cflag; 1399 1400 if (!sc->sc_heldchange) { 1401 if (sc->sc_tx_busy) { 1402 sc->sc_heldtbc = sc->sc_tbc; 1403 sc->sc_tbc = 0; 1404 sc->sc_heldchange = 1; 1405 } else 1406 com_loadchannelregs(sc); 1407 } 1408 1409 if (!ISSET(t->c_cflag, CHWFLOW)) { 1410 /* Disable the high water mark. */ 1411 sc->sc_r_hiwat = 0; 1412 sc->sc_r_lowat = 0; 1413 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1414 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1415 com_schedrx(sc); 1416 } 1417 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1418 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1419 com_hwiflow(sc); 1420 } 1421 } else { 1422 sc->sc_r_hiwat = com_rbuf_hiwat; 1423 sc->sc_r_lowat = com_rbuf_lowat; 1424 } 1425 1426 mutex_spin_exit(&sc->sc_lock); 1427 1428 /* 1429 * Update the tty layer's idea of the carrier bit, in case we changed 1430 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1431 * explicit request. 1432 */ 1433 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1434 1435 #ifdef COM_DEBUG 1436 if (com_debug) 1437 comstatus(sc, "comparam "); 1438 #endif 1439 1440 if (!ISSET(t->c_cflag, CHWFLOW)) { 1441 if (sc->sc_tx_stopped) { 1442 sc->sc_tx_stopped = 0; 1443 comstart(tp); 1444 } 1445 } 1446 1447 return (0); 1448 } 1449 1450 void 1451 com_iflush(struct com_softc *sc) 1452 { 1453 struct com_regs *regsp = &sc->sc_regs; 1454 #ifdef DIAGNOSTIC 1455 int reg; 1456 #endif 1457 int timo; 1458 1459 #ifdef DIAGNOSTIC 1460 reg = 0xffff; 1461 #endif 1462 timo = 50000; 1463 /* flush any pending I/O */ 1464 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1465 && --timo) 1466 #ifdef DIAGNOSTIC 1467 reg = 1468 #else 1469 (void) 1470 #endif 1471 CSR_READ_1(regsp, COM_REG_RXDATA); 1472 #ifdef DIAGNOSTIC 1473 if (!timo) 1474 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1475 #endif 1476 1477 #ifdef COM_16750 1478 uint8_t fifo; 1479 /* 1480 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1481 * This should prevent triggering busy interrupt while 1482 * manipulating divisors. 1483 */ 1484 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1485 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1486 CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST | 1487 FIFO_XMT_RST); 1488 delay(100); 1489 #endif 1490 } 1491 1492 void 1493 com_loadchannelregs(struct com_softc *sc) 1494 { 1495 struct com_regs *regsp = &sc->sc_regs; 1496 1497 /* XXXXX necessary? */ 1498 com_iflush(sc); 1499 1500 if (sc->sc_type == COM_TYPE_PXA2x0) 1501 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1502 else 1503 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1504 1505 if (sc->sc_type == COM_TYPE_OMAP) { 1506 /* disable before changing settings */ 1507 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1508 } 1509 1510 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1511 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1512 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1513 /* no EFR on alchemy */ 1514 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1515 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1516 } 1517 if (sc->sc_type == COM_TYPE_AU1x00) { 1518 /* alchemy has single separate 16-bit clock divisor register */ 1519 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1520 (sc->sc_dlbh << 8)); 1521 } else { 1522 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1523 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1524 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1525 } 1526 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1527 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1528 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1529 #ifdef COM_HAYESP 1530 if (sc->sc_type == COM_TYPE_HAYESP) { 1531 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1532 HAYESP_SETPRESCALER); 1533 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1534 sc->sc_prescaler); 1535 } 1536 #endif 1537 if (sc->sc_type == COM_TYPE_OMAP) { 1538 /* setup the fifos. the FCR value is not used as long 1539 as SCR[6] and SCR[7] are 0, which they are at reset 1540 and we never touch the SCR register */ 1541 uint8_t rx_fifo_trig = 40; 1542 uint8_t tx_fifo_trig = 60; 1543 uint8_t rx_start = 8; 1544 uint8_t rx_halt = 60; 1545 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1546 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1547 1548 /* enable access to TCR & TLR */ 1549 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1550 1551 /* write tcr and tlr values */ 1552 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1553 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1554 1555 /* disable access to TCR & TLR */ 1556 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1557 1558 /* enable again, but mode is based on speed */ 1559 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1560 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1561 } else { 1562 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1563 } 1564 } 1565 1566 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1567 } 1568 1569 int 1570 comhwiflow(struct tty *tp, int block) 1571 { 1572 struct com_softc *sc = 1573 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1574 1575 if (COM_ISALIVE(sc) == 0) 1576 return (0); 1577 1578 if (sc->sc_mcr_rts == 0) 1579 return (0); 1580 1581 mutex_spin_enter(&sc->sc_lock); 1582 1583 if (block) { 1584 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1585 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1586 com_hwiflow(sc); 1587 } 1588 } else { 1589 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1590 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1591 com_schedrx(sc); 1592 } 1593 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1594 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1595 com_hwiflow(sc); 1596 } 1597 } 1598 1599 mutex_spin_exit(&sc->sc_lock); 1600 return (1); 1601 } 1602 1603 /* 1604 * (un)block input via hw flowcontrol 1605 */ 1606 void 1607 com_hwiflow(struct com_softc *sc) 1608 { 1609 struct com_regs *regsp= &sc->sc_regs; 1610 1611 if (sc->sc_mcr_rts == 0) 1612 return; 1613 1614 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1615 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1616 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1617 } else { 1618 SET(sc->sc_mcr, sc->sc_mcr_rts); 1619 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1620 } 1621 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1622 } 1623 1624 1625 void 1626 comstart(struct tty *tp) 1627 { 1628 struct com_softc *sc = 1629 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1630 struct com_regs *regsp = &sc->sc_regs; 1631 int s; 1632 1633 if (COM_ISALIVE(sc) == 0) 1634 return; 1635 1636 s = spltty(); 1637 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1638 goto out; 1639 if (sc->sc_tx_stopped) 1640 goto out; 1641 if (!ttypull(tp)) 1642 goto out; 1643 1644 /* Grab the first contiguous region of buffer space. */ 1645 { 1646 u_char *tba; 1647 int tbc; 1648 1649 tba = tp->t_outq.c_cf; 1650 tbc = ndqb(&tp->t_outq, 0); 1651 1652 mutex_spin_enter(&sc->sc_lock); 1653 1654 sc->sc_tba = tba; 1655 sc->sc_tbc = tbc; 1656 } 1657 1658 SET(tp->t_state, TS_BUSY); 1659 sc->sc_tx_busy = 1; 1660 1661 /* Enable transmit completion interrupts if necessary. */ 1662 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1663 SET(sc->sc_ier, IER_ETXRDY); 1664 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1665 } 1666 1667 /* Output the first chunk of the contiguous buffer. */ 1668 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1669 u_int n; 1670 1671 n = sc->sc_tbc; 1672 if (n > sc->sc_fifolen) 1673 n = sc->sc_fifolen; 1674 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1675 sc->sc_tbc -= n; 1676 sc->sc_tba += n; 1677 } 1678 1679 mutex_spin_exit(&sc->sc_lock); 1680 out: 1681 splx(s); 1682 return; 1683 } 1684 1685 /* 1686 * Stop output on a line. 1687 */ 1688 void 1689 comstop(struct tty *tp, int flag) 1690 { 1691 struct com_softc *sc = 1692 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1693 1694 mutex_spin_enter(&sc->sc_lock); 1695 if (ISSET(tp->t_state, TS_BUSY)) { 1696 /* Stop transmitting at the next chunk. */ 1697 sc->sc_tbc = 0; 1698 sc->sc_heldtbc = 0; 1699 if (!ISSET(tp->t_state, TS_TTSTOP)) 1700 SET(tp->t_state, TS_FLUSH); 1701 } 1702 mutex_spin_exit(&sc->sc_lock); 1703 } 1704 1705 void 1706 comdiag(void *arg) 1707 { 1708 struct com_softc *sc = arg; 1709 int overflows, floods; 1710 1711 mutex_spin_enter(&sc->sc_lock); 1712 overflows = sc->sc_overflows; 1713 sc->sc_overflows = 0; 1714 floods = sc->sc_floods; 1715 sc->sc_floods = 0; 1716 sc->sc_errors = 0; 1717 mutex_spin_exit(&sc->sc_lock); 1718 1719 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1720 device_xname(sc->sc_dev), 1721 overflows, overflows == 1 ? "" : "s", 1722 floods, floods == 1 ? "" : "s"); 1723 } 1724 1725 integrate void 1726 com_rxsoft(struct com_softc *sc, struct tty *tp) 1727 { 1728 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1729 u_char *get, *end; 1730 u_int cc, scc; 1731 u_char lsr; 1732 int code; 1733 1734 end = sc->sc_ebuf; 1735 get = sc->sc_rbget; 1736 scc = cc = com_rbuf_size - sc->sc_rbavail; 1737 1738 if (cc == com_rbuf_size) { 1739 sc->sc_floods++; 1740 if (sc->sc_errors++ == 0) 1741 callout_reset(&sc->sc_diag_callout, 60 * hz, 1742 comdiag, sc); 1743 } 1744 1745 /* If not yet open, drop the entire buffer content here */ 1746 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1747 get += cc << 1; 1748 if (get >= end) 1749 get -= com_rbuf_size << 1; 1750 cc = 0; 1751 } 1752 while (cc) { 1753 code = get[0]; 1754 lsr = get[1]; 1755 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1756 if (ISSET(lsr, LSR_OE)) { 1757 sc->sc_overflows++; 1758 if (sc->sc_errors++ == 0) 1759 callout_reset(&sc->sc_diag_callout, 1760 60 * hz, comdiag, sc); 1761 } 1762 if (ISSET(lsr, LSR_BI | LSR_FE)) 1763 SET(code, TTY_FE); 1764 if (ISSET(lsr, LSR_PE)) 1765 SET(code, TTY_PE); 1766 } 1767 if ((*rint)(code, tp) == -1) { 1768 /* 1769 * The line discipline's buffer is out of space. 1770 */ 1771 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1772 /* 1773 * We're either not using flow control, or the 1774 * line discipline didn't tell us to block for 1775 * some reason. Either way, we have no way to 1776 * know when there's more space available, so 1777 * just drop the rest of the data. 1778 */ 1779 get += cc << 1; 1780 if (get >= end) 1781 get -= com_rbuf_size << 1; 1782 cc = 0; 1783 } else { 1784 /* 1785 * Don't schedule any more receive processing 1786 * until the line discipline tells us there's 1787 * space available (through comhwiflow()). 1788 * Leave the rest of the data in the input 1789 * buffer. 1790 */ 1791 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1792 } 1793 break; 1794 } 1795 get += 2; 1796 if (get >= end) 1797 get = sc->sc_rbuf; 1798 cc--; 1799 } 1800 1801 if (cc != scc) { 1802 sc->sc_rbget = get; 1803 mutex_spin_enter(&sc->sc_lock); 1804 1805 cc = sc->sc_rbavail += scc - cc; 1806 /* Buffers should be ok again, release possible block. */ 1807 if (cc >= sc->sc_r_lowat) { 1808 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1809 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1810 SET(sc->sc_ier, IER_ERXRDY); 1811 #ifdef COM_PXA2X0 1812 if (sc->sc_type == COM_TYPE_PXA2x0) 1813 SET(sc->sc_ier, IER_ERXTOUT); 1814 #endif 1815 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1816 } 1817 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1818 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1819 com_hwiflow(sc); 1820 } 1821 } 1822 mutex_spin_exit(&sc->sc_lock); 1823 } 1824 } 1825 1826 integrate void 1827 com_txsoft(struct com_softc *sc, struct tty *tp) 1828 { 1829 1830 CLR(tp->t_state, TS_BUSY); 1831 if (ISSET(tp->t_state, TS_FLUSH)) 1832 CLR(tp->t_state, TS_FLUSH); 1833 else 1834 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1835 (*tp->t_linesw->l_start)(tp); 1836 } 1837 1838 integrate void 1839 com_stsoft(struct com_softc *sc, struct tty *tp) 1840 { 1841 u_char msr, delta; 1842 1843 mutex_spin_enter(&sc->sc_lock); 1844 msr = sc->sc_msr; 1845 delta = sc->sc_msr_delta; 1846 sc->sc_msr_delta = 0; 1847 mutex_spin_exit(&sc->sc_lock); 1848 1849 if (ISSET(delta, sc->sc_msr_dcd)) { 1850 /* 1851 * Inform the tty layer that carrier detect changed. 1852 */ 1853 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1854 } 1855 1856 if (ISSET(delta, sc->sc_msr_cts)) { 1857 /* Block or unblock output according to flow control. */ 1858 if (ISSET(msr, sc->sc_msr_cts)) { 1859 sc->sc_tx_stopped = 0; 1860 (*tp->t_linesw->l_start)(tp); 1861 } else { 1862 sc->sc_tx_stopped = 1; 1863 } 1864 } 1865 1866 #ifdef COM_DEBUG 1867 if (com_debug) 1868 comstatus(sc, "com_stsoft"); 1869 #endif 1870 } 1871 1872 void 1873 comsoft(void *arg) 1874 { 1875 struct com_softc *sc = arg; 1876 struct tty *tp; 1877 1878 if (COM_ISALIVE(sc) == 0) 1879 return; 1880 1881 tp = sc->sc_tty; 1882 1883 if (sc->sc_rx_ready) { 1884 sc->sc_rx_ready = 0; 1885 com_rxsoft(sc, tp); 1886 } 1887 1888 if (sc->sc_st_check) { 1889 sc->sc_st_check = 0; 1890 com_stsoft(sc, tp); 1891 } 1892 1893 if (sc->sc_tx_done) { 1894 sc->sc_tx_done = 0; 1895 com_txsoft(sc, tp); 1896 } 1897 } 1898 1899 int 1900 comintr(void *arg) 1901 { 1902 struct com_softc *sc = arg; 1903 struct com_regs *regsp = &sc->sc_regs; 1904 1905 u_char *put, *end; 1906 u_int cc; 1907 u_char lsr, iir; 1908 1909 if (COM_ISALIVE(sc) == 0) 1910 return (0); 1911 1912 KASSERT(regsp != NULL); 1913 1914 mutex_spin_enter(&sc->sc_lock); 1915 iir = CSR_READ_1(regsp, COM_REG_IIR); 1916 1917 /* Handle ns16750-specific busy interrupt. */ 1918 #ifdef COM_16750 1919 int timeout; 1920 if ((iir & IIR_BUSY) == IIR_BUSY) { 1921 for (timeout = 10000; 1922 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 1923 if (timeout <= 0) { 1924 aprint_error_dev(sc->sc_dev, 1925 "timeout while waiting for BUSY interrupt " 1926 "acknowledge\n"); 1927 mutex_spin_exit(&sc->sc_lock); 1928 return (0); 1929 } 1930 1931 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1932 iir = CSR_READ_1(regsp, COM_REG_IIR); 1933 } 1934 #endif /* COM_16750 */ 1935 1936 1937 if (ISSET(iir, IIR_NOPEND)) { 1938 mutex_spin_exit(&sc->sc_lock); 1939 return (0); 1940 } 1941 1942 end = sc->sc_ebuf; 1943 put = sc->sc_rbput; 1944 cc = sc->sc_rbavail; 1945 1946 again: do { 1947 u_char msr, delta; 1948 1949 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1950 if (ISSET(lsr, LSR_BI)) { 1951 int cn_trapped = 0; 1952 1953 cn_check_magic(sc->sc_tty->t_dev, 1954 CNC_BREAK, com_cnm_state); 1955 if (cn_trapped) 1956 continue; 1957 #if defined(KGDB) && !defined(DDB) 1958 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1959 kgdb_connect(1); 1960 continue; 1961 } 1962 #endif 1963 } 1964 1965 if (ISSET(lsr, LSR_RCV_MASK) && 1966 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1967 while (cc > 0) { 1968 int cn_trapped = 0; 1969 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1970 put[1] = lsr; 1971 cn_check_magic(sc->sc_tty->t_dev, 1972 put[0], com_cnm_state); 1973 if (cn_trapped) 1974 goto next; 1975 put += 2; 1976 if (put >= end) 1977 put = sc->sc_rbuf; 1978 cc--; 1979 next: 1980 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1981 if (!ISSET(lsr, LSR_RCV_MASK)) 1982 break; 1983 } 1984 1985 /* 1986 * Current string of incoming characters ended because 1987 * no more data was available or we ran out of space. 1988 * Schedule a receive event if any data was received. 1989 * If we're out of space, turn off receive interrupts. 1990 */ 1991 sc->sc_rbput = put; 1992 sc->sc_rbavail = cc; 1993 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1994 sc->sc_rx_ready = 1; 1995 1996 /* 1997 * See if we are in danger of overflowing a buffer. If 1998 * so, use hardware flow control to ease the pressure. 1999 */ 2000 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2001 cc < sc->sc_r_hiwat) { 2002 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2003 com_hwiflow(sc); 2004 } 2005 2006 /* 2007 * If we're out of space, disable receive interrupts 2008 * until the queue has drained a bit. 2009 */ 2010 if (!cc) { 2011 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2012 #ifdef COM_PXA2X0 2013 if (sc->sc_type == COM_TYPE_PXA2x0) 2014 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2015 else 2016 #endif 2017 CLR(sc->sc_ier, IER_ERXRDY); 2018 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2019 } 2020 } else { 2021 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2022 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2023 continue; 2024 } 2025 } 2026 2027 msr = CSR_READ_1(regsp, COM_REG_MSR); 2028 delta = msr ^ sc->sc_msr; 2029 sc->sc_msr = msr; 2030 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2031 (delta & MSR_DCD)) { 2032 mutex_spin_enter(&timecounter_lock); 2033 pps_capture(&sc->sc_pps_state); 2034 pps_event(&sc->sc_pps_state, 2035 (msr & MSR_DCD) ? 2036 PPS_CAPTUREASSERT : 2037 PPS_CAPTURECLEAR); 2038 mutex_spin_exit(&timecounter_lock); 2039 } 2040 2041 /* 2042 * Process normal status changes 2043 */ 2044 if (ISSET(delta, sc->sc_msr_mask)) { 2045 SET(sc->sc_msr_delta, delta); 2046 2047 /* 2048 * Stop output immediately if we lose the output 2049 * flow control signal or carrier detect. 2050 */ 2051 if (ISSET(~msr, sc->sc_msr_mask)) { 2052 sc->sc_tbc = 0; 2053 sc->sc_heldtbc = 0; 2054 #ifdef COM_DEBUG 2055 if (com_debug) 2056 comstatus(sc, "comintr "); 2057 #endif 2058 } 2059 2060 sc->sc_st_check = 1; 2061 } 2062 } while (!ISSET((iir = 2063 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2064 /* 2065 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2066 * by IIR read, so we can't do this way: `process all interrupts, 2067 * then do TX if possible'. 2068 */ 2069 (iir & IIR_IMASK) != IIR_TXRDY); 2070 2071 /* 2072 * Read LSR again, since there may be an interrupt between 2073 * the last LSR read and IIR read above. 2074 */ 2075 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2076 2077 /* 2078 * See if data can be transmitted as well. 2079 * Schedule tx done event if no data left 2080 * and tty was marked busy. 2081 */ 2082 if (ISSET(lsr, LSR_TXRDY)) { 2083 /* 2084 * If we've delayed a parameter change, do it now, and restart 2085 * output. 2086 */ 2087 if (sc->sc_heldchange) { 2088 com_loadchannelregs(sc); 2089 sc->sc_heldchange = 0; 2090 sc->sc_tbc = sc->sc_heldtbc; 2091 sc->sc_heldtbc = 0; 2092 } 2093 2094 /* Output the next chunk of the contiguous buffer, if any. */ 2095 if (sc->sc_tbc > 0) { 2096 u_int n; 2097 2098 n = sc->sc_tbc; 2099 if (n > sc->sc_fifolen) 2100 n = sc->sc_fifolen; 2101 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2102 sc->sc_tbc -= n; 2103 sc->sc_tba += n; 2104 } else { 2105 /* Disable transmit completion interrupts if necessary. */ 2106 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2107 CLR(sc->sc_ier, IER_ETXRDY); 2108 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2109 } 2110 if (sc->sc_tx_busy) { 2111 sc->sc_tx_busy = 0; 2112 sc->sc_tx_done = 1; 2113 } 2114 } 2115 } 2116 2117 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2118 goto again; 2119 2120 mutex_spin_exit(&sc->sc_lock); 2121 2122 /* Wake up the poller. */ 2123 softint_schedule(sc->sc_si); 2124 2125 #ifdef RND_COM 2126 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2127 #endif 2128 2129 return (1); 2130 } 2131 2132 /* 2133 * The following functions are polled getc and putc routines, shared 2134 * by the console and kgdb glue. 2135 * 2136 * The read-ahead code is so that you can detect pending in-band 2137 * cn_magic in polled mode while doing output rather than having to 2138 * wait until the kernel decides it needs input. 2139 */ 2140 2141 #define MAX_READAHEAD 20 2142 static int com_readahead[MAX_READAHEAD]; 2143 static int com_readaheadcount = 0; 2144 2145 int 2146 com_common_getc(dev_t dev, struct com_regs *regsp) 2147 { 2148 int s = splserial(); 2149 u_char stat, c; 2150 2151 /* got a character from reading things earlier */ 2152 if (com_readaheadcount > 0) { 2153 int i; 2154 2155 c = com_readahead[0]; 2156 for (i = 1; i < com_readaheadcount; i++) { 2157 com_readahead[i-1] = com_readahead[i]; 2158 } 2159 com_readaheadcount--; 2160 splx(s); 2161 return (c); 2162 } 2163 2164 /* block until a character becomes available */ 2165 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2166 ; 2167 2168 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2169 stat = CSR_READ_1(regsp, COM_REG_IIR); 2170 { 2171 int cn_trapped = 0; /* unused */ 2172 #ifdef DDB 2173 extern int db_active; 2174 if (!db_active) 2175 #endif 2176 cn_check_magic(dev, c, com_cnm_state); 2177 } 2178 splx(s); 2179 return (c); 2180 } 2181 2182 static void 2183 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2184 { 2185 int s = splserial(); 2186 int cin, stat, timo; 2187 2188 if (com_readaheadcount < MAX_READAHEAD 2189 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2190 int cn_trapped = 0; 2191 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2192 stat = CSR_READ_1(regsp, COM_REG_IIR); 2193 cn_check_magic(dev, cin, com_cnm_state); 2194 com_readahead[com_readaheadcount++] = cin; 2195 } 2196 2197 /* wait for any pending transmission to finish */ 2198 timo = 150000; 2199 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2200 continue; 2201 2202 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2203 COM_BARRIER(regsp, BR | BW); 2204 2205 splx(s); 2206 } 2207 2208 /* 2209 * Initialize UART for use as console or KGDB line. 2210 */ 2211 int 2212 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2213 tcflag_t cflag) 2214 { 2215 2216 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2217 ®sp->cr_ioh)) 2218 return (ENOMEM); /* ??? */ 2219 2220 if (type == COM_TYPE_OMAP) { 2221 /* disable before changing settings */ 2222 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2223 } 2224 2225 rate = comspeed(rate, frequency, type); 2226 if (__predict_true(rate != -1)) { 2227 if (type == COM_TYPE_AU1x00) { 2228 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2229 } else { 2230 /* no EFR on alchemy */ 2231 if (type != COM_TYPE_16550_NOERS) { 2232 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2233 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2234 } 2235 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2236 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2237 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2238 } 2239 } 2240 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2241 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2242 CSR_WRITE_1(regsp, COM_REG_FIFO, 2243 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2244 2245 if (type == COM_TYPE_OMAP) { 2246 /* setup the fifos. the FCR value is not used as long 2247 as SCR[6] and SCR[7] are 0, which they are at reset 2248 and we never touch the SCR register */ 2249 uint8_t rx_fifo_trig = 40; 2250 uint8_t tx_fifo_trig = 60; 2251 uint8_t rx_start = 8; 2252 uint8_t rx_halt = 60; 2253 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2254 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2255 2256 /* enable access to TCR & TLR */ 2257 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2258 2259 /* write tcr and tlr values */ 2260 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2261 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2262 2263 /* disable access to TCR & TLR */ 2264 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2265 2266 /* enable again, but mode is based on speed */ 2267 if (rate > 230400) { 2268 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2269 } else { 2270 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2271 } 2272 } 2273 2274 #ifdef COM_PXA2X0 2275 if (type == COM_TYPE_PXA2x0) 2276 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2277 else 2278 #endif 2279 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2280 2281 return (0); 2282 } 2283 2284 int 2285 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2286 tcflag_t cflag) 2287 { 2288 int res; 2289 2290 comcons_info.regs = *regsp; 2291 2292 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2293 if (res) 2294 return (res); 2295 2296 cn_tab = &comcons; 2297 cn_init_magic(&com_cnm_state); 2298 cn_set_magic("\047\001"); /* default magic is BREAK */ 2299 2300 comcons_info.frequency = frequency; 2301 comcons_info.type = type; 2302 comcons_info.rate = rate; 2303 comcons_info.cflag = cflag; 2304 2305 return (0); 2306 } 2307 2308 int 2309 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2310 int type, tcflag_t cflag) 2311 { 2312 struct com_regs regs; 2313 2314 memset(®s, 0, sizeof regs); 2315 regs.cr_iot = iot; 2316 regs.cr_iobase = iobase; 2317 regs.cr_nports = COM_NPORTS; 2318 #ifdef COM_REGMAP 2319 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2320 #endif 2321 2322 return comcnattach1(®s, rate, frequency, type, cflag); 2323 } 2324 2325 static int 2326 comcnreattach(void) 2327 { 2328 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2329 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2330 } 2331 2332 int 2333 comcngetc(dev_t dev) 2334 { 2335 2336 return (com_common_getc(dev, &comcons_info.regs)); 2337 } 2338 2339 /* 2340 * Console kernel output character routine. 2341 */ 2342 void 2343 comcnputc(dev_t dev, int c) 2344 { 2345 2346 com_common_putc(dev, &comcons_info.regs, c); 2347 } 2348 2349 void 2350 comcnpollc(dev_t dev, int on) 2351 { 2352 2353 com_readaheadcount = 0; 2354 } 2355 2356 #ifdef KGDB 2357 int 2358 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2359 tcflag_t cflag) 2360 { 2361 int res; 2362 2363 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2364 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2365 #if !defined(DDB) 2366 return (EBUSY); /* cannot share with console */ 2367 #else 2368 comkgdbregs = *regsp; 2369 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2370 #endif 2371 } else { 2372 comkgdbregs = *regsp; 2373 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2374 if (res) 2375 return (res); 2376 2377 /* 2378 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2379 * expects this to be initialized 2380 */ 2381 cn_init_magic(&com_cnm_state); 2382 cn_set_magic("\047\001"); 2383 } 2384 2385 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2386 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2387 2388 return (0); 2389 } 2390 2391 int 2392 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2393 int frequency, int type, tcflag_t cflag) 2394 { 2395 struct com_regs regs; 2396 2397 regs.cr_iot = iot; 2398 regs.cr_nports = COM_NPORTS; 2399 regs.cr_iobase = iobase; 2400 #ifdef COM_REGMAP 2401 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2402 #endif 2403 2404 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2405 } 2406 2407 /* ARGSUSED */ 2408 int 2409 com_kgdb_getc(void *arg) 2410 { 2411 2412 return (com_common_getc(NODEV, &comkgdbregs)); 2413 } 2414 2415 /* ARGSUSED */ 2416 void 2417 com_kgdb_putc(void *arg, int c) 2418 { 2419 2420 com_common_putc(NODEV, &comkgdbregs, c); 2421 } 2422 #endif /* KGDB */ 2423 2424 /* helper function to identify the com ports used by 2425 console or KGDB (and not yet autoconf attached) */ 2426 int 2427 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2428 { 2429 bus_space_handle_t help; 2430 2431 if (!comconsattached && 2432 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2433 iobase == comcons_info.regs.cr_iobase) 2434 help = comcons_info.regs.cr_ioh; 2435 #ifdef KGDB 2436 else if (!com_kgdb_attached && 2437 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2438 iobase == comkgdbregs.cr_iobase) 2439 help = comkgdbregs.cr_ioh; 2440 #endif 2441 else 2442 return (0); 2443 2444 if (ioh) 2445 *ioh = help; 2446 return (1); 2447 } 2448 2449 /* 2450 * this routine exists to serve as a shutdown hook for systems that 2451 * have firmware which doesn't interact properly with a com device in 2452 * FIFO mode. 2453 */ 2454 bool 2455 com_cleanup(device_t self, int how) 2456 { 2457 struct com_softc *sc = device_private(self); 2458 2459 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2460 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2461 2462 return true; 2463 } 2464 2465 bool 2466 com_suspend(device_t self, const pmf_qual_t *qual) 2467 { 2468 struct com_softc *sc = device_private(self); 2469 2470 #if 0 2471 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2472 cn_tab = &comcons_suspend; 2473 #endif 2474 2475 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2476 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2477 2478 return true; 2479 } 2480 2481 bool 2482 com_resume(device_t self, const pmf_qual_t *qual) 2483 { 2484 struct com_softc *sc = device_private(self); 2485 2486 mutex_spin_enter(&sc->sc_lock); 2487 com_loadchannelregs(sc); 2488 mutex_spin_exit(&sc->sc_lock); 2489 2490 return true; 2491 } 2492
Indexes created Fri Sep 26 20:09:58 GMT 2025