com.c revision 1.312
1 /* $NetBSD: com.c,v 1.312 2013/07/27 06:54:35 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.312 2013/07/27 06:54:35 kiyohara Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 } while (/* CONSTCOND */ 0) 96 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/ioctl.h> 100 #include <sys/select.h> 101 #include <sys/poll.h> 102 #include <sys/tty.h> 103 #include <sys/proc.h> 104 #include <sys/conf.h> 105 #include <sys/file.h> 106 #include <sys/uio.h> 107 #include <sys/kernel.h> 108 #include <sys/syslog.h> 109 #include <sys/device.h> 110 #include <sys/malloc.h> 111 #include <sys/timepps.h> 112 #include <sys/vnode.h> 113 #include <sys/kauth.h> 114 #include <sys/intr.h> 115 #ifdef RND_COM 116 #include <sys/rnd.h> 117 #endif 118 119 120 #include <sys/bus.h> 121 122 #include <dev/ic/comreg.h> 123 #include <dev/ic/comvar.h> 124 #include <dev/ic/ns16550reg.h> 125 #include <dev/ic/st16650reg.h> 126 #ifdef COM_HAYESP 127 #include <dev/ic/hayespreg.h> 128 #endif 129 #define com_lcr com_cfcr 130 #include <dev/cons.h> 131 132 #ifdef COM_REGMAP 133 #define CSR_WRITE_1(r, o, v) \ 134 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 135 #define CSR_READ_1(r, o) \ 136 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 137 #define CSR_WRITE_2(r, o, v) \ 138 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 139 #define CSR_READ_2(r, o) \ 140 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 141 #define CSR_WRITE_MULTI(r, o, p, n) \ 142 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 143 #else 144 #define CSR_WRITE_1(r, o, v) \ 145 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 146 #define CSR_READ_1(r, o) \ 147 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 148 #define CSR_WRITE_2(r, o, v) \ 149 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 150 #define CSR_READ_2(r, o) \ 151 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 152 #define CSR_WRITE_MULTI(r, o, p, n) \ 153 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 154 #endif 155 156 157 static void com_enable_debugport(struct com_softc *); 158 159 void com_config(struct com_softc *); 160 void com_shutdown(struct com_softc *); 161 int comspeed(long, long, int); 162 static u_char cflag2lcr(tcflag_t); 163 int comparam(struct tty *, struct termios *); 164 void comstart(struct tty *); 165 int comhwiflow(struct tty *, int); 166 167 void com_loadchannelregs(struct com_softc *); 168 void com_hwiflow(struct com_softc *); 169 void com_break(struct com_softc *, int); 170 void com_modem(struct com_softc *, int); 171 void tiocm_to_com(struct com_softc *, u_long, int); 172 int com_to_tiocm(struct com_softc *); 173 void com_iflush(struct com_softc *); 174 175 int com_common_getc(dev_t, struct com_regs *); 176 static void com_common_putc(dev_t, struct com_regs *, int); 177 178 int cominit(struct com_regs *, int, int, int, tcflag_t); 179 180 static int comcnreattach(void); 181 182 int comcngetc(dev_t); 183 void comcnputc(dev_t, int); 184 void comcnpollc(dev_t, int); 185 186 #define integrate static inline 187 void comsoft(void *); 188 integrate void com_rxsoft(struct com_softc *, struct tty *); 189 integrate void com_txsoft(struct com_softc *, struct tty *); 190 integrate void com_stsoft(struct com_softc *, struct tty *); 191 integrate void com_schedrx(struct com_softc *); 192 void comdiag(void *); 193 194 extern struct cfdriver com_cd; 195 196 dev_type_open(comopen); 197 dev_type_close(comclose); 198 dev_type_read(comread); 199 dev_type_write(comwrite); 200 dev_type_ioctl(comioctl); 201 dev_type_stop(comstop); 202 dev_type_tty(comtty); 203 dev_type_poll(compoll); 204 205 static struct comcons_info comcons_info; 206 207 /* 208 * Following are all routines needed for COM to act as console 209 */ 210 static struct consdev comcons = { 211 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 212 NODEV, CN_NORMAL 213 }; 214 215 216 const struct cdevsw com_cdevsw = { 217 comopen, comclose, comread, comwrite, comioctl, 218 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 219 }; 220 221 /* 222 * Make this an option variable one can patch. 223 * But be warned: this must be a power of 2! 224 */ 225 u_int com_rbuf_size = COM_RING_SIZE; 226 227 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 228 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 229 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 230 231 static int comconsattached; 232 static struct cnm_state com_cnm_state; 233 234 #ifdef KGDB 235 #include <sys/kgdb.h> 236 237 static struct com_regs comkgdbregs; 238 static int com_kgdb_attached; 239 240 int com_kgdb_getc(void *); 241 void com_kgdb_putc(void *, int); 242 #endif /* KGDB */ 243 244 #ifdef COM_REGMAP 245 /* initializer for typical 16550-ish hardware */ 246 #define COM_REG_16550 { \ 247 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 248 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 249 /* 16750-specific register set, additional UART status register */ 250 #define COM_REG_16750 { \ 251 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 252 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } 254 255 #ifdef COM_16750 256 const bus_size_t com_std_map[32] = COM_REG_16750; 257 #else 258 const bus_size_t com_std_map[16] = COM_REG_16550; 259 #endif /* COM_16750 */ 260 #endif /* COM_REGMAP */ 261 262 #define COMUNIT_MASK 0x7ffff 263 #define COMDIALOUT_MASK 0x80000 264 265 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 266 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 267 268 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 269 device_is_active((sc)->sc_dev)) 270 271 #define BR BUS_SPACE_BARRIER_READ 272 #define BW BUS_SPACE_BARRIER_WRITE 273 #define COM_BARRIER(r, f) \ 274 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 275 276 /*ARGSUSED*/ 277 int 278 comspeed(long speed, long frequency, int type) 279 { 280 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 281 282 int x, err; 283 int divisor = 16; 284 285 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 286 divisor = 13; 287 } 288 289 #if 0 290 if (speed == 0) 291 return (0); 292 #endif 293 if (speed <= 0) 294 return (-1); 295 x = divrnd(frequency / divisor, speed); 296 if (x <= 0) 297 return (-1); 298 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 299 if (err < 0) 300 err = -err; 301 if (err > COM_TOLERANCE) 302 return (-1); 303 return (x); 304 305 #undef divrnd 306 } 307 308 #ifdef COM_DEBUG 309 int com_debug = 0; 310 311 void comstatus(struct com_softc *, const char *); 312 void 313 comstatus(struct com_softc *sc, const char *str) 314 { 315 struct tty *tp = sc->sc_tty; 316 317 aprint_normal_dev(sc->sc_dev, 318 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 319 str, 320 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 321 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 322 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 323 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 324 sc->sc_tx_stopped ? '+' : '-'); 325 326 aprint_normal_dev(sc->sc_dev, 327 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 328 str, 329 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 330 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 331 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 332 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 333 sc->sc_rx_flags); 334 } 335 #endif 336 337 int 338 com_probe_subr(struct com_regs *regs) 339 { 340 341 /* force access to id reg */ 342 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 343 CSR_WRITE_1(regs, COM_REG_IIR, 0); 344 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 345 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 346 return (0); 347 348 return (1); 349 } 350 351 int 352 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 353 { 354 struct com_regs regs; 355 356 regs.cr_iot = iot; 357 regs.cr_ioh = ioh; 358 #ifdef COM_REGMAP 359 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 360 #endif 361 362 return com_probe_subr(®s); 363 } 364 365 /* 366 * No locking in this routine; it is only called during attach, 367 * or with the port already locked. 368 */ 369 static void 370 com_enable_debugport(struct com_softc *sc) 371 { 372 373 /* Turn on line break interrupt, set carrier. */ 374 sc->sc_ier = IER_ERXRDY; 375 if (sc->sc_type == COM_TYPE_PXA2x0) 376 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 377 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 378 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 379 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 380 } 381 382 void 383 com_attach_subr(struct com_softc *sc) 384 { 385 struct com_regs *regsp = &sc->sc_regs; 386 struct tty *tp; 387 #ifdef COM_16650 388 u_int8_t lcr; 389 #endif 390 const char *fifo_msg = NULL; 391 prop_dictionary_t dict; 392 bool is_console = true; 393 394 aprint_naive("\n"); 395 396 dict = device_properties(sc->sc_dev); 397 prop_dictionary_get_bool(dict, "is_console", &is_console); 398 399 callout_init(&sc->sc_diag_callout, 0); 400 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 401 402 /* Disable interrupts before configuring the device. */ 403 if (sc->sc_type == COM_TYPE_PXA2x0) 404 sc->sc_ier = IER_EUART; 405 else 406 sc->sc_ier = 0; 407 408 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 409 410 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 411 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 412 comconsattached = 1; 413 414 if (cn_tab == NULL && comcnreattach() != 0) { 415 printf("can't re-init serial console @%lx\n", 416 (u_long)comcons_info.regs.cr_iobase); 417 } 418 419 #ifdef COM_16750 420 /* Use in comintr(). */ 421 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 422 #endif 423 424 /* Make sure the console is always "hardwired". */ 425 delay(10000); /* wait for output to finish */ 426 if (is_console) { 427 SET(sc->sc_hwflags, COM_HW_CONSOLE); 428 } 429 430 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 431 } 432 433 /* Probe for FIFO */ 434 switch (sc->sc_type) { 435 case COM_TYPE_HAYESP: 436 goto fifodone; 437 438 case COM_TYPE_AU1x00: 439 sc->sc_fifolen = 16; 440 fifo_msg = "Au1X00 UART, working fifo"; 441 SET(sc->sc_hwflags, COM_HW_FIFO); 442 goto fifodelay; 443 444 case COM_TYPE_16550_NOERS: 445 sc->sc_fifolen = 16; 446 fifo_msg = "ns16650, no ERS, working fifo"; 447 SET(sc->sc_hwflags, COM_HW_FIFO); 448 goto fifodelay; 449 450 case COM_TYPE_OMAP: 451 sc->sc_fifolen = 64; 452 fifo_msg = "OMAP UART, working fifo"; 453 SET(sc->sc_hwflags, COM_HW_FIFO); 454 goto fifodelay; 455 } 456 457 sc->sc_fifolen = 1; 458 /* look for a NS 16550AF UART with FIFOs */ 459 CSR_WRITE_1(regsp, COM_REG_FIFO, 460 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 461 delay(100); 462 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 463 == IIR_FIFO_MASK) 464 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 465 == FIFO_TRIGGER_14) { 466 SET(sc->sc_hwflags, COM_HW_FIFO); 467 468 #ifdef COM_16650 469 /* 470 * IIR changes into the EFR if LCR is set to LCR_EERS 471 * on 16650s. We also know IIR != 0 at this point. 472 * Write 0 into the EFR, and read it. If the result 473 * is 0, we have a 16650. 474 * 475 * Older 16650s were broken; the test to detect them 476 * is taken from the Linux driver. Apparently 477 * setting DLAB enable gives access to the EFR on 478 * these chips. 479 */ 480 lcr = CSR_READ_1(regsp, COM_REG_LCR); 481 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 482 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 483 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 484 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 485 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 486 CLR(sc->sc_hwflags, COM_HW_FIFO); 487 sc->sc_fifolen = 0; 488 } else { 489 SET(sc->sc_hwflags, COM_HW_FLOW); 490 sc->sc_fifolen = 32; 491 } 492 } else 493 #endif 494 sc->sc_fifolen = 16; 495 496 #ifdef COM_16650 497 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 498 if (sc->sc_fifolen == 0) 499 fifo_msg = "st16650, broken fifo"; 500 else if (sc->sc_fifolen == 32) 501 fifo_msg = "st16650a, working fifo"; 502 else 503 #endif 504 fifo_msg = "ns16550a, working fifo"; 505 } else 506 fifo_msg = "ns16550, broken fifo"; 507 else 508 fifo_msg = "ns8250 or ns16450, no fifo"; 509 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 510 fifodelay: 511 /* 512 * Some chips will clear down both Tx and Rx FIFOs when zero is 513 * written to com_fifo. If this chip is the console, writing zero 514 * results in some of the chip/FIFO description being lost, so delay 515 * printing it until now. 516 */ 517 delay(10); 518 aprint_normal(": %s\n", fifo_msg); 519 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 520 sc->sc_fifolen = 1; 521 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 522 } 523 524 fifodone: 525 526 tp = tty_alloc(); 527 tp->t_oproc = comstart; 528 tp->t_param = comparam; 529 tp->t_hwiflow = comhwiflow; 530 tp->t_softc = sc; 531 532 sc->sc_tty = tp; 533 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 534 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 535 sc->sc_rbavail = com_rbuf_size; 536 if (sc->sc_rbuf == NULL) { 537 aprint_error_dev(sc->sc_dev, 538 "unable to allocate ring buffer\n"); 539 return; 540 } 541 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 542 543 tty_attach(tp); 544 545 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 546 SET(sc->sc_mcr, MCR_IENABLE); 547 548 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 549 int maj; 550 551 /* locate the major number */ 552 maj = cdevsw_lookup_major(&com_cdevsw); 553 554 tp->t_dev = cn_tab->cn_dev = makedev(maj, 555 device_unit(sc->sc_dev)); 556 557 aprint_normal_dev(sc->sc_dev, "console\n"); 558 } 559 560 #ifdef KGDB 561 /* 562 * Allow kgdb to "take over" this port. If this is 563 * not the console and is the kgdb device, it has 564 * exclusive use. If it's the console _and_ the 565 * kgdb device, it doesn't. 566 */ 567 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 568 regsp->cr_iobase == comkgdbregs.cr_iobase) { 569 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 570 com_kgdb_attached = 1; 571 572 SET(sc->sc_hwflags, COM_HW_KGDB); 573 } 574 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 575 } 576 #endif 577 578 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 579 580 #ifdef RND_COM 581 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 582 RND_TYPE_TTY, 0); 583 #endif 584 585 /* if there are no enable/disable functions, assume the device 586 is always enabled */ 587 if (!sc->enable) 588 sc->enabled = 1; 589 590 com_config(sc); 591 592 SET(sc->sc_hwflags, COM_HW_DEV_OK); 593 } 594 595 void 596 com_config(struct com_softc *sc) 597 { 598 struct com_regs *regsp = &sc->sc_regs; 599 600 /* Disable interrupts before configuring the device. */ 601 if (sc->sc_type == COM_TYPE_PXA2x0) 602 sc->sc_ier = IER_EUART; 603 else 604 sc->sc_ier = 0; 605 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 606 (void) CSR_READ_1(regsp, COM_REG_IIR); 607 608 #ifdef COM_HAYESP 609 /* Look for a Hayes ESP board. */ 610 if (sc->sc_type == COM_TYPE_HAYESP) { 611 612 /* Set 16550 compatibility mode */ 613 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 614 HAYESP_SETMODE); 615 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 616 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 617 HAYESP_MODE_SCALE); 618 619 /* Set RTS/CTS flow control */ 620 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 621 HAYESP_SETFLOWTYPE); 622 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 623 HAYESP_FLOW_RTS); 624 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 625 HAYESP_FLOW_CTS); 626 627 /* Set flow control levels */ 628 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 629 HAYESP_SETRXFLOW); 630 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 631 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 632 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 633 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 634 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 635 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 636 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 637 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 638 } 639 #endif 640 641 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 642 com_enable_debugport(sc); 643 } 644 645 #if 0 646 static int 647 comcngetc_detached(dev_t dev) 648 { 649 return 0; 650 } 651 652 static void 653 comcnputc_detached(dev_t dev, int c) 654 { 655 } 656 #endif 657 658 int 659 com_detach(device_t self, int flags) 660 { 661 struct com_softc *sc = device_private(self); 662 int maj, mn; 663 664 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 665 return EBUSY; 666 667 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 668 (flags & DETACH_SHUTDOWN) != 0) 669 return EBUSY; 670 671 if (sc->disable != NULL && sc->enabled != 0) { 672 (*sc->disable)(sc); 673 sc->enabled = 0; 674 } 675 676 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 677 comconsattached = 0; 678 cn_tab = NULL; 679 } 680 681 /* locate the major number */ 682 maj = cdevsw_lookup_major(&com_cdevsw); 683 684 /* Nuke the vnodes for any open instances. */ 685 mn = device_unit(self); 686 vdevgone(maj, mn, mn, VCHR); 687 688 mn |= COMDIALOUT_MASK; 689 vdevgone(maj, mn, mn, VCHR); 690 691 if (sc->sc_rbuf == NULL) { 692 /* 693 * Ring buffer allocation failed in the com_attach_subr, 694 * only the tty is allocated, and nothing else. 695 */ 696 tty_free(sc->sc_tty); 697 return 0; 698 } 699 700 /* Free the receive buffer. */ 701 free(sc->sc_rbuf, M_DEVBUF); 702 703 /* Detach and free the tty. */ 704 tty_detach(sc->sc_tty); 705 tty_free(sc->sc_tty); 706 707 /* Unhook the soft interrupt handler. */ 708 softint_disestablish(sc->sc_si); 709 710 #ifdef RND_COM 711 /* Unhook the entropy source. */ 712 rnd_detach_source(&sc->rnd_source); 713 #endif 714 callout_destroy(&sc->sc_diag_callout); 715 716 /* Destroy the lock. */ 717 mutex_destroy(&sc->sc_lock); 718 719 return (0); 720 } 721 722 void 723 com_shutdown(struct com_softc *sc) 724 { 725 struct tty *tp = sc->sc_tty; 726 727 mutex_spin_enter(&sc->sc_lock); 728 729 /* If we were asserting flow control, then deassert it. */ 730 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 731 com_hwiflow(sc); 732 733 /* Clear any break condition set with TIOCSBRK. */ 734 com_break(sc, 0); 735 736 /* 737 * Hang up if necessary. Wait a bit, so the other side has time to 738 * notice even if we immediately open the port again. 739 * Avoid tsleeping above splhigh(). 740 */ 741 if (ISSET(tp->t_cflag, HUPCL)) { 742 com_modem(sc, 0); 743 mutex_spin_exit(&sc->sc_lock); 744 /* XXX will only timeout */ 745 (void) kpause(ttclos, false, hz, NULL); 746 mutex_spin_enter(&sc->sc_lock); 747 } 748 749 /* Turn off interrupts. */ 750 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 751 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 752 if (sc->sc_type == COM_TYPE_PXA2x0) 753 sc->sc_ier |= IER_ERXTOUT; 754 } else 755 sc->sc_ier = 0; 756 757 if (sc->sc_type == COM_TYPE_PXA2x0) 758 sc->sc_ier |= IER_EUART; 759 760 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 761 762 mutex_spin_exit(&sc->sc_lock); 763 764 if (sc->disable) { 765 #ifdef DIAGNOSTIC 766 if (!sc->enabled) 767 panic("com_shutdown: not enabled?"); 768 #endif 769 (*sc->disable)(sc); 770 sc->enabled = 0; 771 } 772 } 773 774 int 775 comopen(dev_t dev, int flag, int mode, struct lwp *l) 776 { 777 struct com_softc *sc; 778 struct tty *tp; 779 int s; 780 int error; 781 782 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 783 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 784 sc->sc_rbuf == NULL) 785 return (ENXIO); 786 787 if (!device_is_active(sc->sc_dev)) 788 return (ENXIO); 789 790 #ifdef KGDB 791 /* 792 * If this is the kgdb port, no other use is permitted. 793 */ 794 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 795 return (EBUSY); 796 #endif 797 798 tp = sc->sc_tty; 799 800 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 801 return (EBUSY); 802 803 s = spltty(); 804 805 /* 806 * Do the following iff this is a first open. 807 */ 808 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 809 struct termios t; 810 811 tp->t_dev = dev; 812 813 if (sc->enable) { 814 if ((*sc->enable)(sc)) { 815 splx(s); 816 aprint_error_dev(sc->sc_dev, 817 "device enable failed\n"); 818 return (EIO); 819 } 820 mutex_spin_enter(&sc->sc_lock); 821 sc->enabled = 1; 822 com_config(sc); 823 } else { 824 mutex_spin_enter(&sc->sc_lock); 825 } 826 827 /* Turn on interrupts. */ 828 sc->sc_ier = IER_ERXRDY | IER_ERLS; 829 if (!ISSET(tp->t_cflag, CLOCAL)) 830 sc->sc_ier |= IER_EMSC; 831 832 if (sc->sc_type == COM_TYPE_PXA2x0) 833 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 834 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 835 836 /* Fetch the current modem control status, needed later. */ 837 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 838 839 /* Clear PPS capture state on first open. */ 840 mutex_spin_enter(&timecounter_lock); 841 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 842 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 843 pps_init(&sc->sc_pps_state); 844 mutex_spin_exit(&timecounter_lock); 845 846 mutex_spin_exit(&sc->sc_lock); 847 848 /* 849 * Initialize the termios status to the defaults. Add in the 850 * sticky bits from TIOCSFLAGS. 851 */ 852 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 853 t.c_ospeed = comcons_info.rate; 854 t.c_cflag = comcons_info.cflag; 855 } else { 856 t.c_ospeed = TTYDEF_SPEED; 857 t.c_cflag = TTYDEF_CFLAG; 858 } 859 t.c_ispeed = t.c_ospeed; 860 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 861 SET(t.c_cflag, CLOCAL); 862 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 863 SET(t.c_cflag, CRTSCTS); 864 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 865 SET(t.c_cflag, MDMBUF); 866 /* Make sure comparam() will do something. */ 867 tp->t_ospeed = 0; 868 (void) comparam(tp, &t); 869 tp->t_iflag = TTYDEF_IFLAG; 870 tp->t_oflag = TTYDEF_OFLAG; 871 tp->t_lflag = TTYDEF_LFLAG; 872 ttychars(tp); 873 ttsetwater(tp); 874 875 mutex_spin_enter(&sc->sc_lock); 876 877 /* 878 * Turn on DTR. We must always do this, even if carrier is not 879 * present, because otherwise we'd have to use TIOCSDTR 880 * immediately after setting CLOCAL, which applications do not 881 * expect. We always assert DTR while the device is open 882 * unless explicitly requested to deassert it. 883 */ 884 com_modem(sc, 1); 885 886 /* Clear the input ring, and unblock. */ 887 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 888 sc->sc_rbavail = com_rbuf_size; 889 com_iflush(sc); 890 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 891 com_hwiflow(sc); 892 893 #ifdef COM_DEBUG 894 if (com_debug) 895 comstatus(sc, "comopen "); 896 #endif 897 898 mutex_spin_exit(&sc->sc_lock); 899 } 900 901 splx(s); 902 903 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 904 if (error) 905 goto bad; 906 907 error = (*tp->t_linesw->l_open)(dev, tp); 908 if (error) 909 goto bad; 910 911 return (0); 912 913 bad: 914 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 915 /* 916 * We failed to open the device, and nobody else had it opened. 917 * Clean up the state as appropriate. 918 */ 919 com_shutdown(sc); 920 } 921 922 return (error); 923 } 924 925 int 926 comclose(dev_t dev, int flag, int mode, struct lwp *l) 927 { 928 struct com_softc *sc = 929 device_lookup_private(&com_cd, COMUNIT(dev)); 930 struct tty *tp = sc->sc_tty; 931 932 /* XXX This is for cons.c. */ 933 if (!ISSET(tp->t_state, TS_ISOPEN)) 934 return (0); 935 936 (*tp->t_linesw->l_close)(tp, flag); 937 ttyclose(tp); 938 939 if (COM_ISALIVE(sc) == 0) 940 return (0); 941 942 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 943 /* 944 * Although we got a last close, the device may still be in 945 * use; e.g. if this was the dialout node, and there are still 946 * processes waiting for carrier on the non-dialout node. 947 */ 948 com_shutdown(sc); 949 } 950 951 return (0); 952 } 953 954 int 955 comread(dev_t dev, struct uio *uio, int flag) 956 { 957 struct com_softc *sc = 958 device_lookup_private(&com_cd, COMUNIT(dev)); 959 struct tty *tp = sc->sc_tty; 960 961 if (COM_ISALIVE(sc) == 0) 962 return (EIO); 963 964 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 965 } 966 967 int 968 comwrite(dev_t dev, struct uio *uio, int flag) 969 { 970 struct com_softc *sc = 971 device_lookup_private(&com_cd, COMUNIT(dev)); 972 struct tty *tp = sc->sc_tty; 973 974 if (COM_ISALIVE(sc) == 0) 975 return (EIO); 976 977 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 978 } 979 980 int 981 compoll(dev_t dev, int events, struct lwp *l) 982 { 983 struct com_softc *sc = 984 device_lookup_private(&com_cd, COMUNIT(dev)); 985 struct tty *tp = sc->sc_tty; 986 987 if (COM_ISALIVE(sc) == 0) 988 return (POLLHUP); 989 990 return ((*tp->t_linesw->l_poll)(tp, events, l)); 991 } 992 993 struct tty * 994 comtty(dev_t dev) 995 { 996 struct com_softc *sc = 997 device_lookup_private(&com_cd, COMUNIT(dev)); 998 struct tty *tp = sc->sc_tty; 999 1000 return (tp); 1001 } 1002 1003 int 1004 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1005 { 1006 struct com_softc *sc; 1007 struct tty *tp; 1008 int error; 1009 1010 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1011 if (sc == NULL) 1012 return ENXIO; 1013 if (COM_ISALIVE(sc) == 0) 1014 return (EIO); 1015 1016 tp = sc->sc_tty; 1017 1018 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1019 if (error != EPASSTHROUGH) 1020 return (error); 1021 1022 error = ttioctl(tp, cmd, data, flag, l); 1023 if (error != EPASSTHROUGH) 1024 return (error); 1025 1026 error = 0; 1027 switch (cmd) { 1028 case TIOCSFLAGS: 1029 error = kauth_authorize_device_tty(l->l_cred, 1030 KAUTH_DEVICE_TTY_PRIVSET, tp); 1031 break; 1032 default: 1033 /* nothing */ 1034 break; 1035 } 1036 if (error) { 1037 return error; 1038 } 1039 1040 mutex_spin_enter(&sc->sc_lock); 1041 1042 switch (cmd) { 1043 case TIOCSBRK: 1044 com_break(sc, 1); 1045 break; 1046 1047 case TIOCCBRK: 1048 com_break(sc, 0); 1049 break; 1050 1051 case TIOCSDTR: 1052 com_modem(sc, 1); 1053 break; 1054 1055 case TIOCCDTR: 1056 com_modem(sc, 0); 1057 break; 1058 1059 case TIOCGFLAGS: 1060 *(int *)data = sc->sc_swflags; 1061 break; 1062 1063 case TIOCSFLAGS: 1064 sc->sc_swflags = *(int *)data; 1065 break; 1066 1067 case TIOCMSET: 1068 case TIOCMBIS: 1069 case TIOCMBIC: 1070 tiocm_to_com(sc, cmd, *(int *)data); 1071 break; 1072 1073 case TIOCMGET: 1074 *(int *)data = com_to_tiocm(sc); 1075 break; 1076 1077 case PPS_IOC_CREATE: 1078 case PPS_IOC_DESTROY: 1079 case PPS_IOC_GETPARAMS: 1080 case PPS_IOC_SETPARAMS: 1081 case PPS_IOC_GETCAP: 1082 case PPS_IOC_FETCH: 1083 #ifdef PPS_SYNC 1084 case PPS_IOC_KCBIND: 1085 #endif 1086 mutex_spin_enter(&timecounter_lock); 1087 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1088 mutex_spin_exit(&timecounter_lock); 1089 break; 1090 1091 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1092 mutex_spin_enter(&timecounter_lock); 1093 #ifndef PPS_TRAILING_EDGE 1094 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1095 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1096 #else 1097 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1098 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1099 #endif 1100 mutex_spin_exit(&timecounter_lock); 1101 break; 1102 1103 default: 1104 error = EPASSTHROUGH; 1105 break; 1106 } 1107 1108 mutex_spin_exit(&sc->sc_lock); 1109 1110 #ifdef COM_DEBUG 1111 if (com_debug) 1112 comstatus(sc, "comioctl "); 1113 #endif 1114 1115 return (error); 1116 } 1117 1118 integrate void 1119 com_schedrx(struct com_softc *sc) 1120 { 1121 1122 sc->sc_rx_ready = 1; 1123 1124 /* Wake up the poller. */ 1125 softint_schedule(sc->sc_si); 1126 } 1127 1128 void 1129 com_break(struct com_softc *sc, int onoff) 1130 { 1131 1132 if (onoff) 1133 SET(sc->sc_lcr, LCR_SBREAK); 1134 else 1135 CLR(sc->sc_lcr, LCR_SBREAK); 1136 1137 if (!sc->sc_heldchange) { 1138 if (sc->sc_tx_busy) { 1139 sc->sc_heldtbc = sc->sc_tbc; 1140 sc->sc_tbc = 0; 1141 sc->sc_heldchange = 1; 1142 } else 1143 com_loadchannelregs(sc); 1144 } 1145 } 1146 1147 void 1148 com_modem(struct com_softc *sc, int onoff) 1149 { 1150 1151 if (sc->sc_mcr_dtr == 0) 1152 return; 1153 1154 if (onoff) 1155 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1156 else 1157 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1158 1159 if (!sc->sc_heldchange) { 1160 if (sc->sc_tx_busy) { 1161 sc->sc_heldtbc = sc->sc_tbc; 1162 sc->sc_tbc = 0; 1163 sc->sc_heldchange = 1; 1164 } else 1165 com_loadchannelregs(sc); 1166 } 1167 } 1168 1169 void 1170 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1171 { 1172 u_char combits; 1173 1174 combits = 0; 1175 if (ISSET(ttybits, TIOCM_DTR)) 1176 SET(combits, MCR_DTR); 1177 if (ISSET(ttybits, TIOCM_RTS)) 1178 SET(combits, MCR_RTS); 1179 1180 switch (how) { 1181 case TIOCMBIC: 1182 CLR(sc->sc_mcr, combits); 1183 break; 1184 1185 case TIOCMBIS: 1186 SET(sc->sc_mcr, combits); 1187 break; 1188 1189 case TIOCMSET: 1190 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1191 SET(sc->sc_mcr, combits); 1192 break; 1193 } 1194 1195 if (!sc->sc_heldchange) { 1196 if (sc->sc_tx_busy) { 1197 sc->sc_heldtbc = sc->sc_tbc; 1198 sc->sc_tbc = 0; 1199 sc->sc_heldchange = 1; 1200 } else 1201 com_loadchannelregs(sc); 1202 } 1203 } 1204 1205 int 1206 com_to_tiocm(struct com_softc *sc) 1207 { 1208 u_char combits; 1209 int ttybits = 0; 1210 1211 combits = sc->sc_mcr; 1212 if (ISSET(combits, MCR_DTR)) 1213 SET(ttybits, TIOCM_DTR); 1214 if (ISSET(combits, MCR_RTS)) 1215 SET(ttybits, TIOCM_RTS); 1216 1217 combits = sc->sc_msr; 1218 if (ISSET(combits, MSR_DCD)) 1219 SET(ttybits, TIOCM_CD); 1220 if (ISSET(combits, MSR_CTS)) 1221 SET(ttybits, TIOCM_CTS); 1222 if (ISSET(combits, MSR_DSR)) 1223 SET(ttybits, TIOCM_DSR); 1224 if (ISSET(combits, MSR_RI | MSR_TERI)) 1225 SET(ttybits, TIOCM_RI); 1226 1227 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1228 SET(ttybits, TIOCM_LE); 1229 1230 return (ttybits); 1231 } 1232 1233 static u_char 1234 cflag2lcr(tcflag_t cflag) 1235 { 1236 u_char lcr = 0; 1237 1238 switch (ISSET(cflag, CSIZE)) { 1239 case CS5: 1240 SET(lcr, LCR_5BITS); 1241 break; 1242 case CS6: 1243 SET(lcr, LCR_6BITS); 1244 break; 1245 case CS7: 1246 SET(lcr, LCR_7BITS); 1247 break; 1248 case CS8: 1249 SET(lcr, LCR_8BITS); 1250 break; 1251 } 1252 if (ISSET(cflag, PARENB)) { 1253 SET(lcr, LCR_PENAB); 1254 if (!ISSET(cflag, PARODD)) 1255 SET(lcr, LCR_PEVEN); 1256 } 1257 if (ISSET(cflag, CSTOPB)) 1258 SET(lcr, LCR_STOPB); 1259 1260 return (lcr); 1261 } 1262 1263 int 1264 comparam(struct tty *tp, struct termios *t) 1265 { 1266 struct com_softc *sc = 1267 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1268 int ospeed; 1269 u_char lcr; 1270 1271 if (COM_ISALIVE(sc) == 0) 1272 return (EIO); 1273 1274 #ifdef COM_HAYESP 1275 if (sc->sc_type == COM_TYPE_HAYESP) { 1276 int prescaler, speed; 1277 1278 /* 1279 * Calculate UART clock prescaler. It should be in 1280 * range of 0 .. 3. 1281 */ 1282 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1283 prescaler++, speed /= 2) 1284 if ((ospeed = comspeed(speed, sc->sc_frequency, 1285 sc->sc_type)) > 0) 1286 break; 1287 1288 if (prescaler == 4) 1289 return (EINVAL); 1290 sc->sc_prescaler = prescaler; 1291 } else 1292 #endif 1293 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1294 1295 /* Check requested parameters. */ 1296 if (ospeed < 0) 1297 return (EINVAL); 1298 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1299 return (EINVAL); 1300 1301 /* 1302 * For the console, always force CLOCAL and !HUPCL, so that the port 1303 * is always active. 1304 */ 1305 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1306 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1307 SET(t->c_cflag, CLOCAL); 1308 CLR(t->c_cflag, HUPCL); 1309 } 1310 1311 /* 1312 * If there were no changes, don't do anything. This avoids dropping 1313 * input and improves performance when all we did was frob things like 1314 * VMIN and VTIME. 1315 */ 1316 if (tp->t_ospeed == t->c_ospeed && 1317 tp->t_cflag == t->c_cflag) 1318 return (0); 1319 1320 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1321 1322 mutex_spin_enter(&sc->sc_lock); 1323 1324 sc->sc_lcr = lcr; 1325 1326 /* 1327 * If we're not in a mode that assumes a connection is present, then 1328 * ignore carrier changes. 1329 */ 1330 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1331 sc->sc_msr_dcd = 0; 1332 else 1333 sc->sc_msr_dcd = MSR_DCD; 1334 /* 1335 * Set the flow control pins depending on the current flow control 1336 * mode. 1337 */ 1338 if (ISSET(t->c_cflag, CRTSCTS)) { 1339 sc->sc_mcr_dtr = MCR_DTR; 1340 sc->sc_mcr_rts = MCR_RTS; 1341 sc->sc_msr_cts = MSR_CTS; 1342 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1343 } else if (ISSET(t->c_cflag, MDMBUF)) { 1344 /* 1345 * For DTR/DCD flow control, make sure we don't toggle DTR for 1346 * carrier detection. 1347 */ 1348 sc->sc_mcr_dtr = 0; 1349 sc->sc_mcr_rts = MCR_DTR; 1350 sc->sc_msr_cts = MSR_DCD; 1351 sc->sc_efr = 0; 1352 } else { 1353 /* 1354 * If no flow control, then always set RTS. This will make 1355 * the other side happy if it mistakenly thinks we're doing 1356 * RTS/CTS flow control. 1357 */ 1358 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1359 sc->sc_mcr_rts = 0; 1360 sc->sc_msr_cts = 0; 1361 sc->sc_efr = 0; 1362 if (ISSET(sc->sc_mcr, MCR_DTR)) 1363 SET(sc->sc_mcr, MCR_RTS); 1364 else 1365 CLR(sc->sc_mcr, MCR_RTS); 1366 } 1367 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1368 1369 #if 0 1370 if (ospeed == 0) 1371 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1372 else 1373 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1374 #endif 1375 1376 sc->sc_dlbl = ospeed; 1377 sc->sc_dlbh = ospeed >> 8; 1378 1379 /* 1380 * Set the FIFO threshold based on the receive speed. 1381 * 1382 * * If it's a low speed, it's probably a mouse or some other 1383 * interactive device, so set the threshold low. 1384 * * If it's a high speed, trim the trigger level down to prevent 1385 * overflows. 1386 * * Otherwise set it a bit higher. 1387 */ 1388 if (sc->sc_type == COM_TYPE_HAYESP) 1389 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1390 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1391 if (t->c_ospeed <= 1200) 1392 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1393 else if (t->c_ospeed <= 38400) 1394 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1395 else 1396 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1397 } else 1398 sc->sc_fifo = 0; 1399 1400 /* And copy to tty. */ 1401 tp->t_ispeed = t->c_ospeed; 1402 tp->t_ospeed = t->c_ospeed; 1403 tp->t_cflag = t->c_cflag; 1404 1405 if (!sc->sc_heldchange) { 1406 if (sc->sc_tx_busy) { 1407 sc->sc_heldtbc = sc->sc_tbc; 1408 sc->sc_tbc = 0; 1409 sc->sc_heldchange = 1; 1410 } else 1411 com_loadchannelregs(sc); 1412 } 1413 1414 if (!ISSET(t->c_cflag, CHWFLOW)) { 1415 /* Disable the high water mark. */ 1416 sc->sc_r_hiwat = 0; 1417 sc->sc_r_lowat = 0; 1418 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1419 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1420 com_schedrx(sc); 1421 } 1422 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1423 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1424 com_hwiflow(sc); 1425 } 1426 } else { 1427 sc->sc_r_hiwat = com_rbuf_hiwat; 1428 sc->sc_r_lowat = com_rbuf_lowat; 1429 } 1430 1431 mutex_spin_exit(&sc->sc_lock); 1432 1433 /* 1434 * Update the tty layer's idea of the carrier bit, in case we changed 1435 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1436 * explicit request. 1437 */ 1438 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1439 1440 #ifdef COM_DEBUG 1441 if (com_debug) 1442 comstatus(sc, "comparam "); 1443 #endif 1444 1445 if (!ISSET(t->c_cflag, CHWFLOW)) { 1446 if (sc->sc_tx_stopped) { 1447 sc->sc_tx_stopped = 0; 1448 comstart(tp); 1449 } 1450 } 1451 1452 return (0); 1453 } 1454 1455 void 1456 com_iflush(struct com_softc *sc) 1457 { 1458 struct com_regs *regsp = &sc->sc_regs; 1459 #ifdef DIAGNOSTIC 1460 int reg; 1461 #endif 1462 int timo; 1463 1464 #ifdef DIAGNOSTIC 1465 reg = 0xffff; 1466 #endif 1467 timo = 50000; 1468 /* flush any pending I/O */ 1469 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1470 && --timo) 1471 #ifdef DIAGNOSTIC 1472 reg = 1473 #else 1474 (void) 1475 #endif 1476 CSR_READ_1(regsp, COM_REG_RXDATA); 1477 #ifdef DIAGNOSTIC 1478 if (!timo) 1479 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1480 #endif 1481 1482 #ifdef COM_16750 1483 uint8_t fifo; 1484 /* 1485 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1486 * This should prevent triggering busy interrupt while 1487 * manipulating divisors. 1488 */ 1489 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1490 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1491 CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST | 1492 FIFO_XMT_RST); 1493 delay(100); 1494 #endif 1495 } 1496 1497 void 1498 com_loadchannelregs(struct com_softc *sc) 1499 { 1500 struct com_regs *regsp = &sc->sc_regs; 1501 1502 /* XXXXX necessary? */ 1503 com_iflush(sc); 1504 1505 if (sc->sc_type == COM_TYPE_PXA2x0) 1506 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1507 else 1508 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1509 1510 if (sc->sc_type == COM_TYPE_OMAP) { 1511 /* disable before changing settings */ 1512 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1513 } 1514 1515 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1516 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1517 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1518 /* no EFR on alchemy */ 1519 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1520 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1521 } 1522 if (sc->sc_type == COM_TYPE_AU1x00) { 1523 /* alchemy has single separate 16-bit clock divisor register */ 1524 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1525 (sc->sc_dlbh << 8)); 1526 } else { 1527 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1528 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1529 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1530 } 1531 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1532 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1533 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1534 #ifdef COM_HAYESP 1535 if (sc->sc_type == COM_TYPE_HAYESP) { 1536 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1537 HAYESP_SETPRESCALER); 1538 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1539 sc->sc_prescaler); 1540 } 1541 #endif 1542 if (sc->sc_type == COM_TYPE_OMAP) { 1543 /* setup the fifos. the FCR value is not used as long 1544 as SCR[6] and SCR[7] are 0, which they are at reset 1545 and we never touch the SCR register */ 1546 uint8_t rx_fifo_trig = 40; 1547 uint8_t tx_fifo_trig = 60; 1548 uint8_t rx_start = 8; 1549 uint8_t rx_halt = 60; 1550 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1551 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1552 1553 /* enable access to TCR & TLR */ 1554 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1555 1556 /* write tcr and tlr values */ 1557 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1558 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1559 1560 /* disable access to TCR & TLR */ 1561 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1562 1563 /* enable again, but mode is based on speed */ 1564 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1565 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1566 } else { 1567 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1568 } 1569 } 1570 1571 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1572 } 1573 1574 int 1575 comhwiflow(struct tty *tp, int block) 1576 { 1577 struct com_softc *sc = 1578 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1579 1580 if (COM_ISALIVE(sc) == 0) 1581 return (0); 1582 1583 if (sc->sc_mcr_rts == 0) 1584 return (0); 1585 1586 mutex_spin_enter(&sc->sc_lock); 1587 1588 if (block) { 1589 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1590 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1591 com_hwiflow(sc); 1592 } 1593 } else { 1594 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1595 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1596 com_schedrx(sc); 1597 } 1598 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1599 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1600 com_hwiflow(sc); 1601 } 1602 } 1603 1604 mutex_spin_exit(&sc->sc_lock); 1605 return (1); 1606 } 1607 1608 /* 1609 * (un)block input via hw flowcontrol 1610 */ 1611 void 1612 com_hwiflow(struct com_softc *sc) 1613 { 1614 struct com_regs *regsp= &sc->sc_regs; 1615 1616 if (sc->sc_mcr_rts == 0) 1617 return; 1618 1619 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1620 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1621 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1622 } else { 1623 SET(sc->sc_mcr, sc->sc_mcr_rts); 1624 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1625 } 1626 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1627 } 1628 1629 1630 void 1631 comstart(struct tty *tp) 1632 { 1633 struct com_softc *sc = 1634 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1635 struct com_regs *regsp = &sc->sc_regs; 1636 int s; 1637 1638 if (COM_ISALIVE(sc) == 0) 1639 return; 1640 1641 s = spltty(); 1642 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1643 goto out; 1644 if (sc->sc_tx_stopped) 1645 goto out; 1646 if (!ttypull(tp)) 1647 goto out; 1648 1649 /* Grab the first contiguous region of buffer space. */ 1650 { 1651 u_char *tba; 1652 int tbc; 1653 1654 tba = tp->t_outq.c_cf; 1655 tbc = ndqb(&tp->t_outq, 0); 1656 1657 mutex_spin_enter(&sc->sc_lock); 1658 1659 sc->sc_tba = tba; 1660 sc->sc_tbc = tbc; 1661 } 1662 1663 SET(tp->t_state, TS_BUSY); 1664 sc->sc_tx_busy = 1; 1665 1666 /* Enable transmit completion interrupts if necessary. */ 1667 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1668 SET(sc->sc_ier, IER_ETXRDY); 1669 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1670 } 1671 1672 /* Output the first chunk of the contiguous buffer. */ 1673 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1674 u_int n; 1675 1676 n = sc->sc_tbc; 1677 if (n > sc->sc_fifolen) 1678 n = sc->sc_fifolen; 1679 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1680 sc->sc_tbc -= n; 1681 sc->sc_tba += n; 1682 } 1683 1684 mutex_spin_exit(&sc->sc_lock); 1685 out: 1686 splx(s); 1687 return; 1688 } 1689 1690 /* 1691 * Stop output on a line. 1692 */ 1693 void 1694 comstop(struct tty *tp, int flag) 1695 { 1696 struct com_softc *sc = 1697 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1698 1699 mutex_spin_enter(&sc->sc_lock); 1700 if (ISSET(tp->t_state, TS_BUSY)) { 1701 /* Stop transmitting at the next chunk. */ 1702 sc->sc_tbc = 0; 1703 sc->sc_heldtbc = 0; 1704 if (!ISSET(tp->t_state, TS_TTSTOP)) 1705 SET(tp->t_state, TS_FLUSH); 1706 } 1707 mutex_spin_exit(&sc->sc_lock); 1708 } 1709 1710 void 1711 comdiag(void *arg) 1712 { 1713 struct com_softc *sc = arg; 1714 int overflows, floods; 1715 1716 mutex_spin_enter(&sc->sc_lock); 1717 overflows = sc->sc_overflows; 1718 sc->sc_overflows = 0; 1719 floods = sc->sc_floods; 1720 sc->sc_floods = 0; 1721 sc->sc_errors = 0; 1722 mutex_spin_exit(&sc->sc_lock); 1723 1724 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1725 device_xname(sc->sc_dev), 1726 overflows, overflows == 1 ? "" : "s", 1727 floods, floods == 1 ? "" : "s"); 1728 } 1729 1730 integrate void 1731 com_rxsoft(struct com_softc *sc, struct tty *tp) 1732 { 1733 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1734 u_char *get, *end; 1735 u_int cc, scc; 1736 u_char lsr; 1737 int code; 1738 1739 end = sc->sc_ebuf; 1740 get = sc->sc_rbget; 1741 scc = cc = com_rbuf_size - sc->sc_rbavail; 1742 1743 if (cc == com_rbuf_size) { 1744 sc->sc_floods++; 1745 if (sc->sc_errors++ == 0) 1746 callout_reset(&sc->sc_diag_callout, 60 * hz, 1747 comdiag, sc); 1748 } 1749 1750 /* If not yet open, drop the entire buffer content here */ 1751 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1752 get += cc << 1; 1753 if (get >= end) 1754 get -= com_rbuf_size << 1; 1755 cc = 0; 1756 } 1757 while (cc) { 1758 code = get[0]; 1759 lsr = get[1]; 1760 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1761 if (ISSET(lsr, LSR_OE)) { 1762 sc->sc_overflows++; 1763 if (sc->sc_errors++ == 0) 1764 callout_reset(&sc->sc_diag_callout, 1765 60 * hz, comdiag, sc); 1766 } 1767 if (ISSET(lsr, LSR_BI | LSR_FE)) 1768 SET(code, TTY_FE); 1769 if (ISSET(lsr, LSR_PE)) 1770 SET(code, TTY_PE); 1771 } 1772 if ((*rint)(code, tp) == -1) { 1773 /* 1774 * The line discipline's buffer is out of space. 1775 */ 1776 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1777 /* 1778 * We're either not using flow control, or the 1779 * line discipline didn't tell us to block for 1780 * some reason. Either way, we have no way to 1781 * know when there's more space available, so 1782 * just drop the rest of the data. 1783 */ 1784 get += cc << 1; 1785 if (get >= end) 1786 get -= com_rbuf_size << 1; 1787 cc = 0; 1788 } else { 1789 /* 1790 * Don't schedule any more receive processing 1791 * until the line discipline tells us there's 1792 * space available (through comhwiflow()). 1793 * Leave the rest of the data in the input 1794 * buffer. 1795 */ 1796 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1797 } 1798 break; 1799 } 1800 get += 2; 1801 if (get >= end) 1802 get = sc->sc_rbuf; 1803 cc--; 1804 } 1805 1806 if (cc != scc) { 1807 sc->sc_rbget = get; 1808 mutex_spin_enter(&sc->sc_lock); 1809 1810 cc = sc->sc_rbavail += scc - cc; 1811 /* Buffers should be ok again, release possible block. */ 1812 if (cc >= sc->sc_r_lowat) { 1813 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1814 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1815 SET(sc->sc_ier, IER_ERXRDY); 1816 #ifdef COM_PXA2X0 1817 if (sc->sc_type == COM_TYPE_PXA2x0) 1818 SET(sc->sc_ier, IER_ERXTOUT); 1819 #endif 1820 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1821 } 1822 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1823 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1824 com_hwiflow(sc); 1825 } 1826 } 1827 mutex_spin_exit(&sc->sc_lock); 1828 } 1829 } 1830 1831 integrate void 1832 com_txsoft(struct com_softc *sc, struct tty *tp) 1833 { 1834 1835 CLR(tp->t_state, TS_BUSY); 1836 if (ISSET(tp->t_state, TS_FLUSH)) 1837 CLR(tp->t_state, TS_FLUSH); 1838 else 1839 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1840 (*tp->t_linesw->l_start)(tp); 1841 } 1842 1843 integrate void 1844 com_stsoft(struct com_softc *sc, struct tty *tp) 1845 { 1846 u_char msr, delta; 1847 1848 mutex_spin_enter(&sc->sc_lock); 1849 msr = sc->sc_msr; 1850 delta = sc->sc_msr_delta; 1851 sc->sc_msr_delta = 0; 1852 mutex_spin_exit(&sc->sc_lock); 1853 1854 if (ISSET(delta, sc->sc_msr_dcd)) { 1855 /* 1856 * Inform the tty layer that carrier detect changed. 1857 */ 1858 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1859 } 1860 1861 if (ISSET(delta, sc->sc_msr_cts)) { 1862 /* Block or unblock output according to flow control. */ 1863 if (ISSET(msr, sc->sc_msr_cts)) { 1864 sc->sc_tx_stopped = 0; 1865 (*tp->t_linesw->l_start)(tp); 1866 } else { 1867 sc->sc_tx_stopped = 1; 1868 } 1869 } 1870 1871 #ifdef COM_DEBUG 1872 if (com_debug) 1873 comstatus(sc, "com_stsoft"); 1874 #endif 1875 } 1876 1877 void 1878 comsoft(void *arg) 1879 { 1880 struct com_softc *sc = arg; 1881 struct tty *tp; 1882 1883 if (COM_ISALIVE(sc) == 0) 1884 return; 1885 1886 tp = sc->sc_tty; 1887 1888 if (sc->sc_rx_ready) { 1889 sc->sc_rx_ready = 0; 1890 com_rxsoft(sc, tp); 1891 } 1892 1893 if (sc->sc_st_check) { 1894 sc->sc_st_check = 0; 1895 com_stsoft(sc, tp); 1896 } 1897 1898 if (sc->sc_tx_done) { 1899 sc->sc_tx_done = 0; 1900 com_txsoft(sc, tp); 1901 } 1902 } 1903 1904 int 1905 comintr(void *arg) 1906 { 1907 struct com_softc *sc = arg; 1908 struct com_regs *regsp = &sc->sc_regs; 1909 1910 u_char *put, *end; 1911 u_int cc; 1912 u_char lsr, iir; 1913 1914 if (COM_ISALIVE(sc) == 0) 1915 return (0); 1916 1917 KASSERT(regsp != NULL); 1918 1919 mutex_spin_enter(&sc->sc_lock); 1920 iir = CSR_READ_1(regsp, COM_REG_IIR); 1921 1922 /* Handle ns16750-specific busy interrupt. */ 1923 #ifdef COM_16750 1924 int timeout; 1925 if ((iir & IIR_BUSY) == IIR_BUSY) { 1926 for (timeout = 10000; 1927 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 1928 if (timeout <= 0) { 1929 aprint_error_dev(sc->sc_dev, 1930 "timeout while waiting for BUSY interrupt " 1931 "acknowledge\n"); 1932 mutex_spin_exit(&sc->sc_lock); 1933 return (0); 1934 } 1935 1936 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1937 iir = CSR_READ_1(regsp, COM_REG_IIR); 1938 } 1939 #endif /* COM_16750 */ 1940 1941 1942 if (ISSET(iir, IIR_NOPEND)) { 1943 mutex_spin_exit(&sc->sc_lock); 1944 return (0); 1945 } 1946 1947 end = sc->sc_ebuf; 1948 put = sc->sc_rbput; 1949 cc = sc->sc_rbavail; 1950 1951 again: do { 1952 u_char msr, delta; 1953 1954 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1955 if (ISSET(lsr, LSR_BI)) { 1956 int cn_trapped = 0; 1957 1958 cn_check_magic(sc->sc_tty->t_dev, 1959 CNC_BREAK, com_cnm_state); 1960 if (cn_trapped) 1961 continue; 1962 #if defined(KGDB) && !defined(DDB) 1963 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1964 kgdb_connect(1); 1965 continue; 1966 } 1967 #endif 1968 } 1969 1970 if (ISSET(lsr, LSR_RCV_MASK) && 1971 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1972 while (cc > 0) { 1973 int cn_trapped = 0; 1974 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1975 put[1] = lsr; 1976 cn_check_magic(sc->sc_tty->t_dev, 1977 put[0], com_cnm_state); 1978 if (cn_trapped) 1979 goto next; 1980 put += 2; 1981 if (put >= end) 1982 put = sc->sc_rbuf; 1983 cc--; 1984 next: 1985 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1986 if (!ISSET(lsr, LSR_RCV_MASK)) 1987 break; 1988 } 1989 1990 /* 1991 * Current string of incoming characters ended because 1992 * no more data was available or we ran out of space. 1993 * Schedule a receive event if any data was received. 1994 * If we're out of space, turn off receive interrupts. 1995 */ 1996 sc->sc_rbput = put; 1997 sc->sc_rbavail = cc; 1998 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1999 sc->sc_rx_ready = 1; 2000 2001 /* 2002 * See if we are in danger of overflowing a buffer. If 2003 * so, use hardware flow control to ease the pressure. 2004 */ 2005 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2006 cc < sc->sc_r_hiwat) { 2007 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2008 com_hwiflow(sc); 2009 } 2010 2011 /* 2012 * If we're out of space, disable receive interrupts 2013 * until the queue has drained a bit. 2014 */ 2015 if (!cc) { 2016 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2017 #ifdef COM_PXA2X0 2018 if (sc->sc_type == COM_TYPE_PXA2x0) 2019 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2020 else 2021 #endif 2022 CLR(sc->sc_ier, IER_ERXRDY); 2023 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2024 } 2025 } else { 2026 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2027 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2028 continue; 2029 } 2030 } 2031 2032 msr = CSR_READ_1(regsp, COM_REG_MSR); 2033 delta = msr ^ sc->sc_msr; 2034 sc->sc_msr = msr; 2035 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2036 (delta & MSR_DCD)) { 2037 mutex_spin_enter(&timecounter_lock); 2038 pps_capture(&sc->sc_pps_state); 2039 pps_event(&sc->sc_pps_state, 2040 (msr & MSR_DCD) ? 2041 PPS_CAPTUREASSERT : 2042 PPS_CAPTURECLEAR); 2043 mutex_spin_exit(&timecounter_lock); 2044 } 2045 2046 /* 2047 * Process normal status changes 2048 */ 2049 if (ISSET(delta, sc->sc_msr_mask)) { 2050 SET(sc->sc_msr_delta, delta); 2051 2052 /* 2053 * Stop output immediately if we lose the output 2054 * flow control signal or carrier detect. 2055 */ 2056 if (ISSET(~msr, sc->sc_msr_mask)) { 2057 sc->sc_tbc = 0; 2058 sc->sc_heldtbc = 0; 2059 #ifdef COM_DEBUG 2060 if (com_debug) 2061 comstatus(sc, "comintr "); 2062 #endif 2063 } 2064 2065 sc->sc_st_check = 1; 2066 } 2067 } while (!ISSET((iir = 2068 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2069 /* 2070 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2071 * by IIR read, so we can't do this way: `process all interrupts, 2072 * then do TX if possible'. 2073 */ 2074 (iir & IIR_IMASK) != IIR_TXRDY); 2075 2076 /* 2077 * Read LSR again, since there may be an interrupt between 2078 * the last LSR read and IIR read above. 2079 */ 2080 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2081 2082 /* 2083 * See if data can be transmitted as well. 2084 * Schedule tx done event if no data left 2085 * and tty was marked busy. 2086 */ 2087 if (ISSET(lsr, LSR_TXRDY)) { 2088 /* 2089 * If we've delayed a parameter change, do it now, and restart 2090 * output. 2091 */ 2092 if (sc->sc_heldchange) { 2093 com_loadchannelregs(sc); 2094 sc->sc_heldchange = 0; 2095 sc->sc_tbc = sc->sc_heldtbc; 2096 sc->sc_heldtbc = 0; 2097 } 2098 2099 /* Output the next chunk of the contiguous buffer, if any. */ 2100 if (sc->sc_tbc > 0) { 2101 u_int n; 2102 2103 n = sc->sc_tbc; 2104 if (n > sc->sc_fifolen) 2105 n = sc->sc_fifolen; 2106 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2107 sc->sc_tbc -= n; 2108 sc->sc_tba += n; 2109 } else { 2110 /* Disable transmit completion interrupts if necessary. */ 2111 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2112 CLR(sc->sc_ier, IER_ETXRDY); 2113 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2114 } 2115 if (sc->sc_tx_busy) { 2116 sc->sc_tx_busy = 0; 2117 sc->sc_tx_done = 1; 2118 } 2119 } 2120 } 2121 2122 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2123 goto again; 2124 2125 mutex_spin_exit(&sc->sc_lock); 2126 2127 /* Wake up the poller. */ 2128 softint_schedule(sc->sc_si); 2129 2130 #ifdef RND_COM 2131 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2132 #endif 2133 2134 return (1); 2135 } 2136 2137 /* 2138 * The following functions are polled getc and putc routines, shared 2139 * by the console and kgdb glue. 2140 * 2141 * The read-ahead code is so that you can detect pending in-band 2142 * cn_magic in polled mode while doing output rather than having to 2143 * wait until the kernel decides it needs input. 2144 */ 2145 2146 #define MAX_READAHEAD 20 2147 static int com_readahead[MAX_READAHEAD]; 2148 static int com_readaheadcount = 0; 2149 2150 int 2151 com_common_getc(dev_t dev, struct com_regs *regsp) 2152 { 2153 int s = splserial(); 2154 u_char stat, c; 2155 2156 /* got a character from reading things earlier */ 2157 if (com_readaheadcount > 0) { 2158 int i; 2159 2160 c = com_readahead[0]; 2161 for (i = 1; i < com_readaheadcount; i++) { 2162 com_readahead[i-1] = com_readahead[i]; 2163 } 2164 com_readaheadcount--; 2165 splx(s); 2166 return (c); 2167 } 2168 2169 /* block until a character becomes available */ 2170 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2171 ; 2172 2173 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2174 stat = CSR_READ_1(regsp, COM_REG_IIR); 2175 { 2176 int cn_trapped = 0; /* unused */ 2177 #ifdef DDB 2178 extern int db_active; 2179 if (!db_active) 2180 #endif 2181 cn_check_magic(dev, c, com_cnm_state); 2182 } 2183 splx(s); 2184 return (c); 2185 } 2186 2187 static void 2188 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2189 { 2190 int s = splserial(); 2191 int cin, stat, timo; 2192 2193 if (com_readaheadcount < MAX_READAHEAD 2194 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2195 int cn_trapped = 0; 2196 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2197 stat = CSR_READ_1(regsp, COM_REG_IIR); 2198 cn_check_magic(dev, cin, com_cnm_state); 2199 com_readahead[com_readaheadcount++] = cin; 2200 } 2201 2202 /* wait for any pending transmission to finish */ 2203 timo = 150000; 2204 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2205 continue; 2206 2207 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2208 COM_BARRIER(regsp, BR | BW); 2209 2210 splx(s); 2211 } 2212 2213 /* 2214 * Initialize UART for use as console or KGDB line. 2215 */ 2216 int 2217 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2218 tcflag_t cflag) 2219 { 2220 2221 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2222 ®sp->cr_ioh)) 2223 return (ENOMEM); /* ??? */ 2224 2225 if (type == COM_TYPE_OMAP) { 2226 /* disable before changing settings */ 2227 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2228 } 2229 2230 rate = comspeed(rate, frequency, type); 2231 if (__predict_true(rate != -1)) { 2232 if (type == COM_TYPE_AU1x00) { 2233 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2234 } else { 2235 /* no EFR on alchemy */ 2236 if (type != COM_TYPE_16550_NOERS) { 2237 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2238 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2239 } 2240 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2241 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2242 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2243 } 2244 } 2245 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2246 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2247 CSR_WRITE_1(regsp, COM_REG_FIFO, 2248 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2249 2250 if (type == COM_TYPE_OMAP) { 2251 /* setup the fifos. the FCR value is not used as long 2252 as SCR[6] and SCR[7] are 0, which they are at reset 2253 and we never touch the SCR register */ 2254 uint8_t rx_fifo_trig = 40; 2255 uint8_t tx_fifo_trig = 60; 2256 uint8_t rx_start = 8; 2257 uint8_t rx_halt = 60; 2258 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2259 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2260 2261 /* enable access to TCR & TLR */ 2262 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2263 2264 /* write tcr and tlr values */ 2265 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2266 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2267 2268 /* disable access to TCR & TLR */ 2269 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2270 2271 /* enable again, but mode is based on speed */ 2272 if (rate > 230400) { 2273 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2274 } else { 2275 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2276 } 2277 } 2278 2279 #ifdef COM_PXA2X0 2280 if (type == COM_TYPE_PXA2x0) 2281 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2282 else 2283 #endif 2284 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2285 2286 return (0); 2287 } 2288 2289 int 2290 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2291 tcflag_t cflag) 2292 { 2293 int res; 2294 2295 comcons_info.regs = *regsp; 2296 2297 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2298 if (res) 2299 return (res); 2300 2301 cn_tab = &comcons; 2302 cn_init_magic(&com_cnm_state); 2303 cn_set_magic("\047\001"); /* default magic is BREAK */ 2304 2305 comcons_info.frequency = frequency; 2306 comcons_info.type = type; 2307 comcons_info.rate = rate; 2308 comcons_info.cflag = cflag; 2309 2310 return (0); 2311 } 2312 2313 int 2314 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2315 int type, tcflag_t cflag) 2316 { 2317 struct com_regs regs; 2318 2319 memset(®s, 0, sizeof regs); 2320 regs.cr_iot = iot; 2321 regs.cr_iobase = iobase; 2322 regs.cr_nports = COM_NPORTS; 2323 #ifdef COM_REGMAP 2324 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2325 #endif 2326 2327 return comcnattach1(®s, rate, frequency, type, cflag); 2328 } 2329 2330 static int 2331 comcnreattach(void) 2332 { 2333 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2334 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2335 } 2336 2337 int 2338 comcngetc(dev_t dev) 2339 { 2340 2341 return (com_common_getc(dev, &comcons_info.regs)); 2342 } 2343 2344 /* 2345 * Console kernel output character routine. 2346 */ 2347 void 2348 comcnputc(dev_t dev, int c) 2349 { 2350 2351 com_common_putc(dev, &comcons_info.regs, c); 2352 } 2353 2354 void 2355 comcnpollc(dev_t dev, int on) 2356 { 2357 2358 com_readaheadcount = 0; 2359 } 2360 2361 #ifdef KGDB 2362 int 2363 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2364 tcflag_t cflag) 2365 { 2366 int res; 2367 2368 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2369 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2370 #if !defined(DDB) 2371 return (EBUSY); /* cannot share with console */ 2372 #else 2373 comkgdbregs = *regsp; 2374 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2375 #endif 2376 } else { 2377 comkgdbregs = *regsp; 2378 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2379 if (res) 2380 return (res); 2381 2382 /* 2383 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2384 * expects this to be initialized 2385 */ 2386 cn_init_magic(&com_cnm_state); 2387 cn_set_magic("\047\001"); 2388 } 2389 2390 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2391 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2392 2393 return (0); 2394 } 2395 2396 int 2397 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2398 int frequency, int type, tcflag_t cflag) 2399 { 2400 struct com_regs regs; 2401 2402 regs.cr_iot = iot; 2403 regs.cr_nports = COM_NPORTS; 2404 regs.cr_iobase = iobase; 2405 #ifdef COM_REGMAP 2406 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2407 #endif 2408 2409 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2410 } 2411 2412 /* ARGSUSED */ 2413 int 2414 com_kgdb_getc(void *arg) 2415 { 2416 2417 return (com_common_getc(NODEV, &comkgdbregs)); 2418 } 2419 2420 /* ARGSUSED */ 2421 void 2422 com_kgdb_putc(void *arg, int c) 2423 { 2424 2425 com_common_putc(NODEV, &comkgdbregs, c); 2426 } 2427 #endif /* KGDB */ 2428 2429 /* helper function to identify the com ports used by 2430 console or KGDB (and not yet autoconf attached) */ 2431 int 2432 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2433 { 2434 bus_space_handle_t help; 2435 2436 if (!comconsattached && 2437 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2438 iobase == comcons_info.regs.cr_iobase) 2439 help = comcons_info.regs.cr_ioh; 2440 #ifdef KGDB 2441 else if (!com_kgdb_attached && 2442 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2443 iobase == comkgdbregs.cr_iobase) 2444 help = comkgdbregs.cr_ioh; 2445 #endif 2446 else 2447 return (0); 2448 2449 if (ioh) 2450 *ioh = help; 2451 return (1); 2452 } 2453 2454 /* 2455 * this routine exists to serve as a shutdown hook for systems that 2456 * have firmware which doesn't interact properly with a com device in 2457 * FIFO mode. 2458 */ 2459 bool 2460 com_cleanup(device_t self, int how) 2461 { 2462 struct com_softc *sc = device_private(self); 2463 2464 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2465 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2466 2467 return true; 2468 } 2469 2470 bool 2471 com_suspend(device_t self, const pmf_qual_t *qual) 2472 { 2473 struct com_softc *sc = device_private(self); 2474 2475 #if 0 2476 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2477 cn_tab = &comcons_suspend; 2478 #endif 2479 2480 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2481 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2482 2483 return true; 2484 } 2485 2486 bool 2487 com_resume(device_t self, const pmf_qual_t *qual) 2488 { 2489 struct com_softc *sc = device_private(self); 2490 2491 mutex_spin_enter(&sc->sc_lock); 2492 com_loadchannelregs(sc); 2493 mutex_spin_exit(&sc->sc_lock); 2494 2495 return true; 2496 } 2497
Indexes created Wed Sep 24 22:09:59 GMT 2025