com.c revision 1.315
1 /* $NetBSD: com.c,v 1.315 2013/09/03 15:32:55 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.315 2013/09/03 15:32:55 jmcneill Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 } while (/* CONSTCOND */ 0) 96 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/ioctl.h> 100 #include <sys/select.h> 101 #include <sys/poll.h> 102 #include <sys/tty.h> 103 #include <sys/proc.h> 104 #include <sys/conf.h> 105 #include <sys/file.h> 106 #include <sys/uio.h> 107 #include <sys/kernel.h> 108 #include <sys/syslog.h> 109 #include <sys/device.h> 110 #include <sys/malloc.h> 111 #include <sys/timepps.h> 112 #include <sys/vnode.h> 113 #include <sys/kauth.h> 114 #include <sys/intr.h> 115 #ifdef RND_COM 116 #include <sys/rnd.h> 117 #endif 118 119 120 #include <sys/bus.h> 121 122 #include <dev/ic/comreg.h> 123 #include <dev/ic/comvar.h> 124 #include <dev/ic/ns16550reg.h> 125 #include <dev/ic/st16650reg.h> 126 #ifdef COM_HAYESP 127 #include <dev/ic/hayespreg.h> 128 #endif 129 #define com_lcr com_cfcr 130 #include <dev/cons.h> 131 132 #ifdef COM_REGMAP 133 #define CSR_WRITE_1(r, o, v) \ 134 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 135 #define CSR_READ_1(r, o) \ 136 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 137 #define CSR_WRITE_2(r, o, v) \ 138 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 139 #define CSR_READ_2(r, o) \ 140 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 141 #define CSR_WRITE_MULTI(r, o, p, n) \ 142 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 143 #else 144 #define CSR_WRITE_1(r, o, v) \ 145 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 146 #define CSR_READ_1(r, o) \ 147 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 148 #define CSR_WRITE_2(r, o, v) \ 149 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 150 #define CSR_READ_2(r, o) \ 151 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 152 #define CSR_WRITE_MULTI(r, o, p, n) \ 153 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 154 #endif 155 156 157 static void com_enable_debugport(struct com_softc *); 158 159 void com_config(struct com_softc *); 160 void com_shutdown(struct com_softc *); 161 int comspeed(long, long, int); 162 static u_char cflag2lcr(tcflag_t); 163 int comparam(struct tty *, struct termios *); 164 void comstart(struct tty *); 165 int comhwiflow(struct tty *, int); 166 167 void com_loadchannelregs(struct com_softc *); 168 void com_hwiflow(struct com_softc *); 169 void com_break(struct com_softc *, int); 170 void com_modem(struct com_softc *, int); 171 void tiocm_to_com(struct com_softc *, u_long, int); 172 int com_to_tiocm(struct com_softc *); 173 void com_iflush(struct com_softc *); 174 175 int com_common_getc(dev_t, struct com_regs *); 176 static void com_common_putc(dev_t, struct com_regs *, int); 177 178 int cominit(struct com_regs *, int, int, int, tcflag_t); 179 180 static int comcnreattach(void); 181 182 int comcngetc(dev_t); 183 void comcnputc(dev_t, int); 184 void comcnpollc(dev_t, int); 185 186 #define integrate static inline 187 void comsoft(void *); 188 integrate void com_rxsoft(struct com_softc *, struct tty *); 189 integrate void com_txsoft(struct com_softc *, struct tty *); 190 integrate void com_stsoft(struct com_softc *, struct tty *); 191 integrate void com_schedrx(struct com_softc *); 192 void comdiag(void *); 193 194 extern struct cfdriver com_cd; 195 196 dev_type_open(comopen); 197 dev_type_close(comclose); 198 dev_type_read(comread); 199 dev_type_write(comwrite); 200 dev_type_ioctl(comioctl); 201 dev_type_stop(comstop); 202 dev_type_tty(comtty); 203 dev_type_poll(compoll); 204 205 static struct comcons_info comcons_info; 206 207 /* 208 * Following are all routines needed for COM to act as console 209 */ 210 static struct consdev comcons = { 211 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 212 NODEV, CN_NORMAL 213 }; 214 215 216 const struct cdevsw com_cdevsw = { 217 comopen, comclose, comread, comwrite, comioctl, 218 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 219 }; 220 221 /* 222 * Make this an option variable one can patch. 223 * But be warned: this must be a power of 2! 224 */ 225 u_int com_rbuf_size = COM_RING_SIZE; 226 227 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 228 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 229 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 230 231 static int comconsattached; 232 static struct cnm_state com_cnm_state; 233 234 #ifdef KGDB 235 #include <sys/kgdb.h> 236 237 static struct com_regs comkgdbregs; 238 static int com_kgdb_attached; 239 240 int com_kgdb_getc(void *); 241 void com_kgdb_putc(void *, int); 242 #endif /* KGDB */ 243 244 #ifdef COM_REGMAP 245 /* initializer for typical 16550-ish hardware */ 246 #define COM_REG_16550 { \ 247 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 248 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 249 const bus_size_t com_std_map[16] = COM_REG_16550; 250 #endif /* COM_REGMAP */ 251 252 #define COMUNIT_MASK 0x7ffff 253 #define COMDIALOUT_MASK 0x80000 254 255 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 256 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 257 258 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 259 device_is_active((sc)->sc_dev)) 260 261 #define BR BUS_SPACE_BARRIER_READ 262 #define BW BUS_SPACE_BARRIER_WRITE 263 #define COM_BARRIER(r, f) \ 264 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 265 266 /*ARGSUSED*/ 267 int 268 comspeed(long speed, long frequency, int type) 269 { 270 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 271 272 int x, err; 273 int divisor = 16; 274 275 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 276 divisor = 13; 277 } 278 279 #if 0 280 if (speed == 0) 281 return (0); 282 #endif 283 if (speed <= 0) 284 return (-1); 285 x = divrnd(frequency / divisor, speed); 286 if (x <= 0) 287 return (-1); 288 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 289 if (err < 0) 290 err = -err; 291 if (err > COM_TOLERANCE) 292 return (-1); 293 return (x); 294 295 #undef divrnd 296 } 297 298 #ifdef COM_DEBUG 299 int com_debug = 0; 300 301 void comstatus(struct com_softc *, const char *); 302 void 303 comstatus(struct com_softc *sc, const char *str) 304 { 305 struct tty *tp = sc->sc_tty; 306 307 aprint_normal_dev(sc->sc_dev, 308 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 309 str, 310 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 311 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 312 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 313 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 314 sc->sc_tx_stopped ? '+' : '-'); 315 316 aprint_normal_dev(sc->sc_dev, 317 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 318 str, 319 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 320 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 321 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 322 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 323 sc->sc_rx_flags); 324 } 325 #endif 326 327 int 328 com_probe_subr(struct com_regs *regs) 329 { 330 331 /* force access to id reg */ 332 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 333 CSR_WRITE_1(regs, COM_REG_IIR, 0); 334 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 335 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 336 return (0); 337 338 return (1); 339 } 340 341 int 342 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 343 { 344 struct com_regs regs; 345 346 regs.cr_iot = iot; 347 regs.cr_ioh = ioh; 348 #ifdef COM_REGMAP 349 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 350 #endif 351 352 return com_probe_subr(®s); 353 } 354 355 /* 356 * No locking in this routine; it is only called during attach, 357 * or with the port already locked. 358 */ 359 static void 360 com_enable_debugport(struct com_softc *sc) 361 { 362 363 /* Turn on line break interrupt, set carrier. */ 364 sc->sc_ier = IER_ERXRDY; 365 if (sc->sc_type == COM_TYPE_PXA2x0) 366 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 367 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 368 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 369 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 370 } 371 372 void 373 com_attach_subr(struct com_softc *sc) 374 { 375 struct com_regs *regsp = &sc->sc_regs; 376 struct tty *tp; 377 u_int8_t lcr; 378 const char *fifo_msg = NULL; 379 prop_dictionary_t dict; 380 bool is_console = true; 381 382 aprint_naive("\n"); 383 384 dict = device_properties(sc->sc_dev); 385 prop_dictionary_get_bool(dict, "is_console", &is_console); 386 387 callout_init(&sc->sc_diag_callout, 0); 388 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 389 390 /* Disable interrupts before configuring the device. */ 391 if (sc->sc_type == COM_TYPE_PXA2x0) 392 sc->sc_ier = IER_EUART; 393 else 394 sc->sc_ier = 0; 395 396 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 397 398 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 399 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 400 comconsattached = 1; 401 402 if (cn_tab == NULL && comcnreattach() != 0) { 403 printf("can't re-init serial console @%lx\n", 404 (u_long)comcons_info.regs.cr_iobase); 405 } 406 407 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 408 409 /* Make sure the console is always "hardwired". */ 410 delay(10000); /* wait for output to finish */ 411 if (is_console) { 412 SET(sc->sc_hwflags, COM_HW_CONSOLE); 413 } 414 415 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 416 } 417 418 /* Probe for FIFO */ 419 switch (sc->sc_type) { 420 case COM_TYPE_HAYESP: 421 goto fifodone; 422 423 case COM_TYPE_AU1x00: 424 sc->sc_fifolen = 16; 425 fifo_msg = "Au1X00 UART, working fifo"; 426 SET(sc->sc_hwflags, COM_HW_FIFO); 427 goto fifodelay; 428 429 case COM_TYPE_16550_NOERS: 430 sc->sc_fifolen = 16; 431 fifo_msg = "ns16650, no ERS, working fifo"; 432 SET(sc->sc_hwflags, COM_HW_FIFO); 433 goto fifodelay; 434 435 case COM_TYPE_OMAP: 436 sc->sc_fifolen = 64; 437 fifo_msg = "OMAP UART, working fifo"; 438 SET(sc->sc_hwflags, COM_HW_FIFO); 439 goto fifodelay; 440 } 441 442 sc->sc_fifolen = 1; 443 /* look for a NS 16550AF UART with FIFOs */ 444 CSR_WRITE_1(regsp, COM_REG_FIFO, 445 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 446 delay(100); 447 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 448 == IIR_FIFO_MASK) 449 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 450 == FIFO_TRIGGER_14) { 451 SET(sc->sc_hwflags, COM_HW_FIFO); 452 453 #ifdef COM_16650 454 /* 455 * IIR changes into the EFR if LCR is set to LCR_EERS 456 * on 16650s. We also know IIR != 0 at this point. 457 * Write 0 into the EFR, and read it. If the result 458 * is 0, we have a 16650. 459 * 460 * Older 16650s were broken; the test to detect them 461 * is taken from the Linux driver. Apparently 462 * setting DLAB enable gives access to the EFR on 463 * these chips. 464 */ 465 lcr = CSR_READ_1(regsp, COM_REG_LCR); 466 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 467 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 468 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 469 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 470 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 471 CLR(sc->sc_hwflags, COM_HW_FIFO); 472 sc->sc_fifolen = 0; 473 } else { 474 SET(sc->sc_hwflags, COM_HW_FLOW); 475 sc->sc_fifolen = 32; 476 } 477 } else 478 #endif 479 sc->sc_fifolen = 16; 480 481 /* 482 * TL16C750 can enable 64byte FIFO, only when DLAB 483 * is 1. However, some 16750 may always enable. For 484 * example, restrictions according to DLAB in a data 485 * sheet for SC16C750 were not described. 486 * Please enable 'options COM_16650', supposing you 487 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 488 * should become effective. 489 */ 490 uint8_t iir1, iir2; 491 const uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 492 493 lcr = CSR_READ_1(regsp, COM_REG_LCR); 494 CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB); 495 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 496 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 497 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 498 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 499 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 500 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 501 502 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 503 504 if (!ISSET(iir1, IIR_64B_FIFO) && 505 ISSET(iir2, IIR_64B_FIFO)) { 506 /* It is TL16C750. */ 507 sc->sc_fifolen = 64; 508 SET(sc->sc_hwflags, COM_HW_AFE); 509 } else 510 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 511 512 #ifdef COM_16650 513 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 514 if (sc->sc_fifolen == 0) 515 fifo_msg = "st16650, broken fifo"; 516 else if (sc->sc_fifolen == 32) 517 fifo_msg = "st16650a, working fifo"; 518 else 519 #endif 520 if (sc->sc_fifolen == 64) 521 fifo_msg = "tl16c750, working fifo"; 522 else 523 fifo_msg = "ns16550a, working fifo"; 524 } else 525 fifo_msg = "ns16550, broken fifo"; 526 else 527 fifo_msg = "ns8250 or ns16450, no fifo"; 528 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 529 fifodelay: 530 /* 531 * Some chips will clear down both Tx and Rx FIFOs when zero is 532 * written to com_fifo. If this chip is the console, writing zero 533 * results in some of the chip/FIFO description being lost, so delay 534 * printing it until now. 535 */ 536 delay(10); 537 aprint_normal(": %s\n", fifo_msg); 538 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 539 sc->sc_fifolen = 1; 540 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 541 } 542 543 fifodone: 544 545 tp = tty_alloc(); 546 tp->t_oproc = comstart; 547 tp->t_param = comparam; 548 tp->t_hwiflow = comhwiflow; 549 tp->t_softc = sc; 550 551 sc->sc_tty = tp; 552 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 553 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 554 sc->sc_rbavail = com_rbuf_size; 555 if (sc->sc_rbuf == NULL) { 556 aprint_error_dev(sc->sc_dev, 557 "unable to allocate ring buffer\n"); 558 return; 559 } 560 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 561 562 tty_attach(tp); 563 564 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 565 SET(sc->sc_mcr, MCR_IENABLE); 566 567 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 568 int maj; 569 570 /* locate the major number */ 571 maj = cdevsw_lookup_major(&com_cdevsw); 572 573 tp->t_dev = cn_tab->cn_dev = makedev(maj, 574 device_unit(sc->sc_dev)); 575 576 aprint_normal_dev(sc->sc_dev, "console\n"); 577 } 578 579 #ifdef KGDB 580 /* 581 * Allow kgdb to "take over" this port. If this is 582 * not the console and is the kgdb device, it has 583 * exclusive use. If it's the console _and_ the 584 * kgdb device, it doesn't. 585 */ 586 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 587 regsp->cr_iobase == comkgdbregs.cr_iobase) { 588 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 589 com_kgdb_attached = 1; 590 591 SET(sc->sc_hwflags, COM_HW_KGDB); 592 } 593 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 594 } 595 #endif 596 597 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 598 599 #ifdef RND_COM 600 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 601 RND_TYPE_TTY, 0); 602 #endif 603 604 /* if there are no enable/disable functions, assume the device 605 is always enabled */ 606 if (!sc->enable) 607 sc->enabled = 1; 608 609 com_config(sc); 610 611 SET(sc->sc_hwflags, COM_HW_DEV_OK); 612 } 613 614 void 615 com_config(struct com_softc *sc) 616 { 617 struct com_regs *regsp = &sc->sc_regs; 618 619 /* Disable interrupts before configuring the device. */ 620 if (sc->sc_type == COM_TYPE_PXA2x0) 621 sc->sc_ier = IER_EUART; 622 else 623 sc->sc_ier = 0; 624 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 625 (void) CSR_READ_1(regsp, COM_REG_IIR); 626 627 #ifdef COM_HAYESP 628 /* Look for a Hayes ESP board. */ 629 if (sc->sc_type == COM_TYPE_HAYESP) { 630 631 /* Set 16550 compatibility mode */ 632 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 633 HAYESP_SETMODE); 634 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 635 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 636 HAYESP_MODE_SCALE); 637 638 /* Set RTS/CTS flow control */ 639 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 640 HAYESP_SETFLOWTYPE); 641 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 642 HAYESP_FLOW_RTS); 643 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 644 HAYESP_FLOW_CTS); 645 646 /* Set flow control levels */ 647 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 648 HAYESP_SETRXFLOW); 649 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 650 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 651 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 652 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 653 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 654 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 655 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 656 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 657 } 658 #endif 659 660 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 661 com_enable_debugport(sc); 662 } 663 664 #if 0 665 static int 666 comcngetc_detached(dev_t dev) 667 { 668 return 0; 669 } 670 671 static void 672 comcnputc_detached(dev_t dev, int c) 673 { 674 } 675 #endif 676 677 int 678 com_detach(device_t self, int flags) 679 { 680 struct com_softc *sc = device_private(self); 681 int maj, mn; 682 683 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 684 return EBUSY; 685 686 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 687 (flags & DETACH_SHUTDOWN) != 0) 688 return EBUSY; 689 690 if (sc->disable != NULL && sc->enabled != 0) { 691 (*sc->disable)(sc); 692 sc->enabled = 0; 693 } 694 695 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 696 comconsattached = 0; 697 cn_tab = NULL; 698 } 699 700 /* locate the major number */ 701 maj = cdevsw_lookup_major(&com_cdevsw); 702 703 /* Nuke the vnodes for any open instances. */ 704 mn = device_unit(self); 705 vdevgone(maj, mn, mn, VCHR); 706 707 mn |= COMDIALOUT_MASK; 708 vdevgone(maj, mn, mn, VCHR); 709 710 if (sc->sc_rbuf == NULL) { 711 /* 712 * Ring buffer allocation failed in the com_attach_subr, 713 * only the tty is allocated, and nothing else. 714 */ 715 tty_free(sc->sc_tty); 716 return 0; 717 } 718 719 /* Free the receive buffer. */ 720 free(sc->sc_rbuf, M_DEVBUF); 721 722 /* Detach and free the tty. */ 723 tty_detach(sc->sc_tty); 724 tty_free(sc->sc_tty); 725 726 /* Unhook the soft interrupt handler. */ 727 softint_disestablish(sc->sc_si); 728 729 #ifdef RND_COM 730 /* Unhook the entropy source. */ 731 rnd_detach_source(&sc->rnd_source); 732 #endif 733 callout_destroy(&sc->sc_diag_callout); 734 735 /* Destroy the lock. */ 736 mutex_destroy(&sc->sc_lock); 737 738 return (0); 739 } 740 741 void 742 com_shutdown(struct com_softc *sc) 743 { 744 struct tty *tp = sc->sc_tty; 745 746 mutex_spin_enter(&sc->sc_lock); 747 748 /* If we were asserting flow control, then deassert it. */ 749 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 750 com_hwiflow(sc); 751 752 /* Clear any break condition set with TIOCSBRK. */ 753 com_break(sc, 0); 754 755 /* 756 * Hang up if necessary. Wait a bit, so the other side has time to 757 * notice even if we immediately open the port again. 758 * Avoid tsleeping above splhigh(). 759 */ 760 if (ISSET(tp->t_cflag, HUPCL)) { 761 com_modem(sc, 0); 762 mutex_spin_exit(&sc->sc_lock); 763 /* XXX will only timeout */ 764 (void) kpause(ttclos, false, hz, NULL); 765 mutex_spin_enter(&sc->sc_lock); 766 } 767 768 /* Turn off interrupts. */ 769 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 770 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 771 if (sc->sc_type == COM_TYPE_PXA2x0) 772 sc->sc_ier |= IER_ERXTOUT; 773 } else 774 sc->sc_ier = 0; 775 776 if (sc->sc_type == COM_TYPE_PXA2x0) 777 sc->sc_ier |= IER_EUART; 778 779 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 780 781 mutex_spin_exit(&sc->sc_lock); 782 783 if (sc->disable) { 784 #ifdef DIAGNOSTIC 785 if (!sc->enabled) 786 panic("com_shutdown: not enabled?"); 787 #endif 788 (*sc->disable)(sc); 789 sc->enabled = 0; 790 } 791 } 792 793 int 794 comopen(dev_t dev, int flag, int mode, struct lwp *l) 795 { 796 struct com_softc *sc; 797 struct tty *tp; 798 int s; 799 int error; 800 801 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 802 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 803 sc->sc_rbuf == NULL) 804 return (ENXIO); 805 806 if (!device_is_active(sc->sc_dev)) 807 return (ENXIO); 808 809 #ifdef KGDB 810 /* 811 * If this is the kgdb port, no other use is permitted. 812 */ 813 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 814 return (EBUSY); 815 #endif 816 817 tp = sc->sc_tty; 818 819 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 820 return (EBUSY); 821 822 s = spltty(); 823 824 /* 825 * Do the following iff this is a first open. 826 */ 827 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 828 struct termios t; 829 830 tp->t_dev = dev; 831 832 if (sc->enable) { 833 if ((*sc->enable)(sc)) { 834 splx(s); 835 aprint_error_dev(sc->sc_dev, 836 "device enable failed\n"); 837 return (EIO); 838 } 839 mutex_spin_enter(&sc->sc_lock); 840 sc->enabled = 1; 841 com_config(sc); 842 } else { 843 mutex_spin_enter(&sc->sc_lock); 844 } 845 846 /* Turn on interrupts. */ 847 sc->sc_ier = IER_ERXRDY | IER_ERLS; 848 if (!ISSET(tp->t_cflag, CLOCAL)) 849 sc->sc_ier |= IER_EMSC; 850 851 if (sc->sc_type == COM_TYPE_PXA2x0) 852 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 853 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 854 855 /* Fetch the current modem control status, needed later. */ 856 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 857 858 /* Clear PPS capture state on first open. */ 859 mutex_spin_enter(&timecounter_lock); 860 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 861 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 862 pps_init(&sc->sc_pps_state); 863 mutex_spin_exit(&timecounter_lock); 864 865 mutex_spin_exit(&sc->sc_lock); 866 867 /* 868 * Initialize the termios status to the defaults. Add in the 869 * sticky bits from TIOCSFLAGS. 870 */ 871 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 872 t.c_ospeed = comcons_info.rate; 873 t.c_cflag = comcons_info.cflag; 874 } else { 875 t.c_ospeed = TTYDEF_SPEED; 876 t.c_cflag = TTYDEF_CFLAG; 877 } 878 t.c_ispeed = t.c_ospeed; 879 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 880 SET(t.c_cflag, CLOCAL); 881 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 882 SET(t.c_cflag, CRTSCTS); 883 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 884 SET(t.c_cflag, MDMBUF); 885 /* Make sure comparam() will do something. */ 886 tp->t_ospeed = 0; 887 (void) comparam(tp, &t); 888 tp->t_iflag = TTYDEF_IFLAG; 889 tp->t_oflag = TTYDEF_OFLAG; 890 tp->t_lflag = TTYDEF_LFLAG; 891 ttychars(tp); 892 ttsetwater(tp); 893 894 mutex_spin_enter(&sc->sc_lock); 895 896 /* 897 * Turn on DTR. We must always do this, even if carrier is not 898 * present, because otherwise we'd have to use TIOCSDTR 899 * immediately after setting CLOCAL, which applications do not 900 * expect. We always assert DTR while the device is open 901 * unless explicitly requested to deassert it. 902 */ 903 com_modem(sc, 1); 904 905 /* Clear the input ring, and unblock. */ 906 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 907 sc->sc_rbavail = com_rbuf_size; 908 com_iflush(sc); 909 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 910 com_hwiflow(sc); 911 912 #ifdef COM_DEBUG 913 if (com_debug) 914 comstatus(sc, "comopen "); 915 #endif 916 917 mutex_spin_exit(&sc->sc_lock); 918 } 919 920 splx(s); 921 922 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 923 if (error) 924 goto bad; 925 926 error = (*tp->t_linesw->l_open)(dev, tp); 927 if (error) 928 goto bad; 929 930 return (0); 931 932 bad: 933 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 934 /* 935 * We failed to open the device, and nobody else had it opened. 936 * Clean up the state as appropriate. 937 */ 938 com_shutdown(sc); 939 } 940 941 return (error); 942 } 943 944 int 945 comclose(dev_t dev, int flag, int mode, struct lwp *l) 946 { 947 struct com_softc *sc = 948 device_lookup_private(&com_cd, COMUNIT(dev)); 949 struct tty *tp = sc->sc_tty; 950 951 /* XXX This is for cons.c. */ 952 if (!ISSET(tp->t_state, TS_ISOPEN)) 953 return (0); 954 955 (*tp->t_linesw->l_close)(tp, flag); 956 ttyclose(tp); 957 958 if (COM_ISALIVE(sc) == 0) 959 return (0); 960 961 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 962 /* 963 * Although we got a last close, the device may still be in 964 * use; e.g. if this was the dialout node, and there are still 965 * processes waiting for carrier on the non-dialout node. 966 */ 967 com_shutdown(sc); 968 } 969 970 return (0); 971 } 972 973 int 974 comread(dev_t dev, struct uio *uio, int flag) 975 { 976 struct com_softc *sc = 977 device_lookup_private(&com_cd, COMUNIT(dev)); 978 struct tty *tp = sc->sc_tty; 979 980 if (COM_ISALIVE(sc) == 0) 981 return (EIO); 982 983 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 984 } 985 986 int 987 comwrite(dev_t dev, struct uio *uio, int flag) 988 { 989 struct com_softc *sc = 990 device_lookup_private(&com_cd, COMUNIT(dev)); 991 struct tty *tp = sc->sc_tty; 992 993 if (COM_ISALIVE(sc) == 0) 994 return (EIO); 995 996 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 997 } 998 999 int 1000 compoll(dev_t dev, int events, struct lwp *l) 1001 { 1002 struct com_softc *sc = 1003 device_lookup_private(&com_cd, COMUNIT(dev)); 1004 struct tty *tp = sc->sc_tty; 1005 1006 if (COM_ISALIVE(sc) == 0) 1007 return (POLLHUP); 1008 1009 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1010 } 1011 1012 struct tty * 1013 comtty(dev_t dev) 1014 { 1015 struct com_softc *sc = 1016 device_lookup_private(&com_cd, COMUNIT(dev)); 1017 struct tty *tp = sc->sc_tty; 1018 1019 return (tp); 1020 } 1021 1022 int 1023 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1024 { 1025 struct com_softc *sc; 1026 struct tty *tp; 1027 int error; 1028 1029 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1030 if (sc == NULL) 1031 return ENXIO; 1032 if (COM_ISALIVE(sc) == 0) 1033 return (EIO); 1034 1035 tp = sc->sc_tty; 1036 1037 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1038 if (error != EPASSTHROUGH) 1039 return (error); 1040 1041 error = ttioctl(tp, cmd, data, flag, l); 1042 if (error != EPASSTHROUGH) 1043 return (error); 1044 1045 error = 0; 1046 switch (cmd) { 1047 case TIOCSFLAGS: 1048 error = kauth_authorize_device_tty(l->l_cred, 1049 KAUTH_DEVICE_TTY_PRIVSET, tp); 1050 break; 1051 default: 1052 /* nothing */ 1053 break; 1054 } 1055 if (error) { 1056 return error; 1057 } 1058 1059 mutex_spin_enter(&sc->sc_lock); 1060 1061 switch (cmd) { 1062 case TIOCSBRK: 1063 com_break(sc, 1); 1064 break; 1065 1066 case TIOCCBRK: 1067 com_break(sc, 0); 1068 break; 1069 1070 case TIOCSDTR: 1071 com_modem(sc, 1); 1072 break; 1073 1074 case TIOCCDTR: 1075 com_modem(sc, 0); 1076 break; 1077 1078 case TIOCGFLAGS: 1079 *(int *)data = sc->sc_swflags; 1080 break; 1081 1082 case TIOCSFLAGS: 1083 sc->sc_swflags = *(int *)data; 1084 break; 1085 1086 case TIOCMSET: 1087 case TIOCMBIS: 1088 case TIOCMBIC: 1089 tiocm_to_com(sc, cmd, *(int *)data); 1090 break; 1091 1092 case TIOCMGET: 1093 *(int *)data = com_to_tiocm(sc); 1094 break; 1095 1096 case PPS_IOC_CREATE: 1097 case PPS_IOC_DESTROY: 1098 case PPS_IOC_GETPARAMS: 1099 case PPS_IOC_SETPARAMS: 1100 case PPS_IOC_GETCAP: 1101 case PPS_IOC_FETCH: 1102 #ifdef PPS_SYNC 1103 case PPS_IOC_KCBIND: 1104 #endif 1105 mutex_spin_enter(&timecounter_lock); 1106 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1107 mutex_spin_exit(&timecounter_lock); 1108 break; 1109 1110 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1111 mutex_spin_enter(&timecounter_lock); 1112 #ifndef PPS_TRAILING_EDGE 1113 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1114 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1115 #else 1116 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1117 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1118 #endif 1119 mutex_spin_exit(&timecounter_lock); 1120 break; 1121 1122 default: 1123 error = EPASSTHROUGH; 1124 break; 1125 } 1126 1127 mutex_spin_exit(&sc->sc_lock); 1128 1129 #ifdef COM_DEBUG 1130 if (com_debug) 1131 comstatus(sc, "comioctl "); 1132 #endif 1133 1134 return (error); 1135 } 1136 1137 integrate void 1138 com_schedrx(struct com_softc *sc) 1139 { 1140 1141 sc->sc_rx_ready = 1; 1142 1143 /* Wake up the poller. */ 1144 softint_schedule(sc->sc_si); 1145 } 1146 1147 void 1148 com_break(struct com_softc *sc, int onoff) 1149 { 1150 1151 if (onoff) 1152 SET(sc->sc_lcr, LCR_SBREAK); 1153 else 1154 CLR(sc->sc_lcr, LCR_SBREAK); 1155 1156 if (!sc->sc_heldchange) { 1157 if (sc->sc_tx_busy) { 1158 sc->sc_heldtbc = sc->sc_tbc; 1159 sc->sc_tbc = 0; 1160 sc->sc_heldchange = 1; 1161 } else 1162 com_loadchannelregs(sc); 1163 } 1164 } 1165 1166 void 1167 com_modem(struct com_softc *sc, int onoff) 1168 { 1169 1170 if (sc->sc_mcr_dtr == 0) 1171 return; 1172 1173 if (onoff) 1174 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1175 else 1176 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1177 1178 if (!sc->sc_heldchange) { 1179 if (sc->sc_tx_busy) { 1180 sc->sc_heldtbc = sc->sc_tbc; 1181 sc->sc_tbc = 0; 1182 sc->sc_heldchange = 1; 1183 } else 1184 com_loadchannelregs(sc); 1185 } 1186 } 1187 1188 void 1189 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1190 { 1191 u_char combits; 1192 1193 combits = 0; 1194 if (ISSET(ttybits, TIOCM_DTR)) 1195 SET(combits, MCR_DTR); 1196 if (ISSET(ttybits, TIOCM_RTS)) 1197 SET(combits, MCR_RTS); 1198 1199 switch (how) { 1200 case TIOCMBIC: 1201 CLR(sc->sc_mcr, combits); 1202 break; 1203 1204 case TIOCMBIS: 1205 SET(sc->sc_mcr, combits); 1206 break; 1207 1208 case TIOCMSET: 1209 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1210 SET(sc->sc_mcr, combits); 1211 break; 1212 } 1213 1214 if (!sc->sc_heldchange) { 1215 if (sc->sc_tx_busy) { 1216 sc->sc_heldtbc = sc->sc_tbc; 1217 sc->sc_tbc = 0; 1218 sc->sc_heldchange = 1; 1219 } else 1220 com_loadchannelregs(sc); 1221 } 1222 } 1223 1224 int 1225 com_to_tiocm(struct com_softc *sc) 1226 { 1227 u_char combits; 1228 int ttybits = 0; 1229 1230 combits = sc->sc_mcr; 1231 if (ISSET(combits, MCR_DTR)) 1232 SET(ttybits, TIOCM_DTR); 1233 if (ISSET(combits, MCR_RTS)) 1234 SET(ttybits, TIOCM_RTS); 1235 1236 combits = sc->sc_msr; 1237 if (ISSET(combits, MSR_DCD)) 1238 SET(ttybits, TIOCM_CD); 1239 if (ISSET(combits, MSR_CTS)) 1240 SET(ttybits, TIOCM_CTS); 1241 if (ISSET(combits, MSR_DSR)) 1242 SET(ttybits, TIOCM_DSR); 1243 if (ISSET(combits, MSR_RI | MSR_TERI)) 1244 SET(ttybits, TIOCM_RI); 1245 1246 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1247 SET(ttybits, TIOCM_LE); 1248 1249 return (ttybits); 1250 } 1251 1252 static u_char 1253 cflag2lcr(tcflag_t cflag) 1254 { 1255 u_char lcr = 0; 1256 1257 switch (ISSET(cflag, CSIZE)) { 1258 case CS5: 1259 SET(lcr, LCR_5BITS); 1260 break; 1261 case CS6: 1262 SET(lcr, LCR_6BITS); 1263 break; 1264 case CS7: 1265 SET(lcr, LCR_7BITS); 1266 break; 1267 case CS8: 1268 SET(lcr, LCR_8BITS); 1269 break; 1270 } 1271 if (ISSET(cflag, PARENB)) { 1272 SET(lcr, LCR_PENAB); 1273 if (!ISSET(cflag, PARODD)) 1274 SET(lcr, LCR_PEVEN); 1275 } 1276 if (ISSET(cflag, CSTOPB)) 1277 SET(lcr, LCR_STOPB); 1278 1279 return (lcr); 1280 } 1281 1282 int 1283 comparam(struct tty *tp, struct termios *t) 1284 { 1285 struct com_softc *sc = 1286 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1287 int ospeed; 1288 u_char lcr; 1289 1290 if (COM_ISALIVE(sc) == 0) 1291 return (EIO); 1292 1293 #ifdef COM_HAYESP 1294 if (sc->sc_type == COM_TYPE_HAYESP) { 1295 int prescaler, speed; 1296 1297 /* 1298 * Calculate UART clock prescaler. It should be in 1299 * range of 0 .. 3. 1300 */ 1301 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1302 prescaler++, speed /= 2) 1303 if ((ospeed = comspeed(speed, sc->sc_frequency, 1304 sc->sc_type)) > 0) 1305 break; 1306 1307 if (prescaler == 4) 1308 return (EINVAL); 1309 sc->sc_prescaler = prescaler; 1310 } else 1311 #endif 1312 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1313 1314 /* Check requested parameters. */ 1315 if (ospeed < 0) 1316 return (EINVAL); 1317 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1318 return (EINVAL); 1319 1320 /* 1321 * For the console, always force CLOCAL and !HUPCL, so that the port 1322 * is always active. 1323 */ 1324 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1325 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1326 SET(t->c_cflag, CLOCAL); 1327 CLR(t->c_cflag, HUPCL); 1328 } 1329 1330 /* 1331 * If there were no changes, don't do anything. This avoids dropping 1332 * input and improves performance when all we did was frob things like 1333 * VMIN and VTIME. 1334 */ 1335 if (tp->t_ospeed == t->c_ospeed && 1336 tp->t_cflag == t->c_cflag) 1337 return (0); 1338 1339 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1340 1341 mutex_spin_enter(&sc->sc_lock); 1342 1343 sc->sc_lcr = lcr; 1344 1345 /* 1346 * If we're not in a mode that assumes a connection is present, then 1347 * ignore carrier changes. 1348 */ 1349 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1350 sc->sc_msr_dcd = 0; 1351 else 1352 sc->sc_msr_dcd = MSR_DCD; 1353 /* 1354 * Set the flow control pins depending on the current flow control 1355 * mode. 1356 */ 1357 if (ISSET(t->c_cflag, CRTSCTS)) { 1358 sc->sc_mcr_dtr = MCR_DTR; 1359 sc->sc_mcr_rts = MCR_RTS; 1360 sc->sc_msr_cts = MSR_CTS; 1361 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1362 SET(sc->sc_mcr, MCR_AFE); 1363 } else { 1364 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1365 } 1366 } else if (ISSET(t->c_cflag, MDMBUF)) { 1367 /* 1368 * For DTR/DCD flow control, make sure we don't toggle DTR for 1369 * carrier detection. 1370 */ 1371 sc->sc_mcr_dtr = 0; 1372 sc->sc_mcr_rts = MCR_DTR; 1373 sc->sc_msr_cts = MSR_DCD; 1374 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1375 CLR(sc->sc_mcr, MCR_AFE); 1376 } else { 1377 sc->sc_efr = 0; 1378 } 1379 } else { 1380 /* 1381 * If no flow control, then always set RTS. This will make 1382 * the other side happy if it mistakenly thinks we're doing 1383 * RTS/CTS flow control. 1384 */ 1385 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1386 sc->sc_mcr_rts = 0; 1387 sc->sc_msr_cts = 0; 1388 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1389 CLR(sc->sc_mcr, MCR_AFE); 1390 } else { 1391 sc->sc_efr = 0; 1392 } 1393 if (ISSET(sc->sc_mcr, MCR_DTR)) 1394 SET(sc->sc_mcr, MCR_RTS); 1395 else 1396 CLR(sc->sc_mcr, MCR_RTS); 1397 } 1398 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1399 1400 #if 0 1401 if (ospeed == 0) 1402 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1403 else 1404 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1405 #endif 1406 1407 sc->sc_dlbl = ospeed; 1408 sc->sc_dlbh = ospeed >> 8; 1409 1410 /* 1411 * Set the FIFO threshold based on the receive speed. 1412 * 1413 * * If it's a low speed, it's probably a mouse or some other 1414 * interactive device, so set the threshold low. 1415 * * If it's a high speed, trim the trigger level down to prevent 1416 * overflows. 1417 * * Otherwise set it a bit higher. 1418 */ 1419 if (sc->sc_type == COM_TYPE_HAYESP) 1420 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1421 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1422 if (t->c_ospeed <= 1200) 1423 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1424 else if (t->c_ospeed <= 38400) 1425 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1426 else 1427 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1428 } else 1429 sc->sc_fifo = 0; 1430 1431 /* And copy to tty. */ 1432 tp->t_ispeed = t->c_ospeed; 1433 tp->t_ospeed = t->c_ospeed; 1434 tp->t_cflag = t->c_cflag; 1435 1436 if (!sc->sc_heldchange) { 1437 if (sc->sc_tx_busy) { 1438 sc->sc_heldtbc = sc->sc_tbc; 1439 sc->sc_tbc = 0; 1440 sc->sc_heldchange = 1; 1441 } else 1442 com_loadchannelregs(sc); 1443 } 1444 1445 if (!ISSET(t->c_cflag, CHWFLOW)) { 1446 /* Disable the high water mark. */ 1447 sc->sc_r_hiwat = 0; 1448 sc->sc_r_lowat = 0; 1449 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1450 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1451 com_schedrx(sc); 1452 } 1453 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1454 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1455 com_hwiflow(sc); 1456 } 1457 } else { 1458 sc->sc_r_hiwat = com_rbuf_hiwat; 1459 sc->sc_r_lowat = com_rbuf_lowat; 1460 } 1461 1462 mutex_spin_exit(&sc->sc_lock); 1463 1464 /* 1465 * Update the tty layer's idea of the carrier bit, in case we changed 1466 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1467 * explicit request. 1468 */ 1469 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1470 1471 #ifdef COM_DEBUG 1472 if (com_debug) 1473 comstatus(sc, "comparam "); 1474 #endif 1475 1476 if (!ISSET(t->c_cflag, CHWFLOW)) { 1477 if (sc->sc_tx_stopped) { 1478 sc->sc_tx_stopped = 0; 1479 comstart(tp); 1480 } 1481 } 1482 1483 return (0); 1484 } 1485 1486 void 1487 com_iflush(struct com_softc *sc) 1488 { 1489 struct com_regs *regsp = &sc->sc_regs; 1490 #ifdef DIAGNOSTIC 1491 int reg; 1492 #endif 1493 int timo; 1494 1495 #ifdef DIAGNOSTIC 1496 reg = 0xffff; 1497 #endif 1498 timo = 50000; 1499 /* flush any pending I/O */ 1500 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1501 && --timo) 1502 #ifdef DIAGNOSTIC 1503 reg = 1504 #else 1505 (void) 1506 #endif 1507 CSR_READ_1(regsp, COM_REG_RXDATA); 1508 #ifdef DIAGNOSTIC 1509 if (!timo) 1510 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1511 #endif 1512 1513 if (sc->sc_type == COM_TYPE_ARMADAXP) { 1514 uint8_t fifo; 1515 /* 1516 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1517 * This should prevent triggering busy interrupt while 1518 * manipulating divisors. 1519 */ 1520 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1521 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1522 CSR_WRITE_1(regsp, COM_REG_FIFO, 1523 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1524 delay(100); 1525 } 1526 } 1527 1528 void 1529 com_loadchannelregs(struct com_softc *sc) 1530 { 1531 struct com_regs *regsp = &sc->sc_regs; 1532 1533 /* XXXXX necessary? */ 1534 com_iflush(sc); 1535 1536 if (sc->sc_type == COM_TYPE_PXA2x0) 1537 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1538 else 1539 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1540 1541 if (sc->sc_type == COM_TYPE_OMAP) { 1542 /* disable before changing settings */ 1543 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1544 } 1545 1546 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1547 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1548 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1549 /* no EFR on alchemy */ 1550 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1551 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1552 } 1553 if (sc->sc_type == COM_TYPE_AU1x00) { 1554 /* alchemy has single separate 16-bit clock divisor register */ 1555 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1556 (sc->sc_dlbh << 8)); 1557 } else { 1558 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1559 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1560 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1561 } 1562 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1563 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1564 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1565 #ifdef COM_HAYESP 1566 if (sc->sc_type == COM_TYPE_HAYESP) { 1567 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1568 HAYESP_SETPRESCALER); 1569 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1570 sc->sc_prescaler); 1571 } 1572 #endif 1573 if (sc->sc_type == COM_TYPE_OMAP) { 1574 /* setup the fifos. the FCR value is not used as long 1575 as SCR[6] and SCR[7] are 0, which they are at reset 1576 and we never touch the SCR register */ 1577 uint8_t rx_fifo_trig = 40; 1578 uint8_t tx_fifo_trig = 60; 1579 uint8_t rx_start = 8; 1580 uint8_t rx_halt = 60; 1581 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1582 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1583 1584 /* enable access to TCR & TLR */ 1585 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1586 1587 /* write tcr and tlr values */ 1588 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1589 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1590 1591 /* disable access to TCR & TLR */ 1592 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1593 1594 /* enable again, but mode is based on speed */ 1595 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1596 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1597 } else { 1598 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1599 } 1600 } 1601 1602 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1603 } 1604 1605 int 1606 comhwiflow(struct tty *tp, int block) 1607 { 1608 struct com_softc *sc = 1609 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1610 1611 if (COM_ISALIVE(sc) == 0) 1612 return (0); 1613 1614 if (sc->sc_mcr_rts == 0) 1615 return (0); 1616 1617 mutex_spin_enter(&sc->sc_lock); 1618 1619 if (block) { 1620 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1621 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1622 com_hwiflow(sc); 1623 } 1624 } else { 1625 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1626 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1627 com_schedrx(sc); 1628 } 1629 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1630 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1631 com_hwiflow(sc); 1632 } 1633 } 1634 1635 mutex_spin_exit(&sc->sc_lock); 1636 return (1); 1637 } 1638 1639 /* 1640 * (un)block input via hw flowcontrol 1641 */ 1642 void 1643 com_hwiflow(struct com_softc *sc) 1644 { 1645 struct com_regs *regsp= &sc->sc_regs; 1646 1647 if (sc->sc_mcr_rts == 0) 1648 return; 1649 1650 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1651 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1652 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1653 } else { 1654 SET(sc->sc_mcr, sc->sc_mcr_rts); 1655 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1656 } 1657 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1658 } 1659 1660 1661 void 1662 comstart(struct tty *tp) 1663 { 1664 struct com_softc *sc = 1665 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1666 struct com_regs *regsp = &sc->sc_regs; 1667 int s; 1668 1669 if (COM_ISALIVE(sc) == 0) 1670 return; 1671 1672 s = spltty(); 1673 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1674 goto out; 1675 if (sc->sc_tx_stopped) 1676 goto out; 1677 if (!ttypull(tp)) 1678 goto out; 1679 1680 /* Grab the first contiguous region of buffer space. */ 1681 { 1682 u_char *tba; 1683 int tbc; 1684 1685 tba = tp->t_outq.c_cf; 1686 tbc = ndqb(&tp->t_outq, 0); 1687 1688 mutex_spin_enter(&sc->sc_lock); 1689 1690 sc->sc_tba = tba; 1691 sc->sc_tbc = tbc; 1692 } 1693 1694 SET(tp->t_state, TS_BUSY); 1695 sc->sc_tx_busy = 1; 1696 1697 /* Enable transmit completion interrupts if necessary. */ 1698 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1699 SET(sc->sc_ier, IER_ETXRDY); 1700 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1701 } 1702 1703 /* Output the first chunk of the contiguous buffer. */ 1704 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1705 u_int n; 1706 1707 n = sc->sc_tbc; 1708 if (n > sc->sc_fifolen) 1709 n = sc->sc_fifolen; 1710 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1711 sc->sc_tbc -= n; 1712 sc->sc_tba += n; 1713 } 1714 1715 mutex_spin_exit(&sc->sc_lock); 1716 out: 1717 splx(s); 1718 return; 1719 } 1720 1721 /* 1722 * Stop output on a line. 1723 */ 1724 void 1725 comstop(struct tty *tp, int flag) 1726 { 1727 struct com_softc *sc = 1728 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1729 1730 mutex_spin_enter(&sc->sc_lock); 1731 if (ISSET(tp->t_state, TS_BUSY)) { 1732 /* Stop transmitting at the next chunk. */ 1733 sc->sc_tbc = 0; 1734 sc->sc_heldtbc = 0; 1735 if (!ISSET(tp->t_state, TS_TTSTOP)) 1736 SET(tp->t_state, TS_FLUSH); 1737 } 1738 mutex_spin_exit(&sc->sc_lock); 1739 } 1740 1741 void 1742 comdiag(void *arg) 1743 { 1744 struct com_softc *sc = arg; 1745 int overflows, floods; 1746 1747 mutex_spin_enter(&sc->sc_lock); 1748 overflows = sc->sc_overflows; 1749 sc->sc_overflows = 0; 1750 floods = sc->sc_floods; 1751 sc->sc_floods = 0; 1752 sc->sc_errors = 0; 1753 mutex_spin_exit(&sc->sc_lock); 1754 1755 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1756 device_xname(sc->sc_dev), 1757 overflows, overflows == 1 ? "" : "s", 1758 floods, floods == 1 ? "" : "s"); 1759 } 1760 1761 integrate void 1762 com_rxsoft(struct com_softc *sc, struct tty *tp) 1763 { 1764 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1765 u_char *get, *end; 1766 u_int cc, scc; 1767 u_char lsr; 1768 int code; 1769 1770 end = sc->sc_ebuf; 1771 get = sc->sc_rbget; 1772 scc = cc = com_rbuf_size - sc->sc_rbavail; 1773 1774 if (cc == com_rbuf_size) { 1775 sc->sc_floods++; 1776 if (sc->sc_errors++ == 0) 1777 callout_reset(&sc->sc_diag_callout, 60 * hz, 1778 comdiag, sc); 1779 } 1780 1781 /* If not yet open, drop the entire buffer content here */ 1782 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1783 get += cc << 1; 1784 if (get >= end) 1785 get -= com_rbuf_size << 1; 1786 cc = 0; 1787 } 1788 while (cc) { 1789 code = get[0]; 1790 lsr = get[1]; 1791 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1792 if (ISSET(lsr, LSR_OE)) { 1793 sc->sc_overflows++; 1794 if (sc->sc_errors++ == 0) 1795 callout_reset(&sc->sc_diag_callout, 1796 60 * hz, comdiag, sc); 1797 } 1798 if (ISSET(lsr, LSR_BI | LSR_FE)) 1799 SET(code, TTY_FE); 1800 if (ISSET(lsr, LSR_PE)) 1801 SET(code, TTY_PE); 1802 } 1803 if ((*rint)(code, tp) == -1) { 1804 /* 1805 * The line discipline's buffer is out of space. 1806 */ 1807 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1808 /* 1809 * We're either not using flow control, or the 1810 * line discipline didn't tell us to block for 1811 * some reason. Either way, we have no way to 1812 * know when there's more space available, so 1813 * just drop the rest of the data. 1814 */ 1815 get += cc << 1; 1816 if (get >= end) 1817 get -= com_rbuf_size << 1; 1818 cc = 0; 1819 } else { 1820 /* 1821 * Don't schedule any more receive processing 1822 * until the line discipline tells us there's 1823 * space available (through comhwiflow()). 1824 * Leave the rest of the data in the input 1825 * buffer. 1826 */ 1827 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1828 } 1829 break; 1830 } 1831 get += 2; 1832 if (get >= end) 1833 get = sc->sc_rbuf; 1834 cc--; 1835 } 1836 1837 if (cc != scc) { 1838 sc->sc_rbget = get; 1839 mutex_spin_enter(&sc->sc_lock); 1840 1841 cc = sc->sc_rbavail += scc - cc; 1842 /* Buffers should be ok again, release possible block. */ 1843 if (cc >= sc->sc_r_lowat) { 1844 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1845 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1846 SET(sc->sc_ier, IER_ERXRDY); 1847 #ifdef COM_PXA2X0 1848 if (sc->sc_type == COM_TYPE_PXA2x0) 1849 SET(sc->sc_ier, IER_ERXTOUT); 1850 #endif 1851 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1852 } 1853 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1854 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1855 com_hwiflow(sc); 1856 } 1857 } 1858 mutex_spin_exit(&sc->sc_lock); 1859 } 1860 } 1861 1862 integrate void 1863 com_txsoft(struct com_softc *sc, struct tty *tp) 1864 { 1865 1866 CLR(tp->t_state, TS_BUSY); 1867 if (ISSET(tp->t_state, TS_FLUSH)) 1868 CLR(tp->t_state, TS_FLUSH); 1869 else 1870 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1871 (*tp->t_linesw->l_start)(tp); 1872 } 1873 1874 integrate void 1875 com_stsoft(struct com_softc *sc, struct tty *tp) 1876 { 1877 u_char msr, delta; 1878 1879 mutex_spin_enter(&sc->sc_lock); 1880 msr = sc->sc_msr; 1881 delta = sc->sc_msr_delta; 1882 sc->sc_msr_delta = 0; 1883 mutex_spin_exit(&sc->sc_lock); 1884 1885 if (ISSET(delta, sc->sc_msr_dcd)) { 1886 /* 1887 * Inform the tty layer that carrier detect changed. 1888 */ 1889 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1890 } 1891 1892 if (ISSET(delta, sc->sc_msr_cts)) { 1893 /* Block or unblock output according to flow control. */ 1894 if (ISSET(msr, sc->sc_msr_cts)) { 1895 sc->sc_tx_stopped = 0; 1896 (*tp->t_linesw->l_start)(tp); 1897 } else { 1898 sc->sc_tx_stopped = 1; 1899 } 1900 } 1901 1902 #ifdef COM_DEBUG 1903 if (com_debug) 1904 comstatus(sc, "com_stsoft"); 1905 #endif 1906 } 1907 1908 void 1909 comsoft(void *arg) 1910 { 1911 struct com_softc *sc = arg; 1912 struct tty *tp; 1913 1914 if (COM_ISALIVE(sc) == 0) 1915 return; 1916 1917 tp = sc->sc_tty; 1918 1919 if (sc->sc_rx_ready) { 1920 sc->sc_rx_ready = 0; 1921 com_rxsoft(sc, tp); 1922 } 1923 1924 if (sc->sc_st_check) { 1925 sc->sc_st_check = 0; 1926 com_stsoft(sc, tp); 1927 } 1928 1929 if (sc->sc_tx_done) { 1930 sc->sc_tx_done = 0; 1931 com_txsoft(sc, tp); 1932 } 1933 } 1934 1935 int 1936 comintr(void *arg) 1937 { 1938 struct com_softc *sc = arg; 1939 struct com_regs *regsp = &sc->sc_regs; 1940 1941 u_char *put, *end; 1942 u_int cc; 1943 u_char lsr, iir; 1944 1945 if (COM_ISALIVE(sc) == 0) 1946 return (0); 1947 1948 KASSERT(regsp != NULL); 1949 1950 mutex_spin_enter(&sc->sc_lock); 1951 iir = CSR_READ_1(regsp, COM_REG_IIR); 1952 1953 if (ISSET(iir, IIR_NOPEND)) { 1954 mutex_spin_exit(&sc->sc_lock); 1955 return (0); 1956 } 1957 1958 end = sc->sc_ebuf; 1959 put = sc->sc_rbput; 1960 cc = sc->sc_rbavail; 1961 1962 again: do { 1963 u_char msr, delta; 1964 1965 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1966 if (ISSET(lsr, LSR_BI)) { 1967 int cn_trapped = 0; 1968 1969 cn_check_magic(sc->sc_tty->t_dev, 1970 CNC_BREAK, com_cnm_state); 1971 if (cn_trapped) 1972 continue; 1973 #if defined(KGDB) && !defined(DDB) 1974 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 1975 kgdb_connect(1); 1976 continue; 1977 } 1978 #endif 1979 } 1980 1981 if (ISSET(lsr, LSR_RCV_MASK) && 1982 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1983 while (cc > 0) { 1984 int cn_trapped = 0; 1985 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 1986 put[1] = lsr; 1987 cn_check_magic(sc->sc_tty->t_dev, 1988 put[0], com_cnm_state); 1989 if (cn_trapped) 1990 goto next; 1991 put += 2; 1992 if (put >= end) 1993 put = sc->sc_rbuf; 1994 cc--; 1995 next: 1996 lsr = CSR_READ_1(regsp, COM_REG_LSR); 1997 if (!ISSET(lsr, LSR_RCV_MASK)) 1998 break; 1999 } 2000 2001 /* 2002 * Current string of incoming characters ended because 2003 * no more data was available or we ran out of space. 2004 * Schedule a receive event if any data was received. 2005 * If we're out of space, turn off receive interrupts. 2006 */ 2007 sc->sc_rbput = put; 2008 sc->sc_rbavail = cc; 2009 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2010 sc->sc_rx_ready = 1; 2011 2012 /* 2013 * See if we are in danger of overflowing a buffer. If 2014 * so, use hardware flow control to ease the pressure. 2015 */ 2016 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2017 cc < sc->sc_r_hiwat) { 2018 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2019 com_hwiflow(sc); 2020 } 2021 2022 /* 2023 * If we're out of space, disable receive interrupts 2024 * until the queue has drained a bit. 2025 */ 2026 if (!cc) { 2027 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2028 #ifdef COM_PXA2X0 2029 if (sc->sc_type == COM_TYPE_PXA2x0) 2030 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2031 else 2032 #endif 2033 CLR(sc->sc_ier, IER_ERXRDY); 2034 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2035 } 2036 } else { 2037 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2038 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2039 continue; 2040 } 2041 } 2042 2043 msr = CSR_READ_1(regsp, COM_REG_MSR); 2044 delta = msr ^ sc->sc_msr; 2045 sc->sc_msr = msr; 2046 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2047 (delta & MSR_DCD)) { 2048 mutex_spin_enter(&timecounter_lock); 2049 pps_capture(&sc->sc_pps_state); 2050 pps_event(&sc->sc_pps_state, 2051 (msr & MSR_DCD) ? 2052 PPS_CAPTUREASSERT : 2053 PPS_CAPTURECLEAR); 2054 mutex_spin_exit(&timecounter_lock); 2055 } 2056 2057 /* 2058 * Process normal status changes 2059 */ 2060 if (ISSET(delta, sc->sc_msr_mask)) { 2061 SET(sc->sc_msr_delta, delta); 2062 2063 /* 2064 * Stop output immediately if we lose the output 2065 * flow control signal or carrier detect. 2066 */ 2067 if (ISSET(~msr, sc->sc_msr_mask)) { 2068 sc->sc_tbc = 0; 2069 sc->sc_heldtbc = 0; 2070 #ifdef COM_DEBUG 2071 if (com_debug) 2072 comstatus(sc, "comintr "); 2073 #endif 2074 } 2075 2076 sc->sc_st_check = 1; 2077 } 2078 } while (!ISSET((iir = 2079 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2080 /* 2081 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2082 * by IIR read, so we can't do this way: `process all interrupts, 2083 * then do TX if possible'. 2084 */ 2085 (iir & IIR_IMASK) != IIR_TXRDY); 2086 2087 /* 2088 * Read LSR again, since there may be an interrupt between 2089 * the last LSR read and IIR read above. 2090 */ 2091 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2092 2093 /* 2094 * See if data can be transmitted as well. 2095 * Schedule tx done event if no data left 2096 * and tty was marked busy. 2097 */ 2098 if (ISSET(lsr, LSR_TXRDY)) { 2099 /* 2100 * If we've delayed a parameter change, do it now, and restart 2101 * output. 2102 */ 2103 if (sc->sc_heldchange) { 2104 com_loadchannelregs(sc); 2105 sc->sc_heldchange = 0; 2106 sc->sc_tbc = sc->sc_heldtbc; 2107 sc->sc_heldtbc = 0; 2108 } 2109 2110 /* Output the next chunk of the contiguous buffer, if any. */ 2111 if (sc->sc_tbc > 0) { 2112 u_int n; 2113 2114 n = sc->sc_tbc; 2115 if (n > sc->sc_fifolen) 2116 n = sc->sc_fifolen; 2117 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2118 sc->sc_tbc -= n; 2119 sc->sc_tba += n; 2120 } else { 2121 /* Disable transmit completion interrupts if necessary. */ 2122 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2123 CLR(sc->sc_ier, IER_ETXRDY); 2124 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2125 } 2126 if (sc->sc_tx_busy) { 2127 sc->sc_tx_busy = 0; 2128 sc->sc_tx_done = 1; 2129 } 2130 } 2131 } 2132 2133 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2134 goto again; 2135 2136 mutex_spin_exit(&sc->sc_lock); 2137 2138 /* Wake up the poller. */ 2139 softint_schedule(sc->sc_si); 2140 2141 #ifdef RND_COM 2142 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2143 #endif 2144 2145 return (1); 2146 } 2147 2148 /* 2149 * The following functions are polled getc and putc routines, shared 2150 * by the console and kgdb glue. 2151 * 2152 * The read-ahead code is so that you can detect pending in-band 2153 * cn_magic in polled mode while doing output rather than having to 2154 * wait until the kernel decides it needs input. 2155 */ 2156 2157 #define MAX_READAHEAD 20 2158 static int com_readahead[MAX_READAHEAD]; 2159 static int com_readaheadcount = 0; 2160 2161 int 2162 com_common_getc(dev_t dev, struct com_regs *regsp) 2163 { 2164 int s = splserial(); 2165 u_char stat, c; 2166 2167 /* got a character from reading things earlier */ 2168 if (com_readaheadcount > 0) { 2169 int i; 2170 2171 c = com_readahead[0]; 2172 for (i = 1; i < com_readaheadcount; i++) { 2173 com_readahead[i-1] = com_readahead[i]; 2174 } 2175 com_readaheadcount--; 2176 splx(s); 2177 return (c); 2178 } 2179 2180 /* block until a character becomes available */ 2181 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2182 ; 2183 2184 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2185 stat = CSR_READ_1(regsp, COM_REG_IIR); 2186 { 2187 int cn_trapped = 0; /* unused */ 2188 #ifdef DDB 2189 extern int db_active; 2190 if (!db_active) 2191 #endif 2192 cn_check_magic(dev, c, com_cnm_state); 2193 } 2194 splx(s); 2195 return (c); 2196 } 2197 2198 static void 2199 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2200 { 2201 int s = splserial(); 2202 int cin, stat, timo; 2203 2204 if (com_readaheadcount < MAX_READAHEAD 2205 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2206 int cn_trapped = 0; 2207 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2208 stat = CSR_READ_1(regsp, COM_REG_IIR); 2209 cn_check_magic(dev, cin, com_cnm_state); 2210 com_readahead[com_readaheadcount++] = cin; 2211 } 2212 2213 /* wait for any pending transmission to finish */ 2214 timo = 150000; 2215 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2216 continue; 2217 2218 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2219 COM_BARRIER(regsp, BR | BW); 2220 2221 splx(s); 2222 } 2223 2224 /* 2225 * Initialize UART for use as console or KGDB line. 2226 */ 2227 int 2228 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2229 tcflag_t cflag) 2230 { 2231 2232 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2233 ®sp->cr_ioh)) 2234 return (ENOMEM); /* ??? */ 2235 2236 if (type == COM_TYPE_OMAP) { 2237 /* disable before changing settings */ 2238 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2239 } 2240 2241 rate = comspeed(rate, frequency, type); 2242 if (__predict_true(rate != -1)) { 2243 if (type == COM_TYPE_AU1x00) { 2244 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2245 } else { 2246 /* no EFR on alchemy */ 2247 if (type != COM_TYPE_16550_NOERS) { 2248 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2249 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2250 } 2251 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2252 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2253 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2254 } 2255 } 2256 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2257 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2258 CSR_WRITE_1(regsp, COM_REG_FIFO, 2259 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2260 2261 if (type == COM_TYPE_OMAP) { 2262 /* setup the fifos. the FCR value is not used as long 2263 as SCR[6] and SCR[7] are 0, which they are at reset 2264 and we never touch the SCR register */ 2265 uint8_t rx_fifo_trig = 40; 2266 uint8_t tx_fifo_trig = 60; 2267 uint8_t rx_start = 8; 2268 uint8_t rx_halt = 60; 2269 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2270 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2271 2272 /* enable access to TCR & TLR */ 2273 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2274 2275 /* write tcr and tlr values */ 2276 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2277 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2278 2279 /* disable access to TCR & TLR */ 2280 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2281 2282 /* enable again, but mode is based on speed */ 2283 if (rate > 230400) { 2284 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2285 } else { 2286 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2287 } 2288 } 2289 2290 #ifdef COM_PXA2X0 2291 if (type == COM_TYPE_PXA2x0) 2292 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2293 else 2294 #endif 2295 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2296 2297 return (0); 2298 } 2299 2300 int 2301 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2302 tcflag_t cflag) 2303 { 2304 int res; 2305 2306 comcons_info.regs = *regsp; 2307 2308 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2309 if (res) 2310 return (res); 2311 2312 cn_tab = &comcons; 2313 cn_init_magic(&com_cnm_state); 2314 cn_set_magic("\047\001"); /* default magic is BREAK */ 2315 2316 comcons_info.frequency = frequency; 2317 comcons_info.type = type; 2318 comcons_info.rate = rate; 2319 comcons_info.cflag = cflag; 2320 2321 return (0); 2322 } 2323 2324 int 2325 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2326 int type, tcflag_t cflag) 2327 { 2328 struct com_regs regs; 2329 2330 memset(®s, 0, sizeof regs); 2331 regs.cr_iot = iot; 2332 regs.cr_iobase = iobase; 2333 regs.cr_nports = COM_NPORTS; 2334 #ifdef COM_REGMAP 2335 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2336 #endif 2337 2338 return comcnattach1(®s, rate, frequency, type, cflag); 2339 } 2340 2341 static int 2342 comcnreattach(void) 2343 { 2344 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2345 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2346 } 2347 2348 int 2349 comcngetc(dev_t dev) 2350 { 2351 2352 return (com_common_getc(dev, &comcons_info.regs)); 2353 } 2354 2355 /* 2356 * Console kernel output character routine. 2357 */ 2358 void 2359 comcnputc(dev_t dev, int c) 2360 { 2361 2362 com_common_putc(dev, &comcons_info.regs, c); 2363 } 2364 2365 void 2366 comcnpollc(dev_t dev, int on) 2367 { 2368 2369 com_readaheadcount = 0; 2370 } 2371 2372 #ifdef KGDB 2373 int 2374 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2375 tcflag_t cflag) 2376 { 2377 int res; 2378 2379 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2380 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2381 #if !defined(DDB) 2382 return (EBUSY); /* cannot share with console */ 2383 #else 2384 comkgdbregs = *regsp; 2385 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2386 #endif 2387 } else { 2388 comkgdbregs = *regsp; 2389 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2390 if (res) 2391 return (res); 2392 2393 /* 2394 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2395 * expects this to be initialized 2396 */ 2397 cn_init_magic(&com_cnm_state); 2398 cn_set_magic("\047\001"); 2399 } 2400 2401 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2402 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2403 2404 return (0); 2405 } 2406 2407 int 2408 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2409 int frequency, int type, tcflag_t cflag) 2410 { 2411 struct com_regs regs; 2412 2413 regs.cr_iot = iot; 2414 regs.cr_nports = COM_NPORTS; 2415 regs.cr_iobase = iobase; 2416 #ifdef COM_REGMAP 2417 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2418 #endif 2419 2420 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2421 } 2422 2423 /* ARGSUSED */ 2424 int 2425 com_kgdb_getc(void *arg) 2426 { 2427 2428 return (com_common_getc(NODEV, &comkgdbregs)); 2429 } 2430 2431 /* ARGSUSED */ 2432 void 2433 com_kgdb_putc(void *arg, int c) 2434 { 2435 2436 com_common_putc(NODEV, &comkgdbregs, c); 2437 } 2438 #endif /* KGDB */ 2439 2440 /* helper function to identify the com ports used by 2441 console or KGDB (and not yet autoconf attached) */ 2442 int 2443 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2444 { 2445 bus_space_handle_t help; 2446 2447 if (!comconsattached && 2448 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2449 iobase == comcons_info.regs.cr_iobase) 2450 help = comcons_info.regs.cr_ioh; 2451 #ifdef KGDB 2452 else if (!com_kgdb_attached && 2453 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2454 iobase == comkgdbregs.cr_iobase) 2455 help = comkgdbregs.cr_ioh; 2456 #endif 2457 else 2458 return (0); 2459 2460 if (ioh) 2461 *ioh = help; 2462 return (1); 2463 } 2464 2465 /* 2466 * this routine exists to serve as a shutdown hook for systems that 2467 * have firmware which doesn't interact properly with a com device in 2468 * FIFO mode. 2469 */ 2470 bool 2471 com_cleanup(device_t self, int how) 2472 { 2473 struct com_softc *sc = device_private(self); 2474 2475 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2476 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2477 2478 return true; 2479 } 2480 2481 bool 2482 com_suspend(device_t self, const pmf_qual_t *qual) 2483 { 2484 struct com_softc *sc = device_private(self); 2485 2486 #if 0 2487 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2488 cn_tab = &comcons_suspend; 2489 #endif 2490 2491 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2492 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2493 2494 return true; 2495 } 2496 2497 bool 2498 com_resume(device_t self, const pmf_qual_t *qual) 2499 { 2500 struct com_softc *sc = device_private(self); 2501 2502 mutex_spin_enter(&sc->sc_lock); 2503 com_loadchannelregs(sc); 2504 mutex_spin_exit(&sc->sc_lock); 2505 2506 return true; 2507 } 2508
Indexes created Thu Sep 25 16:09:42 GMT 2025