com.c revision 1.317
1 /* $NetBSD: com.c,v 1.317 2013/10/03 13:23:03 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.317 2013/10/03 13:23:03 kiyohara Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 (void)cn_trapped; \ 96 } while (/* CONSTCOND */ 0) 97 98 #include <sys/param.h> 99 #include <sys/systm.h> 100 #include <sys/ioctl.h> 101 #include <sys/select.h> 102 #include <sys/poll.h> 103 #include <sys/tty.h> 104 #include <sys/proc.h> 105 #include <sys/conf.h> 106 #include <sys/file.h> 107 #include <sys/uio.h> 108 #include <sys/kernel.h> 109 #include <sys/syslog.h> 110 #include <sys/device.h> 111 #include <sys/malloc.h> 112 #include <sys/timepps.h> 113 #include <sys/vnode.h> 114 #include <sys/kauth.h> 115 #include <sys/intr.h> 116 #ifdef RND_COM 117 #include <sys/rnd.h> 118 #endif 119 120 121 #include <sys/bus.h> 122 123 #include <dev/ic/comreg.h> 124 #include <dev/ic/comvar.h> 125 #include <dev/ic/ns16550reg.h> 126 #include <dev/ic/st16650reg.h> 127 #ifdef COM_HAYESP 128 #include <dev/ic/hayespreg.h> 129 #endif 130 #define com_lcr com_cfcr 131 #include <dev/cons.h> 132 133 #ifdef COM_REGMAP 134 #define CSR_WRITE_1(r, o, v) \ 135 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 136 #define CSR_READ_1(r, o) \ 137 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 138 #define CSR_WRITE_2(r, o, v) \ 139 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 140 #define CSR_READ_2(r, o) \ 141 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 142 #define CSR_WRITE_MULTI(r, o, p, n) \ 143 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 144 #else 145 #define CSR_WRITE_1(r, o, v) \ 146 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 147 #define CSR_READ_1(r, o) \ 148 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 149 #define CSR_WRITE_2(r, o, v) \ 150 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 151 #define CSR_READ_2(r, o) \ 152 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 153 #define CSR_WRITE_MULTI(r, o, p, n) \ 154 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 155 #endif 156 157 158 static void com_enable_debugport(struct com_softc *); 159 160 void com_config(struct com_softc *); 161 void com_shutdown(struct com_softc *); 162 int comspeed(long, long, int); 163 static u_char cflag2lcr(tcflag_t); 164 int comparam(struct tty *, struct termios *); 165 void comstart(struct tty *); 166 int comhwiflow(struct tty *, int); 167 168 void com_loadchannelregs(struct com_softc *); 169 void com_hwiflow(struct com_softc *); 170 void com_break(struct com_softc *, int); 171 void com_modem(struct com_softc *, int); 172 void tiocm_to_com(struct com_softc *, u_long, int); 173 int com_to_tiocm(struct com_softc *); 174 void com_iflush(struct com_softc *); 175 176 int com_common_getc(dev_t, struct com_regs *); 177 static void com_common_putc(dev_t, struct com_regs *, int); 178 179 int cominit(struct com_regs *, int, int, int, tcflag_t); 180 181 static int comcnreattach(void); 182 183 int comcngetc(dev_t); 184 void comcnputc(dev_t, int); 185 void comcnpollc(dev_t, int); 186 187 #define integrate static inline 188 void comsoft(void *); 189 integrate void com_rxsoft(struct com_softc *, struct tty *); 190 integrate void com_txsoft(struct com_softc *, struct tty *); 191 integrate void com_stsoft(struct com_softc *, struct tty *); 192 integrate void com_schedrx(struct com_softc *); 193 void comdiag(void *); 194 195 extern struct cfdriver com_cd; 196 197 dev_type_open(comopen); 198 dev_type_close(comclose); 199 dev_type_read(comread); 200 dev_type_write(comwrite); 201 dev_type_ioctl(comioctl); 202 dev_type_stop(comstop); 203 dev_type_tty(comtty); 204 dev_type_poll(compoll); 205 206 static struct comcons_info comcons_info; 207 208 /* 209 * Following are all routines needed for COM to act as console 210 */ 211 static struct consdev comcons = { 212 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 213 NODEV, CN_NORMAL 214 }; 215 216 217 const struct cdevsw com_cdevsw = { 218 comopen, comclose, comread, comwrite, comioctl, 219 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 220 }; 221 222 /* 223 * Make this an option variable one can patch. 224 * But be warned: this must be a power of 2! 225 */ 226 u_int com_rbuf_size = COM_RING_SIZE; 227 228 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 229 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 230 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 231 232 static int comconsattached; 233 static struct cnm_state com_cnm_state; 234 235 #ifdef KGDB 236 #include <sys/kgdb.h> 237 238 static struct com_regs comkgdbregs; 239 static int com_kgdb_attached; 240 241 int com_kgdb_getc(void *); 242 void com_kgdb_putc(void *, int); 243 #endif /* KGDB */ 244 245 #ifdef COM_REGMAP 246 /* initializer for typical 16550-ish hardware */ 247 #define COM_REG_16550 { \ 248 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 249 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 250 /* 16750-specific register set, additional UART status register */ 251 #define COM_REG_16750 { \ 252 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 253 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 254 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } 255 256 #ifdef COM_16750 257 const bus_size_t com_std_map[32] = COM_REG_16750; 258 #else 259 const bus_size_t com_std_map[16] = COM_REG_16550; 260 #endif /* COM_16750 */ 261 #endif /* COM_REGMAP */ 262 263 #define COMUNIT_MASK 0x7ffff 264 #define COMDIALOUT_MASK 0x80000 265 266 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 267 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 268 269 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 270 device_is_active((sc)->sc_dev)) 271 272 #define BR BUS_SPACE_BARRIER_READ 273 #define BW BUS_SPACE_BARRIER_WRITE 274 #define COM_BARRIER(r, f) \ 275 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 276 277 /*ARGSUSED*/ 278 int 279 comspeed(long speed, long frequency, int type) 280 { 281 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 282 283 int x, err; 284 int divisor = 16; 285 286 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 287 divisor = 13; 288 } 289 290 #if 0 291 if (speed == 0) 292 return (0); 293 #endif 294 if (speed <= 0) 295 return (-1); 296 x = divrnd(frequency / divisor, speed); 297 if (x <= 0) 298 return (-1); 299 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 300 if (err < 0) 301 err = -err; 302 if (err > COM_TOLERANCE) 303 return (-1); 304 return (x); 305 306 #undef divrnd 307 } 308 309 #ifdef COM_DEBUG 310 int com_debug = 0; 311 312 void comstatus(struct com_softc *, const char *); 313 void 314 comstatus(struct com_softc *sc, const char *str) 315 { 316 struct tty *tp = sc->sc_tty; 317 318 aprint_normal_dev(sc->sc_dev, 319 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 320 str, 321 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 322 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 323 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 324 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 325 sc->sc_tx_stopped ? '+' : '-'); 326 327 aprint_normal_dev(sc->sc_dev, 328 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 329 str, 330 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 331 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 332 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 333 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 334 sc->sc_rx_flags); 335 } 336 #endif 337 338 int 339 com_probe_subr(struct com_regs *regs) 340 { 341 342 /* force access to id reg */ 343 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 344 CSR_WRITE_1(regs, COM_REG_IIR, 0); 345 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 346 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 347 return (0); 348 349 return (1); 350 } 351 352 int 353 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 354 { 355 struct com_regs regs; 356 357 regs.cr_iot = iot; 358 regs.cr_ioh = ioh; 359 #ifdef COM_REGMAP 360 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 361 #endif 362 363 return com_probe_subr(®s); 364 } 365 366 /* 367 * No locking in this routine; it is only called during attach, 368 * or with the port already locked. 369 */ 370 static void 371 com_enable_debugport(struct com_softc *sc) 372 { 373 374 /* Turn on line break interrupt, set carrier. */ 375 sc->sc_ier = IER_ERXRDY; 376 if (sc->sc_type == COM_TYPE_PXA2x0) 377 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 378 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 379 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 380 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 381 } 382 383 void 384 com_attach_subr(struct com_softc *sc) 385 { 386 struct com_regs *regsp = &sc->sc_regs; 387 struct tty *tp; 388 u_int8_t lcr; 389 const char *fifo_msg = NULL; 390 prop_dictionary_t dict; 391 bool is_console = true; 392 393 aprint_naive("\n"); 394 395 dict = device_properties(sc->sc_dev); 396 prop_dictionary_get_bool(dict, "is_console", &is_console); 397 398 callout_init(&sc->sc_diag_callout, 0); 399 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 400 401 /* Disable interrupts before configuring the device. */ 402 if (sc->sc_type == COM_TYPE_PXA2x0) 403 sc->sc_ier = IER_EUART; 404 else 405 sc->sc_ier = 0; 406 407 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 408 409 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 410 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 411 comconsattached = 1; 412 413 if (cn_tab == NULL && comcnreattach() != 0) { 414 printf("can't re-init serial console @%lx\n", 415 (u_long)comcons_info.regs.cr_iobase); 416 } 417 418 #ifdef COM_16750 419 /* Use in comintr(). */ 420 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 421 #endif 422 423 /* Make sure the console is always "hardwired". */ 424 delay(10000); /* wait for output to finish */ 425 if (is_console) { 426 SET(sc->sc_hwflags, COM_HW_CONSOLE); 427 } 428 429 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 430 } 431 432 /* Probe for FIFO */ 433 switch (sc->sc_type) { 434 case COM_TYPE_HAYESP: 435 goto fifodone; 436 437 case COM_TYPE_AU1x00: 438 sc->sc_fifolen = 16; 439 fifo_msg = "Au1X00 UART, working fifo"; 440 SET(sc->sc_hwflags, COM_HW_FIFO); 441 goto fifodelay; 442 443 case COM_TYPE_16550_NOERS: 444 sc->sc_fifolen = 16; 445 fifo_msg = "ns16650, no ERS, working fifo"; 446 SET(sc->sc_hwflags, COM_HW_FIFO); 447 goto fifodelay; 448 449 case COM_TYPE_OMAP: 450 sc->sc_fifolen = 64; 451 fifo_msg = "OMAP UART, working fifo"; 452 SET(sc->sc_hwflags, COM_HW_FIFO); 453 goto fifodelay; 454 } 455 456 sc->sc_fifolen = 1; 457 /* look for a NS 16550AF UART with FIFOs */ 458 CSR_WRITE_1(regsp, COM_REG_FIFO, 459 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 460 delay(100); 461 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 462 == IIR_FIFO_MASK) 463 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 464 == FIFO_TRIGGER_14) { 465 SET(sc->sc_hwflags, COM_HW_FIFO); 466 467 #ifdef COM_16650 468 /* 469 * IIR changes into the EFR if LCR is set to LCR_EERS 470 * on 16650s. We also know IIR != 0 at this point. 471 * Write 0 into the EFR, and read it. If the result 472 * is 0, we have a 16650. 473 * 474 * Older 16650s were broken; the test to detect them 475 * is taken from the Linux driver. Apparently 476 * setting DLAB enable gives access to the EFR on 477 * these chips. 478 */ 479 lcr = CSR_READ_1(regsp, COM_REG_LCR); 480 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 481 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 482 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 483 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 484 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 485 CLR(sc->sc_hwflags, COM_HW_FIFO); 486 sc->sc_fifolen = 0; 487 } else { 488 SET(sc->sc_hwflags, COM_HW_FLOW); 489 sc->sc_fifolen = 32; 490 } 491 } else 492 #endif 493 sc->sc_fifolen = 16; 494 495 /* 496 * TL16C750 can enable 64byte FIFO, only when DLAB 497 * is 1. However, some 16750 may always enable. For 498 * example, restrictions according to DLAB in a data 499 * sheet for SC16C750 were not described. 500 * Please enable 'options COM_16650', supposing you 501 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 502 * should become effective. 503 */ 504 uint8_t iir1, iir2; 505 const uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 506 507 lcr = CSR_READ_1(regsp, COM_REG_LCR); 508 CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB); 509 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 510 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 511 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 512 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 513 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 514 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 515 516 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 517 518 if (!ISSET(iir1, IIR_64B_FIFO) && 519 ISSET(iir2, IIR_64B_FIFO)) { 520 /* It is TL16C750. */ 521 sc->sc_fifolen = 64; 522 SET(sc->sc_hwflags, COM_HW_AFE); 523 } else 524 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 525 526 #ifdef COM_16650 527 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 528 if (sc->sc_fifolen == 0) 529 fifo_msg = "st16650, broken fifo"; 530 else if (sc->sc_fifolen == 32) 531 fifo_msg = "st16650a, working fifo"; 532 else 533 #endif 534 if (sc->sc_fifolen == 64) 535 fifo_msg = "tl16c750, working fifo"; 536 else 537 fifo_msg = "ns16550a, working fifo"; 538 } else 539 fifo_msg = "ns16550, broken fifo"; 540 else 541 fifo_msg = "ns8250 or ns16450, no fifo"; 542 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 543 fifodelay: 544 /* 545 * Some chips will clear down both Tx and Rx FIFOs when zero is 546 * written to com_fifo. If this chip is the console, writing zero 547 * results in some of the chip/FIFO description being lost, so delay 548 * printing it until now. 549 */ 550 delay(10); 551 aprint_normal(": %s\n", fifo_msg); 552 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 553 sc->sc_fifolen = 1; 554 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 555 } 556 557 fifodone: 558 559 tp = tty_alloc(); 560 tp->t_oproc = comstart; 561 tp->t_param = comparam; 562 tp->t_hwiflow = comhwiflow; 563 tp->t_softc = sc; 564 565 sc->sc_tty = tp; 566 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 567 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 568 sc->sc_rbavail = com_rbuf_size; 569 if (sc->sc_rbuf == NULL) { 570 aprint_error_dev(sc->sc_dev, 571 "unable to allocate ring buffer\n"); 572 return; 573 } 574 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 575 576 tty_attach(tp); 577 578 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 579 SET(sc->sc_mcr, MCR_IENABLE); 580 581 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 582 int maj; 583 584 /* locate the major number */ 585 maj = cdevsw_lookup_major(&com_cdevsw); 586 587 tp->t_dev = cn_tab->cn_dev = makedev(maj, 588 device_unit(sc->sc_dev)); 589 590 aprint_normal_dev(sc->sc_dev, "console\n"); 591 } 592 593 #ifdef KGDB 594 /* 595 * Allow kgdb to "take over" this port. If this is 596 * not the console and is the kgdb device, it has 597 * exclusive use. If it's the console _and_ the 598 * kgdb device, it doesn't. 599 */ 600 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 601 regsp->cr_iobase == comkgdbregs.cr_iobase) { 602 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 603 com_kgdb_attached = 1; 604 605 SET(sc->sc_hwflags, COM_HW_KGDB); 606 } 607 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 608 } 609 #endif 610 611 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 612 613 #ifdef RND_COM 614 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 615 RND_TYPE_TTY, 0); 616 #endif 617 618 /* if there are no enable/disable functions, assume the device 619 is always enabled */ 620 if (!sc->enable) 621 sc->enabled = 1; 622 623 com_config(sc); 624 625 SET(sc->sc_hwflags, COM_HW_DEV_OK); 626 } 627 628 void 629 com_config(struct com_softc *sc) 630 { 631 struct com_regs *regsp = &sc->sc_regs; 632 633 /* Disable interrupts before configuring the device. */ 634 if (sc->sc_type == COM_TYPE_PXA2x0) 635 sc->sc_ier = IER_EUART; 636 else 637 sc->sc_ier = 0; 638 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 639 (void) CSR_READ_1(regsp, COM_REG_IIR); 640 641 #ifdef COM_HAYESP 642 /* Look for a Hayes ESP board. */ 643 if (sc->sc_type == COM_TYPE_HAYESP) { 644 645 /* Set 16550 compatibility mode */ 646 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 647 HAYESP_SETMODE); 648 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 649 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 650 HAYESP_MODE_SCALE); 651 652 /* Set RTS/CTS flow control */ 653 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 654 HAYESP_SETFLOWTYPE); 655 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 656 HAYESP_FLOW_RTS); 657 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 658 HAYESP_FLOW_CTS); 659 660 /* Set flow control levels */ 661 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 662 HAYESP_SETRXFLOW); 663 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 664 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 665 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 666 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 667 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 668 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 669 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 670 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 671 } 672 #endif 673 674 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 675 com_enable_debugport(sc); 676 } 677 678 #if 0 679 static int 680 comcngetc_detached(dev_t dev) 681 { 682 return 0; 683 } 684 685 static void 686 comcnputc_detached(dev_t dev, int c) 687 { 688 } 689 #endif 690 691 int 692 com_detach(device_t self, int flags) 693 { 694 struct com_softc *sc = device_private(self); 695 int maj, mn; 696 697 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 698 return EBUSY; 699 700 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 701 (flags & DETACH_SHUTDOWN) != 0) 702 return EBUSY; 703 704 if (sc->disable != NULL && sc->enabled != 0) { 705 (*sc->disable)(sc); 706 sc->enabled = 0; 707 } 708 709 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 710 comconsattached = 0; 711 cn_tab = NULL; 712 } 713 714 /* locate the major number */ 715 maj = cdevsw_lookup_major(&com_cdevsw); 716 717 /* Nuke the vnodes for any open instances. */ 718 mn = device_unit(self); 719 vdevgone(maj, mn, mn, VCHR); 720 721 mn |= COMDIALOUT_MASK; 722 vdevgone(maj, mn, mn, VCHR); 723 724 if (sc->sc_rbuf == NULL) { 725 /* 726 * Ring buffer allocation failed in the com_attach_subr, 727 * only the tty is allocated, and nothing else. 728 */ 729 tty_free(sc->sc_tty); 730 return 0; 731 } 732 733 /* Free the receive buffer. */ 734 free(sc->sc_rbuf, M_DEVBUF); 735 736 /* Detach and free the tty. */ 737 tty_detach(sc->sc_tty); 738 tty_free(sc->sc_tty); 739 740 /* Unhook the soft interrupt handler. */ 741 softint_disestablish(sc->sc_si); 742 743 #ifdef RND_COM 744 /* Unhook the entropy source. */ 745 rnd_detach_source(&sc->rnd_source); 746 #endif 747 callout_destroy(&sc->sc_diag_callout); 748 749 /* Destroy the lock. */ 750 mutex_destroy(&sc->sc_lock); 751 752 return (0); 753 } 754 755 void 756 com_shutdown(struct com_softc *sc) 757 { 758 struct tty *tp = sc->sc_tty; 759 760 mutex_spin_enter(&sc->sc_lock); 761 762 /* If we were asserting flow control, then deassert it. */ 763 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 764 com_hwiflow(sc); 765 766 /* Clear any break condition set with TIOCSBRK. */ 767 com_break(sc, 0); 768 769 /* 770 * Hang up if necessary. Wait a bit, so the other side has time to 771 * notice even if we immediately open the port again. 772 * Avoid tsleeping above splhigh(). 773 */ 774 if (ISSET(tp->t_cflag, HUPCL)) { 775 com_modem(sc, 0); 776 mutex_spin_exit(&sc->sc_lock); 777 /* XXX will only timeout */ 778 (void) kpause(ttclos, false, hz, NULL); 779 mutex_spin_enter(&sc->sc_lock); 780 } 781 782 /* Turn off interrupts. */ 783 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 784 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 785 if (sc->sc_type == COM_TYPE_PXA2x0) 786 sc->sc_ier |= IER_ERXTOUT; 787 } else 788 sc->sc_ier = 0; 789 790 if (sc->sc_type == COM_TYPE_PXA2x0) 791 sc->sc_ier |= IER_EUART; 792 793 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 794 795 mutex_spin_exit(&sc->sc_lock); 796 797 if (sc->disable) { 798 #ifdef DIAGNOSTIC 799 if (!sc->enabled) 800 panic("com_shutdown: not enabled?"); 801 #endif 802 (*sc->disable)(sc); 803 sc->enabled = 0; 804 } 805 } 806 807 int 808 comopen(dev_t dev, int flag, int mode, struct lwp *l) 809 { 810 struct com_softc *sc; 811 struct tty *tp; 812 int s; 813 int error; 814 815 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 816 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 817 sc->sc_rbuf == NULL) 818 return (ENXIO); 819 820 if (!device_is_active(sc->sc_dev)) 821 return (ENXIO); 822 823 #ifdef KGDB 824 /* 825 * If this is the kgdb port, no other use is permitted. 826 */ 827 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 828 return (EBUSY); 829 #endif 830 831 tp = sc->sc_tty; 832 833 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 834 return (EBUSY); 835 836 s = spltty(); 837 838 /* 839 * Do the following iff this is a first open. 840 */ 841 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 842 struct termios t; 843 844 tp->t_dev = dev; 845 846 if (sc->enable) { 847 if ((*sc->enable)(sc)) { 848 splx(s); 849 aprint_error_dev(sc->sc_dev, 850 "device enable failed\n"); 851 return (EIO); 852 } 853 mutex_spin_enter(&sc->sc_lock); 854 sc->enabled = 1; 855 com_config(sc); 856 } else { 857 mutex_spin_enter(&sc->sc_lock); 858 } 859 860 /* Turn on interrupts. */ 861 sc->sc_ier = IER_ERXRDY | IER_ERLS; 862 if (!ISSET(tp->t_cflag, CLOCAL)) 863 sc->sc_ier |= IER_EMSC; 864 865 if (sc->sc_type == COM_TYPE_PXA2x0) 866 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 867 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 868 869 /* Fetch the current modem control status, needed later. */ 870 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 871 872 /* Clear PPS capture state on first open. */ 873 mutex_spin_enter(&timecounter_lock); 874 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 875 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 876 pps_init(&sc->sc_pps_state); 877 mutex_spin_exit(&timecounter_lock); 878 879 mutex_spin_exit(&sc->sc_lock); 880 881 /* 882 * Initialize the termios status to the defaults. Add in the 883 * sticky bits from TIOCSFLAGS. 884 */ 885 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 886 t.c_ospeed = comcons_info.rate; 887 t.c_cflag = comcons_info.cflag; 888 } else { 889 t.c_ospeed = TTYDEF_SPEED; 890 t.c_cflag = TTYDEF_CFLAG; 891 } 892 t.c_ispeed = t.c_ospeed; 893 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 894 SET(t.c_cflag, CLOCAL); 895 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 896 SET(t.c_cflag, CRTSCTS); 897 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 898 SET(t.c_cflag, MDMBUF); 899 /* Make sure comparam() will do something. */ 900 tp->t_ospeed = 0; 901 (void) comparam(tp, &t); 902 tp->t_iflag = TTYDEF_IFLAG; 903 tp->t_oflag = TTYDEF_OFLAG; 904 tp->t_lflag = TTYDEF_LFLAG; 905 ttychars(tp); 906 ttsetwater(tp); 907 908 mutex_spin_enter(&sc->sc_lock); 909 910 /* 911 * Turn on DTR. We must always do this, even if carrier is not 912 * present, because otherwise we'd have to use TIOCSDTR 913 * immediately after setting CLOCAL, which applications do not 914 * expect. We always assert DTR while the device is open 915 * unless explicitly requested to deassert it. 916 */ 917 com_modem(sc, 1); 918 919 /* Clear the input ring, and unblock. */ 920 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 921 sc->sc_rbavail = com_rbuf_size; 922 com_iflush(sc); 923 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 924 com_hwiflow(sc); 925 926 #ifdef COM_DEBUG 927 if (com_debug) 928 comstatus(sc, "comopen "); 929 #endif 930 931 mutex_spin_exit(&sc->sc_lock); 932 } 933 934 splx(s); 935 936 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 937 if (error) 938 goto bad; 939 940 error = (*tp->t_linesw->l_open)(dev, tp); 941 if (error) 942 goto bad; 943 944 return (0); 945 946 bad: 947 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 948 /* 949 * We failed to open the device, and nobody else had it opened. 950 * Clean up the state as appropriate. 951 */ 952 com_shutdown(sc); 953 } 954 955 return (error); 956 } 957 958 int 959 comclose(dev_t dev, int flag, int mode, struct lwp *l) 960 { 961 struct com_softc *sc = 962 device_lookup_private(&com_cd, COMUNIT(dev)); 963 struct tty *tp = sc->sc_tty; 964 965 /* XXX This is for cons.c. */ 966 if (!ISSET(tp->t_state, TS_ISOPEN)) 967 return (0); 968 969 (*tp->t_linesw->l_close)(tp, flag); 970 ttyclose(tp); 971 972 if (COM_ISALIVE(sc) == 0) 973 return (0); 974 975 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 976 /* 977 * Although we got a last close, the device may still be in 978 * use; e.g. if this was the dialout node, and there are still 979 * processes waiting for carrier on the non-dialout node. 980 */ 981 com_shutdown(sc); 982 } 983 984 return (0); 985 } 986 987 int 988 comread(dev_t dev, struct uio *uio, int flag) 989 { 990 struct com_softc *sc = 991 device_lookup_private(&com_cd, COMUNIT(dev)); 992 struct tty *tp = sc->sc_tty; 993 994 if (COM_ISALIVE(sc) == 0) 995 return (EIO); 996 997 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 998 } 999 1000 int 1001 comwrite(dev_t dev, struct uio *uio, int flag) 1002 { 1003 struct com_softc *sc = 1004 device_lookup_private(&com_cd, COMUNIT(dev)); 1005 struct tty *tp = sc->sc_tty; 1006 1007 if (COM_ISALIVE(sc) == 0) 1008 return (EIO); 1009 1010 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1011 } 1012 1013 int 1014 compoll(dev_t dev, int events, struct lwp *l) 1015 { 1016 struct com_softc *sc = 1017 device_lookup_private(&com_cd, COMUNIT(dev)); 1018 struct tty *tp = sc->sc_tty; 1019 1020 if (COM_ISALIVE(sc) == 0) 1021 return (POLLHUP); 1022 1023 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1024 } 1025 1026 struct tty * 1027 comtty(dev_t dev) 1028 { 1029 struct com_softc *sc = 1030 device_lookup_private(&com_cd, COMUNIT(dev)); 1031 struct tty *tp = sc->sc_tty; 1032 1033 return (tp); 1034 } 1035 1036 int 1037 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1038 { 1039 struct com_softc *sc; 1040 struct tty *tp; 1041 int error; 1042 1043 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1044 if (sc == NULL) 1045 return ENXIO; 1046 if (COM_ISALIVE(sc) == 0) 1047 return (EIO); 1048 1049 tp = sc->sc_tty; 1050 1051 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1052 if (error != EPASSTHROUGH) 1053 return (error); 1054 1055 error = ttioctl(tp, cmd, data, flag, l); 1056 if (error != EPASSTHROUGH) 1057 return (error); 1058 1059 error = 0; 1060 switch (cmd) { 1061 case TIOCSFLAGS: 1062 error = kauth_authorize_device_tty(l->l_cred, 1063 KAUTH_DEVICE_TTY_PRIVSET, tp); 1064 break; 1065 default: 1066 /* nothing */ 1067 break; 1068 } 1069 if (error) { 1070 return error; 1071 } 1072 1073 mutex_spin_enter(&sc->sc_lock); 1074 1075 switch (cmd) { 1076 case TIOCSBRK: 1077 com_break(sc, 1); 1078 break; 1079 1080 case TIOCCBRK: 1081 com_break(sc, 0); 1082 break; 1083 1084 case TIOCSDTR: 1085 com_modem(sc, 1); 1086 break; 1087 1088 case TIOCCDTR: 1089 com_modem(sc, 0); 1090 break; 1091 1092 case TIOCGFLAGS: 1093 *(int *)data = sc->sc_swflags; 1094 break; 1095 1096 case TIOCSFLAGS: 1097 sc->sc_swflags = *(int *)data; 1098 break; 1099 1100 case TIOCMSET: 1101 case TIOCMBIS: 1102 case TIOCMBIC: 1103 tiocm_to_com(sc, cmd, *(int *)data); 1104 break; 1105 1106 case TIOCMGET: 1107 *(int *)data = com_to_tiocm(sc); 1108 break; 1109 1110 case PPS_IOC_CREATE: 1111 case PPS_IOC_DESTROY: 1112 case PPS_IOC_GETPARAMS: 1113 case PPS_IOC_SETPARAMS: 1114 case PPS_IOC_GETCAP: 1115 case PPS_IOC_FETCH: 1116 #ifdef PPS_SYNC 1117 case PPS_IOC_KCBIND: 1118 #endif 1119 mutex_spin_enter(&timecounter_lock); 1120 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1121 mutex_spin_exit(&timecounter_lock); 1122 break; 1123 1124 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1125 mutex_spin_enter(&timecounter_lock); 1126 #ifndef PPS_TRAILING_EDGE 1127 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1128 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1129 #else 1130 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1131 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1132 #endif 1133 mutex_spin_exit(&timecounter_lock); 1134 break; 1135 1136 default: 1137 error = EPASSTHROUGH; 1138 break; 1139 } 1140 1141 mutex_spin_exit(&sc->sc_lock); 1142 1143 #ifdef COM_DEBUG 1144 if (com_debug) 1145 comstatus(sc, "comioctl "); 1146 #endif 1147 1148 return (error); 1149 } 1150 1151 integrate void 1152 com_schedrx(struct com_softc *sc) 1153 { 1154 1155 sc->sc_rx_ready = 1; 1156 1157 /* Wake up the poller. */ 1158 softint_schedule(sc->sc_si); 1159 } 1160 1161 void 1162 com_break(struct com_softc *sc, int onoff) 1163 { 1164 1165 if (onoff) 1166 SET(sc->sc_lcr, LCR_SBREAK); 1167 else 1168 CLR(sc->sc_lcr, LCR_SBREAK); 1169 1170 if (!sc->sc_heldchange) { 1171 if (sc->sc_tx_busy) { 1172 sc->sc_heldtbc = sc->sc_tbc; 1173 sc->sc_tbc = 0; 1174 sc->sc_heldchange = 1; 1175 } else 1176 com_loadchannelregs(sc); 1177 } 1178 } 1179 1180 void 1181 com_modem(struct com_softc *sc, int onoff) 1182 { 1183 1184 if (sc->sc_mcr_dtr == 0) 1185 return; 1186 1187 if (onoff) 1188 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1189 else 1190 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1191 1192 if (!sc->sc_heldchange) { 1193 if (sc->sc_tx_busy) { 1194 sc->sc_heldtbc = sc->sc_tbc; 1195 sc->sc_tbc = 0; 1196 sc->sc_heldchange = 1; 1197 } else 1198 com_loadchannelregs(sc); 1199 } 1200 } 1201 1202 void 1203 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1204 { 1205 u_char combits; 1206 1207 combits = 0; 1208 if (ISSET(ttybits, TIOCM_DTR)) 1209 SET(combits, MCR_DTR); 1210 if (ISSET(ttybits, TIOCM_RTS)) 1211 SET(combits, MCR_RTS); 1212 1213 switch (how) { 1214 case TIOCMBIC: 1215 CLR(sc->sc_mcr, combits); 1216 break; 1217 1218 case TIOCMBIS: 1219 SET(sc->sc_mcr, combits); 1220 break; 1221 1222 case TIOCMSET: 1223 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1224 SET(sc->sc_mcr, combits); 1225 break; 1226 } 1227 1228 if (!sc->sc_heldchange) { 1229 if (sc->sc_tx_busy) { 1230 sc->sc_heldtbc = sc->sc_tbc; 1231 sc->sc_tbc = 0; 1232 sc->sc_heldchange = 1; 1233 } else 1234 com_loadchannelregs(sc); 1235 } 1236 } 1237 1238 int 1239 com_to_tiocm(struct com_softc *sc) 1240 { 1241 u_char combits; 1242 int ttybits = 0; 1243 1244 combits = sc->sc_mcr; 1245 if (ISSET(combits, MCR_DTR)) 1246 SET(ttybits, TIOCM_DTR); 1247 if (ISSET(combits, MCR_RTS)) 1248 SET(ttybits, TIOCM_RTS); 1249 1250 combits = sc->sc_msr; 1251 if (ISSET(combits, MSR_DCD)) 1252 SET(ttybits, TIOCM_CD); 1253 if (ISSET(combits, MSR_CTS)) 1254 SET(ttybits, TIOCM_CTS); 1255 if (ISSET(combits, MSR_DSR)) 1256 SET(ttybits, TIOCM_DSR); 1257 if (ISSET(combits, MSR_RI | MSR_TERI)) 1258 SET(ttybits, TIOCM_RI); 1259 1260 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1261 SET(ttybits, TIOCM_LE); 1262 1263 return (ttybits); 1264 } 1265 1266 static u_char 1267 cflag2lcr(tcflag_t cflag) 1268 { 1269 u_char lcr = 0; 1270 1271 switch (ISSET(cflag, CSIZE)) { 1272 case CS5: 1273 SET(lcr, LCR_5BITS); 1274 break; 1275 case CS6: 1276 SET(lcr, LCR_6BITS); 1277 break; 1278 case CS7: 1279 SET(lcr, LCR_7BITS); 1280 break; 1281 case CS8: 1282 SET(lcr, LCR_8BITS); 1283 break; 1284 } 1285 if (ISSET(cflag, PARENB)) { 1286 SET(lcr, LCR_PENAB); 1287 if (!ISSET(cflag, PARODD)) 1288 SET(lcr, LCR_PEVEN); 1289 } 1290 if (ISSET(cflag, CSTOPB)) 1291 SET(lcr, LCR_STOPB); 1292 1293 return (lcr); 1294 } 1295 1296 int 1297 comparam(struct tty *tp, struct termios *t) 1298 { 1299 struct com_softc *sc = 1300 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1301 int ospeed; 1302 u_char lcr; 1303 1304 if (COM_ISALIVE(sc) == 0) 1305 return (EIO); 1306 1307 #ifdef COM_HAYESP 1308 if (sc->sc_type == COM_TYPE_HAYESP) { 1309 int prescaler, speed; 1310 1311 /* 1312 * Calculate UART clock prescaler. It should be in 1313 * range of 0 .. 3. 1314 */ 1315 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1316 prescaler++, speed /= 2) 1317 if ((ospeed = comspeed(speed, sc->sc_frequency, 1318 sc->sc_type)) > 0) 1319 break; 1320 1321 if (prescaler == 4) 1322 return (EINVAL); 1323 sc->sc_prescaler = prescaler; 1324 } else 1325 #endif 1326 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1327 1328 /* Check requested parameters. */ 1329 if (ospeed < 0) 1330 return (EINVAL); 1331 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1332 return (EINVAL); 1333 1334 /* 1335 * For the console, always force CLOCAL and !HUPCL, so that the port 1336 * is always active. 1337 */ 1338 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1339 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1340 SET(t->c_cflag, CLOCAL); 1341 CLR(t->c_cflag, HUPCL); 1342 } 1343 1344 /* 1345 * If there were no changes, don't do anything. This avoids dropping 1346 * input and improves performance when all we did was frob things like 1347 * VMIN and VTIME. 1348 */ 1349 if (tp->t_ospeed == t->c_ospeed && 1350 tp->t_cflag == t->c_cflag) 1351 return (0); 1352 1353 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1354 1355 mutex_spin_enter(&sc->sc_lock); 1356 1357 sc->sc_lcr = lcr; 1358 1359 /* 1360 * If we're not in a mode that assumes a connection is present, then 1361 * ignore carrier changes. 1362 */ 1363 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1364 sc->sc_msr_dcd = 0; 1365 else 1366 sc->sc_msr_dcd = MSR_DCD; 1367 /* 1368 * Set the flow control pins depending on the current flow control 1369 * mode. 1370 */ 1371 if (ISSET(t->c_cflag, CRTSCTS)) { 1372 sc->sc_mcr_dtr = MCR_DTR; 1373 sc->sc_mcr_rts = MCR_RTS; 1374 sc->sc_msr_cts = MSR_CTS; 1375 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1376 SET(sc->sc_mcr, MCR_AFE); 1377 } else { 1378 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1379 } 1380 } else if (ISSET(t->c_cflag, MDMBUF)) { 1381 /* 1382 * For DTR/DCD flow control, make sure we don't toggle DTR for 1383 * carrier detection. 1384 */ 1385 sc->sc_mcr_dtr = 0; 1386 sc->sc_mcr_rts = MCR_DTR; 1387 sc->sc_msr_cts = MSR_DCD; 1388 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1389 CLR(sc->sc_mcr, MCR_AFE); 1390 } else { 1391 sc->sc_efr = 0; 1392 } 1393 } else { 1394 /* 1395 * If no flow control, then always set RTS. This will make 1396 * the other side happy if it mistakenly thinks we're doing 1397 * RTS/CTS flow control. 1398 */ 1399 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1400 sc->sc_mcr_rts = 0; 1401 sc->sc_msr_cts = 0; 1402 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1403 CLR(sc->sc_mcr, MCR_AFE); 1404 } else { 1405 sc->sc_efr = 0; 1406 } 1407 if (ISSET(sc->sc_mcr, MCR_DTR)) 1408 SET(sc->sc_mcr, MCR_RTS); 1409 else 1410 CLR(sc->sc_mcr, MCR_RTS); 1411 } 1412 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1413 1414 #if 0 1415 if (ospeed == 0) 1416 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1417 else 1418 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1419 #endif 1420 1421 sc->sc_dlbl = ospeed; 1422 sc->sc_dlbh = ospeed >> 8; 1423 1424 /* 1425 * Set the FIFO threshold based on the receive speed. 1426 * 1427 * * If it's a low speed, it's probably a mouse or some other 1428 * interactive device, so set the threshold low. 1429 * * If it's a high speed, trim the trigger level down to prevent 1430 * overflows. 1431 * * Otherwise set it a bit higher. 1432 */ 1433 if (sc->sc_type == COM_TYPE_HAYESP) 1434 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1435 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1436 if (t->c_ospeed <= 1200) 1437 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1438 else if (t->c_ospeed <= 38400) 1439 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1440 else 1441 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1442 } else 1443 sc->sc_fifo = 0; 1444 1445 /* And copy to tty. */ 1446 tp->t_ispeed = t->c_ospeed; 1447 tp->t_ospeed = t->c_ospeed; 1448 tp->t_cflag = t->c_cflag; 1449 1450 if (!sc->sc_heldchange) { 1451 if (sc->sc_tx_busy) { 1452 sc->sc_heldtbc = sc->sc_tbc; 1453 sc->sc_tbc = 0; 1454 sc->sc_heldchange = 1; 1455 } else 1456 com_loadchannelregs(sc); 1457 } 1458 1459 if (!ISSET(t->c_cflag, CHWFLOW)) { 1460 /* Disable the high water mark. */ 1461 sc->sc_r_hiwat = 0; 1462 sc->sc_r_lowat = 0; 1463 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1464 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1465 com_schedrx(sc); 1466 } 1467 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1468 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1469 com_hwiflow(sc); 1470 } 1471 } else { 1472 sc->sc_r_hiwat = com_rbuf_hiwat; 1473 sc->sc_r_lowat = com_rbuf_lowat; 1474 } 1475 1476 mutex_spin_exit(&sc->sc_lock); 1477 1478 /* 1479 * Update the tty layer's idea of the carrier bit, in case we changed 1480 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1481 * explicit request. 1482 */ 1483 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1484 1485 #ifdef COM_DEBUG 1486 if (com_debug) 1487 comstatus(sc, "comparam "); 1488 #endif 1489 1490 if (!ISSET(t->c_cflag, CHWFLOW)) { 1491 if (sc->sc_tx_stopped) { 1492 sc->sc_tx_stopped = 0; 1493 comstart(tp); 1494 } 1495 } 1496 1497 return (0); 1498 } 1499 1500 void 1501 com_iflush(struct com_softc *sc) 1502 { 1503 struct com_regs *regsp = &sc->sc_regs; 1504 #ifdef DIAGNOSTIC 1505 int reg; 1506 #endif 1507 int timo; 1508 1509 #ifdef DIAGNOSTIC 1510 reg = 0xffff; 1511 #endif 1512 timo = 50000; 1513 /* flush any pending I/O */ 1514 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1515 && --timo) 1516 #ifdef DIAGNOSTIC 1517 reg = 1518 #else 1519 (void) 1520 #endif 1521 CSR_READ_1(regsp, COM_REG_RXDATA); 1522 #ifdef DIAGNOSTIC 1523 if (!timo) 1524 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1525 #endif 1526 1527 #ifdef COM_16750 1528 uint8_t fifo; 1529 /* 1530 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1531 * This should prevent triggering busy interrupt while 1532 * manipulating divisors. 1533 */ 1534 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1535 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1536 CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST | 1537 FIFO_XMT_RST); 1538 delay(100); 1539 #endif 1540 } 1541 1542 void 1543 com_loadchannelregs(struct com_softc *sc) 1544 { 1545 struct com_regs *regsp = &sc->sc_regs; 1546 1547 /* XXXXX necessary? */ 1548 com_iflush(sc); 1549 1550 if (sc->sc_type == COM_TYPE_PXA2x0) 1551 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1552 else 1553 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1554 1555 if (sc->sc_type == COM_TYPE_OMAP) { 1556 /* disable before changing settings */ 1557 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1558 } 1559 1560 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1561 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1562 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1563 /* no EFR on alchemy */ 1564 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1565 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1566 } 1567 if (sc->sc_type == COM_TYPE_AU1x00) { 1568 /* alchemy has single separate 16-bit clock divisor register */ 1569 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1570 (sc->sc_dlbh << 8)); 1571 } else { 1572 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1573 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1574 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1575 } 1576 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1577 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1578 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1579 #ifdef COM_HAYESP 1580 if (sc->sc_type == COM_TYPE_HAYESP) { 1581 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1582 HAYESP_SETPRESCALER); 1583 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1584 sc->sc_prescaler); 1585 } 1586 #endif 1587 if (sc->sc_type == COM_TYPE_OMAP) { 1588 /* setup the fifos. the FCR value is not used as long 1589 as SCR[6] and SCR[7] are 0, which they are at reset 1590 and we never touch the SCR register */ 1591 uint8_t rx_fifo_trig = 40; 1592 uint8_t tx_fifo_trig = 60; 1593 uint8_t rx_start = 8; 1594 uint8_t rx_halt = 60; 1595 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1596 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1597 1598 /* enable access to TCR & TLR */ 1599 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1600 1601 /* write tcr and tlr values */ 1602 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1603 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1604 1605 /* disable access to TCR & TLR */ 1606 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1607 1608 /* enable again, but mode is based on speed */ 1609 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1610 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1611 } else { 1612 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1613 } 1614 } 1615 1616 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1617 } 1618 1619 int 1620 comhwiflow(struct tty *tp, int block) 1621 { 1622 struct com_softc *sc = 1623 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1624 1625 if (COM_ISALIVE(sc) == 0) 1626 return (0); 1627 1628 if (sc->sc_mcr_rts == 0) 1629 return (0); 1630 1631 mutex_spin_enter(&sc->sc_lock); 1632 1633 if (block) { 1634 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1635 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1636 com_hwiflow(sc); 1637 } 1638 } else { 1639 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1640 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1641 com_schedrx(sc); 1642 } 1643 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1644 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1645 com_hwiflow(sc); 1646 } 1647 } 1648 1649 mutex_spin_exit(&sc->sc_lock); 1650 return (1); 1651 } 1652 1653 /* 1654 * (un)block input via hw flowcontrol 1655 */ 1656 void 1657 com_hwiflow(struct com_softc *sc) 1658 { 1659 struct com_regs *regsp= &sc->sc_regs; 1660 1661 if (sc->sc_mcr_rts == 0) 1662 return; 1663 1664 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1665 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1666 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1667 } else { 1668 SET(sc->sc_mcr, sc->sc_mcr_rts); 1669 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1670 } 1671 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1672 } 1673 1674 1675 void 1676 comstart(struct tty *tp) 1677 { 1678 struct com_softc *sc = 1679 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1680 struct com_regs *regsp = &sc->sc_regs; 1681 int s; 1682 1683 if (COM_ISALIVE(sc) == 0) 1684 return; 1685 1686 s = spltty(); 1687 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1688 goto out; 1689 if (sc->sc_tx_stopped) 1690 goto out; 1691 if (!ttypull(tp)) 1692 goto out; 1693 1694 /* Grab the first contiguous region of buffer space. */ 1695 { 1696 u_char *tba; 1697 int tbc; 1698 1699 tba = tp->t_outq.c_cf; 1700 tbc = ndqb(&tp->t_outq, 0); 1701 1702 mutex_spin_enter(&sc->sc_lock); 1703 1704 sc->sc_tba = tba; 1705 sc->sc_tbc = tbc; 1706 } 1707 1708 SET(tp->t_state, TS_BUSY); 1709 sc->sc_tx_busy = 1; 1710 1711 /* Enable transmit completion interrupts if necessary. */ 1712 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1713 SET(sc->sc_ier, IER_ETXRDY); 1714 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1715 } 1716 1717 /* Output the first chunk of the contiguous buffer. */ 1718 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1719 u_int n; 1720 1721 n = sc->sc_tbc; 1722 if (n > sc->sc_fifolen) 1723 n = sc->sc_fifolen; 1724 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1725 sc->sc_tbc -= n; 1726 sc->sc_tba += n; 1727 } 1728 1729 mutex_spin_exit(&sc->sc_lock); 1730 out: 1731 splx(s); 1732 return; 1733 } 1734 1735 /* 1736 * Stop output on a line. 1737 */ 1738 void 1739 comstop(struct tty *tp, int flag) 1740 { 1741 struct com_softc *sc = 1742 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1743 1744 mutex_spin_enter(&sc->sc_lock); 1745 if (ISSET(tp->t_state, TS_BUSY)) { 1746 /* Stop transmitting at the next chunk. */ 1747 sc->sc_tbc = 0; 1748 sc->sc_heldtbc = 0; 1749 if (!ISSET(tp->t_state, TS_TTSTOP)) 1750 SET(tp->t_state, TS_FLUSH); 1751 } 1752 mutex_spin_exit(&sc->sc_lock); 1753 } 1754 1755 void 1756 comdiag(void *arg) 1757 { 1758 struct com_softc *sc = arg; 1759 int overflows, floods; 1760 1761 mutex_spin_enter(&sc->sc_lock); 1762 overflows = sc->sc_overflows; 1763 sc->sc_overflows = 0; 1764 floods = sc->sc_floods; 1765 sc->sc_floods = 0; 1766 sc->sc_errors = 0; 1767 mutex_spin_exit(&sc->sc_lock); 1768 1769 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1770 device_xname(sc->sc_dev), 1771 overflows, overflows == 1 ? "" : "s", 1772 floods, floods == 1 ? "" : "s"); 1773 } 1774 1775 integrate void 1776 com_rxsoft(struct com_softc *sc, struct tty *tp) 1777 { 1778 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1779 u_char *get, *end; 1780 u_int cc, scc; 1781 u_char lsr; 1782 int code; 1783 1784 end = sc->sc_ebuf; 1785 get = sc->sc_rbget; 1786 scc = cc = com_rbuf_size - sc->sc_rbavail; 1787 1788 if (cc == com_rbuf_size) { 1789 sc->sc_floods++; 1790 if (sc->sc_errors++ == 0) 1791 callout_reset(&sc->sc_diag_callout, 60 * hz, 1792 comdiag, sc); 1793 } 1794 1795 /* If not yet open, drop the entire buffer content here */ 1796 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1797 get += cc << 1; 1798 if (get >= end) 1799 get -= com_rbuf_size << 1; 1800 cc = 0; 1801 } 1802 while (cc) { 1803 code = get[0]; 1804 lsr = get[1]; 1805 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1806 if (ISSET(lsr, LSR_OE)) { 1807 sc->sc_overflows++; 1808 if (sc->sc_errors++ == 0) 1809 callout_reset(&sc->sc_diag_callout, 1810 60 * hz, comdiag, sc); 1811 } 1812 if (ISSET(lsr, LSR_BI | LSR_FE)) 1813 SET(code, TTY_FE); 1814 if (ISSET(lsr, LSR_PE)) 1815 SET(code, TTY_PE); 1816 } 1817 if ((*rint)(code, tp) == -1) { 1818 /* 1819 * The line discipline's buffer is out of space. 1820 */ 1821 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1822 /* 1823 * We're either not using flow control, or the 1824 * line discipline didn't tell us to block for 1825 * some reason. Either way, we have no way to 1826 * know when there's more space available, so 1827 * just drop the rest of the data. 1828 */ 1829 get += cc << 1; 1830 if (get >= end) 1831 get -= com_rbuf_size << 1; 1832 cc = 0; 1833 } else { 1834 /* 1835 * Don't schedule any more receive processing 1836 * until the line discipline tells us there's 1837 * space available (through comhwiflow()). 1838 * Leave the rest of the data in the input 1839 * buffer. 1840 */ 1841 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1842 } 1843 break; 1844 } 1845 get += 2; 1846 if (get >= end) 1847 get = sc->sc_rbuf; 1848 cc--; 1849 } 1850 1851 if (cc != scc) { 1852 sc->sc_rbget = get; 1853 mutex_spin_enter(&sc->sc_lock); 1854 1855 cc = sc->sc_rbavail += scc - cc; 1856 /* Buffers should be ok again, release possible block. */ 1857 if (cc >= sc->sc_r_lowat) { 1858 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1859 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1860 SET(sc->sc_ier, IER_ERXRDY); 1861 #ifdef COM_PXA2X0 1862 if (sc->sc_type == COM_TYPE_PXA2x0) 1863 SET(sc->sc_ier, IER_ERXTOUT); 1864 #endif 1865 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1866 } 1867 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1868 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1869 com_hwiflow(sc); 1870 } 1871 } 1872 mutex_spin_exit(&sc->sc_lock); 1873 } 1874 } 1875 1876 integrate void 1877 com_txsoft(struct com_softc *sc, struct tty *tp) 1878 { 1879 1880 CLR(tp->t_state, TS_BUSY); 1881 if (ISSET(tp->t_state, TS_FLUSH)) 1882 CLR(tp->t_state, TS_FLUSH); 1883 else 1884 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1885 (*tp->t_linesw->l_start)(tp); 1886 } 1887 1888 integrate void 1889 com_stsoft(struct com_softc *sc, struct tty *tp) 1890 { 1891 u_char msr, delta; 1892 1893 mutex_spin_enter(&sc->sc_lock); 1894 msr = sc->sc_msr; 1895 delta = sc->sc_msr_delta; 1896 sc->sc_msr_delta = 0; 1897 mutex_spin_exit(&sc->sc_lock); 1898 1899 if (ISSET(delta, sc->sc_msr_dcd)) { 1900 /* 1901 * Inform the tty layer that carrier detect changed. 1902 */ 1903 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1904 } 1905 1906 if (ISSET(delta, sc->sc_msr_cts)) { 1907 /* Block or unblock output according to flow control. */ 1908 if (ISSET(msr, sc->sc_msr_cts)) { 1909 sc->sc_tx_stopped = 0; 1910 (*tp->t_linesw->l_start)(tp); 1911 } else { 1912 sc->sc_tx_stopped = 1; 1913 } 1914 } 1915 1916 #ifdef COM_DEBUG 1917 if (com_debug) 1918 comstatus(sc, "com_stsoft"); 1919 #endif 1920 } 1921 1922 void 1923 comsoft(void *arg) 1924 { 1925 struct com_softc *sc = arg; 1926 struct tty *tp; 1927 1928 if (COM_ISALIVE(sc) == 0) 1929 return; 1930 1931 tp = sc->sc_tty; 1932 1933 if (sc->sc_rx_ready) { 1934 sc->sc_rx_ready = 0; 1935 com_rxsoft(sc, tp); 1936 } 1937 1938 if (sc->sc_st_check) { 1939 sc->sc_st_check = 0; 1940 com_stsoft(sc, tp); 1941 } 1942 1943 if (sc->sc_tx_done) { 1944 sc->sc_tx_done = 0; 1945 com_txsoft(sc, tp); 1946 } 1947 } 1948 1949 int 1950 comintr(void *arg) 1951 { 1952 struct com_softc *sc = arg; 1953 struct com_regs *regsp = &sc->sc_regs; 1954 1955 u_char *put, *end; 1956 u_int cc; 1957 u_char lsr, iir; 1958 1959 if (COM_ISALIVE(sc) == 0) 1960 return (0); 1961 1962 KASSERT(regsp != NULL); 1963 1964 mutex_spin_enter(&sc->sc_lock); 1965 iir = CSR_READ_1(regsp, COM_REG_IIR); 1966 1967 /* Handle ns16750-specific busy interrupt. */ 1968 #ifdef COM_16750 1969 int timeout; 1970 if ((iir & IIR_BUSY) == IIR_BUSY) { 1971 for (timeout = 10000; 1972 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 1973 if (timeout <= 0) { 1974 aprint_error_dev(sc->sc_dev, 1975 "timeout while waiting for BUSY interrupt " 1976 "acknowledge\n"); 1977 mutex_spin_exit(&sc->sc_lock); 1978 return (0); 1979 } 1980 1981 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1982 iir = CSR_READ_1(regsp, COM_REG_IIR); 1983 } 1984 #endif /* COM_16750 */ 1985 1986 1987 if (ISSET(iir, IIR_NOPEND)) { 1988 mutex_spin_exit(&sc->sc_lock); 1989 return (0); 1990 } 1991 1992 end = sc->sc_ebuf; 1993 put = sc->sc_rbput; 1994 cc = sc->sc_rbavail; 1995 1996 again: do { 1997 u_char msr, delta; 1998 1999 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2000 if (ISSET(lsr, LSR_BI)) { 2001 int cn_trapped = 0; /* see above: cn_trap() */ 2002 2003 cn_check_magic(sc->sc_tty->t_dev, 2004 CNC_BREAK, com_cnm_state); 2005 if (cn_trapped) 2006 continue; 2007 #if defined(KGDB) && !defined(DDB) 2008 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2009 kgdb_connect(1); 2010 continue; 2011 } 2012 #endif 2013 } 2014 2015 if (ISSET(lsr, LSR_RCV_MASK) && 2016 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2017 while (cc > 0) { 2018 int cn_trapped = 0; 2019 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2020 put[1] = lsr; 2021 cn_check_magic(sc->sc_tty->t_dev, 2022 put[0], com_cnm_state); 2023 if (cn_trapped) 2024 goto next; 2025 put += 2; 2026 if (put >= end) 2027 put = sc->sc_rbuf; 2028 cc--; 2029 next: 2030 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2031 if (!ISSET(lsr, LSR_RCV_MASK)) 2032 break; 2033 } 2034 2035 /* 2036 * Current string of incoming characters ended because 2037 * no more data was available or we ran out of space. 2038 * Schedule a receive event if any data was received. 2039 * If we're out of space, turn off receive interrupts. 2040 */ 2041 sc->sc_rbput = put; 2042 sc->sc_rbavail = cc; 2043 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2044 sc->sc_rx_ready = 1; 2045 2046 /* 2047 * See if we are in danger of overflowing a buffer. If 2048 * so, use hardware flow control to ease the pressure. 2049 */ 2050 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2051 cc < sc->sc_r_hiwat) { 2052 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2053 com_hwiflow(sc); 2054 } 2055 2056 /* 2057 * If we're out of space, disable receive interrupts 2058 * until the queue has drained a bit. 2059 */ 2060 if (!cc) { 2061 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2062 #ifdef COM_PXA2X0 2063 if (sc->sc_type == COM_TYPE_PXA2x0) 2064 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2065 else 2066 #endif 2067 CLR(sc->sc_ier, IER_ERXRDY); 2068 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2069 } 2070 } else { 2071 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2072 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2073 continue; 2074 } 2075 } 2076 2077 msr = CSR_READ_1(regsp, COM_REG_MSR); 2078 delta = msr ^ sc->sc_msr; 2079 sc->sc_msr = msr; 2080 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2081 (delta & MSR_DCD)) { 2082 mutex_spin_enter(&timecounter_lock); 2083 pps_capture(&sc->sc_pps_state); 2084 pps_event(&sc->sc_pps_state, 2085 (msr & MSR_DCD) ? 2086 PPS_CAPTUREASSERT : 2087 PPS_CAPTURECLEAR); 2088 mutex_spin_exit(&timecounter_lock); 2089 } 2090 2091 /* 2092 * Process normal status changes 2093 */ 2094 if (ISSET(delta, sc->sc_msr_mask)) { 2095 SET(sc->sc_msr_delta, delta); 2096 2097 /* 2098 * Stop output immediately if we lose the output 2099 * flow control signal or carrier detect. 2100 */ 2101 if (ISSET(~msr, sc->sc_msr_mask)) { 2102 sc->sc_tbc = 0; 2103 sc->sc_heldtbc = 0; 2104 #ifdef COM_DEBUG 2105 if (com_debug) 2106 comstatus(sc, "comintr "); 2107 #endif 2108 } 2109 2110 sc->sc_st_check = 1; 2111 } 2112 } while (!ISSET((iir = 2113 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2114 /* 2115 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2116 * by IIR read, so we can't do this way: `process all interrupts, 2117 * then do TX if possible'. 2118 */ 2119 (iir & IIR_IMASK) != IIR_TXRDY); 2120 2121 /* 2122 * Read LSR again, since there may be an interrupt between 2123 * the last LSR read and IIR read above. 2124 */ 2125 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2126 2127 /* 2128 * See if data can be transmitted as well. 2129 * Schedule tx done event if no data left 2130 * and tty was marked busy. 2131 */ 2132 if (ISSET(lsr, LSR_TXRDY)) { 2133 /* 2134 * If we've delayed a parameter change, do it now, and restart 2135 * output. 2136 */ 2137 if (sc->sc_heldchange) { 2138 com_loadchannelregs(sc); 2139 sc->sc_heldchange = 0; 2140 sc->sc_tbc = sc->sc_heldtbc; 2141 sc->sc_heldtbc = 0; 2142 } 2143 2144 /* Output the next chunk of the contiguous buffer, if any. */ 2145 if (sc->sc_tbc > 0) { 2146 u_int n; 2147 2148 n = sc->sc_tbc; 2149 if (n > sc->sc_fifolen) 2150 n = sc->sc_fifolen; 2151 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2152 sc->sc_tbc -= n; 2153 sc->sc_tba += n; 2154 } else { 2155 /* Disable transmit completion interrupts if necessary. */ 2156 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2157 CLR(sc->sc_ier, IER_ETXRDY); 2158 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2159 } 2160 if (sc->sc_tx_busy) { 2161 sc->sc_tx_busy = 0; 2162 sc->sc_tx_done = 1; 2163 } 2164 } 2165 } 2166 2167 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2168 goto again; 2169 2170 mutex_spin_exit(&sc->sc_lock); 2171 2172 /* Wake up the poller. */ 2173 softint_schedule(sc->sc_si); 2174 2175 #ifdef RND_COM 2176 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2177 #endif 2178 2179 return (1); 2180 } 2181 2182 /* 2183 * The following functions are polled getc and putc routines, shared 2184 * by the console and kgdb glue. 2185 * 2186 * The read-ahead code is so that you can detect pending in-band 2187 * cn_magic in polled mode while doing output rather than having to 2188 * wait until the kernel decides it needs input. 2189 */ 2190 2191 #define MAX_READAHEAD 20 2192 static int com_readahead[MAX_READAHEAD]; 2193 static int com_readaheadcount = 0; 2194 2195 int 2196 com_common_getc(dev_t dev, struct com_regs *regsp) 2197 { 2198 int s = splserial(); 2199 u_char stat, c; 2200 2201 /* got a character from reading things earlier */ 2202 if (com_readaheadcount > 0) { 2203 int i; 2204 2205 c = com_readahead[0]; 2206 for (i = 1; i < com_readaheadcount; i++) { 2207 com_readahead[i-1] = com_readahead[i]; 2208 } 2209 com_readaheadcount--; 2210 splx(s); 2211 return (c); 2212 } 2213 2214 /* block until a character becomes available */ 2215 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2216 ; 2217 2218 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2219 stat = CSR_READ_1(regsp, COM_REG_IIR); 2220 { 2221 int cn_trapped = 0; /* required by cn_trap, see above */ 2222 #ifdef DDB 2223 extern int db_active; 2224 if (!db_active) 2225 #endif 2226 cn_check_magic(dev, c, com_cnm_state); 2227 } 2228 splx(s); 2229 return (c); 2230 } 2231 2232 static void 2233 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2234 { 2235 int s = splserial(); 2236 int cin, stat, timo; 2237 2238 if (com_readaheadcount < MAX_READAHEAD 2239 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2240 int cn_trapped = 0; 2241 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2242 stat = CSR_READ_1(regsp, COM_REG_IIR); 2243 cn_check_magic(dev, cin, com_cnm_state); 2244 com_readahead[com_readaheadcount++] = cin; 2245 } 2246 2247 /* wait for any pending transmission to finish */ 2248 timo = 150000; 2249 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2250 continue; 2251 2252 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2253 COM_BARRIER(regsp, BR | BW); 2254 2255 splx(s); 2256 } 2257 2258 /* 2259 * Initialize UART for use as console or KGDB line. 2260 */ 2261 int 2262 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2263 tcflag_t cflag) 2264 { 2265 2266 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2267 ®sp->cr_ioh)) 2268 return (ENOMEM); /* ??? */ 2269 2270 if (type == COM_TYPE_OMAP) { 2271 /* disable before changing settings */ 2272 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2273 } 2274 2275 rate = comspeed(rate, frequency, type); 2276 if (__predict_true(rate != -1)) { 2277 if (type == COM_TYPE_AU1x00) { 2278 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2279 } else { 2280 /* no EFR on alchemy */ 2281 if (type != COM_TYPE_16550_NOERS) { 2282 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2283 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2284 } 2285 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2286 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2287 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2288 } 2289 } 2290 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2291 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2292 CSR_WRITE_1(regsp, COM_REG_FIFO, 2293 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2294 2295 if (type == COM_TYPE_OMAP) { 2296 /* setup the fifos. the FCR value is not used as long 2297 as SCR[6] and SCR[7] are 0, which they are at reset 2298 and we never touch the SCR register */ 2299 uint8_t rx_fifo_trig = 40; 2300 uint8_t tx_fifo_trig = 60; 2301 uint8_t rx_start = 8; 2302 uint8_t rx_halt = 60; 2303 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2304 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2305 2306 /* enable access to TCR & TLR */ 2307 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2308 2309 /* write tcr and tlr values */ 2310 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2311 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2312 2313 /* disable access to TCR & TLR */ 2314 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2315 2316 /* enable again, but mode is based on speed */ 2317 if (rate > 230400) { 2318 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2319 } else { 2320 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2321 } 2322 } 2323 2324 #ifdef COM_PXA2X0 2325 if (type == COM_TYPE_PXA2x0) 2326 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2327 else 2328 #endif 2329 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2330 2331 return (0); 2332 } 2333 2334 int 2335 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2336 tcflag_t cflag) 2337 { 2338 int res; 2339 2340 comcons_info.regs = *regsp; 2341 2342 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2343 if (res) 2344 return (res); 2345 2346 cn_tab = &comcons; 2347 cn_init_magic(&com_cnm_state); 2348 cn_set_magic("\047\001"); /* default magic is BREAK */ 2349 2350 comcons_info.frequency = frequency; 2351 comcons_info.type = type; 2352 comcons_info.rate = rate; 2353 comcons_info.cflag = cflag; 2354 2355 return (0); 2356 } 2357 2358 int 2359 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2360 int type, tcflag_t cflag) 2361 { 2362 struct com_regs regs; 2363 2364 memset(®s, 0, sizeof regs); 2365 regs.cr_iot = iot; 2366 regs.cr_iobase = iobase; 2367 regs.cr_nports = COM_NPORTS; 2368 #ifdef COM_REGMAP 2369 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2370 #endif 2371 2372 return comcnattach1(®s, rate, frequency, type, cflag); 2373 } 2374 2375 static int 2376 comcnreattach(void) 2377 { 2378 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2379 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2380 } 2381 2382 int 2383 comcngetc(dev_t dev) 2384 { 2385 2386 return (com_common_getc(dev, &comcons_info.regs)); 2387 } 2388 2389 /* 2390 * Console kernel output character routine. 2391 */ 2392 void 2393 comcnputc(dev_t dev, int c) 2394 { 2395 2396 com_common_putc(dev, &comcons_info.regs, c); 2397 } 2398 2399 void 2400 comcnpollc(dev_t dev, int on) 2401 { 2402 2403 com_readaheadcount = 0; 2404 } 2405 2406 #ifdef KGDB 2407 int 2408 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2409 tcflag_t cflag) 2410 { 2411 int res; 2412 2413 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2414 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2415 #if !defined(DDB) 2416 return (EBUSY); /* cannot share with console */ 2417 #else 2418 comkgdbregs = *regsp; 2419 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2420 #endif 2421 } else { 2422 comkgdbregs = *regsp; 2423 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2424 if (res) 2425 return (res); 2426 2427 /* 2428 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2429 * expects this to be initialized 2430 */ 2431 cn_init_magic(&com_cnm_state); 2432 cn_set_magic("\047\001"); 2433 } 2434 2435 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2436 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2437 2438 return (0); 2439 } 2440 2441 int 2442 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2443 int frequency, int type, tcflag_t cflag) 2444 { 2445 struct com_regs regs; 2446 2447 regs.cr_iot = iot; 2448 regs.cr_nports = COM_NPORTS; 2449 regs.cr_iobase = iobase; 2450 #ifdef COM_REGMAP 2451 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2452 #endif 2453 2454 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2455 } 2456 2457 /* ARGSUSED */ 2458 int 2459 com_kgdb_getc(void *arg) 2460 { 2461 2462 return (com_common_getc(NODEV, &comkgdbregs)); 2463 } 2464 2465 /* ARGSUSED */ 2466 void 2467 com_kgdb_putc(void *arg, int c) 2468 { 2469 2470 com_common_putc(NODEV, &comkgdbregs, c); 2471 } 2472 #endif /* KGDB */ 2473 2474 /* helper function to identify the com ports used by 2475 console or KGDB (and not yet autoconf attached) */ 2476 int 2477 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2478 { 2479 bus_space_handle_t help; 2480 2481 if (!comconsattached && 2482 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2483 iobase == comcons_info.regs.cr_iobase) 2484 help = comcons_info.regs.cr_ioh; 2485 #ifdef KGDB 2486 else if (!com_kgdb_attached && 2487 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2488 iobase == comkgdbregs.cr_iobase) 2489 help = comkgdbregs.cr_ioh; 2490 #endif 2491 else 2492 return (0); 2493 2494 if (ioh) 2495 *ioh = help; 2496 return (1); 2497 } 2498 2499 /* 2500 * this routine exists to serve as a shutdown hook for systems that 2501 * have firmware which doesn't interact properly with a com device in 2502 * FIFO mode. 2503 */ 2504 bool 2505 com_cleanup(device_t self, int how) 2506 { 2507 struct com_softc *sc = device_private(self); 2508 2509 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2510 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2511 2512 return true; 2513 } 2514 2515 bool 2516 com_suspend(device_t self, const pmf_qual_t *qual) 2517 { 2518 struct com_softc *sc = device_private(self); 2519 2520 #if 0 2521 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2522 cn_tab = &comcons_suspend; 2523 #endif 2524 2525 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2526 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2527 2528 return true; 2529 } 2530 2531 bool 2532 com_resume(device_t self, const pmf_qual_t *qual) 2533 { 2534 struct com_softc *sc = device_private(self); 2535 2536 mutex_spin_enter(&sc->sc_lock); 2537 com_loadchannelregs(sc); 2538 mutex_spin_exit(&sc->sc_lock); 2539 2540 return true; 2541 } 2542
Indexes created Fri Sep 26 20:09:58 GMT 2025