com.c revision 1.319
1 /* $NetBSD: com.c,v 1.319 2013/12/15 15:55:39 mbalmer Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.319 2013/12/15 15:55:39 mbalmer Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 (void)cn_trapped; \ 96 } while (/* CONSTCOND */ 0) 97 98 #include <sys/param.h> 99 #include <sys/systm.h> 100 #include <sys/ioctl.h> 101 #include <sys/select.h> 102 #include <sys/poll.h> 103 #include <sys/tty.h> 104 #include <sys/proc.h> 105 #include <sys/conf.h> 106 #include <sys/file.h> 107 #include <sys/uio.h> 108 #include <sys/kernel.h> 109 #include <sys/syslog.h> 110 #include <sys/device.h> 111 #include <sys/malloc.h> 112 #include <sys/timepps.h> 113 #include <sys/vnode.h> 114 #include <sys/kauth.h> 115 #include <sys/intr.h> 116 #ifdef RND_COM 117 #include <sys/rnd.h> 118 #endif 119 120 121 #include <sys/bus.h> 122 123 #include <dev/ic/comreg.h> 124 #include <dev/ic/comvar.h> 125 #include <dev/ic/ns16550reg.h> 126 #include <dev/ic/st16650reg.h> 127 #ifdef COM_HAYESP 128 #include <dev/ic/hayespreg.h> 129 #endif 130 #define com_lcr com_cfcr 131 #include <dev/cons.h> 132 133 #ifdef COM_REGMAP 134 #define CSR_WRITE_1(r, o, v) \ 135 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 136 #define CSR_READ_1(r, o) \ 137 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 138 #define CSR_WRITE_2(r, o, v) \ 139 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 140 #define CSR_READ_2(r, o) \ 141 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 142 #define CSR_WRITE_MULTI(r, o, p, n) \ 143 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 144 #else 145 #define CSR_WRITE_1(r, o, v) \ 146 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 147 #define CSR_READ_1(r, o) \ 148 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 149 #define CSR_WRITE_2(r, o, v) \ 150 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 151 #define CSR_READ_2(r, o) \ 152 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 153 #define CSR_WRITE_MULTI(r, o, p, n) \ 154 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 155 #endif 156 157 158 static void com_enable_debugport(struct com_softc *); 159 160 void com_config(struct com_softc *); 161 void com_shutdown(struct com_softc *); 162 int comspeed(long, long, int); 163 static u_char cflag2lcr(tcflag_t); 164 int comparam(struct tty *, struct termios *); 165 void comstart(struct tty *); 166 int comhwiflow(struct tty *, int); 167 168 void com_loadchannelregs(struct com_softc *); 169 void com_hwiflow(struct com_softc *); 170 void com_break(struct com_softc *, int); 171 void com_modem(struct com_softc *, int); 172 void tiocm_to_com(struct com_softc *, u_long, int); 173 int com_to_tiocm(struct com_softc *); 174 void com_iflush(struct com_softc *); 175 176 int com_common_getc(dev_t, struct com_regs *); 177 static void com_common_putc(dev_t, struct com_regs *, int); 178 179 int cominit(struct com_regs *, int, int, int, tcflag_t); 180 181 static int comcnreattach(void); 182 183 int comcngetc(dev_t); 184 void comcnputc(dev_t, int); 185 void comcnpollc(dev_t, int); 186 187 #define integrate static inline 188 void comsoft(void *); 189 integrate void com_rxsoft(struct com_softc *, struct tty *); 190 integrate void com_txsoft(struct com_softc *, struct tty *); 191 integrate void com_stsoft(struct com_softc *, struct tty *); 192 integrate void com_schedrx(struct com_softc *); 193 void comdiag(void *); 194 195 extern struct cfdriver com_cd; 196 197 dev_type_open(comopen); 198 dev_type_close(comclose); 199 dev_type_read(comread); 200 dev_type_write(comwrite); 201 dev_type_ioctl(comioctl); 202 dev_type_stop(comstop); 203 dev_type_tty(comtty); 204 dev_type_poll(compoll); 205 206 static struct comcons_info comcons_info; 207 208 /* 209 * Following are all routines needed for COM to act as console 210 */ 211 static struct consdev comcons = { 212 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 213 NODEV, CN_NORMAL 214 }; 215 216 217 const struct cdevsw com_cdevsw = { 218 comopen, comclose, comread, comwrite, comioctl, 219 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY 220 }; 221 222 /* 223 * Make this an option variable one can patch. 224 * But be warned: this must be a power of 2! 225 */ 226 u_int com_rbuf_size = COM_RING_SIZE; 227 228 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 229 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 230 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 231 232 static int comconsattached; 233 static struct cnm_state com_cnm_state; 234 235 #ifdef KGDB 236 #include <sys/kgdb.h> 237 238 static struct com_regs comkgdbregs; 239 static int com_kgdb_attached; 240 241 int com_kgdb_getc(void *); 242 void com_kgdb_putc(void *, int); 243 #endif /* KGDB */ 244 245 #ifdef COM_REGMAP 246 /* initializer for typical 16550-ish hardware */ 247 #define COM_REG_16550 { \ 248 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 249 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 250 /* 16750-specific register set, additional UART status register */ 251 #define COM_REG_16750 { \ 252 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 253 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 254 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } 255 256 #ifdef COM_16750 257 const bus_size_t com_std_map[32] = COM_REG_16750; 258 #else 259 const bus_size_t com_std_map[16] = COM_REG_16550; 260 #endif /* COM_16750 */ 261 #endif /* COM_REGMAP */ 262 263 #define COMUNIT_MASK 0x7ffff 264 #define COMDIALOUT_MASK 0x80000 265 266 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 267 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 268 269 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 270 device_is_active((sc)->sc_dev)) 271 272 #define BR BUS_SPACE_BARRIER_READ 273 #define BW BUS_SPACE_BARRIER_WRITE 274 #define COM_BARRIER(r, f) \ 275 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 276 277 /*ARGSUSED*/ 278 int 279 comspeed(long speed, long frequency, int type) 280 { 281 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 282 283 int x, err; 284 int divisor = 16; 285 286 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 287 divisor = 13; 288 } 289 290 #if 0 291 if (speed == 0) 292 return (0); 293 #endif 294 if (speed <= 0) 295 return (-1); 296 x = divrnd(frequency / divisor, speed); 297 if (x <= 0) 298 return (-1); 299 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 300 if (err < 0) 301 err = -err; 302 if (err > COM_TOLERANCE) 303 return (-1); 304 return (x); 305 306 #undef divrnd 307 } 308 309 #ifdef COM_DEBUG 310 int com_debug = 0; 311 312 void comstatus(struct com_softc *, const char *); 313 void 314 comstatus(struct com_softc *sc, const char *str) 315 { 316 struct tty *tp = sc->sc_tty; 317 318 aprint_normal_dev(sc->sc_dev, 319 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 320 str, 321 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 322 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 323 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 324 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 325 sc->sc_tx_stopped ? '+' : '-'); 326 327 aprint_normal_dev(sc->sc_dev, 328 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 329 str, 330 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 331 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 332 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 333 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 334 sc->sc_rx_flags); 335 } 336 #endif 337 338 int 339 com_probe_subr(struct com_regs *regs) 340 { 341 342 /* force access to id reg */ 343 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 344 CSR_WRITE_1(regs, COM_REG_IIR, 0); 345 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 346 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 347 return (0); 348 349 return (1); 350 } 351 352 int 353 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 354 { 355 struct com_regs regs; 356 357 regs.cr_iot = iot; 358 regs.cr_ioh = ioh; 359 #ifdef COM_REGMAP 360 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 361 #endif 362 363 return com_probe_subr(®s); 364 } 365 366 /* 367 * No locking in this routine; it is only called during attach, 368 * or with the port already locked. 369 */ 370 static void 371 com_enable_debugport(struct com_softc *sc) 372 { 373 374 /* Turn on line break interrupt, set carrier. */ 375 sc->sc_ier = IER_ERXRDY; 376 if (sc->sc_type == COM_TYPE_PXA2x0) 377 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 378 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 379 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 380 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 381 } 382 383 void 384 com_attach_subr(struct com_softc *sc) 385 { 386 struct com_regs *regsp = &sc->sc_regs; 387 struct tty *tp; 388 #ifdef COM_16650 389 u_int8_t lcr; 390 #endif 391 const char *fifo_msg = NULL; 392 prop_dictionary_t dict; 393 bool is_console = true; 394 395 aprint_naive("\n"); 396 397 dict = device_properties(sc->sc_dev); 398 prop_dictionary_get_bool(dict, "is_console", &is_console); 399 400 callout_init(&sc->sc_diag_callout, 0); 401 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 402 403 /* Disable interrupts before configuring the device. */ 404 if (sc->sc_type == COM_TYPE_PXA2x0) 405 sc->sc_ier = IER_EUART; 406 else 407 sc->sc_ier = 0; 408 409 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 410 411 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 412 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 413 comconsattached = 1; 414 415 if (cn_tab == NULL && comcnreattach() != 0) { 416 printf("can't re-init serial console @%lx\n", 417 (u_long)comcons_info.regs.cr_iobase); 418 } 419 420 #ifdef COM_16750 421 /* Use in comintr(). */ 422 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 423 #endif 424 425 /* Make sure the console is always "hardwired". */ 426 delay(10000); /* wait for output to finish */ 427 if (is_console) { 428 SET(sc->sc_hwflags, COM_HW_CONSOLE); 429 } 430 431 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 432 } 433 434 /* Probe for FIFO */ 435 switch (sc->sc_type) { 436 case COM_TYPE_HAYESP: 437 goto fifodone; 438 439 case COM_TYPE_AU1x00: 440 sc->sc_fifolen = 16; 441 fifo_msg = "Au1X00 UART, working fifo"; 442 SET(sc->sc_hwflags, COM_HW_FIFO); 443 goto fifodelay; 444 445 case COM_TYPE_16550_NOERS: 446 sc->sc_fifolen = 16; 447 fifo_msg = "ns16650, no ERS, working fifo"; 448 SET(sc->sc_hwflags, COM_HW_FIFO); 449 goto fifodelay; 450 451 case COM_TYPE_OMAP: 452 sc->sc_fifolen = 64; 453 fifo_msg = "OMAP UART, working fifo"; 454 SET(sc->sc_hwflags, COM_HW_FIFO); 455 goto fifodelay; 456 } 457 458 sc->sc_fifolen = 1; 459 /* look for a NS 16550AF UART with FIFOs */ 460 CSR_WRITE_1(regsp, COM_REG_FIFO, 461 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 462 delay(100); 463 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 464 == IIR_FIFO_MASK) 465 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 466 == FIFO_TRIGGER_14) { 467 SET(sc->sc_hwflags, COM_HW_FIFO); 468 469 #ifdef COM_16650 470 /* 471 * IIR changes into the EFR if LCR is set to LCR_EERS 472 * on 16650s. We also know IIR != 0 at this point. 473 * Write 0 into the EFR, and read it. If the result 474 * is 0, we have a 16650. 475 * 476 * Older 16650s were broken; the test to detect them 477 * is taken from the Linux driver. Apparently 478 * setting DLAB enable gives access to the EFR on 479 * these chips. 480 */ 481 lcr = CSR_READ_1(regsp, COM_REG_LCR); 482 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 483 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 484 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 485 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 486 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 487 CLR(sc->sc_hwflags, COM_HW_FIFO); 488 sc->sc_fifolen = 0; 489 } else { 490 SET(sc->sc_hwflags, COM_HW_FLOW); 491 sc->sc_fifolen = 32; 492 } 493 } else 494 #endif 495 sc->sc_fifolen = 16; 496 497 #ifdef COM_16750 498 /* 499 * TL16C750 can enable 64byte FIFO, only when DLAB 500 * is 1. However, some 16750 may always enable. For 501 * example, restrictions according to DLAB in a data 502 * sheet for SC16C750 were not described. 503 * Please enable 'options COM_16650', supposing you 504 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 505 * should become effective. 506 */ 507 uint8_t iir1, iir2; 508 const uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 509 510 lcr = CSR_READ_1(regsp, COM_REG_LCR); 511 CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB); 512 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 513 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 514 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 515 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 516 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 517 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 518 519 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 520 521 if (!ISSET(iir1, IIR_64B_FIFO) && 522 ISSET(iir2, IIR_64B_FIFO)) { 523 /* It is TL16C750. */ 524 sc->sc_fifolen = 64; 525 SET(sc->sc_hwflags, COM_HW_AFE); 526 } else 527 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 528 #endif 529 530 #ifdef COM_16650 531 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 532 if (sc->sc_fifolen == 0) 533 fifo_msg = "st16650, broken fifo"; 534 else if (sc->sc_fifolen == 32) 535 fifo_msg = "st16650a, working fifo"; 536 else 537 #endif 538 #ifdef COM_16750 539 if (sc->sc_fifolen == 64) 540 fifo_msg = "tl16c750, working fifo"; 541 else 542 #endif 543 fifo_msg = "ns16550a, working fifo"; 544 } else 545 fifo_msg = "ns16550, broken fifo"; 546 else 547 fifo_msg = "ns8250 or ns16450, no fifo"; 548 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 549 fifodelay: 550 /* 551 * Some chips will clear down both Tx and Rx FIFOs when zero is 552 * written to com_fifo. If this chip is the console, writing zero 553 * results in some of the chip/FIFO description being lost, so delay 554 * printing it until now. 555 */ 556 delay(10); 557 aprint_normal(": %s\n", fifo_msg); 558 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 559 sc->sc_fifolen = 1; 560 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 561 } 562 563 fifodone: 564 565 tp = tty_alloc(); 566 tp->t_oproc = comstart; 567 tp->t_param = comparam; 568 tp->t_hwiflow = comhwiflow; 569 tp->t_softc = sc; 570 571 sc->sc_tty = tp; 572 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 573 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 574 sc->sc_rbavail = com_rbuf_size; 575 if (sc->sc_rbuf == NULL) { 576 aprint_error_dev(sc->sc_dev, 577 "unable to allocate ring buffer\n"); 578 return; 579 } 580 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 581 582 tty_attach(tp); 583 584 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 585 SET(sc->sc_mcr, MCR_IENABLE); 586 587 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 588 int maj; 589 590 /* locate the major number */ 591 maj = cdevsw_lookup_major(&com_cdevsw); 592 593 tp->t_dev = cn_tab->cn_dev = makedev(maj, 594 device_unit(sc->sc_dev)); 595 596 aprint_normal_dev(sc->sc_dev, "console\n"); 597 } 598 599 #ifdef KGDB 600 /* 601 * Allow kgdb to "take over" this port. If this is 602 * not the console and is the kgdb device, it has 603 * exclusive use. If it's the console _and_ the 604 * kgdb device, it doesn't. 605 */ 606 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 607 regsp->cr_iobase == comkgdbregs.cr_iobase) { 608 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 609 com_kgdb_attached = 1; 610 611 SET(sc->sc_hwflags, COM_HW_KGDB); 612 } 613 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 614 } 615 #endif 616 617 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 618 619 #ifdef RND_COM 620 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 621 RND_TYPE_TTY, 0); 622 #endif 623 624 /* if there are no enable/disable functions, assume the device 625 is always enabled */ 626 if (!sc->enable) 627 sc->enabled = 1; 628 629 com_config(sc); 630 631 SET(sc->sc_hwflags, COM_HW_DEV_OK); 632 } 633 634 void 635 com_config(struct com_softc *sc) 636 { 637 struct com_regs *regsp = &sc->sc_regs; 638 639 /* Disable interrupts before configuring the device. */ 640 if (sc->sc_type == COM_TYPE_PXA2x0) 641 sc->sc_ier = IER_EUART; 642 else 643 sc->sc_ier = 0; 644 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 645 (void) CSR_READ_1(regsp, COM_REG_IIR); 646 647 #ifdef COM_HAYESP 648 /* Look for a Hayes ESP board. */ 649 if (sc->sc_type == COM_TYPE_HAYESP) { 650 651 /* Set 16550 compatibility mode */ 652 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 653 HAYESP_SETMODE); 654 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 655 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 656 HAYESP_MODE_SCALE); 657 658 /* Set RTS/CTS flow control */ 659 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 660 HAYESP_SETFLOWTYPE); 661 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 662 HAYESP_FLOW_RTS); 663 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 664 HAYESP_FLOW_CTS); 665 666 /* Set flow control levels */ 667 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 668 HAYESP_SETRXFLOW); 669 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 670 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 671 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 672 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 673 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 674 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 675 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 676 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 677 } 678 #endif 679 680 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 681 com_enable_debugport(sc); 682 } 683 684 #if 0 685 static int 686 comcngetc_detached(dev_t dev) 687 { 688 return 0; 689 } 690 691 static void 692 comcnputc_detached(dev_t dev, int c) 693 { 694 } 695 #endif 696 697 int 698 com_detach(device_t self, int flags) 699 { 700 struct com_softc *sc = device_private(self); 701 int maj, mn; 702 703 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 704 return EBUSY; 705 706 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 707 (flags & DETACH_SHUTDOWN) != 0) 708 return EBUSY; 709 710 if (sc->disable != NULL && sc->enabled != 0) { 711 (*sc->disable)(sc); 712 sc->enabled = 0; 713 } 714 715 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 716 comconsattached = 0; 717 cn_tab = NULL; 718 } 719 720 /* locate the major number */ 721 maj = cdevsw_lookup_major(&com_cdevsw); 722 723 /* Nuke the vnodes for any open instances. */ 724 mn = device_unit(self); 725 vdevgone(maj, mn, mn, VCHR); 726 727 mn |= COMDIALOUT_MASK; 728 vdevgone(maj, mn, mn, VCHR); 729 730 if (sc->sc_rbuf == NULL) { 731 /* 732 * Ring buffer allocation failed in the com_attach_subr, 733 * only the tty is allocated, and nothing else. 734 */ 735 tty_free(sc->sc_tty); 736 return 0; 737 } 738 739 /* Free the receive buffer. */ 740 free(sc->sc_rbuf, M_DEVBUF); 741 742 /* Detach and free the tty. */ 743 tty_detach(sc->sc_tty); 744 tty_free(sc->sc_tty); 745 746 /* Unhook the soft interrupt handler. */ 747 softint_disestablish(sc->sc_si); 748 749 #ifdef RND_COM 750 /* Unhook the entropy source. */ 751 rnd_detach_source(&sc->rnd_source); 752 #endif 753 callout_destroy(&sc->sc_diag_callout); 754 755 /* Destroy the lock. */ 756 mutex_destroy(&sc->sc_lock); 757 758 return (0); 759 } 760 761 void 762 com_shutdown(struct com_softc *sc) 763 { 764 struct tty *tp = sc->sc_tty; 765 766 mutex_spin_enter(&sc->sc_lock); 767 768 /* If we were asserting flow control, then deassert it. */ 769 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 770 com_hwiflow(sc); 771 772 /* Clear any break condition set with TIOCSBRK. */ 773 com_break(sc, 0); 774 775 /* 776 * Hang up if necessary. Wait a bit, so the other side has time to 777 * notice even if we immediately open the port again. 778 * Avoid tsleeping above splhigh(). 779 */ 780 if (ISSET(tp->t_cflag, HUPCL)) { 781 com_modem(sc, 0); 782 mutex_spin_exit(&sc->sc_lock); 783 /* XXX will only timeout */ 784 (void) kpause(ttclos, false, hz, NULL); 785 mutex_spin_enter(&sc->sc_lock); 786 } 787 788 /* Turn off interrupts. */ 789 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 790 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 791 if (sc->sc_type == COM_TYPE_PXA2x0) 792 sc->sc_ier |= IER_ERXTOUT; 793 } else 794 sc->sc_ier = 0; 795 796 if (sc->sc_type == COM_TYPE_PXA2x0) 797 sc->sc_ier |= IER_EUART; 798 799 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 800 801 mutex_spin_exit(&sc->sc_lock); 802 803 if (sc->disable) { 804 #ifdef DIAGNOSTIC 805 if (!sc->enabled) 806 panic("com_shutdown: not enabled?"); 807 #endif 808 (*sc->disable)(sc); 809 sc->enabled = 0; 810 } 811 } 812 813 int 814 comopen(dev_t dev, int flag, int mode, struct lwp *l) 815 { 816 struct com_softc *sc; 817 struct tty *tp; 818 int s; 819 int error; 820 821 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 822 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 823 sc->sc_rbuf == NULL) 824 return (ENXIO); 825 826 if (!device_is_active(sc->sc_dev)) 827 return (ENXIO); 828 829 #ifdef KGDB 830 /* 831 * If this is the kgdb port, no other use is permitted. 832 */ 833 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 834 return (EBUSY); 835 #endif 836 837 tp = sc->sc_tty; 838 839 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 840 return (EBUSY); 841 842 s = spltty(); 843 844 /* 845 * Do the following iff this is a first open. 846 */ 847 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 848 struct termios t; 849 850 tp->t_dev = dev; 851 852 if (sc->enable) { 853 if ((*sc->enable)(sc)) { 854 splx(s); 855 aprint_error_dev(sc->sc_dev, 856 "device enable failed\n"); 857 return (EIO); 858 } 859 mutex_spin_enter(&sc->sc_lock); 860 sc->enabled = 1; 861 com_config(sc); 862 } else { 863 mutex_spin_enter(&sc->sc_lock); 864 } 865 866 /* Turn on interrupts. */ 867 sc->sc_ier = IER_ERXRDY | IER_ERLS; 868 if (!ISSET(tp->t_cflag, CLOCAL)) 869 sc->sc_ier |= IER_EMSC; 870 871 if (sc->sc_type == COM_TYPE_PXA2x0) 872 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 873 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 874 875 /* Fetch the current modem control status, needed later. */ 876 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 877 878 /* Clear PPS capture state on first open. */ 879 mutex_spin_enter(&timecounter_lock); 880 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 881 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 882 pps_init(&sc->sc_pps_state); 883 mutex_spin_exit(&timecounter_lock); 884 885 mutex_spin_exit(&sc->sc_lock); 886 887 /* 888 * Initialize the termios status to the defaults. Add in the 889 * sticky bits from TIOCSFLAGS. 890 */ 891 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 892 t.c_ospeed = comcons_info.rate; 893 t.c_cflag = comcons_info.cflag; 894 } else { 895 t.c_ospeed = TTYDEF_SPEED; 896 t.c_cflag = TTYDEF_CFLAG; 897 } 898 t.c_ispeed = t.c_ospeed; 899 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 900 SET(t.c_cflag, CLOCAL); 901 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 902 SET(t.c_cflag, CRTSCTS); 903 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 904 SET(t.c_cflag, MDMBUF); 905 /* Make sure comparam() will do something. */ 906 tp->t_ospeed = 0; 907 (void) comparam(tp, &t); 908 tp->t_iflag = TTYDEF_IFLAG; 909 tp->t_oflag = TTYDEF_OFLAG; 910 tp->t_lflag = TTYDEF_LFLAG; 911 ttychars(tp); 912 ttsetwater(tp); 913 914 mutex_spin_enter(&sc->sc_lock); 915 916 /* 917 * Turn on DTR. We must always do this, even if carrier is not 918 * present, because otherwise we'd have to use TIOCSDTR 919 * immediately after setting CLOCAL, which applications do not 920 * expect. We always assert DTR while the device is open 921 * unless explicitly requested to deassert it. 922 */ 923 com_modem(sc, 1); 924 925 /* Clear the input ring, and unblock. */ 926 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 927 sc->sc_rbavail = com_rbuf_size; 928 com_iflush(sc); 929 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 930 com_hwiflow(sc); 931 932 #ifdef COM_DEBUG 933 if (com_debug) 934 comstatus(sc, "comopen "); 935 #endif 936 937 mutex_spin_exit(&sc->sc_lock); 938 } 939 940 splx(s); 941 942 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 943 if (error) 944 goto bad; 945 946 error = (*tp->t_linesw->l_open)(dev, tp); 947 if (error) 948 goto bad; 949 950 return (0); 951 952 bad: 953 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 954 /* 955 * We failed to open the device, and nobody else had it opened. 956 * Clean up the state as appropriate. 957 */ 958 com_shutdown(sc); 959 } 960 961 return (error); 962 } 963 964 int 965 comclose(dev_t dev, int flag, int mode, struct lwp *l) 966 { 967 struct com_softc *sc = 968 device_lookup_private(&com_cd, COMUNIT(dev)); 969 struct tty *tp = sc->sc_tty; 970 971 /* XXX This is for cons.c. */ 972 if (!ISSET(tp->t_state, TS_ISOPEN)) 973 return (0); 974 975 (*tp->t_linesw->l_close)(tp, flag); 976 ttyclose(tp); 977 978 if (COM_ISALIVE(sc) == 0) 979 return (0); 980 981 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 982 /* 983 * Although we got a last close, the device may still be in 984 * use; e.g. if this was the dialout node, and there are still 985 * processes waiting for carrier on the non-dialout node. 986 */ 987 com_shutdown(sc); 988 } 989 990 return (0); 991 } 992 993 int 994 comread(dev_t dev, struct uio *uio, int flag) 995 { 996 struct com_softc *sc = 997 device_lookup_private(&com_cd, COMUNIT(dev)); 998 struct tty *tp = sc->sc_tty; 999 1000 if (COM_ISALIVE(sc) == 0) 1001 return (EIO); 1002 1003 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1004 } 1005 1006 int 1007 comwrite(dev_t dev, struct uio *uio, int flag) 1008 { 1009 struct com_softc *sc = 1010 device_lookup_private(&com_cd, COMUNIT(dev)); 1011 struct tty *tp = sc->sc_tty; 1012 1013 if (COM_ISALIVE(sc) == 0) 1014 return (EIO); 1015 1016 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1017 } 1018 1019 int 1020 compoll(dev_t dev, int events, struct lwp *l) 1021 { 1022 struct com_softc *sc = 1023 device_lookup_private(&com_cd, COMUNIT(dev)); 1024 struct tty *tp = sc->sc_tty; 1025 1026 if (COM_ISALIVE(sc) == 0) 1027 return (POLLHUP); 1028 1029 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1030 } 1031 1032 struct tty * 1033 comtty(dev_t dev) 1034 { 1035 struct com_softc *sc = 1036 device_lookup_private(&com_cd, COMUNIT(dev)); 1037 struct tty *tp = sc->sc_tty; 1038 1039 return (tp); 1040 } 1041 1042 int 1043 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1044 { 1045 struct com_softc *sc; 1046 struct tty *tp; 1047 int error; 1048 1049 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1050 if (sc == NULL) 1051 return ENXIO; 1052 if (COM_ISALIVE(sc) == 0) 1053 return (EIO); 1054 1055 tp = sc->sc_tty; 1056 1057 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1058 if (error != EPASSTHROUGH) 1059 return (error); 1060 1061 error = ttioctl(tp, cmd, data, flag, l); 1062 if (error != EPASSTHROUGH) 1063 return (error); 1064 1065 error = 0; 1066 switch (cmd) { 1067 case TIOCSFLAGS: 1068 error = kauth_authorize_device_tty(l->l_cred, 1069 KAUTH_DEVICE_TTY_PRIVSET, tp); 1070 break; 1071 default: 1072 /* nothing */ 1073 break; 1074 } 1075 if (error) { 1076 return error; 1077 } 1078 1079 mutex_spin_enter(&sc->sc_lock); 1080 1081 switch (cmd) { 1082 case TIOCSBRK: 1083 com_break(sc, 1); 1084 break; 1085 1086 case TIOCCBRK: 1087 com_break(sc, 0); 1088 break; 1089 1090 case TIOCSDTR: 1091 com_modem(sc, 1); 1092 break; 1093 1094 case TIOCCDTR: 1095 com_modem(sc, 0); 1096 break; 1097 1098 case TIOCGFLAGS: 1099 *(int *)data = sc->sc_swflags; 1100 break; 1101 1102 case TIOCSFLAGS: 1103 sc->sc_swflags = *(int *)data; 1104 break; 1105 1106 case TIOCMSET: 1107 case TIOCMBIS: 1108 case TIOCMBIC: 1109 tiocm_to_com(sc, cmd, *(int *)data); 1110 break; 1111 1112 case TIOCMGET: 1113 *(int *)data = com_to_tiocm(sc); 1114 break; 1115 1116 case PPS_IOC_CREATE: 1117 case PPS_IOC_DESTROY: 1118 case PPS_IOC_GETPARAMS: 1119 case PPS_IOC_SETPARAMS: 1120 case PPS_IOC_GETCAP: 1121 case PPS_IOC_FETCH: 1122 #ifdef PPS_SYNC 1123 case PPS_IOC_KCBIND: 1124 #endif 1125 mutex_spin_enter(&timecounter_lock); 1126 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1127 mutex_spin_exit(&timecounter_lock); 1128 break; 1129 1130 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1131 mutex_spin_enter(&timecounter_lock); 1132 #ifndef PPS_TRAILING_EDGE 1133 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1134 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1135 #else 1136 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1137 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1138 #endif 1139 mutex_spin_exit(&timecounter_lock); 1140 break; 1141 1142 default: 1143 error = EPASSTHROUGH; 1144 break; 1145 } 1146 1147 mutex_spin_exit(&sc->sc_lock); 1148 1149 #ifdef COM_DEBUG 1150 if (com_debug) 1151 comstatus(sc, "comioctl "); 1152 #endif 1153 1154 return (error); 1155 } 1156 1157 integrate void 1158 com_schedrx(struct com_softc *sc) 1159 { 1160 1161 sc->sc_rx_ready = 1; 1162 1163 /* Wake up the poller. */ 1164 softint_schedule(sc->sc_si); 1165 } 1166 1167 void 1168 com_break(struct com_softc *sc, int onoff) 1169 { 1170 1171 if (onoff) 1172 SET(sc->sc_lcr, LCR_SBREAK); 1173 else 1174 CLR(sc->sc_lcr, LCR_SBREAK); 1175 1176 if (!sc->sc_heldchange) { 1177 if (sc->sc_tx_busy) { 1178 sc->sc_heldtbc = sc->sc_tbc; 1179 sc->sc_tbc = 0; 1180 sc->sc_heldchange = 1; 1181 } else 1182 com_loadchannelregs(sc); 1183 } 1184 } 1185 1186 void 1187 com_modem(struct com_softc *sc, int onoff) 1188 { 1189 1190 if (sc->sc_mcr_dtr == 0) 1191 return; 1192 1193 if (onoff) 1194 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1195 else 1196 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1197 1198 if (!sc->sc_heldchange) { 1199 if (sc->sc_tx_busy) { 1200 sc->sc_heldtbc = sc->sc_tbc; 1201 sc->sc_tbc = 0; 1202 sc->sc_heldchange = 1; 1203 } else 1204 com_loadchannelregs(sc); 1205 } 1206 } 1207 1208 void 1209 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1210 { 1211 u_char combits; 1212 1213 combits = 0; 1214 if (ISSET(ttybits, TIOCM_DTR)) 1215 SET(combits, MCR_DTR); 1216 if (ISSET(ttybits, TIOCM_RTS)) 1217 SET(combits, MCR_RTS); 1218 1219 switch (how) { 1220 case TIOCMBIC: 1221 CLR(sc->sc_mcr, combits); 1222 break; 1223 1224 case TIOCMBIS: 1225 SET(sc->sc_mcr, combits); 1226 break; 1227 1228 case TIOCMSET: 1229 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1230 SET(sc->sc_mcr, combits); 1231 break; 1232 } 1233 1234 if (!sc->sc_heldchange) { 1235 if (sc->sc_tx_busy) { 1236 sc->sc_heldtbc = sc->sc_tbc; 1237 sc->sc_tbc = 0; 1238 sc->sc_heldchange = 1; 1239 } else 1240 com_loadchannelregs(sc); 1241 } 1242 } 1243 1244 int 1245 com_to_tiocm(struct com_softc *sc) 1246 { 1247 u_char combits; 1248 int ttybits = 0; 1249 1250 combits = sc->sc_mcr; 1251 if (ISSET(combits, MCR_DTR)) 1252 SET(ttybits, TIOCM_DTR); 1253 if (ISSET(combits, MCR_RTS)) 1254 SET(ttybits, TIOCM_RTS); 1255 1256 combits = sc->sc_msr; 1257 if (ISSET(combits, MSR_DCD)) 1258 SET(ttybits, TIOCM_CD); 1259 if (ISSET(combits, MSR_CTS)) 1260 SET(ttybits, TIOCM_CTS); 1261 if (ISSET(combits, MSR_DSR)) 1262 SET(ttybits, TIOCM_DSR); 1263 if (ISSET(combits, MSR_RI | MSR_TERI)) 1264 SET(ttybits, TIOCM_RI); 1265 1266 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1267 SET(ttybits, TIOCM_LE); 1268 1269 return (ttybits); 1270 } 1271 1272 static u_char 1273 cflag2lcr(tcflag_t cflag) 1274 { 1275 u_char lcr = 0; 1276 1277 switch (ISSET(cflag, CSIZE)) { 1278 case CS5: 1279 SET(lcr, LCR_5BITS); 1280 break; 1281 case CS6: 1282 SET(lcr, LCR_6BITS); 1283 break; 1284 case CS7: 1285 SET(lcr, LCR_7BITS); 1286 break; 1287 case CS8: 1288 SET(lcr, LCR_8BITS); 1289 break; 1290 } 1291 if (ISSET(cflag, PARENB)) { 1292 SET(lcr, LCR_PENAB); 1293 if (!ISSET(cflag, PARODD)) 1294 SET(lcr, LCR_PEVEN); 1295 } 1296 if (ISSET(cflag, CSTOPB)) 1297 SET(lcr, LCR_STOPB); 1298 1299 return (lcr); 1300 } 1301 1302 int 1303 comparam(struct tty *tp, struct termios *t) 1304 { 1305 struct com_softc *sc = 1306 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1307 int ospeed; 1308 u_char lcr; 1309 1310 if (COM_ISALIVE(sc) == 0) 1311 return (EIO); 1312 1313 #ifdef COM_HAYESP 1314 if (sc->sc_type == COM_TYPE_HAYESP) { 1315 int prescaler, speed; 1316 1317 /* 1318 * Calculate UART clock prescaler. It should be in 1319 * range of 0 .. 3. 1320 */ 1321 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1322 prescaler++, speed /= 2) 1323 if ((ospeed = comspeed(speed, sc->sc_frequency, 1324 sc->sc_type)) > 0) 1325 break; 1326 1327 if (prescaler == 4) 1328 return (EINVAL); 1329 sc->sc_prescaler = prescaler; 1330 } else 1331 #endif 1332 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1333 1334 /* Check requested parameters. */ 1335 if (ospeed < 0) 1336 return (EINVAL); 1337 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1338 return (EINVAL); 1339 1340 /* 1341 * For the console, always force CLOCAL and !HUPCL, so that the port 1342 * is always active. 1343 */ 1344 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1345 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1346 SET(t->c_cflag, CLOCAL); 1347 CLR(t->c_cflag, HUPCL); 1348 } 1349 1350 /* 1351 * If there were no changes, don't do anything. This avoids dropping 1352 * input and improves performance when all we did was frob things like 1353 * VMIN and VTIME. 1354 */ 1355 if (tp->t_ospeed == t->c_ospeed && 1356 tp->t_cflag == t->c_cflag) 1357 return (0); 1358 1359 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1360 1361 mutex_spin_enter(&sc->sc_lock); 1362 1363 sc->sc_lcr = lcr; 1364 1365 /* 1366 * If we're not in a mode that assumes a connection is present, then 1367 * ignore carrier changes. 1368 */ 1369 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1370 sc->sc_msr_dcd = 0; 1371 else 1372 sc->sc_msr_dcd = MSR_DCD; 1373 /* 1374 * Set the flow control pins depending on the current flow control 1375 * mode. 1376 */ 1377 if (ISSET(t->c_cflag, CRTSCTS)) { 1378 sc->sc_mcr_dtr = MCR_DTR; 1379 sc->sc_mcr_rts = MCR_RTS; 1380 sc->sc_msr_cts = MSR_CTS; 1381 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1382 SET(sc->sc_mcr, MCR_AFE); 1383 } else { 1384 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1385 } 1386 } else if (ISSET(t->c_cflag, MDMBUF)) { 1387 /* 1388 * For DTR/DCD flow control, make sure we don't toggle DTR for 1389 * carrier detection. 1390 */ 1391 sc->sc_mcr_dtr = 0; 1392 sc->sc_mcr_rts = MCR_DTR; 1393 sc->sc_msr_cts = MSR_DCD; 1394 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1395 CLR(sc->sc_mcr, MCR_AFE); 1396 } else { 1397 sc->sc_efr = 0; 1398 } 1399 } else { 1400 /* 1401 * If no flow control, then always set RTS. This will make 1402 * the other side happy if it mistakenly thinks we're doing 1403 * RTS/CTS flow control. 1404 */ 1405 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1406 sc->sc_mcr_rts = 0; 1407 sc->sc_msr_cts = 0; 1408 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1409 CLR(sc->sc_mcr, MCR_AFE); 1410 } else { 1411 sc->sc_efr = 0; 1412 } 1413 if (ISSET(sc->sc_mcr, MCR_DTR)) 1414 SET(sc->sc_mcr, MCR_RTS); 1415 else 1416 CLR(sc->sc_mcr, MCR_RTS); 1417 } 1418 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1419 1420 #if 0 1421 if (ospeed == 0) 1422 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1423 else 1424 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1425 #endif 1426 1427 sc->sc_dlbl = ospeed; 1428 sc->sc_dlbh = ospeed >> 8; 1429 1430 /* 1431 * Set the FIFO threshold based on the receive speed. 1432 * 1433 * * If it's a low speed, it's probably a mouse or some other 1434 * interactive device, so set the threshold low. 1435 * * If it's a high speed, trim the trigger level down to prevent 1436 * overflows. 1437 * * Otherwise set it a bit higher. 1438 */ 1439 if (sc->sc_type == COM_TYPE_HAYESP) 1440 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1441 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1442 if (t->c_ospeed <= 1200) 1443 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1444 else if (t->c_ospeed <= 38400) 1445 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1446 else 1447 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1448 } else 1449 sc->sc_fifo = 0; 1450 1451 /* And copy to tty. */ 1452 tp->t_ispeed = t->c_ospeed; 1453 tp->t_ospeed = t->c_ospeed; 1454 tp->t_cflag = t->c_cflag; 1455 1456 if (!sc->sc_heldchange) { 1457 if (sc->sc_tx_busy) { 1458 sc->sc_heldtbc = sc->sc_tbc; 1459 sc->sc_tbc = 0; 1460 sc->sc_heldchange = 1; 1461 } else 1462 com_loadchannelregs(sc); 1463 } 1464 1465 if (!ISSET(t->c_cflag, CHWFLOW)) { 1466 /* Disable the high water mark. */ 1467 sc->sc_r_hiwat = 0; 1468 sc->sc_r_lowat = 0; 1469 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1470 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1471 com_schedrx(sc); 1472 } 1473 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1474 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1475 com_hwiflow(sc); 1476 } 1477 } else { 1478 sc->sc_r_hiwat = com_rbuf_hiwat; 1479 sc->sc_r_lowat = com_rbuf_lowat; 1480 } 1481 1482 mutex_spin_exit(&sc->sc_lock); 1483 1484 /* 1485 * Update the tty layer's idea of the carrier bit, in case we changed 1486 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1487 * explicit request. 1488 */ 1489 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1490 1491 #ifdef COM_DEBUG 1492 if (com_debug) 1493 comstatus(sc, "comparam "); 1494 #endif 1495 1496 if (!ISSET(t->c_cflag, CHWFLOW)) { 1497 if (sc->sc_tx_stopped) { 1498 sc->sc_tx_stopped = 0; 1499 comstart(tp); 1500 } 1501 } 1502 1503 return (0); 1504 } 1505 1506 void 1507 com_iflush(struct com_softc *sc) 1508 { 1509 struct com_regs *regsp = &sc->sc_regs; 1510 #ifdef DIAGNOSTIC 1511 int reg; 1512 #endif 1513 int timo; 1514 1515 #ifdef DIAGNOSTIC 1516 reg = 0xffff; 1517 #endif 1518 timo = 50000; 1519 /* flush any pending I/O */ 1520 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1521 && --timo) 1522 #ifdef DIAGNOSTIC 1523 reg = 1524 #else 1525 (void) 1526 #endif 1527 CSR_READ_1(regsp, COM_REG_RXDATA); 1528 #ifdef DIAGNOSTIC 1529 if (!timo) 1530 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1531 #endif 1532 1533 #ifdef COM_16750 1534 uint8_t fifo; 1535 /* 1536 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1537 * This should prevent triggering busy interrupt while 1538 * manipulating divisors. 1539 */ 1540 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1541 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1542 CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST | 1543 FIFO_XMT_RST); 1544 delay(100); 1545 #endif 1546 } 1547 1548 void 1549 com_loadchannelregs(struct com_softc *sc) 1550 { 1551 struct com_regs *regsp = &sc->sc_regs; 1552 1553 /* XXXXX necessary? */ 1554 com_iflush(sc); 1555 1556 if (sc->sc_type == COM_TYPE_PXA2x0) 1557 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1558 else 1559 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1560 1561 if (sc->sc_type == COM_TYPE_OMAP) { 1562 /* disable before changing settings */ 1563 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1564 } 1565 1566 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1567 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1568 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1569 /* no EFR on alchemy */ 1570 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1571 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1572 } 1573 if (sc->sc_type == COM_TYPE_AU1x00) { 1574 /* alchemy has single separate 16-bit clock divisor register */ 1575 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1576 (sc->sc_dlbh << 8)); 1577 } else { 1578 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1579 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1580 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1581 } 1582 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1583 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1584 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1585 #ifdef COM_HAYESP 1586 if (sc->sc_type == COM_TYPE_HAYESP) { 1587 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1588 HAYESP_SETPRESCALER); 1589 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1590 sc->sc_prescaler); 1591 } 1592 #endif 1593 if (sc->sc_type == COM_TYPE_OMAP) { 1594 /* setup the fifos. the FCR value is not used as long 1595 as SCR[6] and SCR[7] are 0, which they are at reset 1596 and we never touch the SCR register */ 1597 uint8_t rx_fifo_trig = 40; 1598 uint8_t tx_fifo_trig = 60; 1599 uint8_t rx_start = 8; 1600 uint8_t rx_halt = 60; 1601 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1602 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1603 1604 /* enable access to TCR & TLR */ 1605 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1606 1607 /* write tcr and tlr values */ 1608 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1609 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1610 1611 /* disable access to TCR & TLR */ 1612 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1613 1614 /* enable again, but mode is based on speed */ 1615 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1616 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1617 } else { 1618 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1619 } 1620 } 1621 1622 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1623 } 1624 1625 int 1626 comhwiflow(struct tty *tp, int block) 1627 { 1628 struct com_softc *sc = 1629 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1630 1631 if (COM_ISALIVE(sc) == 0) 1632 return (0); 1633 1634 if (sc->sc_mcr_rts == 0) 1635 return (0); 1636 1637 mutex_spin_enter(&sc->sc_lock); 1638 1639 if (block) { 1640 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1641 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1642 com_hwiflow(sc); 1643 } 1644 } else { 1645 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1646 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1647 com_schedrx(sc); 1648 } 1649 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1650 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1651 com_hwiflow(sc); 1652 } 1653 } 1654 1655 mutex_spin_exit(&sc->sc_lock); 1656 return (1); 1657 } 1658 1659 /* 1660 * (un)block input via hw flowcontrol 1661 */ 1662 void 1663 com_hwiflow(struct com_softc *sc) 1664 { 1665 struct com_regs *regsp= &sc->sc_regs; 1666 1667 if (sc->sc_mcr_rts == 0) 1668 return; 1669 1670 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1671 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1672 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1673 } else { 1674 SET(sc->sc_mcr, sc->sc_mcr_rts); 1675 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1676 } 1677 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1678 } 1679 1680 1681 void 1682 comstart(struct tty *tp) 1683 { 1684 struct com_softc *sc = 1685 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1686 struct com_regs *regsp = &sc->sc_regs; 1687 int s; 1688 1689 if (COM_ISALIVE(sc) == 0) 1690 return; 1691 1692 s = spltty(); 1693 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1694 goto out; 1695 if (sc->sc_tx_stopped) 1696 goto out; 1697 if (!ttypull(tp)) 1698 goto out; 1699 1700 /* Grab the first contiguous region of buffer space. */ 1701 { 1702 u_char *tba; 1703 int tbc; 1704 1705 tba = tp->t_outq.c_cf; 1706 tbc = ndqb(&tp->t_outq, 0); 1707 1708 mutex_spin_enter(&sc->sc_lock); 1709 1710 sc->sc_tba = tba; 1711 sc->sc_tbc = tbc; 1712 } 1713 1714 SET(tp->t_state, TS_BUSY); 1715 sc->sc_tx_busy = 1; 1716 1717 /* Enable transmit completion interrupts if necessary. */ 1718 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1719 SET(sc->sc_ier, IER_ETXRDY); 1720 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1721 } 1722 1723 /* Output the first chunk of the contiguous buffer. */ 1724 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1725 u_int n; 1726 1727 n = sc->sc_tbc; 1728 if (n > sc->sc_fifolen) 1729 n = sc->sc_fifolen; 1730 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1731 sc->sc_tbc -= n; 1732 sc->sc_tba += n; 1733 } 1734 1735 mutex_spin_exit(&sc->sc_lock); 1736 out: 1737 splx(s); 1738 return; 1739 } 1740 1741 /* 1742 * Stop output on a line. 1743 */ 1744 void 1745 comstop(struct tty *tp, int flag) 1746 { 1747 struct com_softc *sc = 1748 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1749 1750 mutex_spin_enter(&sc->sc_lock); 1751 if (ISSET(tp->t_state, TS_BUSY)) { 1752 /* Stop transmitting at the next chunk. */ 1753 sc->sc_tbc = 0; 1754 sc->sc_heldtbc = 0; 1755 if (!ISSET(tp->t_state, TS_TTSTOP)) 1756 SET(tp->t_state, TS_FLUSH); 1757 } 1758 mutex_spin_exit(&sc->sc_lock); 1759 } 1760 1761 void 1762 comdiag(void *arg) 1763 { 1764 struct com_softc *sc = arg; 1765 int overflows, floods; 1766 1767 mutex_spin_enter(&sc->sc_lock); 1768 overflows = sc->sc_overflows; 1769 sc->sc_overflows = 0; 1770 floods = sc->sc_floods; 1771 sc->sc_floods = 0; 1772 sc->sc_errors = 0; 1773 mutex_spin_exit(&sc->sc_lock); 1774 1775 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1776 device_xname(sc->sc_dev), 1777 overflows, overflows == 1 ? "" : "s", 1778 floods, floods == 1 ? "" : "s"); 1779 } 1780 1781 integrate void 1782 com_rxsoft(struct com_softc *sc, struct tty *tp) 1783 { 1784 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1785 u_char *get, *end; 1786 u_int cc, scc; 1787 u_char lsr; 1788 int code; 1789 1790 end = sc->sc_ebuf; 1791 get = sc->sc_rbget; 1792 scc = cc = com_rbuf_size - sc->sc_rbavail; 1793 1794 if (cc == com_rbuf_size) { 1795 sc->sc_floods++; 1796 if (sc->sc_errors++ == 0) 1797 callout_reset(&sc->sc_diag_callout, 60 * hz, 1798 comdiag, sc); 1799 } 1800 1801 /* If not yet open, drop the entire buffer content here */ 1802 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1803 get += cc << 1; 1804 if (get >= end) 1805 get -= com_rbuf_size << 1; 1806 cc = 0; 1807 } 1808 while (cc) { 1809 code = get[0]; 1810 lsr = get[1]; 1811 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1812 if (ISSET(lsr, LSR_OE)) { 1813 sc->sc_overflows++; 1814 if (sc->sc_errors++ == 0) 1815 callout_reset(&sc->sc_diag_callout, 1816 60 * hz, comdiag, sc); 1817 } 1818 if (ISSET(lsr, LSR_BI | LSR_FE)) 1819 SET(code, TTY_FE); 1820 if (ISSET(lsr, LSR_PE)) 1821 SET(code, TTY_PE); 1822 } 1823 if ((*rint)(code, tp) == -1) { 1824 /* 1825 * The line discipline's buffer is out of space. 1826 */ 1827 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1828 /* 1829 * We're either not using flow control, or the 1830 * line discipline didn't tell us to block for 1831 * some reason. Either way, we have no way to 1832 * know when there's more space available, so 1833 * just drop the rest of the data. 1834 */ 1835 get += cc << 1; 1836 if (get >= end) 1837 get -= com_rbuf_size << 1; 1838 cc = 0; 1839 } else { 1840 /* 1841 * Don't schedule any more receive processing 1842 * until the line discipline tells us there's 1843 * space available (through comhwiflow()). 1844 * Leave the rest of the data in the input 1845 * buffer. 1846 */ 1847 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1848 } 1849 break; 1850 } 1851 get += 2; 1852 if (get >= end) 1853 get = sc->sc_rbuf; 1854 cc--; 1855 } 1856 1857 if (cc != scc) { 1858 sc->sc_rbget = get; 1859 mutex_spin_enter(&sc->sc_lock); 1860 1861 cc = sc->sc_rbavail += scc - cc; 1862 /* Buffers should be ok again, release possible block. */ 1863 if (cc >= sc->sc_r_lowat) { 1864 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1865 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1866 SET(sc->sc_ier, IER_ERXRDY); 1867 #ifdef COM_PXA2X0 1868 if (sc->sc_type == COM_TYPE_PXA2x0) 1869 SET(sc->sc_ier, IER_ERXTOUT); 1870 #endif 1871 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1872 } 1873 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1874 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1875 com_hwiflow(sc); 1876 } 1877 } 1878 mutex_spin_exit(&sc->sc_lock); 1879 } 1880 } 1881 1882 integrate void 1883 com_txsoft(struct com_softc *sc, struct tty *tp) 1884 { 1885 1886 CLR(tp->t_state, TS_BUSY); 1887 if (ISSET(tp->t_state, TS_FLUSH)) 1888 CLR(tp->t_state, TS_FLUSH); 1889 else 1890 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1891 (*tp->t_linesw->l_start)(tp); 1892 } 1893 1894 integrate void 1895 com_stsoft(struct com_softc *sc, struct tty *tp) 1896 { 1897 u_char msr, delta; 1898 1899 mutex_spin_enter(&sc->sc_lock); 1900 msr = sc->sc_msr; 1901 delta = sc->sc_msr_delta; 1902 sc->sc_msr_delta = 0; 1903 mutex_spin_exit(&sc->sc_lock); 1904 1905 if (ISSET(delta, sc->sc_msr_dcd)) { 1906 /* 1907 * Inform the tty layer that carrier detect changed. 1908 */ 1909 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1910 } 1911 1912 if (ISSET(delta, sc->sc_msr_cts)) { 1913 /* Block or unblock output according to flow control. */ 1914 if (ISSET(msr, sc->sc_msr_cts)) { 1915 sc->sc_tx_stopped = 0; 1916 (*tp->t_linesw->l_start)(tp); 1917 } else { 1918 sc->sc_tx_stopped = 1; 1919 } 1920 } 1921 1922 #ifdef COM_DEBUG 1923 if (com_debug) 1924 comstatus(sc, "com_stsoft"); 1925 #endif 1926 } 1927 1928 void 1929 comsoft(void *arg) 1930 { 1931 struct com_softc *sc = arg; 1932 struct tty *tp; 1933 1934 if (COM_ISALIVE(sc) == 0) 1935 return; 1936 1937 tp = sc->sc_tty; 1938 1939 if (sc->sc_rx_ready) { 1940 sc->sc_rx_ready = 0; 1941 com_rxsoft(sc, tp); 1942 } 1943 1944 if (sc->sc_st_check) { 1945 sc->sc_st_check = 0; 1946 com_stsoft(sc, tp); 1947 } 1948 1949 if (sc->sc_tx_done) { 1950 sc->sc_tx_done = 0; 1951 com_txsoft(sc, tp); 1952 } 1953 } 1954 1955 int 1956 comintr(void *arg) 1957 { 1958 struct com_softc *sc = arg; 1959 struct com_regs *regsp = &sc->sc_regs; 1960 1961 u_char *put, *end; 1962 u_int cc; 1963 u_char lsr, iir; 1964 1965 if (COM_ISALIVE(sc) == 0) 1966 return (0); 1967 1968 KASSERT(regsp != NULL); 1969 1970 mutex_spin_enter(&sc->sc_lock); 1971 iir = CSR_READ_1(regsp, COM_REG_IIR); 1972 1973 /* Handle ns16750-specific busy interrupt. */ 1974 #ifdef COM_16750 1975 int timeout; 1976 if ((iir & IIR_BUSY) == IIR_BUSY) { 1977 for (timeout = 10000; 1978 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 1979 if (timeout <= 0) { 1980 aprint_error_dev(sc->sc_dev, 1981 "timeout while waiting for BUSY interrupt " 1982 "acknowledge\n"); 1983 mutex_spin_exit(&sc->sc_lock); 1984 return (0); 1985 } 1986 1987 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1988 iir = CSR_READ_1(regsp, COM_REG_IIR); 1989 } 1990 #endif /* COM_16750 */ 1991 1992 1993 if (ISSET(iir, IIR_NOPEND)) { 1994 mutex_spin_exit(&sc->sc_lock); 1995 return (0); 1996 } 1997 1998 end = sc->sc_ebuf; 1999 put = sc->sc_rbput; 2000 cc = sc->sc_rbavail; 2001 2002 again: do { 2003 u_char msr, delta; 2004 2005 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2006 if (ISSET(lsr, LSR_BI)) { 2007 int cn_trapped = 0; /* see above: cn_trap() */ 2008 2009 cn_check_magic(sc->sc_tty->t_dev, 2010 CNC_BREAK, com_cnm_state); 2011 if (cn_trapped) 2012 continue; 2013 #if defined(KGDB) && !defined(DDB) 2014 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2015 kgdb_connect(1); 2016 continue; 2017 } 2018 #endif 2019 } 2020 2021 if (ISSET(lsr, LSR_RCV_MASK) && 2022 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2023 while (cc > 0) { 2024 int cn_trapped = 0; 2025 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2026 put[1] = lsr; 2027 cn_check_magic(sc->sc_tty->t_dev, 2028 put[0], com_cnm_state); 2029 if (cn_trapped) 2030 goto next; 2031 put += 2; 2032 if (put >= end) 2033 put = sc->sc_rbuf; 2034 cc--; 2035 next: 2036 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2037 if (!ISSET(lsr, LSR_RCV_MASK)) 2038 break; 2039 } 2040 2041 /* 2042 * Current string of incoming characters ended because 2043 * no more data was available or we ran out of space. 2044 * Schedule a receive event if any data was received. 2045 * If we're out of space, turn off receive interrupts. 2046 */ 2047 sc->sc_rbput = put; 2048 sc->sc_rbavail = cc; 2049 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2050 sc->sc_rx_ready = 1; 2051 2052 /* 2053 * See if we are in danger of overflowing a buffer. If 2054 * so, use hardware flow control to ease the pressure. 2055 */ 2056 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2057 cc < sc->sc_r_hiwat) { 2058 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2059 com_hwiflow(sc); 2060 } 2061 2062 /* 2063 * If we're out of space, disable receive interrupts 2064 * until the queue has drained a bit. 2065 */ 2066 if (!cc) { 2067 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2068 #ifdef COM_PXA2X0 2069 if (sc->sc_type == COM_TYPE_PXA2x0) 2070 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2071 else 2072 #endif 2073 CLR(sc->sc_ier, IER_ERXRDY); 2074 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2075 } 2076 } else { 2077 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2078 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2079 continue; 2080 } 2081 } 2082 2083 msr = CSR_READ_1(regsp, COM_REG_MSR); 2084 delta = msr ^ sc->sc_msr; 2085 sc->sc_msr = msr; 2086 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2087 (delta & MSR_DCD)) { 2088 mutex_spin_enter(&timecounter_lock); 2089 pps_capture(&sc->sc_pps_state); 2090 pps_event(&sc->sc_pps_state, 2091 (msr & MSR_DCD) ? 2092 PPS_CAPTUREASSERT : 2093 PPS_CAPTURECLEAR); 2094 mutex_spin_exit(&timecounter_lock); 2095 } 2096 2097 /* 2098 * Process normal status changes 2099 */ 2100 if (ISSET(delta, sc->sc_msr_mask)) { 2101 SET(sc->sc_msr_delta, delta); 2102 2103 /* 2104 * Stop output immediately if we lose the output 2105 * flow control signal or carrier detect. 2106 */ 2107 if (ISSET(~msr, sc->sc_msr_mask)) { 2108 sc->sc_tbc = 0; 2109 sc->sc_heldtbc = 0; 2110 #ifdef COM_DEBUG 2111 if (com_debug) 2112 comstatus(sc, "comintr "); 2113 #endif 2114 } 2115 2116 sc->sc_st_check = 1; 2117 } 2118 } while (!ISSET((iir = 2119 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2120 /* 2121 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2122 * by IIR read, so we can't do this way: `process all interrupts, 2123 * then do TX if possible'. 2124 */ 2125 (iir & IIR_IMASK) != IIR_TXRDY); 2126 2127 /* 2128 * Read LSR again, since there may be an interrupt between 2129 * the last LSR read and IIR read above. 2130 */ 2131 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2132 2133 /* 2134 * See if data can be transmitted as well. 2135 * Schedule tx done event if no data left 2136 * and tty was marked busy. 2137 */ 2138 if (ISSET(lsr, LSR_TXRDY)) { 2139 /* 2140 * If we've delayed a parameter change, do it now, and restart 2141 * output. 2142 */ 2143 if (sc->sc_heldchange) { 2144 com_loadchannelregs(sc); 2145 sc->sc_heldchange = 0; 2146 sc->sc_tbc = sc->sc_heldtbc; 2147 sc->sc_heldtbc = 0; 2148 } 2149 2150 /* Output the next chunk of the contiguous buffer, if any. */ 2151 if (sc->sc_tbc > 0) { 2152 u_int n; 2153 2154 n = sc->sc_tbc; 2155 if (n > sc->sc_fifolen) 2156 n = sc->sc_fifolen; 2157 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2158 sc->sc_tbc -= n; 2159 sc->sc_tba += n; 2160 } else { 2161 /* Disable transmit completion interrupts if necessary. */ 2162 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2163 CLR(sc->sc_ier, IER_ETXRDY); 2164 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2165 } 2166 if (sc->sc_tx_busy) { 2167 sc->sc_tx_busy = 0; 2168 sc->sc_tx_done = 1; 2169 } 2170 } 2171 } 2172 2173 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2174 goto again; 2175 2176 mutex_spin_exit(&sc->sc_lock); 2177 2178 /* Wake up the poller. */ 2179 softint_schedule(sc->sc_si); 2180 2181 #ifdef RND_COM 2182 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2183 #endif 2184 2185 return (1); 2186 } 2187 2188 /* 2189 * The following functions are polled getc and putc routines, shared 2190 * by the console and kgdb glue. 2191 * 2192 * The read-ahead code is so that you can detect pending in-band 2193 * cn_magic in polled mode while doing output rather than having to 2194 * wait until the kernel decides it needs input. 2195 */ 2196 2197 #define MAX_READAHEAD 20 2198 static int com_readahead[MAX_READAHEAD]; 2199 static int com_readaheadcount = 0; 2200 2201 int 2202 com_common_getc(dev_t dev, struct com_regs *regsp) 2203 { 2204 int s = splserial(); 2205 u_char stat, c; 2206 2207 /* got a character from reading things earlier */ 2208 if (com_readaheadcount > 0) { 2209 int i; 2210 2211 c = com_readahead[0]; 2212 for (i = 1; i < com_readaheadcount; i++) { 2213 com_readahead[i-1] = com_readahead[i]; 2214 } 2215 com_readaheadcount--; 2216 splx(s); 2217 return (c); 2218 } 2219 2220 /* block until a character becomes available */ 2221 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) 2222 ; 2223 2224 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2225 stat = CSR_READ_1(regsp, COM_REG_IIR); 2226 { 2227 int cn_trapped = 0; /* required by cn_trap, see above */ 2228 #ifdef DDB 2229 extern int db_active; 2230 if (!db_active) 2231 #endif 2232 cn_check_magic(dev, c, com_cnm_state); 2233 } 2234 splx(s); 2235 return (c); 2236 } 2237 2238 static void 2239 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2240 { 2241 int s = splserial(); 2242 int cin, stat, timo; 2243 2244 if (com_readaheadcount < MAX_READAHEAD 2245 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2246 int cn_trapped = 0; 2247 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2248 stat = CSR_READ_1(regsp, COM_REG_IIR); 2249 cn_check_magic(dev, cin, com_cnm_state); 2250 com_readahead[com_readaheadcount++] = cin; 2251 } 2252 2253 /* wait for any pending transmission to finish */ 2254 timo = 150000; 2255 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2256 continue; 2257 2258 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2259 COM_BARRIER(regsp, BR | BW); 2260 2261 splx(s); 2262 } 2263 2264 /* 2265 * Initialize UART for use as console or KGDB line. 2266 */ 2267 int 2268 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2269 tcflag_t cflag) 2270 { 2271 2272 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2273 ®sp->cr_ioh)) 2274 return (ENOMEM); /* ??? */ 2275 2276 if (type == COM_TYPE_OMAP) { 2277 /* disable before changing settings */ 2278 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2279 } 2280 2281 rate = comspeed(rate, frequency, type); 2282 if (__predict_true(rate != -1)) { 2283 if (type == COM_TYPE_AU1x00) { 2284 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2285 } else { 2286 /* no EFR on alchemy */ 2287 if (type != COM_TYPE_16550_NOERS) { 2288 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2289 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2290 } 2291 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2292 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2293 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2294 } 2295 } 2296 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2297 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2298 CSR_WRITE_1(regsp, COM_REG_FIFO, 2299 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2300 2301 if (type == COM_TYPE_OMAP) { 2302 /* setup the fifos. the FCR value is not used as long 2303 as SCR[6] and SCR[7] are 0, which they are at reset 2304 and we never touch the SCR register */ 2305 uint8_t rx_fifo_trig = 40; 2306 uint8_t tx_fifo_trig = 60; 2307 uint8_t rx_start = 8; 2308 uint8_t rx_halt = 60; 2309 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2310 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2311 2312 /* enable access to TCR & TLR */ 2313 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2314 2315 /* write tcr and tlr values */ 2316 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2317 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2318 2319 /* disable access to TCR & TLR */ 2320 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2321 2322 /* enable again, but mode is based on speed */ 2323 if (rate > 230400) { 2324 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2325 } else { 2326 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2327 } 2328 } 2329 2330 #ifdef COM_PXA2X0 2331 if (type == COM_TYPE_PXA2x0) 2332 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2333 else 2334 #endif 2335 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2336 2337 return (0); 2338 } 2339 2340 int 2341 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2342 tcflag_t cflag) 2343 { 2344 int res; 2345 2346 comcons_info.regs = *regsp; 2347 2348 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2349 if (res) 2350 return (res); 2351 2352 cn_tab = &comcons; 2353 cn_init_magic(&com_cnm_state); 2354 cn_set_magic("\047\001"); /* default magic is BREAK */ 2355 2356 comcons_info.frequency = frequency; 2357 comcons_info.type = type; 2358 comcons_info.rate = rate; 2359 comcons_info.cflag = cflag; 2360 2361 return (0); 2362 } 2363 2364 int 2365 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2366 int type, tcflag_t cflag) 2367 { 2368 struct com_regs regs; 2369 2370 memset(®s, 0, sizeof regs); 2371 regs.cr_iot = iot; 2372 regs.cr_iobase = iobase; 2373 regs.cr_nports = COM_NPORTS; 2374 #ifdef COM_REGMAP 2375 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2376 #endif 2377 2378 return comcnattach1(®s, rate, frequency, type, cflag); 2379 } 2380 2381 static int 2382 comcnreattach(void) 2383 { 2384 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2385 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2386 } 2387 2388 int 2389 comcngetc(dev_t dev) 2390 { 2391 2392 return (com_common_getc(dev, &comcons_info.regs)); 2393 } 2394 2395 /* 2396 * Console kernel output character routine. 2397 */ 2398 void 2399 comcnputc(dev_t dev, int c) 2400 { 2401 2402 com_common_putc(dev, &comcons_info.regs, c); 2403 } 2404 2405 void 2406 comcnpollc(dev_t dev, int on) 2407 { 2408 2409 com_readaheadcount = 0; 2410 } 2411 2412 #ifdef KGDB 2413 int 2414 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2415 tcflag_t cflag) 2416 { 2417 int res; 2418 2419 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2420 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2421 #if !defined(DDB) 2422 return (EBUSY); /* cannot share with console */ 2423 #else 2424 comkgdbregs = *regsp; 2425 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2426 #endif 2427 } else { 2428 comkgdbregs = *regsp; 2429 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2430 if (res) 2431 return (res); 2432 2433 /* 2434 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2435 * expects this to be initialized 2436 */ 2437 cn_init_magic(&com_cnm_state); 2438 cn_set_magic("\047\001"); 2439 } 2440 2441 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2442 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2443 2444 return (0); 2445 } 2446 2447 int 2448 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2449 int frequency, int type, tcflag_t cflag) 2450 { 2451 struct com_regs regs; 2452 2453 regs.cr_iot = iot; 2454 regs.cr_nports = COM_NPORTS; 2455 regs.cr_iobase = iobase; 2456 #ifdef COM_REGMAP 2457 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2458 #endif 2459 2460 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2461 } 2462 2463 /* ARGSUSED */ 2464 int 2465 com_kgdb_getc(void *arg) 2466 { 2467 2468 return (com_common_getc(NODEV, &comkgdbregs)); 2469 } 2470 2471 /* ARGSUSED */ 2472 void 2473 com_kgdb_putc(void *arg, int c) 2474 { 2475 2476 com_common_putc(NODEV, &comkgdbregs, c); 2477 } 2478 #endif /* KGDB */ 2479 2480 /* helper function to identify the com ports used by 2481 console or KGDB (and not yet autoconf attached) */ 2482 int 2483 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2484 { 2485 bus_space_handle_t help; 2486 2487 if (!comconsattached && 2488 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2489 iobase == comcons_info.regs.cr_iobase) 2490 help = comcons_info.regs.cr_ioh; 2491 #ifdef KGDB 2492 else if (!com_kgdb_attached && 2493 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2494 iobase == comkgdbregs.cr_iobase) 2495 help = comkgdbregs.cr_ioh; 2496 #endif 2497 else 2498 return (0); 2499 2500 if (ioh) 2501 *ioh = help; 2502 return (1); 2503 } 2504 2505 /* 2506 * this routine exists to serve as a shutdown hook for systems that 2507 * have firmware which doesn't interact properly with a com device in 2508 * FIFO mode. 2509 */ 2510 bool 2511 com_cleanup(device_t self, int how) 2512 { 2513 struct com_softc *sc = device_private(self); 2514 2515 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2516 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2517 2518 return true; 2519 } 2520 2521 bool 2522 com_suspend(device_t self, const pmf_qual_t *qual) 2523 { 2524 struct com_softc *sc = device_private(self); 2525 2526 #if 0 2527 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2528 cn_tab = &comcons_suspend; 2529 #endif 2530 2531 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2532 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2533 2534 return true; 2535 } 2536 2537 bool 2538 com_resume(device_t self, const pmf_qual_t *qual) 2539 { 2540 struct com_softc *sc = device_private(self); 2541 2542 mutex_spin_enter(&sc->sc_lock); 2543 com_loadchannelregs(sc); 2544 mutex_spin_exit(&sc->sc_lock); 2545 2546 return true; 2547 } 2548
Indexes created Wed Sep 24 05:09:52 GMT 2025