com.c revision 1.323
1 /* $NetBSD: com.c,v 1.323 2014/03/16 05:20:27 dholland Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.323 2014/03/16 05:20:27 dholland Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 (void)cn_trapped; \ 96 } while (/* CONSTCOND */ 0) 97 98 #include <sys/param.h> 99 #include <sys/systm.h> 100 #include <sys/ioctl.h> 101 #include <sys/select.h> 102 #include <sys/poll.h> 103 #include <sys/tty.h> 104 #include <sys/proc.h> 105 #include <sys/conf.h> 106 #include <sys/file.h> 107 #include <sys/uio.h> 108 #include <sys/kernel.h> 109 #include <sys/syslog.h> 110 #include <sys/device.h> 111 #include <sys/malloc.h> 112 #include <sys/timepps.h> 113 #include <sys/vnode.h> 114 #include <sys/kauth.h> 115 #include <sys/intr.h> 116 #ifdef RND_COM 117 #include <sys/rnd.h> 118 #endif 119 120 121 #include <sys/bus.h> 122 123 #include <dev/ic/comreg.h> 124 #include <dev/ic/comvar.h> 125 #include <dev/ic/ns16550reg.h> 126 #include <dev/ic/st16650reg.h> 127 #ifdef COM_HAYESP 128 #include <dev/ic/hayespreg.h> 129 #endif 130 #define com_lcr com_cfcr 131 #include <dev/cons.h> 132 133 #ifdef COM_REGMAP 134 #define CSR_WRITE_1(r, o, v) \ 135 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 136 #define CSR_READ_1(r, o) \ 137 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 138 #define CSR_WRITE_2(r, o, v) \ 139 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 140 #define CSR_READ_2(r, o) \ 141 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 142 #define CSR_WRITE_MULTI(r, o, p, n) \ 143 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 144 #else 145 #define CSR_WRITE_1(r, o, v) \ 146 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 147 #define CSR_READ_1(r, o) \ 148 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 149 #define CSR_WRITE_2(r, o, v) \ 150 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 151 #define CSR_READ_2(r, o) \ 152 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 153 #define CSR_WRITE_MULTI(r, o, p, n) \ 154 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 155 #endif 156 157 158 static void com_enable_debugport(struct com_softc *); 159 160 void com_config(struct com_softc *); 161 void com_shutdown(struct com_softc *); 162 int comspeed(long, long, int); 163 static u_char cflag2lcr(tcflag_t); 164 int comparam(struct tty *, struct termios *); 165 void comstart(struct tty *); 166 int comhwiflow(struct tty *, int); 167 168 void com_loadchannelregs(struct com_softc *); 169 void com_hwiflow(struct com_softc *); 170 void com_break(struct com_softc *, int); 171 void com_modem(struct com_softc *, int); 172 void tiocm_to_com(struct com_softc *, u_long, int); 173 int com_to_tiocm(struct com_softc *); 174 void com_iflush(struct com_softc *); 175 176 int com_common_getc(dev_t, struct com_regs *); 177 static void com_common_putc(dev_t, struct com_regs *, int); 178 179 int cominit(struct com_regs *, int, int, int, tcflag_t); 180 181 static int comcnreattach(void); 182 183 int comcngetc(dev_t); 184 void comcnputc(dev_t, int); 185 void comcnpollc(dev_t, int); 186 187 #define integrate static inline 188 void comsoft(void *); 189 integrate void com_rxsoft(struct com_softc *, struct tty *); 190 integrate void com_txsoft(struct com_softc *, struct tty *); 191 integrate void com_stsoft(struct com_softc *, struct tty *); 192 integrate void com_schedrx(struct com_softc *); 193 void comdiag(void *); 194 195 extern struct cfdriver com_cd; 196 197 dev_type_open(comopen); 198 dev_type_close(comclose); 199 dev_type_read(comread); 200 dev_type_write(comwrite); 201 dev_type_ioctl(comioctl); 202 dev_type_stop(comstop); 203 dev_type_tty(comtty); 204 dev_type_poll(compoll); 205 206 static struct comcons_info comcons_info; 207 208 /* 209 * Following are all routines needed for COM to act as console 210 */ 211 static struct consdev comcons = { 212 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 213 NODEV, CN_NORMAL 214 }; 215 216 217 const struct cdevsw com_cdevsw = { 218 .d_open = comopen, 219 .d_close = comclose, 220 .d_read = comread, 221 .d_write = comwrite, 222 .d_ioctl = comioctl, 223 .d_stop = comstop, 224 .d_tty = comtty, 225 .d_poll = compoll, 226 .d_mmap = nommap, 227 .d_kqfilter = ttykqfilter, 228 .d_flag = D_TTY 229 }; 230 231 /* 232 * Make this an option variable one can patch. 233 * But be warned: this must be a power of 2! 234 */ 235 u_int com_rbuf_size = COM_RING_SIZE; 236 237 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 238 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 239 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 240 241 static int comconsattached; 242 static struct cnm_state com_cnm_state; 243 244 #ifdef KGDB 245 #include <sys/kgdb.h> 246 247 static struct com_regs comkgdbregs; 248 static int com_kgdb_attached; 249 250 int com_kgdb_getc(void *); 251 void com_kgdb_putc(void *, int); 252 #endif /* KGDB */ 253 254 #ifdef COM_REGMAP 255 /* initializer for typical 16550-ish hardware */ 256 #define COM_REG_16550 { \ 257 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 258 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 259 /* 16750-specific register set, additional UART status register */ 260 #define COM_REG_16750 { \ 261 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 262 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } 264 265 #ifdef COM_16750 266 const bus_size_t com_std_map[32] = COM_REG_16750; 267 #else 268 const bus_size_t com_std_map[16] = COM_REG_16550; 269 #endif /* COM_16750 */ 270 #endif /* COM_REGMAP */ 271 272 #define COMUNIT_MASK 0x7ffff 273 #define COMDIALOUT_MASK 0x80000 274 275 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 276 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 277 278 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 279 device_is_active((sc)->sc_dev)) 280 281 #define BR BUS_SPACE_BARRIER_READ 282 #define BW BUS_SPACE_BARRIER_WRITE 283 #define COM_BARRIER(r, f) \ 284 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 285 286 /*ARGSUSED*/ 287 int 288 comspeed(long speed, long frequency, int type) 289 { 290 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 291 292 int x, err; 293 int divisor = 16; 294 295 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 296 divisor = 13; 297 } 298 299 #if 0 300 if (speed == 0) 301 return (0); 302 #endif 303 if (speed <= 0) 304 return (-1); 305 x = divrnd(frequency / divisor, speed); 306 if (x <= 0) 307 return (-1); 308 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 309 if (err < 0) 310 err = -err; 311 if (err > COM_TOLERANCE) 312 return (-1); 313 return (x); 314 315 #undef divrnd 316 } 317 318 #ifdef COM_DEBUG 319 int com_debug = 0; 320 321 void comstatus(struct com_softc *, const char *); 322 void 323 comstatus(struct com_softc *sc, const char *str) 324 { 325 struct tty *tp = sc->sc_tty; 326 327 aprint_normal_dev(sc->sc_dev, 328 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 329 str, 330 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 331 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 332 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 333 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 334 sc->sc_tx_stopped ? '+' : '-'); 335 336 aprint_normal_dev(sc->sc_dev, 337 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 338 str, 339 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 340 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 341 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 342 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 343 sc->sc_rx_flags); 344 } 345 #endif 346 347 int 348 com_probe_subr(struct com_regs *regs) 349 { 350 351 /* force access to id reg */ 352 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 353 CSR_WRITE_1(regs, COM_REG_IIR, 0); 354 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 355 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 356 return (0); 357 358 return (1); 359 } 360 361 int 362 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 363 { 364 struct com_regs regs; 365 366 regs.cr_iot = iot; 367 regs.cr_ioh = ioh; 368 #ifdef COM_REGMAP 369 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 370 #endif 371 372 return com_probe_subr(®s); 373 } 374 375 /* 376 * No locking in this routine; it is only called during attach, 377 * or with the port already locked. 378 */ 379 static void 380 com_enable_debugport(struct com_softc *sc) 381 { 382 383 /* Turn on line break interrupt, set carrier. */ 384 sc->sc_ier = IER_ERXRDY; 385 if (sc->sc_type == COM_TYPE_PXA2x0) 386 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 387 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 388 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 389 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 390 } 391 392 void 393 com_attach_subr(struct com_softc *sc) 394 { 395 struct com_regs *regsp = &sc->sc_regs; 396 struct tty *tp; 397 #if defined(COM_16650) || defined(COM_16750) 398 u_int8_t lcr; 399 #endif 400 const char *fifo_msg = NULL; 401 prop_dictionary_t dict; 402 bool is_console = true; 403 404 aprint_naive("\n"); 405 406 dict = device_properties(sc->sc_dev); 407 prop_dictionary_get_bool(dict, "is_console", &is_console); 408 409 callout_init(&sc->sc_diag_callout, 0); 410 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 411 412 /* Disable interrupts before configuring the device. */ 413 if (sc->sc_type == COM_TYPE_PXA2x0) 414 sc->sc_ier = IER_EUART; 415 else 416 sc->sc_ier = 0; 417 418 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 419 420 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 421 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 422 comconsattached = 1; 423 424 if (cn_tab == NULL && comcnreattach() != 0) { 425 printf("can't re-init serial console @%lx\n", 426 (u_long)comcons_info.regs.cr_iobase); 427 } 428 429 #ifdef COM_16750 430 /* Use in comintr(). */ 431 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 432 #endif 433 434 /* Make sure the console is always "hardwired". */ 435 delay(10000); /* wait for output to finish */ 436 if (is_console) { 437 SET(sc->sc_hwflags, COM_HW_CONSOLE); 438 } 439 440 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 441 } 442 443 /* Probe for FIFO */ 444 switch (sc->sc_type) { 445 case COM_TYPE_HAYESP: 446 goto fifodone; 447 448 case COM_TYPE_AU1x00: 449 sc->sc_fifolen = 16; 450 fifo_msg = "Au1X00 UART, working fifo"; 451 SET(sc->sc_hwflags, COM_HW_FIFO); 452 goto fifodelay; 453 454 case COM_TYPE_16550_NOERS: 455 sc->sc_fifolen = 16; 456 fifo_msg = "ns16650, no ERS, working fifo"; 457 SET(sc->sc_hwflags, COM_HW_FIFO); 458 goto fifodelay; 459 460 case COM_TYPE_OMAP: 461 sc->sc_fifolen = 64; 462 fifo_msg = "OMAP UART, working fifo"; 463 SET(sc->sc_hwflags, COM_HW_FIFO); 464 goto fifodelay; 465 } 466 467 sc->sc_fifolen = 1; 468 /* look for a NS 16550AF UART with FIFOs */ 469 CSR_WRITE_1(regsp, COM_REG_FIFO, 470 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 471 delay(100); 472 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 473 == IIR_FIFO_MASK) 474 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 475 == FIFO_TRIGGER_14) { 476 SET(sc->sc_hwflags, COM_HW_FIFO); 477 478 #ifdef COM_16650 479 /* 480 * IIR changes into the EFR if LCR is set to LCR_EERS 481 * on 16650s. We also know IIR != 0 at this point. 482 * Write 0 into the EFR, and read it. If the result 483 * is 0, we have a 16650. 484 * 485 * Older 16650s were broken; the test to detect them 486 * is taken from the Linux driver. Apparently 487 * setting DLAB enable gives access to the EFR on 488 * these chips. 489 */ 490 lcr = CSR_READ_1(regsp, COM_REG_LCR); 491 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 492 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 493 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 494 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 495 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 496 CLR(sc->sc_hwflags, COM_HW_FIFO); 497 sc->sc_fifolen = 0; 498 } else { 499 SET(sc->sc_hwflags, COM_HW_FLOW); 500 sc->sc_fifolen = 32; 501 } 502 } else 503 #endif 504 sc->sc_fifolen = 16; 505 506 #ifdef COM_16750 507 /* 508 * TL16C750 can enable 64byte FIFO, only when DLAB 509 * is 1. However, some 16750 may always enable. For 510 * example, restrictions according to DLAB in a data 511 * sheet for SC16C750 were not described. 512 * Please enable 'options COM_16650', supposing you 513 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 514 * should become effective. 515 */ 516 uint8_t iir1, iir2; 517 const uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 518 519 lcr = CSR_READ_1(regsp, COM_REG_LCR); 520 CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB); 521 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 522 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 523 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 524 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 525 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 526 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 527 528 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 529 530 if (!ISSET(iir1, IIR_64B_FIFO) && 531 ISSET(iir2, IIR_64B_FIFO)) { 532 /* It is TL16C750. */ 533 sc->sc_fifolen = 64; 534 SET(sc->sc_hwflags, COM_HW_AFE); 535 } else 536 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 537 #endif 538 539 #ifdef COM_16650 540 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 541 if (sc->sc_fifolen == 0) 542 fifo_msg = "st16650, broken fifo"; 543 else if (sc->sc_fifolen == 32) 544 fifo_msg = "st16650a, working fifo"; 545 else 546 #endif 547 #ifdef COM_16750 548 if (sc->sc_fifolen == 64) 549 fifo_msg = "tl16c750, working fifo"; 550 else 551 #endif 552 fifo_msg = "ns16550a, working fifo"; 553 } else 554 fifo_msg = "ns16550, broken fifo"; 555 else 556 fifo_msg = "ns8250 or ns16450, no fifo"; 557 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 558 fifodelay: 559 /* 560 * Some chips will clear down both Tx and Rx FIFOs when zero is 561 * written to com_fifo. If this chip is the console, writing zero 562 * results in some of the chip/FIFO description being lost, so delay 563 * printing it until now. 564 */ 565 delay(10); 566 aprint_normal(": %s\n", fifo_msg); 567 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 568 sc->sc_fifolen = 1; 569 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 570 } 571 572 fifodone: 573 574 tp = tty_alloc(); 575 tp->t_oproc = comstart; 576 tp->t_param = comparam; 577 tp->t_hwiflow = comhwiflow; 578 tp->t_softc = sc; 579 580 sc->sc_tty = tp; 581 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 582 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 583 sc->sc_rbavail = com_rbuf_size; 584 if (sc->sc_rbuf == NULL) { 585 aprint_error_dev(sc->sc_dev, 586 "unable to allocate ring buffer\n"); 587 return; 588 } 589 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 590 591 tty_attach(tp); 592 593 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 594 SET(sc->sc_mcr, MCR_IENABLE); 595 596 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 597 int maj; 598 599 /* locate the major number */ 600 maj = cdevsw_lookup_major(&com_cdevsw); 601 602 tp->t_dev = cn_tab->cn_dev = makedev(maj, 603 device_unit(sc->sc_dev)); 604 605 aprint_normal_dev(sc->sc_dev, "console\n"); 606 } 607 608 #ifdef KGDB 609 /* 610 * Allow kgdb to "take over" this port. If this is 611 * not the console and is the kgdb device, it has 612 * exclusive use. If it's the console _and_ the 613 * kgdb device, it doesn't. 614 */ 615 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 616 regsp->cr_iobase == comkgdbregs.cr_iobase) { 617 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 618 com_kgdb_attached = 1; 619 620 SET(sc->sc_hwflags, COM_HW_KGDB); 621 } 622 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 623 } 624 #endif 625 626 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 627 628 #ifdef RND_COM 629 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 630 RND_TYPE_TTY, 0); 631 #endif 632 633 /* if there are no enable/disable functions, assume the device 634 is always enabled */ 635 if (!sc->enable) 636 sc->enabled = 1; 637 638 com_config(sc); 639 640 SET(sc->sc_hwflags, COM_HW_DEV_OK); 641 } 642 643 void 644 com_config(struct com_softc *sc) 645 { 646 struct com_regs *regsp = &sc->sc_regs; 647 648 /* Disable interrupts before configuring the device. */ 649 if (sc->sc_type == COM_TYPE_PXA2x0) 650 sc->sc_ier = IER_EUART; 651 else 652 sc->sc_ier = 0; 653 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 654 (void) CSR_READ_1(regsp, COM_REG_IIR); 655 656 #ifdef COM_HAYESP 657 /* Look for a Hayes ESP board. */ 658 if (sc->sc_type == COM_TYPE_HAYESP) { 659 660 /* Set 16550 compatibility mode */ 661 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 662 HAYESP_SETMODE); 663 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 664 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 665 HAYESP_MODE_SCALE); 666 667 /* Set RTS/CTS flow control */ 668 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 669 HAYESP_SETFLOWTYPE); 670 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 671 HAYESP_FLOW_RTS); 672 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 673 HAYESP_FLOW_CTS); 674 675 /* Set flow control levels */ 676 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 677 HAYESP_SETRXFLOW); 678 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 679 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 680 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 681 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 682 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 683 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 684 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 685 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 686 } 687 #endif 688 689 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 690 com_enable_debugport(sc); 691 } 692 693 #if 0 694 static int 695 comcngetc_detached(dev_t dev) 696 { 697 return 0; 698 } 699 700 static void 701 comcnputc_detached(dev_t dev, int c) 702 { 703 } 704 #endif 705 706 int 707 com_detach(device_t self, int flags) 708 { 709 struct com_softc *sc = device_private(self); 710 int maj, mn; 711 712 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 713 return EBUSY; 714 715 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 716 (flags & DETACH_SHUTDOWN) != 0) 717 return EBUSY; 718 719 if (sc->disable != NULL && sc->enabled != 0) { 720 (*sc->disable)(sc); 721 sc->enabled = 0; 722 } 723 724 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 725 comconsattached = 0; 726 cn_tab = NULL; 727 } 728 729 /* locate the major number */ 730 maj = cdevsw_lookup_major(&com_cdevsw); 731 732 /* Nuke the vnodes for any open instances. */ 733 mn = device_unit(self); 734 vdevgone(maj, mn, mn, VCHR); 735 736 mn |= COMDIALOUT_MASK; 737 vdevgone(maj, mn, mn, VCHR); 738 739 if (sc->sc_rbuf == NULL) { 740 /* 741 * Ring buffer allocation failed in the com_attach_subr, 742 * only the tty is allocated, and nothing else. 743 */ 744 tty_free(sc->sc_tty); 745 return 0; 746 } 747 748 /* Free the receive buffer. */ 749 free(sc->sc_rbuf, M_DEVBUF); 750 751 /* Detach and free the tty. */ 752 tty_detach(sc->sc_tty); 753 tty_free(sc->sc_tty); 754 755 /* Unhook the soft interrupt handler. */ 756 softint_disestablish(sc->sc_si); 757 758 #ifdef RND_COM 759 /* Unhook the entropy source. */ 760 rnd_detach_source(&sc->rnd_source); 761 #endif 762 callout_destroy(&sc->sc_diag_callout); 763 764 /* Destroy the lock. */ 765 mutex_destroy(&sc->sc_lock); 766 767 return (0); 768 } 769 770 void 771 com_shutdown(struct com_softc *sc) 772 { 773 struct tty *tp = sc->sc_tty; 774 775 mutex_spin_enter(&sc->sc_lock); 776 777 /* If we were asserting flow control, then deassert it. */ 778 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 779 com_hwiflow(sc); 780 781 /* Clear any break condition set with TIOCSBRK. */ 782 com_break(sc, 0); 783 784 /* 785 * Hang up if necessary. Wait a bit, so the other side has time to 786 * notice even if we immediately open the port again. 787 * Avoid tsleeping above splhigh(). 788 */ 789 if (ISSET(tp->t_cflag, HUPCL)) { 790 com_modem(sc, 0); 791 mutex_spin_exit(&sc->sc_lock); 792 /* XXX will only timeout */ 793 (void) kpause(ttclos, false, hz, NULL); 794 mutex_spin_enter(&sc->sc_lock); 795 } 796 797 /* Turn off interrupts. */ 798 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 799 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 800 if (sc->sc_type == COM_TYPE_PXA2x0) 801 sc->sc_ier |= IER_ERXTOUT; 802 } else 803 sc->sc_ier = 0; 804 805 if (sc->sc_type == COM_TYPE_PXA2x0) 806 sc->sc_ier |= IER_EUART; 807 808 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 809 810 mutex_spin_exit(&sc->sc_lock); 811 812 if (sc->disable) { 813 #ifdef DIAGNOSTIC 814 if (!sc->enabled) 815 panic("com_shutdown: not enabled?"); 816 #endif 817 (*sc->disable)(sc); 818 sc->enabled = 0; 819 } 820 } 821 822 int 823 comopen(dev_t dev, int flag, int mode, struct lwp *l) 824 { 825 struct com_softc *sc; 826 struct tty *tp; 827 int s; 828 int error; 829 830 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 831 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 832 sc->sc_rbuf == NULL) 833 return (ENXIO); 834 835 if (!device_is_active(sc->sc_dev)) 836 return (ENXIO); 837 838 #ifdef KGDB 839 /* 840 * If this is the kgdb port, no other use is permitted. 841 */ 842 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 843 return (EBUSY); 844 #endif 845 846 tp = sc->sc_tty; 847 848 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 849 return (EBUSY); 850 851 s = spltty(); 852 853 /* 854 * Do the following iff this is a first open. 855 */ 856 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 857 struct termios t; 858 859 tp->t_dev = dev; 860 861 if (sc->enable) { 862 if ((*sc->enable)(sc)) { 863 splx(s); 864 aprint_error_dev(sc->sc_dev, 865 "device enable failed\n"); 866 return (EIO); 867 } 868 mutex_spin_enter(&sc->sc_lock); 869 sc->enabled = 1; 870 com_config(sc); 871 } else { 872 mutex_spin_enter(&sc->sc_lock); 873 } 874 875 /* Turn on interrupts. */ 876 sc->sc_ier = IER_ERXRDY | IER_ERLS; 877 if (!ISSET(tp->t_cflag, CLOCAL)) 878 sc->sc_ier |= IER_EMSC; 879 880 if (sc->sc_type == COM_TYPE_PXA2x0) 881 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 882 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 883 884 /* Fetch the current modem control status, needed later. */ 885 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 886 887 /* Clear PPS capture state on first open. */ 888 mutex_spin_enter(&timecounter_lock); 889 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 890 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 891 pps_init(&sc->sc_pps_state); 892 mutex_spin_exit(&timecounter_lock); 893 894 mutex_spin_exit(&sc->sc_lock); 895 896 /* 897 * Initialize the termios status to the defaults. Add in the 898 * sticky bits from TIOCSFLAGS. 899 */ 900 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 901 t.c_ospeed = comcons_info.rate; 902 t.c_cflag = comcons_info.cflag; 903 } else { 904 t.c_ospeed = TTYDEF_SPEED; 905 t.c_cflag = TTYDEF_CFLAG; 906 } 907 t.c_ispeed = t.c_ospeed; 908 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 909 SET(t.c_cflag, CLOCAL); 910 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 911 SET(t.c_cflag, CRTSCTS); 912 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 913 SET(t.c_cflag, MDMBUF); 914 /* Make sure comparam() will do something. */ 915 tp->t_ospeed = 0; 916 (void) comparam(tp, &t); 917 tp->t_iflag = TTYDEF_IFLAG; 918 tp->t_oflag = TTYDEF_OFLAG; 919 tp->t_lflag = TTYDEF_LFLAG; 920 ttychars(tp); 921 ttsetwater(tp); 922 923 mutex_spin_enter(&sc->sc_lock); 924 925 /* 926 * Turn on DTR. We must always do this, even if carrier is not 927 * present, because otherwise we'd have to use TIOCSDTR 928 * immediately after setting CLOCAL, which applications do not 929 * expect. We always assert DTR while the device is open 930 * unless explicitly requested to deassert it. 931 */ 932 com_modem(sc, 1); 933 934 /* Clear the input ring, and unblock. */ 935 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 936 sc->sc_rbavail = com_rbuf_size; 937 com_iflush(sc); 938 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 939 com_hwiflow(sc); 940 941 #ifdef COM_DEBUG 942 if (com_debug) 943 comstatus(sc, "comopen "); 944 #endif 945 946 mutex_spin_exit(&sc->sc_lock); 947 } 948 949 splx(s); 950 951 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 952 if (error) 953 goto bad; 954 955 error = (*tp->t_linesw->l_open)(dev, tp); 956 if (error) 957 goto bad; 958 959 return (0); 960 961 bad: 962 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 963 /* 964 * We failed to open the device, and nobody else had it opened. 965 * Clean up the state as appropriate. 966 */ 967 com_shutdown(sc); 968 } 969 970 return (error); 971 } 972 973 int 974 comclose(dev_t dev, int flag, int mode, struct lwp *l) 975 { 976 struct com_softc *sc = 977 device_lookup_private(&com_cd, COMUNIT(dev)); 978 struct tty *tp = sc->sc_tty; 979 980 /* XXX This is for cons.c. */ 981 if (!ISSET(tp->t_state, TS_ISOPEN)) 982 return (0); 983 984 (*tp->t_linesw->l_close)(tp, flag); 985 ttyclose(tp); 986 987 if (COM_ISALIVE(sc) == 0) 988 return (0); 989 990 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 991 /* 992 * Although we got a last close, the device may still be in 993 * use; e.g. if this was the dialout node, and there are still 994 * processes waiting for carrier on the non-dialout node. 995 */ 996 com_shutdown(sc); 997 } 998 999 return (0); 1000 } 1001 1002 int 1003 comread(dev_t dev, struct uio *uio, int flag) 1004 { 1005 struct com_softc *sc = 1006 device_lookup_private(&com_cd, COMUNIT(dev)); 1007 struct tty *tp = sc->sc_tty; 1008 1009 if (COM_ISALIVE(sc) == 0) 1010 return (EIO); 1011 1012 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1013 } 1014 1015 int 1016 comwrite(dev_t dev, struct uio *uio, int flag) 1017 { 1018 struct com_softc *sc = 1019 device_lookup_private(&com_cd, COMUNIT(dev)); 1020 struct tty *tp = sc->sc_tty; 1021 1022 if (COM_ISALIVE(sc) == 0) 1023 return (EIO); 1024 1025 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1026 } 1027 1028 int 1029 compoll(dev_t dev, int events, struct lwp *l) 1030 { 1031 struct com_softc *sc = 1032 device_lookup_private(&com_cd, COMUNIT(dev)); 1033 struct tty *tp = sc->sc_tty; 1034 1035 if (COM_ISALIVE(sc) == 0) 1036 return (POLLHUP); 1037 1038 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1039 } 1040 1041 struct tty * 1042 comtty(dev_t dev) 1043 { 1044 struct com_softc *sc = 1045 device_lookup_private(&com_cd, COMUNIT(dev)); 1046 struct tty *tp = sc->sc_tty; 1047 1048 return (tp); 1049 } 1050 1051 int 1052 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1053 { 1054 struct com_softc *sc; 1055 struct tty *tp; 1056 int error; 1057 1058 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1059 if (sc == NULL) 1060 return ENXIO; 1061 if (COM_ISALIVE(sc) == 0) 1062 return (EIO); 1063 1064 tp = sc->sc_tty; 1065 1066 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1067 if (error != EPASSTHROUGH) 1068 return (error); 1069 1070 error = ttioctl(tp, cmd, data, flag, l); 1071 if (error != EPASSTHROUGH) 1072 return (error); 1073 1074 error = 0; 1075 switch (cmd) { 1076 case TIOCSFLAGS: 1077 error = kauth_authorize_device_tty(l->l_cred, 1078 KAUTH_DEVICE_TTY_PRIVSET, tp); 1079 break; 1080 default: 1081 /* nothing */ 1082 break; 1083 } 1084 if (error) { 1085 return error; 1086 } 1087 1088 mutex_spin_enter(&sc->sc_lock); 1089 1090 switch (cmd) { 1091 case TIOCSBRK: 1092 com_break(sc, 1); 1093 break; 1094 1095 case TIOCCBRK: 1096 com_break(sc, 0); 1097 break; 1098 1099 case TIOCSDTR: 1100 com_modem(sc, 1); 1101 break; 1102 1103 case TIOCCDTR: 1104 com_modem(sc, 0); 1105 break; 1106 1107 case TIOCGFLAGS: 1108 *(int *)data = sc->sc_swflags; 1109 break; 1110 1111 case TIOCSFLAGS: 1112 sc->sc_swflags = *(int *)data; 1113 break; 1114 1115 case TIOCMSET: 1116 case TIOCMBIS: 1117 case TIOCMBIC: 1118 tiocm_to_com(sc, cmd, *(int *)data); 1119 break; 1120 1121 case TIOCMGET: 1122 *(int *)data = com_to_tiocm(sc); 1123 break; 1124 1125 case PPS_IOC_CREATE: 1126 case PPS_IOC_DESTROY: 1127 case PPS_IOC_GETPARAMS: 1128 case PPS_IOC_SETPARAMS: 1129 case PPS_IOC_GETCAP: 1130 case PPS_IOC_FETCH: 1131 #ifdef PPS_SYNC 1132 case PPS_IOC_KCBIND: 1133 #endif 1134 mutex_spin_enter(&timecounter_lock); 1135 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1136 mutex_spin_exit(&timecounter_lock); 1137 break; 1138 1139 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1140 mutex_spin_enter(&timecounter_lock); 1141 #ifndef PPS_TRAILING_EDGE 1142 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1143 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1144 #else 1145 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1146 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1147 #endif 1148 mutex_spin_exit(&timecounter_lock); 1149 break; 1150 1151 default: 1152 error = EPASSTHROUGH; 1153 break; 1154 } 1155 1156 mutex_spin_exit(&sc->sc_lock); 1157 1158 #ifdef COM_DEBUG 1159 if (com_debug) 1160 comstatus(sc, "comioctl "); 1161 #endif 1162 1163 return (error); 1164 } 1165 1166 integrate void 1167 com_schedrx(struct com_softc *sc) 1168 { 1169 1170 sc->sc_rx_ready = 1; 1171 1172 /* Wake up the poller. */ 1173 softint_schedule(sc->sc_si); 1174 } 1175 1176 void 1177 com_break(struct com_softc *sc, int onoff) 1178 { 1179 1180 if (onoff) 1181 SET(sc->sc_lcr, LCR_SBREAK); 1182 else 1183 CLR(sc->sc_lcr, LCR_SBREAK); 1184 1185 if (!sc->sc_heldchange) { 1186 if (sc->sc_tx_busy) { 1187 sc->sc_heldtbc = sc->sc_tbc; 1188 sc->sc_tbc = 0; 1189 sc->sc_heldchange = 1; 1190 } else 1191 com_loadchannelregs(sc); 1192 } 1193 } 1194 1195 void 1196 com_modem(struct com_softc *sc, int onoff) 1197 { 1198 1199 if (sc->sc_mcr_dtr == 0) 1200 return; 1201 1202 if (onoff) 1203 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1204 else 1205 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1206 1207 if (!sc->sc_heldchange) { 1208 if (sc->sc_tx_busy) { 1209 sc->sc_heldtbc = sc->sc_tbc; 1210 sc->sc_tbc = 0; 1211 sc->sc_heldchange = 1; 1212 } else 1213 com_loadchannelregs(sc); 1214 } 1215 } 1216 1217 void 1218 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1219 { 1220 u_char combits; 1221 1222 combits = 0; 1223 if (ISSET(ttybits, TIOCM_DTR)) 1224 SET(combits, MCR_DTR); 1225 if (ISSET(ttybits, TIOCM_RTS)) 1226 SET(combits, MCR_RTS); 1227 1228 switch (how) { 1229 case TIOCMBIC: 1230 CLR(sc->sc_mcr, combits); 1231 break; 1232 1233 case TIOCMBIS: 1234 SET(sc->sc_mcr, combits); 1235 break; 1236 1237 case TIOCMSET: 1238 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1239 SET(sc->sc_mcr, combits); 1240 break; 1241 } 1242 1243 if (!sc->sc_heldchange) { 1244 if (sc->sc_tx_busy) { 1245 sc->sc_heldtbc = sc->sc_tbc; 1246 sc->sc_tbc = 0; 1247 sc->sc_heldchange = 1; 1248 } else 1249 com_loadchannelregs(sc); 1250 } 1251 } 1252 1253 int 1254 com_to_tiocm(struct com_softc *sc) 1255 { 1256 u_char combits; 1257 int ttybits = 0; 1258 1259 combits = sc->sc_mcr; 1260 if (ISSET(combits, MCR_DTR)) 1261 SET(ttybits, TIOCM_DTR); 1262 if (ISSET(combits, MCR_RTS)) 1263 SET(ttybits, TIOCM_RTS); 1264 1265 combits = sc->sc_msr; 1266 if (ISSET(combits, MSR_DCD)) 1267 SET(ttybits, TIOCM_CD); 1268 if (ISSET(combits, MSR_CTS)) 1269 SET(ttybits, TIOCM_CTS); 1270 if (ISSET(combits, MSR_DSR)) 1271 SET(ttybits, TIOCM_DSR); 1272 if (ISSET(combits, MSR_RI | MSR_TERI)) 1273 SET(ttybits, TIOCM_RI); 1274 1275 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1276 SET(ttybits, TIOCM_LE); 1277 1278 return (ttybits); 1279 } 1280 1281 static u_char 1282 cflag2lcr(tcflag_t cflag) 1283 { 1284 u_char lcr = 0; 1285 1286 switch (ISSET(cflag, CSIZE)) { 1287 case CS5: 1288 SET(lcr, LCR_5BITS); 1289 break; 1290 case CS6: 1291 SET(lcr, LCR_6BITS); 1292 break; 1293 case CS7: 1294 SET(lcr, LCR_7BITS); 1295 break; 1296 case CS8: 1297 SET(lcr, LCR_8BITS); 1298 break; 1299 } 1300 if (ISSET(cflag, PARENB)) { 1301 SET(lcr, LCR_PENAB); 1302 if (!ISSET(cflag, PARODD)) 1303 SET(lcr, LCR_PEVEN); 1304 } 1305 if (ISSET(cflag, CSTOPB)) 1306 SET(lcr, LCR_STOPB); 1307 1308 return (lcr); 1309 } 1310 1311 int 1312 comparam(struct tty *tp, struct termios *t) 1313 { 1314 struct com_softc *sc = 1315 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1316 int ospeed; 1317 u_char lcr; 1318 1319 if (COM_ISALIVE(sc) == 0) 1320 return (EIO); 1321 1322 #ifdef COM_HAYESP 1323 if (sc->sc_type == COM_TYPE_HAYESP) { 1324 int prescaler, speed; 1325 1326 /* 1327 * Calculate UART clock prescaler. It should be in 1328 * range of 0 .. 3. 1329 */ 1330 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1331 prescaler++, speed /= 2) 1332 if ((ospeed = comspeed(speed, sc->sc_frequency, 1333 sc->sc_type)) > 0) 1334 break; 1335 1336 if (prescaler == 4) 1337 return (EINVAL); 1338 sc->sc_prescaler = prescaler; 1339 } else 1340 #endif 1341 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1342 1343 /* Check requested parameters. */ 1344 if (ospeed < 0) 1345 return (EINVAL); 1346 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1347 return (EINVAL); 1348 1349 /* 1350 * For the console, always force CLOCAL and !HUPCL, so that the port 1351 * is always active. 1352 */ 1353 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1354 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1355 SET(t->c_cflag, CLOCAL); 1356 CLR(t->c_cflag, HUPCL); 1357 } 1358 1359 /* 1360 * If there were no changes, don't do anything. This avoids dropping 1361 * input and improves performance when all we did was frob things like 1362 * VMIN and VTIME. 1363 */ 1364 if (tp->t_ospeed == t->c_ospeed && 1365 tp->t_cflag == t->c_cflag) 1366 return (0); 1367 1368 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1369 1370 mutex_spin_enter(&sc->sc_lock); 1371 1372 sc->sc_lcr = lcr; 1373 1374 /* 1375 * If we're not in a mode that assumes a connection is present, then 1376 * ignore carrier changes. 1377 */ 1378 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1379 sc->sc_msr_dcd = 0; 1380 else 1381 sc->sc_msr_dcd = MSR_DCD; 1382 /* 1383 * Set the flow control pins depending on the current flow control 1384 * mode. 1385 */ 1386 if (ISSET(t->c_cflag, CRTSCTS)) { 1387 sc->sc_mcr_dtr = MCR_DTR; 1388 sc->sc_mcr_rts = MCR_RTS; 1389 sc->sc_msr_cts = MSR_CTS; 1390 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1391 SET(sc->sc_mcr, MCR_AFE); 1392 } else { 1393 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1394 } 1395 } else if (ISSET(t->c_cflag, MDMBUF)) { 1396 /* 1397 * For DTR/DCD flow control, make sure we don't toggle DTR for 1398 * carrier detection. 1399 */ 1400 sc->sc_mcr_dtr = 0; 1401 sc->sc_mcr_rts = MCR_DTR; 1402 sc->sc_msr_cts = MSR_DCD; 1403 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1404 CLR(sc->sc_mcr, MCR_AFE); 1405 } else { 1406 sc->sc_efr = 0; 1407 } 1408 } else { 1409 /* 1410 * If no flow control, then always set RTS. This will make 1411 * the other side happy if it mistakenly thinks we're doing 1412 * RTS/CTS flow control. 1413 */ 1414 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1415 sc->sc_mcr_rts = 0; 1416 sc->sc_msr_cts = 0; 1417 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1418 CLR(sc->sc_mcr, MCR_AFE); 1419 } else { 1420 sc->sc_efr = 0; 1421 } 1422 if (ISSET(sc->sc_mcr, MCR_DTR)) 1423 SET(sc->sc_mcr, MCR_RTS); 1424 else 1425 CLR(sc->sc_mcr, MCR_RTS); 1426 } 1427 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1428 1429 #if 0 1430 if (ospeed == 0) 1431 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1432 else 1433 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1434 #endif 1435 1436 sc->sc_dlbl = ospeed; 1437 sc->sc_dlbh = ospeed >> 8; 1438 1439 /* 1440 * Set the FIFO threshold based on the receive speed. 1441 * 1442 * * If it's a low speed, it's probably a mouse or some other 1443 * interactive device, so set the threshold low. 1444 * * If it's a high speed, trim the trigger level down to prevent 1445 * overflows. 1446 * * Otherwise set it a bit higher. 1447 */ 1448 if (sc->sc_type == COM_TYPE_HAYESP) 1449 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1450 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1451 if (t->c_ospeed <= 1200) 1452 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1453 else if (t->c_ospeed <= 38400) 1454 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1455 else 1456 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1457 } else 1458 sc->sc_fifo = 0; 1459 1460 /* And copy to tty. */ 1461 tp->t_ispeed = t->c_ospeed; 1462 tp->t_ospeed = t->c_ospeed; 1463 tp->t_cflag = t->c_cflag; 1464 1465 if (!sc->sc_heldchange) { 1466 if (sc->sc_tx_busy) { 1467 sc->sc_heldtbc = sc->sc_tbc; 1468 sc->sc_tbc = 0; 1469 sc->sc_heldchange = 1; 1470 } else 1471 com_loadchannelregs(sc); 1472 } 1473 1474 if (!ISSET(t->c_cflag, CHWFLOW)) { 1475 /* Disable the high water mark. */ 1476 sc->sc_r_hiwat = 0; 1477 sc->sc_r_lowat = 0; 1478 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1479 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1480 com_schedrx(sc); 1481 } 1482 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1483 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1484 com_hwiflow(sc); 1485 } 1486 } else { 1487 sc->sc_r_hiwat = com_rbuf_hiwat; 1488 sc->sc_r_lowat = com_rbuf_lowat; 1489 } 1490 1491 mutex_spin_exit(&sc->sc_lock); 1492 1493 /* 1494 * Update the tty layer's idea of the carrier bit, in case we changed 1495 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1496 * explicit request. 1497 */ 1498 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1499 1500 #ifdef COM_DEBUG 1501 if (com_debug) 1502 comstatus(sc, "comparam "); 1503 #endif 1504 1505 if (!ISSET(t->c_cflag, CHWFLOW)) { 1506 if (sc->sc_tx_stopped) { 1507 sc->sc_tx_stopped = 0; 1508 comstart(tp); 1509 } 1510 } 1511 1512 return (0); 1513 } 1514 1515 void 1516 com_iflush(struct com_softc *sc) 1517 { 1518 struct com_regs *regsp = &sc->sc_regs; 1519 #ifdef DIAGNOSTIC 1520 int reg; 1521 #endif 1522 int timo; 1523 1524 #ifdef DIAGNOSTIC 1525 reg = 0xffff; 1526 #endif 1527 timo = 50000; 1528 /* flush any pending I/O */ 1529 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1530 && --timo) 1531 #ifdef DIAGNOSTIC 1532 reg = 1533 #else 1534 (void) 1535 #endif 1536 CSR_READ_1(regsp, COM_REG_RXDATA); 1537 #ifdef DIAGNOSTIC 1538 if (!timo) 1539 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1540 #endif 1541 1542 #ifdef COM_16750 1543 uint8_t fifo; 1544 /* 1545 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1546 * This should prevent triggering busy interrupt while 1547 * manipulating divisors. 1548 */ 1549 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1550 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1551 CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST | 1552 FIFO_XMT_RST); 1553 delay(100); 1554 #endif 1555 } 1556 1557 void 1558 com_loadchannelregs(struct com_softc *sc) 1559 { 1560 struct com_regs *regsp = &sc->sc_regs; 1561 1562 /* XXXXX necessary? */ 1563 com_iflush(sc); 1564 1565 if (sc->sc_type == COM_TYPE_PXA2x0) 1566 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1567 else 1568 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1569 1570 if (sc->sc_type == COM_TYPE_OMAP) { 1571 /* disable before changing settings */ 1572 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1573 } 1574 1575 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1576 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1577 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1578 /* no EFR on alchemy */ 1579 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1580 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1581 } 1582 if (sc->sc_type == COM_TYPE_AU1x00) { 1583 /* alchemy has single separate 16-bit clock divisor register */ 1584 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1585 (sc->sc_dlbh << 8)); 1586 } else { 1587 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1588 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1589 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1590 } 1591 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1592 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1593 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1594 #ifdef COM_HAYESP 1595 if (sc->sc_type == COM_TYPE_HAYESP) { 1596 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1597 HAYESP_SETPRESCALER); 1598 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1599 sc->sc_prescaler); 1600 } 1601 #endif 1602 if (sc->sc_type == COM_TYPE_OMAP) { 1603 /* setup the fifos. the FCR value is not used as long 1604 as SCR[6] and SCR[7] are 0, which they are at reset 1605 and we never touch the SCR register */ 1606 uint8_t rx_fifo_trig = 40; 1607 uint8_t tx_fifo_trig = 60; 1608 uint8_t rx_start = 8; 1609 uint8_t rx_halt = 60; 1610 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1611 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1612 1613 /* enable access to TCR & TLR */ 1614 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1615 1616 /* write tcr and tlr values */ 1617 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1618 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1619 1620 /* disable access to TCR & TLR */ 1621 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1622 1623 /* enable again, but mode is based on speed */ 1624 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1625 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1626 } else { 1627 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1628 } 1629 } 1630 1631 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1632 } 1633 1634 int 1635 comhwiflow(struct tty *tp, int block) 1636 { 1637 struct com_softc *sc = 1638 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1639 1640 if (COM_ISALIVE(sc) == 0) 1641 return (0); 1642 1643 if (sc->sc_mcr_rts == 0) 1644 return (0); 1645 1646 mutex_spin_enter(&sc->sc_lock); 1647 1648 if (block) { 1649 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1650 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1651 com_hwiflow(sc); 1652 } 1653 } else { 1654 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1655 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1656 com_schedrx(sc); 1657 } 1658 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1659 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1660 com_hwiflow(sc); 1661 } 1662 } 1663 1664 mutex_spin_exit(&sc->sc_lock); 1665 return (1); 1666 } 1667 1668 /* 1669 * (un)block input via hw flowcontrol 1670 */ 1671 void 1672 com_hwiflow(struct com_softc *sc) 1673 { 1674 struct com_regs *regsp= &sc->sc_regs; 1675 1676 if (sc->sc_mcr_rts == 0) 1677 return; 1678 1679 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1680 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1681 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1682 } else { 1683 SET(sc->sc_mcr, sc->sc_mcr_rts); 1684 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1685 } 1686 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1687 } 1688 1689 1690 void 1691 comstart(struct tty *tp) 1692 { 1693 struct com_softc *sc = 1694 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1695 struct com_regs *regsp = &sc->sc_regs; 1696 int s; 1697 1698 if (COM_ISALIVE(sc) == 0) 1699 return; 1700 1701 s = spltty(); 1702 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1703 goto out; 1704 if (sc->sc_tx_stopped) 1705 goto out; 1706 if (!ttypull(tp)) 1707 goto out; 1708 1709 /* Grab the first contiguous region of buffer space. */ 1710 { 1711 u_char *tba; 1712 int tbc; 1713 1714 tba = tp->t_outq.c_cf; 1715 tbc = ndqb(&tp->t_outq, 0); 1716 1717 mutex_spin_enter(&sc->sc_lock); 1718 1719 sc->sc_tba = tba; 1720 sc->sc_tbc = tbc; 1721 } 1722 1723 SET(tp->t_state, TS_BUSY); 1724 sc->sc_tx_busy = 1; 1725 1726 /* Enable transmit completion interrupts if necessary. */ 1727 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1728 SET(sc->sc_ier, IER_ETXRDY); 1729 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1730 } 1731 1732 /* Output the first chunk of the contiguous buffer. */ 1733 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1734 u_int n; 1735 1736 n = sc->sc_tbc; 1737 if (n > sc->sc_fifolen) 1738 n = sc->sc_fifolen; 1739 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1740 sc->sc_tbc -= n; 1741 sc->sc_tba += n; 1742 } 1743 1744 mutex_spin_exit(&sc->sc_lock); 1745 out: 1746 splx(s); 1747 return; 1748 } 1749 1750 /* 1751 * Stop output on a line. 1752 */ 1753 void 1754 comstop(struct tty *tp, int flag) 1755 { 1756 struct com_softc *sc = 1757 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1758 1759 mutex_spin_enter(&sc->sc_lock); 1760 if (ISSET(tp->t_state, TS_BUSY)) { 1761 /* Stop transmitting at the next chunk. */ 1762 sc->sc_tbc = 0; 1763 sc->sc_heldtbc = 0; 1764 if (!ISSET(tp->t_state, TS_TTSTOP)) 1765 SET(tp->t_state, TS_FLUSH); 1766 } 1767 mutex_spin_exit(&sc->sc_lock); 1768 } 1769 1770 void 1771 comdiag(void *arg) 1772 { 1773 struct com_softc *sc = arg; 1774 int overflows, floods; 1775 1776 mutex_spin_enter(&sc->sc_lock); 1777 overflows = sc->sc_overflows; 1778 sc->sc_overflows = 0; 1779 floods = sc->sc_floods; 1780 sc->sc_floods = 0; 1781 sc->sc_errors = 0; 1782 mutex_spin_exit(&sc->sc_lock); 1783 1784 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1785 device_xname(sc->sc_dev), 1786 overflows, overflows == 1 ? "" : "s", 1787 floods, floods == 1 ? "" : "s"); 1788 } 1789 1790 integrate void 1791 com_rxsoft(struct com_softc *sc, struct tty *tp) 1792 { 1793 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1794 u_char *get, *end; 1795 u_int cc, scc; 1796 u_char lsr; 1797 int code; 1798 1799 end = sc->sc_ebuf; 1800 get = sc->sc_rbget; 1801 scc = cc = com_rbuf_size - sc->sc_rbavail; 1802 1803 if (cc == com_rbuf_size) { 1804 sc->sc_floods++; 1805 if (sc->sc_errors++ == 0) 1806 callout_reset(&sc->sc_diag_callout, 60 * hz, 1807 comdiag, sc); 1808 } 1809 1810 /* If not yet open, drop the entire buffer content here */ 1811 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1812 get += cc << 1; 1813 if (get >= end) 1814 get -= com_rbuf_size << 1; 1815 cc = 0; 1816 } 1817 while (cc) { 1818 code = get[0]; 1819 lsr = get[1]; 1820 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1821 if (ISSET(lsr, LSR_OE)) { 1822 sc->sc_overflows++; 1823 if (sc->sc_errors++ == 0) 1824 callout_reset(&sc->sc_diag_callout, 1825 60 * hz, comdiag, sc); 1826 } 1827 if (ISSET(lsr, LSR_BI | LSR_FE)) 1828 SET(code, TTY_FE); 1829 if (ISSET(lsr, LSR_PE)) 1830 SET(code, TTY_PE); 1831 } 1832 if ((*rint)(code, tp) == -1) { 1833 /* 1834 * The line discipline's buffer is out of space. 1835 */ 1836 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1837 /* 1838 * We're either not using flow control, or the 1839 * line discipline didn't tell us to block for 1840 * some reason. Either way, we have no way to 1841 * know when there's more space available, so 1842 * just drop the rest of the data. 1843 */ 1844 get += cc << 1; 1845 if (get >= end) 1846 get -= com_rbuf_size << 1; 1847 cc = 0; 1848 } else { 1849 /* 1850 * Don't schedule any more receive processing 1851 * until the line discipline tells us there's 1852 * space available (through comhwiflow()). 1853 * Leave the rest of the data in the input 1854 * buffer. 1855 */ 1856 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1857 } 1858 break; 1859 } 1860 get += 2; 1861 if (get >= end) 1862 get = sc->sc_rbuf; 1863 cc--; 1864 } 1865 1866 if (cc != scc) { 1867 sc->sc_rbget = get; 1868 mutex_spin_enter(&sc->sc_lock); 1869 1870 cc = sc->sc_rbavail += scc - cc; 1871 /* Buffers should be ok again, release possible block. */ 1872 if (cc >= sc->sc_r_lowat) { 1873 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1874 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1875 SET(sc->sc_ier, IER_ERXRDY); 1876 #ifdef COM_PXA2X0 1877 if (sc->sc_type == COM_TYPE_PXA2x0) 1878 SET(sc->sc_ier, IER_ERXTOUT); 1879 #endif 1880 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1881 } 1882 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1883 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1884 com_hwiflow(sc); 1885 } 1886 } 1887 mutex_spin_exit(&sc->sc_lock); 1888 } 1889 } 1890 1891 integrate void 1892 com_txsoft(struct com_softc *sc, struct tty *tp) 1893 { 1894 1895 CLR(tp->t_state, TS_BUSY); 1896 if (ISSET(tp->t_state, TS_FLUSH)) 1897 CLR(tp->t_state, TS_FLUSH); 1898 else 1899 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1900 (*tp->t_linesw->l_start)(tp); 1901 } 1902 1903 integrate void 1904 com_stsoft(struct com_softc *sc, struct tty *tp) 1905 { 1906 u_char msr, delta; 1907 1908 mutex_spin_enter(&sc->sc_lock); 1909 msr = sc->sc_msr; 1910 delta = sc->sc_msr_delta; 1911 sc->sc_msr_delta = 0; 1912 mutex_spin_exit(&sc->sc_lock); 1913 1914 if (ISSET(delta, sc->sc_msr_dcd)) { 1915 /* 1916 * Inform the tty layer that carrier detect changed. 1917 */ 1918 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1919 } 1920 1921 if (ISSET(delta, sc->sc_msr_cts)) { 1922 /* Block or unblock output according to flow control. */ 1923 if (ISSET(msr, sc->sc_msr_cts)) { 1924 sc->sc_tx_stopped = 0; 1925 (*tp->t_linesw->l_start)(tp); 1926 } else { 1927 sc->sc_tx_stopped = 1; 1928 } 1929 } 1930 1931 #ifdef COM_DEBUG 1932 if (com_debug) 1933 comstatus(sc, "com_stsoft"); 1934 #endif 1935 } 1936 1937 void 1938 comsoft(void *arg) 1939 { 1940 struct com_softc *sc = arg; 1941 struct tty *tp; 1942 1943 if (COM_ISALIVE(sc) == 0) 1944 return; 1945 1946 tp = sc->sc_tty; 1947 1948 if (sc->sc_rx_ready) { 1949 sc->sc_rx_ready = 0; 1950 com_rxsoft(sc, tp); 1951 } 1952 1953 if (sc->sc_st_check) { 1954 sc->sc_st_check = 0; 1955 com_stsoft(sc, tp); 1956 } 1957 1958 if (sc->sc_tx_done) { 1959 sc->sc_tx_done = 0; 1960 com_txsoft(sc, tp); 1961 } 1962 } 1963 1964 int 1965 comintr(void *arg) 1966 { 1967 struct com_softc *sc = arg; 1968 struct com_regs *regsp = &sc->sc_regs; 1969 1970 u_char *put, *end; 1971 u_int cc; 1972 u_char lsr, iir; 1973 1974 if (COM_ISALIVE(sc) == 0) 1975 return (0); 1976 1977 KASSERT(regsp != NULL); 1978 1979 mutex_spin_enter(&sc->sc_lock); 1980 iir = CSR_READ_1(regsp, COM_REG_IIR); 1981 1982 /* Handle ns16750-specific busy interrupt. */ 1983 #ifdef COM_16750 1984 int timeout; 1985 if ((iir & IIR_BUSY) == IIR_BUSY) { 1986 for (timeout = 10000; 1987 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 1988 if (timeout <= 0) { 1989 aprint_error_dev(sc->sc_dev, 1990 "timeout while waiting for BUSY interrupt " 1991 "acknowledge\n"); 1992 mutex_spin_exit(&sc->sc_lock); 1993 return (0); 1994 } 1995 1996 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1997 iir = CSR_READ_1(regsp, COM_REG_IIR); 1998 } 1999 #endif /* COM_16750 */ 2000 2001 2002 if (ISSET(iir, IIR_NOPEND)) { 2003 mutex_spin_exit(&sc->sc_lock); 2004 return (0); 2005 } 2006 2007 end = sc->sc_ebuf; 2008 put = sc->sc_rbput; 2009 cc = sc->sc_rbavail; 2010 2011 again: do { 2012 u_char msr, delta; 2013 2014 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2015 if (ISSET(lsr, LSR_BI)) { 2016 int cn_trapped = 0; /* see above: cn_trap() */ 2017 2018 cn_check_magic(sc->sc_tty->t_dev, 2019 CNC_BREAK, com_cnm_state); 2020 if (cn_trapped) 2021 continue; 2022 #if defined(KGDB) && !defined(DDB) 2023 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2024 kgdb_connect(1); 2025 continue; 2026 } 2027 #endif 2028 } 2029 2030 if (ISSET(lsr, LSR_RCV_MASK) && 2031 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2032 while (cc > 0) { 2033 int cn_trapped = 0; 2034 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2035 put[1] = lsr; 2036 cn_check_magic(sc->sc_tty->t_dev, 2037 put[0], com_cnm_state); 2038 if (cn_trapped) 2039 goto next; 2040 put += 2; 2041 if (put >= end) 2042 put = sc->sc_rbuf; 2043 cc--; 2044 next: 2045 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2046 if (!ISSET(lsr, LSR_RCV_MASK)) 2047 break; 2048 } 2049 2050 /* 2051 * Current string of incoming characters ended because 2052 * no more data was available or we ran out of space. 2053 * Schedule a receive event if any data was received. 2054 * If we're out of space, turn off receive interrupts. 2055 */ 2056 sc->sc_rbput = put; 2057 sc->sc_rbavail = cc; 2058 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2059 sc->sc_rx_ready = 1; 2060 2061 /* 2062 * See if we are in danger of overflowing a buffer. If 2063 * so, use hardware flow control to ease the pressure. 2064 */ 2065 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2066 cc < sc->sc_r_hiwat) { 2067 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2068 com_hwiflow(sc); 2069 } 2070 2071 /* 2072 * If we're out of space, disable receive interrupts 2073 * until the queue has drained a bit. 2074 */ 2075 if (!cc) { 2076 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2077 #ifdef COM_PXA2X0 2078 if (sc->sc_type == COM_TYPE_PXA2x0) 2079 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2080 else 2081 #endif 2082 CLR(sc->sc_ier, IER_ERXRDY); 2083 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2084 } 2085 } else { 2086 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2087 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2088 continue; 2089 } 2090 } 2091 2092 msr = CSR_READ_1(regsp, COM_REG_MSR); 2093 delta = msr ^ sc->sc_msr; 2094 sc->sc_msr = msr; 2095 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2096 (delta & MSR_DCD)) { 2097 mutex_spin_enter(&timecounter_lock); 2098 pps_capture(&sc->sc_pps_state); 2099 pps_event(&sc->sc_pps_state, 2100 (msr & MSR_DCD) ? 2101 PPS_CAPTUREASSERT : 2102 PPS_CAPTURECLEAR); 2103 mutex_spin_exit(&timecounter_lock); 2104 } 2105 2106 /* 2107 * Process normal status changes 2108 */ 2109 if (ISSET(delta, sc->sc_msr_mask)) { 2110 SET(sc->sc_msr_delta, delta); 2111 2112 /* 2113 * Stop output immediately if we lose the output 2114 * flow control signal or carrier detect. 2115 */ 2116 if (ISSET(~msr, sc->sc_msr_mask)) { 2117 sc->sc_tbc = 0; 2118 sc->sc_heldtbc = 0; 2119 #ifdef COM_DEBUG 2120 if (com_debug) 2121 comstatus(sc, "comintr "); 2122 #endif 2123 } 2124 2125 sc->sc_st_check = 1; 2126 } 2127 } while (!ISSET((iir = 2128 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2129 /* 2130 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2131 * by IIR read, so we can't do this way: `process all interrupts, 2132 * then do TX if possible'. 2133 */ 2134 (iir & IIR_IMASK) != IIR_TXRDY); 2135 2136 /* 2137 * Read LSR again, since there may be an interrupt between 2138 * the last LSR read and IIR read above. 2139 */ 2140 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2141 2142 /* 2143 * See if data can be transmitted as well. 2144 * Schedule tx done event if no data left 2145 * and tty was marked busy. 2146 */ 2147 if (ISSET(lsr, LSR_TXRDY)) { 2148 /* 2149 * If we've delayed a parameter change, do it now, and restart 2150 * output. 2151 */ 2152 if (sc->sc_heldchange) { 2153 com_loadchannelregs(sc); 2154 sc->sc_heldchange = 0; 2155 sc->sc_tbc = sc->sc_heldtbc; 2156 sc->sc_heldtbc = 0; 2157 } 2158 2159 /* Output the next chunk of the contiguous buffer, if any. */ 2160 if (sc->sc_tbc > 0) { 2161 u_int n; 2162 2163 n = sc->sc_tbc; 2164 if (n > sc->sc_fifolen) 2165 n = sc->sc_fifolen; 2166 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2167 sc->sc_tbc -= n; 2168 sc->sc_tba += n; 2169 } else { 2170 /* Disable transmit completion interrupts if necessary. */ 2171 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2172 CLR(sc->sc_ier, IER_ETXRDY); 2173 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2174 } 2175 if (sc->sc_tx_busy) { 2176 sc->sc_tx_busy = 0; 2177 sc->sc_tx_done = 1; 2178 } 2179 } 2180 } 2181 2182 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2183 goto again; 2184 2185 mutex_spin_exit(&sc->sc_lock); 2186 2187 /* Wake up the poller. */ 2188 softint_schedule(sc->sc_si); 2189 2190 #ifdef RND_COM 2191 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2192 #endif 2193 2194 return (1); 2195 } 2196 2197 /* 2198 * The following functions are polled getc and putc routines, shared 2199 * by the console and kgdb glue. 2200 * 2201 * The read-ahead code is so that you can detect pending in-band 2202 * cn_magic in polled mode while doing output rather than having to 2203 * wait until the kernel decides it needs input. 2204 */ 2205 2206 #define MAX_READAHEAD 20 2207 static int com_readahead[MAX_READAHEAD]; 2208 static int com_readaheadcount = 0; 2209 2210 int 2211 com_common_getc(dev_t dev, struct com_regs *regsp) 2212 { 2213 int s = splserial(); 2214 u_char stat, c; 2215 2216 /* got a character from reading things earlier */ 2217 if (com_readaheadcount > 0) { 2218 int i; 2219 2220 c = com_readahead[0]; 2221 for (i = 1; i < com_readaheadcount; i++) { 2222 com_readahead[i-1] = com_readahead[i]; 2223 } 2224 com_readaheadcount--; 2225 splx(s); 2226 return (c); 2227 } 2228 2229 /* don't block until a character becomes available */ 2230 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2231 splx(s); 2232 return -1; 2233 } 2234 2235 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2236 stat = CSR_READ_1(regsp, COM_REG_IIR); 2237 { 2238 int cn_trapped = 0; /* required by cn_trap, see above */ 2239 #ifdef DDB 2240 extern int db_active; 2241 if (!db_active) 2242 #endif 2243 cn_check_magic(dev, c, com_cnm_state); 2244 } 2245 splx(s); 2246 return (c); 2247 } 2248 2249 static void 2250 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2251 { 2252 int s = splserial(); 2253 int cin, stat, timo; 2254 2255 if (com_readaheadcount < MAX_READAHEAD 2256 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2257 int cn_trapped = 0; 2258 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2259 stat = CSR_READ_1(regsp, COM_REG_IIR); 2260 cn_check_magic(dev, cin, com_cnm_state); 2261 com_readahead[com_readaheadcount++] = cin; 2262 } 2263 2264 /* wait for any pending transmission to finish */ 2265 timo = 150000; 2266 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2267 continue; 2268 2269 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2270 COM_BARRIER(regsp, BR | BW); 2271 2272 splx(s); 2273 } 2274 2275 /* 2276 * Initialize UART for use as console or KGDB line. 2277 */ 2278 int 2279 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2280 tcflag_t cflag) 2281 { 2282 2283 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2284 ®sp->cr_ioh)) 2285 return (ENOMEM); /* ??? */ 2286 2287 if (type == COM_TYPE_OMAP) { 2288 /* disable before changing settings */ 2289 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2290 } 2291 2292 rate = comspeed(rate, frequency, type); 2293 if (__predict_true(rate != -1)) { 2294 if (type == COM_TYPE_AU1x00) { 2295 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2296 } else { 2297 /* no EFR on alchemy */ 2298 if (type != COM_TYPE_16550_NOERS) { 2299 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2300 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2301 } 2302 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2303 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2304 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2305 } 2306 } 2307 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2308 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2309 CSR_WRITE_1(regsp, COM_REG_FIFO, 2310 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2311 2312 if (type == COM_TYPE_OMAP) { 2313 /* setup the fifos. the FCR value is not used as long 2314 as SCR[6] and SCR[7] are 0, which they are at reset 2315 and we never touch the SCR register */ 2316 uint8_t rx_fifo_trig = 40; 2317 uint8_t tx_fifo_trig = 60; 2318 uint8_t rx_start = 8; 2319 uint8_t rx_halt = 60; 2320 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2321 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2322 2323 /* enable access to TCR & TLR */ 2324 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2325 2326 /* write tcr and tlr values */ 2327 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2328 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2329 2330 /* disable access to TCR & TLR */ 2331 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2332 2333 /* enable again, but mode is based on speed */ 2334 if (rate > 230400) { 2335 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2336 } else { 2337 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2338 } 2339 } 2340 2341 #ifdef COM_PXA2X0 2342 if (type == COM_TYPE_PXA2x0) 2343 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2344 else 2345 #endif 2346 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2347 2348 return (0); 2349 } 2350 2351 int 2352 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2353 tcflag_t cflag) 2354 { 2355 int res; 2356 2357 comcons_info.regs = *regsp; 2358 2359 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2360 if (res) 2361 return (res); 2362 2363 cn_tab = &comcons; 2364 cn_init_magic(&com_cnm_state); 2365 cn_set_magic("\047\001"); /* default magic is BREAK */ 2366 2367 comcons_info.frequency = frequency; 2368 comcons_info.type = type; 2369 comcons_info.rate = rate; 2370 comcons_info.cflag = cflag; 2371 2372 return (0); 2373 } 2374 2375 int 2376 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2377 int type, tcflag_t cflag) 2378 { 2379 struct com_regs regs; 2380 2381 memset(®s, 0, sizeof regs); 2382 regs.cr_iot = iot; 2383 regs.cr_iobase = iobase; 2384 regs.cr_nports = COM_NPORTS; 2385 #ifdef COM_REGMAP 2386 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2387 #endif 2388 2389 return comcnattach1(®s, rate, frequency, type, cflag); 2390 } 2391 2392 static int 2393 comcnreattach(void) 2394 { 2395 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2396 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2397 } 2398 2399 int 2400 comcngetc(dev_t dev) 2401 { 2402 2403 return (com_common_getc(dev, &comcons_info.regs)); 2404 } 2405 2406 /* 2407 * Console kernel output character routine. 2408 */ 2409 void 2410 comcnputc(dev_t dev, int c) 2411 { 2412 2413 com_common_putc(dev, &comcons_info.regs, c); 2414 } 2415 2416 void 2417 comcnpollc(dev_t dev, int on) 2418 { 2419 2420 com_readaheadcount = 0; 2421 } 2422 2423 #ifdef KGDB 2424 int 2425 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2426 tcflag_t cflag) 2427 { 2428 int res; 2429 2430 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2431 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2432 #if !defined(DDB) 2433 return (EBUSY); /* cannot share with console */ 2434 #else 2435 comkgdbregs = *regsp; 2436 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2437 #endif 2438 } else { 2439 comkgdbregs = *regsp; 2440 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2441 if (res) 2442 return (res); 2443 2444 /* 2445 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2446 * expects this to be initialized 2447 */ 2448 cn_init_magic(&com_cnm_state); 2449 cn_set_magic("\047\001"); 2450 } 2451 2452 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2453 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2454 2455 return (0); 2456 } 2457 2458 int 2459 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2460 int frequency, int type, tcflag_t cflag) 2461 { 2462 struct com_regs regs; 2463 2464 regs.cr_iot = iot; 2465 regs.cr_nports = COM_NPORTS; 2466 regs.cr_iobase = iobase; 2467 #ifdef COM_REGMAP 2468 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2469 #endif 2470 2471 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2472 } 2473 2474 /* ARGSUSED */ 2475 int 2476 com_kgdb_getc(void *arg) 2477 { 2478 2479 return (com_common_getc(NODEV, &comkgdbregs)); 2480 } 2481 2482 /* ARGSUSED */ 2483 void 2484 com_kgdb_putc(void *arg, int c) 2485 { 2486 2487 com_common_putc(NODEV, &comkgdbregs, c); 2488 } 2489 #endif /* KGDB */ 2490 2491 /* helper function to identify the com ports used by 2492 console or KGDB (and not yet autoconf attached) */ 2493 int 2494 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2495 { 2496 bus_space_handle_t help; 2497 2498 if (!comconsattached && 2499 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2500 iobase == comcons_info.regs.cr_iobase) 2501 help = comcons_info.regs.cr_ioh; 2502 #ifdef KGDB 2503 else if (!com_kgdb_attached && 2504 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2505 iobase == comkgdbregs.cr_iobase) 2506 help = comkgdbregs.cr_ioh; 2507 #endif 2508 else 2509 return (0); 2510 2511 if (ioh) 2512 *ioh = help; 2513 return (1); 2514 } 2515 2516 /* 2517 * this routine exists to serve as a shutdown hook for systems that 2518 * have firmware which doesn't interact properly with a com device in 2519 * FIFO mode. 2520 */ 2521 bool 2522 com_cleanup(device_t self, int how) 2523 { 2524 struct com_softc *sc = device_private(self); 2525 2526 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2527 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2528 2529 return true; 2530 } 2531 2532 bool 2533 com_suspend(device_t self, const pmf_qual_t *qual) 2534 { 2535 struct com_softc *sc = device_private(self); 2536 2537 #if 0 2538 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2539 cn_tab = &comcons_suspend; 2540 #endif 2541 2542 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2543 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2544 2545 return true; 2546 } 2547 2548 bool 2549 com_resume(device_t self, const pmf_qual_t *qual) 2550 { 2551 struct com_softc *sc = device_private(self); 2552 2553 mutex_spin_enter(&sc->sc_lock); 2554 com_loadchannelregs(sc); 2555 mutex_spin_exit(&sc->sc_lock); 2556 2557 return true; 2558 } 2559
Indexes created Fri Sep 26 20:09:58 GMT 2025