com.c revision 1.325
1 /* $NetBSD: com.c,v 1.325 2014/04/08 00:09:15 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.325 2014/04/08 00:09:15 christos Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 (void)cn_trapped; \ 96 } while (/* CONSTCOND */ 0) 97 98 #include <sys/param.h> 99 #include <sys/systm.h> 100 #include <sys/ioctl.h> 101 #include <sys/select.h> 102 #include <sys/poll.h> 103 #include <sys/tty.h> 104 #include <sys/proc.h> 105 #include <sys/conf.h> 106 #include <sys/file.h> 107 #include <sys/uio.h> 108 #include <sys/kernel.h> 109 #include <sys/syslog.h> 110 #include <sys/device.h> 111 #include <sys/malloc.h> 112 #include <sys/timepps.h> 113 #include <sys/vnode.h> 114 #include <sys/kauth.h> 115 #include <sys/intr.h> 116 #ifdef RND_COM 117 #include <sys/rnd.h> 118 #endif 119 120 121 #include <sys/bus.h> 122 123 #include <dev/ic/comreg.h> 124 #include <dev/ic/comvar.h> 125 #include <dev/ic/ns16550reg.h> 126 #include <dev/ic/st16650reg.h> 127 #ifdef COM_HAYESP 128 #include <dev/ic/hayespreg.h> 129 #endif 130 #define com_lcr com_cfcr 131 #include <dev/cons.h> 132 133 #ifdef COM_REGMAP 134 #define CSR_WRITE_1(r, o, v) \ 135 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 136 #define CSR_READ_1(r, o) \ 137 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 138 #define CSR_WRITE_2(r, o, v) \ 139 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 140 #define CSR_READ_2(r, o) \ 141 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 142 #define CSR_WRITE_MULTI(r, o, p, n) \ 143 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 144 #else 145 #define CSR_WRITE_1(r, o, v) \ 146 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 147 #define CSR_READ_1(r, o) \ 148 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 149 #define CSR_WRITE_2(r, o, v) \ 150 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 151 #define CSR_READ_2(r, o) \ 152 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 153 #define CSR_WRITE_MULTI(r, o, p, n) \ 154 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 155 #endif 156 157 158 static void com_enable_debugport(struct com_softc *); 159 160 void com_config(struct com_softc *); 161 void com_shutdown(struct com_softc *); 162 int comspeed(long, long, int); 163 static u_char cflag2lcr(tcflag_t); 164 int comparam(struct tty *, struct termios *); 165 void comstart(struct tty *); 166 int comhwiflow(struct tty *, int); 167 168 void com_loadchannelregs(struct com_softc *); 169 void com_hwiflow(struct com_softc *); 170 void com_break(struct com_softc *, int); 171 void com_modem(struct com_softc *, int); 172 void tiocm_to_com(struct com_softc *, u_long, int); 173 int com_to_tiocm(struct com_softc *); 174 void com_iflush(struct com_softc *); 175 176 int com_common_getc(dev_t, struct com_regs *); 177 static void com_common_putc(dev_t, struct com_regs *, int); 178 179 int cominit(struct com_regs *, int, int, int, tcflag_t); 180 181 static int comcnreattach(void); 182 183 int comcngetc(dev_t); 184 void comcnputc(dev_t, int); 185 void comcnpollc(dev_t, int); 186 187 #define integrate static inline 188 void comsoft(void *); 189 integrate void com_rxsoft(struct com_softc *, struct tty *); 190 integrate void com_txsoft(struct com_softc *, struct tty *); 191 integrate void com_stsoft(struct com_softc *, struct tty *); 192 integrate void com_schedrx(struct com_softc *); 193 void comdiag(void *); 194 195 extern struct cfdriver com_cd; 196 197 dev_type_open(comopen); 198 dev_type_close(comclose); 199 dev_type_read(comread); 200 dev_type_write(comwrite); 201 dev_type_ioctl(comioctl); 202 dev_type_stop(comstop); 203 dev_type_tty(comtty); 204 dev_type_poll(compoll); 205 206 static struct comcons_info comcons_info; 207 208 /* 209 * Following are all routines needed for COM to act as console 210 */ 211 static struct consdev comcons = { 212 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 213 NODEV, CN_NORMAL 214 }; 215 216 217 const struct cdevsw com_cdevsw = { 218 .d_open = comopen, 219 .d_close = comclose, 220 .d_read = comread, 221 .d_write = comwrite, 222 .d_ioctl = comioctl, 223 .d_stop = comstop, 224 .d_tty = comtty, 225 .d_poll = compoll, 226 .d_mmap = nommap, 227 .d_kqfilter = ttykqfilter, 228 .d_flag = D_TTY 229 }; 230 231 /* 232 * Make this an option variable one can patch. 233 * But be warned: this must be a power of 2! 234 */ 235 u_int com_rbuf_size = COM_RING_SIZE; 236 237 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 238 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 239 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 240 241 static int comconsattached; 242 static struct cnm_state com_cnm_state; 243 244 #ifdef KGDB 245 #include <sys/kgdb.h> 246 247 static struct com_regs comkgdbregs; 248 static int com_kgdb_attached; 249 250 int com_kgdb_getc(void *); 251 void com_kgdb_putc(void *, int); 252 #endif /* KGDB */ 253 254 #ifdef COM_REGMAP 255 /* initializer for typical 16550-ish hardware */ 256 #define COM_REG_16550 { \ 257 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 258 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 259 /* 16750-specific register set, additional UART status register */ 260 #define COM_REG_16750 { \ 261 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 262 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } 264 265 #ifdef COM_16750 266 const bus_size_t com_std_map[32] = COM_REG_16750; 267 #else 268 const bus_size_t com_std_map[16] = COM_REG_16550; 269 #endif /* COM_16750 */ 270 #endif /* COM_REGMAP */ 271 272 #define COMUNIT_MASK 0x7ffff 273 #define COMDIALOUT_MASK 0x80000 274 275 #define COMUNIT(x) (minor(x) & COMUNIT_MASK) 276 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK) 277 278 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 279 device_is_active((sc)->sc_dev)) 280 281 #define BR BUS_SPACE_BARRIER_READ 282 #define BW BUS_SPACE_BARRIER_WRITE 283 #define COM_BARRIER(r, f) \ 284 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 285 286 /*ARGSUSED*/ 287 int 288 comspeed(long speed, long frequency, int type) 289 { 290 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 291 292 int x, err; 293 int divisor = 16; 294 295 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 296 divisor = 13; 297 } 298 299 if (speed == 0) 300 return (0); 301 if (speed < 0) 302 return (-1); 303 x = divrnd(frequency / divisor, speed); 304 if (x <= 0) 305 return (-1); 306 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 307 if (err < 0) 308 err = -err; 309 if (err > COM_TOLERANCE) 310 return (-1); 311 return (x); 312 313 #undef divrnd 314 } 315 316 #ifdef COM_DEBUG 317 int com_debug = 0; 318 319 void comstatus(struct com_softc *, const char *); 320 void 321 comstatus(struct com_softc *sc, const char *str) 322 { 323 struct tty *tp = sc->sc_tty; 324 325 aprint_normal_dev(sc->sc_dev, 326 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 327 str, 328 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 329 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 330 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 331 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 332 sc->sc_tx_stopped ? '+' : '-'); 333 334 aprint_normal_dev(sc->sc_dev, 335 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 336 str, 337 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 338 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 339 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 340 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 341 sc->sc_rx_flags); 342 } 343 #endif 344 345 int 346 com_probe_subr(struct com_regs *regs) 347 { 348 349 /* force access to id reg */ 350 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 351 CSR_WRITE_1(regs, COM_REG_IIR, 0); 352 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 353 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 354 return (0); 355 356 return (1); 357 } 358 359 int 360 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 361 { 362 struct com_regs regs; 363 364 regs.cr_iot = iot; 365 regs.cr_ioh = ioh; 366 #ifdef COM_REGMAP 367 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 368 #endif 369 370 return com_probe_subr(®s); 371 } 372 373 /* 374 * No locking in this routine; it is only called during attach, 375 * or with the port already locked. 376 */ 377 static void 378 com_enable_debugport(struct com_softc *sc) 379 { 380 381 /* Turn on line break interrupt, set carrier. */ 382 sc->sc_ier = IER_ERXRDY; 383 if (sc->sc_type == COM_TYPE_PXA2x0) 384 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 385 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 386 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 387 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 388 } 389 390 void 391 com_attach_subr(struct com_softc *sc) 392 { 393 struct com_regs *regsp = &sc->sc_regs; 394 struct tty *tp; 395 #if defined(COM_16650) || defined(COM_16750) 396 u_int8_t lcr; 397 #endif 398 const char *fifo_msg = NULL; 399 prop_dictionary_t dict; 400 bool is_console = true; 401 402 aprint_naive("\n"); 403 404 dict = device_properties(sc->sc_dev); 405 prop_dictionary_get_bool(dict, "is_console", &is_console); 406 407 callout_init(&sc->sc_diag_callout, 0); 408 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 409 410 /* Disable interrupts before configuring the device. */ 411 if (sc->sc_type == COM_TYPE_PXA2x0) 412 sc->sc_ier = IER_EUART; 413 else 414 sc->sc_ier = 0; 415 416 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 417 418 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 419 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 420 comconsattached = 1; 421 422 if (cn_tab == NULL && comcnreattach() != 0) { 423 printf("can't re-init serial console @%lx\n", 424 (u_long)comcons_info.regs.cr_iobase); 425 } 426 427 #ifdef COM_16750 428 /* Use in comintr(). */ 429 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 430 #endif 431 432 /* Make sure the console is always "hardwired". */ 433 delay(10000); /* wait for output to finish */ 434 if (is_console) { 435 SET(sc->sc_hwflags, COM_HW_CONSOLE); 436 } 437 438 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 439 } 440 441 /* Probe for FIFO */ 442 switch (sc->sc_type) { 443 case COM_TYPE_HAYESP: 444 goto fifodone; 445 446 case COM_TYPE_AU1x00: 447 sc->sc_fifolen = 16; 448 fifo_msg = "Au1X00 UART, working fifo"; 449 SET(sc->sc_hwflags, COM_HW_FIFO); 450 goto fifodelay; 451 452 case COM_TYPE_16550_NOERS: 453 sc->sc_fifolen = 16; 454 fifo_msg = "ns16650, no ERS, working fifo"; 455 SET(sc->sc_hwflags, COM_HW_FIFO); 456 goto fifodelay; 457 458 case COM_TYPE_OMAP: 459 sc->sc_fifolen = 64; 460 fifo_msg = "OMAP UART, working fifo"; 461 SET(sc->sc_hwflags, COM_HW_FIFO); 462 goto fifodelay; 463 } 464 465 sc->sc_fifolen = 1; 466 /* look for a NS 16550AF UART with FIFOs */ 467 CSR_WRITE_1(regsp, COM_REG_FIFO, 468 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 469 delay(100); 470 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 471 == IIR_FIFO_MASK) 472 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 473 == FIFO_TRIGGER_14) { 474 SET(sc->sc_hwflags, COM_HW_FIFO); 475 476 #ifdef COM_16650 477 /* 478 * IIR changes into the EFR if LCR is set to LCR_EERS 479 * on 16650s. We also know IIR != 0 at this point. 480 * Write 0 into the EFR, and read it. If the result 481 * is 0, we have a 16650. 482 * 483 * Older 16650s were broken; the test to detect them 484 * is taken from the Linux driver. Apparently 485 * setting DLAB enable gives access to the EFR on 486 * these chips. 487 */ 488 lcr = CSR_READ_1(regsp, COM_REG_LCR); 489 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 490 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 491 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 492 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 493 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 494 CLR(sc->sc_hwflags, COM_HW_FIFO); 495 sc->sc_fifolen = 0; 496 } else { 497 SET(sc->sc_hwflags, COM_HW_FLOW); 498 sc->sc_fifolen = 32; 499 } 500 } else 501 #endif 502 sc->sc_fifolen = 16; 503 504 #ifdef COM_16750 505 /* 506 * TL16C750 can enable 64byte FIFO, only when DLAB 507 * is 1. However, some 16750 may always enable. For 508 * example, restrictions according to DLAB in a data 509 * sheet for SC16C750 were not described. 510 * Please enable 'options COM_16650', supposing you 511 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 512 * should become effective. 513 */ 514 uint8_t iir1, iir2; 515 const uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 516 517 lcr = CSR_READ_1(regsp, COM_REG_LCR); 518 CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB); 519 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 520 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 521 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 522 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 523 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 524 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 525 526 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 527 528 if (!ISSET(iir1, IIR_64B_FIFO) && 529 ISSET(iir2, IIR_64B_FIFO)) { 530 /* It is TL16C750. */ 531 sc->sc_fifolen = 64; 532 SET(sc->sc_hwflags, COM_HW_AFE); 533 } else 534 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 535 #endif 536 537 #ifdef COM_16650 538 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 539 if (sc->sc_fifolen == 0) 540 fifo_msg = "st16650, broken fifo"; 541 else if (sc->sc_fifolen == 32) 542 fifo_msg = "st16650a, working fifo"; 543 else 544 #endif 545 #ifdef COM_16750 546 if (sc->sc_fifolen == 64) 547 fifo_msg = "tl16c750, working fifo"; 548 else 549 #endif 550 fifo_msg = "ns16550a, working fifo"; 551 } else 552 fifo_msg = "ns16550, broken fifo"; 553 else 554 fifo_msg = "ns8250 or ns16450, no fifo"; 555 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 556 fifodelay: 557 /* 558 * Some chips will clear down both Tx and Rx FIFOs when zero is 559 * written to com_fifo. If this chip is the console, writing zero 560 * results in some of the chip/FIFO description being lost, so delay 561 * printing it until now. 562 */ 563 delay(10); 564 aprint_normal(": %s\n", fifo_msg); 565 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 566 sc->sc_fifolen = 1; 567 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 568 } 569 570 fifodone: 571 572 tp = tty_alloc(); 573 tp->t_oproc = comstart; 574 tp->t_param = comparam; 575 tp->t_hwiflow = comhwiflow; 576 tp->t_softc = sc; 577 578 sc->sc_tty = tp; 579 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 580 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 581 sc->sc_rbavail = com_rbuf_size; 582 if (sc->sc_rbuf == NULL) { 583 aprint_error_dev(sc->sc_dev, 584 "unable to allocate ring buffer\n"); 585 return; 586 } 587 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 588 589 tty_attach(tp); 590 591 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 592 SET(sc->sc_mcr, MCR_IENABLE); 593 594 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 595 int maj; 596 597 /* locate the major number */ 598 maj = cdevsw_lookup_major(&com_cdevsw); 599 600 tp->t_dev = cn_tab->cn_dev = makedev(maj, 601 device_unit(sc->sc_dev)); 602 603 aprint_normal_dev(sc->sc_dev, "console\n"); 604 } 605 606 #ifdef KGDB 607 /* 608 * Allow kgdb to "take over" this port. If this is 609 * not the console and is the kgdb device, it has 610 * exclusive use. If it's the console _and_ the 611 * kgdb device, it doesn't. 612 */ 613 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 614 regsp->cr_iobase == comkgdbregs.cr_iobase) { 615 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 616 com_kgdb_attached = 1; 617 618 SET(sc->sc_hwflags, COM_HW_KGDB); 619 } 620 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 621 } 622 #endif 623 624 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 625 626 #ifdef RND_COM 627 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 628 RND_TYPE_TTY, 0); 629 #endif 630 631 /* if there are no enable/disable functions, assume the device 632 is always enabled */ 633 if (!sc->enable) 634 sc->enabled = 1; 635 636 com_config(sc); 637 638 SET(sc->sc_hwflags, COM_HW_DEV_OK); 639 } 640 641 void 642 com_config(struct com_softc *sc) 643 { 644 struct com_regs *regsp = &sc->sc_regs; 645 646 /* Disable interrupts before configuring the device. */ 647 if (sc->sc_type == COM_TYPE_PXA2x0) 648 sc->sc_ier = IER_EUART; 649 else 650 sc->sc_ier = 0; 651 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 652 (void) CSR_READ_1(regsp, COM_REG_IIR); 653 654 #ifdef COM_HAYESP 655 /* Look for a Hayes ESP board. */ 656 if (sc->sc_type == COM_TYPE_HAYESP) { 657 658 /* Set 16550 compatibility mode */ 659 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 660 HAYESP_SETMODE); 661 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 662 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 663 HAYESP_MODE_SCALE); 664 665 /* Set RTS/CTS flow control */ 666 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 667 HAYESP_SETFLOWTYPE); 668 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 669 HAYESP_FLOW_RTS); 670 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 671 HAYESP_FLOW_CTS); 672 673 /* Set flow control levels */ 674 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 675 HAYESP_SETRXFLOW); 676 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 677 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 678 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 679 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 680 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 681 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 682 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 683 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 684 } 685 #endif 686 687 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 688 com_enable_debugport(sc); 689 } 690 691 #if 0 692 static int 693 comcngetc_detached(dev_t dev) 694 { 695 return 0; 696 } 697 698 static void 699 comcnputc_detached(dev_t dev, int c) 700 { 701 } 702 #endif 703 704 int 705 com_detach(device_t self, int flags) 706 { 707 struct com_softc *sc = device_private(self); 708 int maj, mn; 709 710 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 711 return EBUSY; 712 713 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 714 (flags & DETACH_SHUTDOWN) != 0) 715 return EBUSY; 716 717 if (sc->disable != NULL && sc->enabled != 0) { 718 (*sc->disable)(sc); 719 sc->enabled = 0; 720 } 721 722 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 723 comconsattached = 0; 724 cn_tab = NULL; 725 } 726 727 /* locate the major number */ 728 maj = cdevsw_lookup_major(&com_cdevsw); 729 730 /* Nuke the vnodes for any open instances. */ 731 mn = device_unit(self); 732 vdevgone(maj, mn, mn, VCHR); 733 734 mn |= COMDIALOUT_MASK; 735 vdevgone(maj, mn, mn, VCHR); 736 737 if (sc->sc_rbuf == NULL) { 738 /* 739 * Ring buffer allocation failed in the com_attach_subr, 740 * only the tty is allocated, and nothing else. 741 */ 742 tty_free(sc->sc_tty); 743 return 0; 744 } 745 746 /* Free the receive buffer. */ 747 free(sc->sc_rbuf, M_DEVBUF); 748 749 /* Detach and free the tty. */ 750 tty_detach(sc->sc_tty); 751 tty_free(sc->sc_tty); 752 753 /* Unhook the soft interrupt handler. */ 754 softint_disestablish(sc->sc_si); 755 756 #ifdef RND_COM 757 /* Unhook the entropy source. */ 758 rnd_detach_source(&sc->rnd_source); 759 #endif 760 callout_destroy(&sc->sc_diag_callout); 761 762 /* Destroy the lock. */ 763 mutex_destroy(&sc->sc_lock); 764 765 return (0); 766 } 767 768 void 769 com_shutdown(struct com_softc *sc) 770 { 771 struct tty *tp = sc->sc_tty; 772 773 mutex_spin_enter(&sc->sc_lock); 774 775 /* If we were asserting flow control, then deassert it. */ 776 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 777 com_hwiflow(sc); 778 779 /* Clear any break condition set with TIOCSBRK. */ 780 com_break(sc, 0); 781 782 /* 783 * Hang up if necessary. Wait a bit, so the other side has time to 784 * notice even if we immediately open the port again. 785 * Avoid tsleeping above splhigh(). 786 */ 787 if (ISSET(tp->t_cflag, HUPCL)) { 788 com_modem(sc, 0); 789 mutex_spin_exit(&sc->sc_lock); 790 /* XXX will only timeout */ 791 (void) kpause(ttclos, false, hz, NULL); 792 mutex_spin_enter(&sc->sc_lock); 793 } 794 795 /* Turn off interrupts. */ 796 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 797 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 798 if (sc->sc_type == COM_TYPE_PXA2x0) 799 sc->sc_ier |= IER_ERXTOUT; 800 } else 801 sc->sc_ier = 0; 802 803 if (sc->sc_type == COM_TYPE_PXA2x0) 804 sc->sc_ier |= IER_EUART; 805 806 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 807 808 mutex_spin_exit(&sc->sc_lock); 809 810 if (sc->disable) { 811 #ifdef DIAGNOSTIC 812 if (!sc->enabled) 813 panic("com_shutdown: not enabled?"); 814 #endif 815 (*sc->disable)(sc); 816 sc->enabled = 0; 817 } 818 } 819 820 int 821 comopen(dev_t dev, int flag, int mode, struct lwp *l) 822 { 823 struct com_softc *sc; 824 struct tty *tp; 825 int s; 826 int error; 827 828 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 829 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 830 sc->sc_rbuf == NULL) 831 return (ENXIO); 832 833 if (!device_is_active(sc->sc_dev)) 834 return (ENXIO); 835 836 #ifdef KGDB 837 /* 838 * If this is the kgdb port, no other use is permitted. 839 */ 840 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 841 return (EBUSY); 842 #endif 843 844 tp = sc->sc_tty; 845 846 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 847 return (EBUSY); 848 849 s = spltty(); 850 851 /* 852 * Do the following iff this is a first open. 853 */ 854 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 855 struct termios t; 856 857 tp->t_dev = dev; 858 859 if (sc->enable) { 860 if ((*sc->enable)(sc)) { 861 splx(s); 862 aprint_error_dev(sc->sc_dev, 863 "device enable failed\n"); 864 return (EIO); 865 } 866 mutex_spin_enter(&sc->sc_lock); 867 sc->enabled = 1; 868 com_config(sc); 869 } else { 870 mutex_spin_enter(&sc->sc_lock); 871 } 872 873 /* Turn on interrupts. */ 874 sc->sc_ier = IER_ERXRDY | IER_ERLS; 875 if (!ISSET(tp->t_cflag, CLOCAL)) 876 sc->sc_ier |= IER_EMSC; 877 878 if (sc->sc_type == COM_TYPE_PXA2x0) 879 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 880 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 881 882 /* Fetch the current modem control status, needed later. */ 883 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 884 885 /* Clear PPS capture state on first open. */ 886 mutex_spin_enter(&timecounter_lock); 887 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 888 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 889 pps_init(&sc->sc_pps_state); 890 mutex_spin_exit(&timecounter_lock); 891 892 mutex_spin_exit(&sc->sc_lock); 893 894 /* 895 * Initialize the termios status to the defaults. Add in the 896 * sticky bits from TIOCSFLAGS. 897 */ 898 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 899 t.c_ospeed = comcons_info.rate; 900 t.c_cflag = comcons_info.cflag; 901 } else { 902 t.c_ospeed = TTYDEF_SPEED; 903 t.c_cflag = TTYDEF_CFLAG; 904 } 905 t.c_ispeed = t.c_ospeed; 906 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 907 SET(t.c_cflag, CLOCAL); 908 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 909 SET(t.c_cflag, CRTSCTS); 910 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 911 SET(t.c_cflag, MDMBUF); 912 /* Make sure comparam() will do something. */ 913 tp->t_ospeed = 0; 914 (void) comparam(tp, &t); 915 tp->t_iflag = TTYDEF_IFLAG; 916 tp->t_oflag = TTYDEF_OFLAG; 917 tp->t_lflag = TTYDEF_LFLAG; 918 ttychars(tp); 919 ttsetwater(tp); 920 921 mutex_spin_enter(&sc->sc_lock); 922 923 /* 924 * Turn on DTR. We must always do this, even if carrier is not 925 * present, because otherwise we'd have to use TIOCSDTR 926 * immediately after setting CLOCAL, which applications do not 927 * expect. We always assert DTR while the device is open 928 * unless explicitly requested to deassert it. 929 */ 930 com_modem(sc, 1); 931 932 /* Clear the input ring, and unblock. */ 933 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 934 sc->sc_rbavail = com_rbuf_size; 935 com_iflush(sc); 936 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 937 com_hwiflow(sc); 938 939 #ifdef COM_DEBUG 940 if (com_debug) 941 comstatus(sc, "comopen "); 942 #endif 943 944 mutex_spin_exit(&sc->sc_lock); 945 } 946 947 splx(s); 948 949 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 950 if (error) 951 goto bad; 952 953 error = (*tp->t_linesw->l_open)(dev, tp); 954 if (error) 955 goto bad; 956 957 return (0); 958 959 bad: 960 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 961 /* 962 * We failed to open the device, and nobody else had it opened. 963 * Clean up the state as appropriate. 964 */ 965 com_shutdown(sc); 966 } 967 968 return (error); 969 } 970 971 int 972 comclose(dev_t dev, int flag, int mode, struct lwp *l) 973 { 974 struct com_softc *sc = 975 device_lookup_private(&com_cd, COMUNIT(dev)); 976 struct tty *tp = sc->sc_tty; 977 978 /* XXX This is for cons.c. */ 979 if (!ISSET(tp->t_state, TS_ISOPEN)) 980 return (0); 981 982 (*tp->t_linesw->l_close)(tp, flag); 983 ttyclose(tp); 984 985 if (COM_ISALIVE(sc) == 0) 986 return (0); 987 988 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 989 /* 990 * Although we got a last close, the device may still be in 991 * use; e.g. if this was the dialout node, and there are still 992 * processes waiting for carrier on the non-dialout node. 993 */ 994 com_shutdown(sc); 995 } 996 997 return (0); 998 } 999 1000 int 1001 comread(dev_t dev, struct uio *uio, int flag) 1002 { 1003 struct com_softc *sc = 1004 device_lookup_private(&com_cd, COMUNIT(dev)); 1005 struct tty *tp = sc->sc_tty; 1006 1007 if (COM_ISALIVE(sc) == 0) 1008 return (EIO); 1009 1010 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1011 } 1012 1013 int 1014 comwrite(dev_t dev, struct uio *uio, int flag) 1015 { 1016 struct com_softc *sc = 1017 device_lookup_private(&com_cd, COMUNIT(dev)); 1018 struct tty *tp = sc->sc_tty; 1019 1020 if (COM_ISALIVE(sc) == 0) 1021 return (EIO); 1022 1023 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1024 } 1025 1026 int 1027 compoll(dev_t dev, int events, struct lwp *l) 1028 { 1029 struct com_softc *sc = 1030 device_lookup_private(&com_cd, COMUNIT(dev)); 1031 struct tty *tp = sc->sc_tty; 1032 1033 if (COM_ISALIVE(sc) == 0) 1034 return (POLLHUP); 1035 1036 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1037 } 1038 1039 struct tty * 1040 comtty(dev_t dev) 1041 { 1042 struct com_softc *sc = 1043 device_lookup_private(&com_cd, COMUNIT(dev)); 1044 struct tty *tp = sc->sc_tty; 1045 1046 return (tp); 1047 } 1048 1049 int 1050 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1051 { 1052 struct com_softc *sc; 1053 struct tty *tp; 1054 int error; 1055 1056 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1057 if (sc == NULL) 1058 return ENXIO; 1059 if (COM_ISALIVE(sc) == 0) 1060 return (EIO); 1061 1062 tp = sc->sc_tty; 1063 1064 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1065 if (error != EPASSTHROUGH) 1066 return (error); 1067 1068 error = ttioctl(tp, cmd, data, flag, l); 1069 if (error != EPASSTHROUGH) 1070 return (error); 1071 1072 error = 0; 1073 switch (cmd) { 1074 case TIOCSFLAGS: 1075 error = kauth_authorize_device_tty(l->l_cred, 1076 KAUTH_DEVICE_TTY_PRIVSET, tp); 1077 break; 1078 default: 1079 /* nothing */ 1080 break; 1081 } 1082 if (error) { 1083 return error; 1084 } 1085 1086 mutex_spin_enter(&sc->sc_lock); 1087 1088 switch (cmd) { 1089 case TIOCSBRK: 1090 com_break(sc, 1); 1091 break; 1092 1093 case TIOCCBRK: 1094 com_break(sc, 0); 1095 break; 1096 1097 case TIOCSDTR: 1098 com_modem(sc, 1); 1099 break; 1100 1101 case TIOCCDTR: 1102 com_modem(sc, 0); 1103 break; 1104 1105 case TIOCGFLAGS: 1106 *(int *)data = sc->sc_swflags; 1107 break; 1108 1109 case TIOCSFLAGS: 1110 sc->sc_swflags = *(int *)data; 1111 break; 1112 1113 case TIOCMSET: 1114 case TIOCMBIS: 1115 case TIOCMBIC: 1116 tiocm_to_com(sc, cmd, *(int *)data); 1117 break; 1118 1119 case TIOCMGET: 1120 *(int *)data = com_to_tiocm(sc); 1121 break; 1122 1123 case PPS_IOC_CREATE: 1124 case PPS_IOC_DESTROY: 1125 case PPS_IOC_GETPARAMS: 1126 case PPS_IOC_SETPARAMS: 1127 case PPS_IOC_GETCAP: 1128 case PPS_IOC_FETCH: 1129 #ifdef PPS_SYNC 1130 case PPS_IOC_KCBIND: 1131 #endif 1132 mutex_spin_enter(&timecounter_lock); 1133 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1134 mutex_spin_exit(&timecounter_lock); 1135 break; 1136 1137 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1138 mutex_spin_enter(&timecounter_lock); 1139 #ifndef PPS_TRAILING_EDGE 1140 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1141 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1142 #else 1143 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1144 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1145 #endif 1146 mutex_spin_exit(&timecounter_lock); 1147 break; 1148 1149 default: 1150 error = EPASSTHROUGH; 1151 break; 1152 } 1153 1154 mutex_spin_exit(&sc->sc_lock); 1155 1156 #ifdef COM_DEBUG 1157 if (com_debug) 1158 comstatus(sc, "comioctl "); 1159 #endif 1160 1161 return (error); 1162 } 1163 1164 integrate void 1165 com_schedrx(struct com_softc *sc) 1166 { 1167 1168 sc->sc_rx_ready = 1; 1169 1170 /* Wake up the poller. */ 1171 softint_schedule(sc->sc_si); 1172 } 1173 1174 void 1175 com_break(struct com_softc *sc, int onoff) 1176 { 1177 1178 if (onoff) 1179 SET(sc->sc_lcr, LCR_SBREAK); 1180 else 1181 CLR(sc->sc_lcr, LCR_SBREAK); 1182 1183 if (!sc->sc_heldchange) { 1184 if (sc->sc_tx_busy) { 1185 sc->sc_heldtbc = sc->sc_tbc; 1186 sc->sc_tbc = 0; 1187 sc->sc_heldchange = 1; 1188 } else 1189 com_loadchannelregs(sc); 1190 } 1191 } 1192 1193 void 1194 com_modem(struct com_softc *sc, int onoff) 1195 { 1196 1197 if (sc->sc_mcr_dtr == 0) 1198 return; 1199 1200 if (onoff) 1201 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1202 else 1203 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1204 1205 if (!sc->sc_heldchange) { 1206 if (sc->sc_tx_busy) { 1207 sc->sc_heldtbc = sc->sc_tbc; 1208 sc->sc_tbc = 0; 1209 sc->sc_heldchange = 1; 1210 } else 1211 com_loadchannelregs(sc); 1212 } 1213 } 1214 1215 void 1216 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1217 { 1218 u_char combits; 1219 1220 combits = 0; 1221 if (ISSET(ttybits, TIOCM_DTR)) 1222 SET(combits, MCR_DTR); 1223 if (ISSET(ttybits, TIOCM_RTS)) 1224 SET(combits, MCR_RTS); 1225 1226 switch (how) { 1227 case TIOCMBIC: 1228 CLR(sc->sc_mcr, combits); 1229 break; 1230 1231 case TIOCMBIS: 1232 SET(sc->sc_mcr, combits); 1233 break; 1234 1235 case TIOCMSET: 1236 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1237 SET(sc->sc_mcr, combits); 1238 break; 1239 } 1240 1241 if (!sc->sc_heldchange) { 1242 if (sc->sc_tx_busy) { 1243 sc->sc_heldtbc = sc->sc_tbc; 1244 sc->sc_tbc = 0; 1245 sc->sc_heldchange = 1; 1246 } else 1247 com_loadchannelregs(sc); 1248 } 1249 } 1250 1251 int 1252 com_to_tiocm(struct com_softc *sc) 1253 { 1254 u_char combits; 1255 int ttybits = 0; 1256 1257 combits = sc->sc_mcr; 1258 if (ISSET(combits, MCR_DTR)) 1259 SET(ttybits, TIOCM_DTR); 1260 if (ISSET(combits, MCR_RTS)) 1261 SET(ttybits, TIOCM_RTS); 1262 1263 combits = sc->sc_msr; 1264 if (ISSET(combits, MSR_DCD)) 1265 SET(ttybits, TIOCM_CD); 1266 if (ISSET(combits, MSR_CTS)) 1267 SET(ttybits, TIOCM_CTS); 1268 if (ISSET(combits, MSR_DSR)) 1269 SET(ttybits, TIOCM_DSR); 1270 if (ISSET(combits, MSR_RI | MSR_TERI)) 1271 SET(ttybits, TIOCM_RI); 1272 1273 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1274 SET(ttybits, TIOCM_LE); 1275 1276 return (ttybits); 1277 } 1278 1279 static u_char 1280 cflag2lcr(tcflag_t cflag) 1281 { 1282 u_char lcr = 0; 1283 1284 switch (ISSET(cflag, CSIZE)) { 1285 case CS5: 1286 SET(lcr, LCR_5BITS); 1287 break; 1288 case CS6: 1289 SET(lcr, LCR_6BITS); 1290 break; 1291 case CS7: 1292 SET(lcr, LCR_7BITS); 1293 break; 1294 case CS8: 1295 SET(lcr, LCR_8BITS); 1296 break; 1297 } 1298 if (ISSET(cflag, PARENB)) { 1299 SET(lcr, LCR_PENAB); 1300 if (!ISSET(cflag, PARODD)) 1301 SET(lcr, LCR_PEVEN); 1302 } 1303 if (ISSET(cflag, CSTOPB)) 1304 SET(lcr, LCR_STOPB); 1305 1306 return (lcr); 1307 } 1308 1309 int 1310 comparam(struct tty *tp, struct termios *t) 1311 { 1312 struct com_softc *sc = 1313 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1314 int ospeed; 1315 u_char lcr; 1316 1317 if (COM_ISALIVE(sc) == 0) 1318 return (EIO); 1319 1320 #ifdef COM_HAYESP 1321 if (sc->sc_type == COM_TYPE_HAYESP) { 1322 int prescaler, speed; 1323 1324 /* 1325 * Calculate UART clock prescaler. It should be in 1326 * range of 0 .. 3. 1327 */ 1328 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1329 prescaler++, speed /= 2) 1330 if ((ospeed = comspeed(speed, sc->sc_frequency, 1331 sc->sc_type)) > 0) 1332 break; 1333 1334 if (prescaler == 4) 1335 return (EINVAL); 1336 sc->sc_prescaler = prescaler; 1337 } else 1338 #endif 1339 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1340 1341 /* Check requested parameters. */ 1342 if (ospeed < 0) 1343 return (EINVAL); 1344 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1345 return (EINVAL); 1346 1347 /* 1348 * For the console, always force CLOCAL and !HUPCL, so that the port 1349 * is always active. 1350 */ 1351 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1352 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1353 SET(t->c_cflag, CLOCAL); 1354 CLR(t->c_cflag, HUPCL); 1355 } 1356 1357 /* 1358 * If there were no changes, don't do anything. This avoids dropping 1359 * input and improves performance when all we did was frob things like 1360 * VMIN and VTIME. 1361 */ 1362 if (tp->t_ospeed == t->c_ospeed && 1363 tp->t_cflag == t->c_cflag) 1364 return (0); 1365 1366 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1367 1368 mutex_spin_enter(&sc->sc_lock); 1369 1370 sc->sc_lcr = lcr; 1371 1372 /* 1373 * If we're not in a mode that assumes a connection is present, then 1374 * ignore carrier changes. 1375 */ 1376 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1377 sc->sc_msr_dcd = 0; 1378 else 1379 sc->sc_msr_dcd = MSR_DCD; 1380 /* 1381 * Set the flow control pins depending on the current flow control 1382 * mode. 1383 */ 1384 if (ISSET(t->c_cflag, CRTSCTS)) { 1385 sc->sc_mcr_dtr = MCR_DTR; 1386 sc->sc_mcr_rts = MCR_RTS; 1387 sc->sc_msr_cts = MSR_CTS; 1388 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1389 SET(sc->sc_mcr, MCR_AFE); 1390 } else { 1391 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1392 } 1393 } else if (ISSET(t->c_cflag, MDMBUF)) { 1394 /* 1395 * For DTR/DCD flow control, make sure we don't toggle DTR for 1396 * carrier detection. 1397 */ 1398 sc->sc_mcr_dtr = 0; 1399 sc->sc_mcr_rts = MCR_DTR; 1400 sc->sc_msr_cts = MSR_DCD; 1401 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1402 CLR(sc->sc_mcr, MCR_AFE); 1403 } else { 1404 sc->sc_efr = 0; 1405 } 1406 } else { 1407 /* 1408 * If no flow control, then always set RTS. This will make 1409 * the other side happy if it mistakenly thinks we're doing 1410 * RTS/CTS flow control. 1411 */ 1412 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1413 sc->sc_mcr_rts = 0; 1414 sc->sc_msr_cts = 0; 1415 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1416 CLR(sc->sc_mcr, MCR_AFE); 1417 } else { 1418 sc->sc_efr = 0; 1419 } 1420 if (ISSET(sc->sc_mcr, MCR_DTR)) 1421 SET(sc->sc_mcr, MCR_RTS); 1422 else 1423 CLR(sc->sc_mcr, MCR_RTS); 1424 } 1425 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1426 1427 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1428 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1429 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1430 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1431 1432 sc->sc_dlbl = ospeed; 1433 sc->sc_dlbh = ospeed >> 8; 1434 1435 /* 1436 * Set the FIFO threshold based on the receive speed. 1437 * 1438 * * If it's a low speed, it's probably a mouse or some other 1439 * interactive device, so set the threshold low. 1440 * * If it's a high speed, trim the trigger level down to prevent 1441 * overflows. 1442 * * Otherwise set it a bit higher. 1443 */ 1444 if (sc->sc_type == COM_TYPE_HAYESP) 1445 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1446 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1447 if (t->c_ospeed <= 1200) 1448 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1449 else if (t->c_ospeed <= 38400) 1450 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1451 else 1452 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1453 } else 1454 sc->sc_fifo = 0; 1455 1456 /* And copy to tty. */ 1457 tp->t_ispeed = t->c_ospeed; 1458 tp->t_ospeed = t->c_ospeed; 1459 tp->t_cflag = t->c_cflag; 1460 1461 if (!sc->sc_heldchange) { 1462 if (sc->sc_tx_busy) { 1463 sc->sc_heldtbc = sc->sc_tbc; 1464 sc->sc_tbc = 0; 1465 sc->sc_heldchange = 1; 1466 } else 1467 com_loadchannelregs(sc); 1468 } 1469 1470 if (!ISSET(t->c_cflag, CHWFLOW)) { 1471 /* Disable the high water mark. */ 1472 sc->sc_r_hiwat = 0; 1473 sc->sc_r_lowat = 0; 1474 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1475 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1476 com_schedrx(sc); 1477 } 1478 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1479 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1480 com_hwiflow(sc); 1481 } 1482 } else { 1483 sc->sc_r_hiwat = com_rbuf_hiwat; 1484 sc->sc_r_lowat = com_rbuf_lowat; 1485 } 1486 1487 mutex_spin_exit(&sc->sc_lock); 1488 1489 /* 1490 * Update the tty layer's idea of the carrier bit, in case we changed 1491 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1492 * explicit request. 1493 */ 1494 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1495 1496 #ifdef COM_DEBUG 1497 if (com_debug) 1498 comstatus(sc, "comparam "); 1499 #endif 1500 1501 if (!ISSET(t->c_cflag, CHWFLOW)) { 1502 if (sc->sc_tx_stopped) { 1503 sc->sc_tx_stopped = 0; 1504 comstart(tp); 1505 } 1506 } 1507 1508 return (0); 1509 } 1510 1511 void 1512 com_iflush(struct com_softc *sc) 1513 { 1514 struct com_regs *regsp = &sc->sc_regs; 1515 #ifdef DIAGNOSTIC 1516 int reg; 1517 #endif 1518 int timo; 1519 1520 #ifdef DIAGNOSTIC 1521 reg = 0xffff; 1522 #endif 1523 timo = 50000; 1524 /* flush any pending I/O */ 1525 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1526 && --timo) 1527 #ifdef DIAGNOSTIC 1528 reg = 1529 #else 1530 (void) 1531 #endif 1532 CSR_READ_1(regsp, COM_REG_RXDATA); 1533 #ifdef DIAGNOSTIC 1534 if (!timo) 1535 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1536 #endif 1537 1538 #ifdef COM_16750 1539 uint8_t fifo; 1540 /* 1541 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1542 * This should prevent triggering busy interrupt while 1543 * manipulating divisors. 1544 */ 1545 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1546 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1547 CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST | 1548 FIFO_XMT_RST); 1549 delay(100); 1550 #endif 1551 } 1552 1553 void 1554 com_loadchannelregs(struct com_softc *sc) 1555 { 1556 struct com_regs *regsp = &sc->sc_regs; 1557 1558 /* XXXXX necessary? */ 1559 com_iflush(sc); 1560 1561 if (sc->sc_type == COM_TYPE_PXA2x0) 1562 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1563 else 1564 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1565 1566 if (sc->sc_type == COM_TYPE_OMAP) { 1567 /* disable before changing settings */ 1568 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1569 } 1570 1571 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1572 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1573 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1574 /* no EFR on alchemy */ 1575 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1576 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1577 } 1578 if (sc->sc_type == COM_TYPE_AU1x00) { 1579 /* alchemy has single separate 16-bit clock divisor register */ 1580 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1581 (sc->sc_dlbh << 8)); 1582 } else { 1583 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1584 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1585 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1586 } 1587 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1588 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1589 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1590 #ifdef COM_HAYESP 1591 if (sc->sc_type == COM_TYPE_HAYESP) { 1592 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1593 HAYESP_SETPRESCALER); 1594 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1595 sc->sc_prescaler); 1596 } 1597 #endif 1598 if (sc->sc_type == COM_TYPE_OMAP) { 1599 /* setup the fifos. the FCR value is not used as long 1600 as SCR[6] and SCR[7] are 0, which they are at reset 1601 and we never touch the SCR register */ 1602 uint8_t rx_fifo_trig = 40; 1603 uint8_t tx_fifo_trig = 60; 1604 uint8_t rx_start = 8; 1605 uint8_t rx_halt = 60; 1606 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1607 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1608 1609 /* enable access to TCR & TLR */ 1610 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1611 1612 /* write tcr and tlr values */ 1613 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1614 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1615 1616 /* disable access to TCR & TLR */ 1617 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1618 1619 /* enable again, but mode is based on speed */ 1620 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1621 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1622 } else { 1623 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1624 } 1625 } 1626 1627 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1628 } 1629 1630 int 1631 comhwiflow(struct tty *tp, int block) 1632 { 1633 struct com_softc *sc = 1634 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1635 1636 if (COM_ISALIVE(sc) == 0) 1637 return (0); 1638 1639 if (sc->sc_mcr_rts == 0) 1640 return (0); 1641 1642 mutex_spin_enter(&sc->sc_lock); 1643 1644 if (block) { 1645 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1646 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1647 com_hwiflow(sc); 1648 } 1649 } else { 1650 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1651 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1652 com_schedrx(sc); 1653 } 1654 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1655 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1656 com_hwiflow(sc); 1657 } 1658 } 1659 1660 mutex_spin_exit(&sc->sc_lock); 1661 return (1); 1662 } 1663 1664 /* 1665 * (un)block input via hw flowcontrol 1666 */ 1667 void 1668 com_hwiflow(struct com_softc *sc) 1669 { 1670 struct com_regs *regsp= &sc->sc_regs; 1671 1672 if (sc->sc_mcr_rts == 0) 1673 return; 1674 1675 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1676 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1677 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1678 } else { 1679 SET(sc->sc_mcr, sc->sc_mcr_rts); 1680 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1681 } 1682 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1683 } 1684 1685 1686 void 1687 comstart(struct tty *tp) 1688 { 1689 struct com_softc *sc = 1690 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1691 struct com_regs *regsp = &sc->sc_regs; 1692 int s; 1693 1694 if (COM_ISALIVE(sc) == 0) 1695 return; 1696 1697 s = spltty(); 1698 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1699 goto out; 1700 if (sc->sc_tx_stopped) 1701 goto out; 1702 if (!ttypull(tp)) 1703 goto out; 1704 1705 /* Grab the first contiguous region of buffer space. */ 1706 { 1707 u_char *tba; 1708 int tbc; 1709 1710 tba = tp->t_outq.c_cf; 1711 tbc = ndqb(&tp->t_outq, 0); 1712 1713 mutex_spin_enter(&sc->sc_lock); 1714 1715 sc->sc_tba = tba; 1716 sc->sc_tbc = tbc; 1717 } 1718 1719 SET(tp->t_state, TS_BUSY); 1720 sc->sc_tx_busy = 1; 1721 1722 /* Enable transmit completion interrupts if necessary. */ 1723 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1724 SET(sc->sc_ier, IER_ETXRDY); 1725 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1726 } 1727 1728 /* Output the first chunk of the contiguous buffer. */ 1729 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1730 u_int n; 1731 1732 n = sc->sc_tbc; 1733 if (n > sc->sc_fifolen) 1734 n = sc->sc_fifolen; 1735 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1736 sc->sc_tbc -= n; 1737 sc->sc_tba += n; 1738 } 1739 1740 mutex_spin_exit(&sc->sc_lock); 1741 out: 1742 splx(s); 1743 return; 1744 } 1745 1746 /* 1747 * Stop output on a line. 1748 */ 1749 void 1750 comstop(struct tty *tp, int flag) 1751 { 1752 struct com_softc *sc = 1753 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1754 1755 mutex_spin_enter(&sc->sc_lock); 1756 if (ISSET(tp->t_state, TS_BUSY)) { 1757 /* Stop transmitting at the next chunk. */ 1758 sc->sc_tbc = 0; 1759 sc->sc_heldtbc = 0; 1760 if (!ISSET(tp->t_state, TS_TTSTOP)) 1761 SET(tp->t_state, TS_FLUSH); 1762 } 1763 mutex_spin_exit(&sc->sc_lock); 1764 } 1765 1766 void 1767 comdiag(void *arg) 1768 { 1769 struct com_softc *sc = arg; 1770 int overflows, floods; 1771 1772 mutex_spin_enter(&sc->sc_lock); 1773 overflows = sc->sc_overflows; 1774 sc->sc_overflows = 0; 1775 floods = sc->sc_floods; 1776 sc->sc_floods = 0; 1777 sc->sc_errors = 0; 1778 mutex_spin_exit(&sc->sc_lock); 1779 1780 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1781 device_xname(sc->sc_dev), 1782 overflows, overflows == 1 ? "" : "s", 1783 floods, floods == 1 ? "" : "s"); 1784 } 1785 1786 integrate void 1787 com_rxsoft(struct com_softc *sc, struct tty *tp) 1788 { 1789 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1790 u_char *get, *end; 1791 u_int cc, scc; 1792 u_char lsr; 1793 int code; 1794 1795 end = sc->sc_ebuf; 1796 get = sc->sc_rbget; 1797 scc = cc = com_rbuf_size - sc->sc_rbavail; 1798 1799 if (cc == com_rbuf_size) { 1800 sc->sc_floods++; 1801 if (sc->sc_errors++ == 0) 1802 callout_reset(&sc->sc_diag_callout, 60 * hz, 1803 comdiag, sc); 1804 } 1805 1806 /* If not yet open, drop the entire buffer content here */ 1807 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1808 get += cc << 1; 1809 if (get >= end) 1810 get -= com_rbuf_size << 1; 1811 cc = 0; 1812 } 1813 while (cc) { 1814 code = get[0]; 1815 lsr = get[1]; 1816 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1817 if (ISSET(lsr, LSR_OE)) { 1818 sc->sc_overflows++; 1819 if (sc->sc_errors++ == 0) 1820 callout_reset(&sc->sc_diag_callout, 1821 60 * hz, comdiag, sc); 1822 } 1823 if (ISSET(lsr, LSR_BI | LSR_FE)) 1824 SET(code, TTY_FE); 1825 if (ISSET(lsr, LSR_PE)) 1826 SET(code, TTY_PE); 1827 } 1828 if ((*rint)(code, tp) == -1) { 1829 /* 1830 * The line discipline's buffer is out of space. 1831 */ 1832 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1833 /* 1834 * We're either not using flow control, or the 1835 * line discipline didn't tell us to block for 1836 * some reason. Either way, we have no way to 1837 * know when there's more space available, so 1838 * just drop the rest of the data. 1839 */ 1840 get += cc << 1; 1841 if (get >= end) 1842 get -= com_rbuf_size << 1; 1843 cc = 0; 1844 } else { 1845 /* 1846 * Don't schedule any more receive processing 1847 * until the line discipline tells us there's 1848 * space available (through comhwiflow()). 1849 * Leave the rest of the data in the input 1850 * buffer. 1851 */ 1852 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1853 } 1854 break; 1855 } 1856 get += 2; 1857 if (get >= end) 1858 get = sc->sc_rbuf; 1859 cc--; 1860 } 1861 1862 if (cc != scc) { 1863 sc->sc_rbget = get; 1864 mutex_spin_enter(&sc->sc_lock); 1865 1866 cc = sc->sc_rbavail += scc - cc; 1867 /* Buffers should be ok again, release possible block. */ 1868 if (cc >= sc->sc_r_lowat) { 1869 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1870 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1871 SET(sc->sc_ier, IER_ERXRDY); 1872 #ifdef COM_PXA2X0 1873 if (sc->sc_type == COM_TYPE_PXA2x0) 1874 SET(sc->sc_ier, IER_ERXTOUT); 1875 #endif 1876 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1877 } 1878 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1879 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1880 com_hwiflow(sc); 1881 } 1882 } 1883 mutex_spin_exit(&sc->sc_lock); 1884 } 1885 } 1886 1887 integrate void 1888 com_txsoft(struct com_softc *sc, struct tty *tp) 1889 { 1890 1891 CLR(tp->t_state, TS_BUSY); 1892 if (ISSET(tp->t_state, TS_FLUSH)) 1893 CLR(tp->t_state, TS_FLUSH); 1894 else 1895 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1896 (*tp->t_linesw->l_start)(tp); 1897 } 1898 1899 integrate void 1900 com_stsoft(struct com_softc *sc, struct tty *tp) 1901 { 1902 u_char msr, delta; 1903 1904 mutex_spin_enter(&sc->sc_lock); 1905 msr = sc->sc_msr; 1906 delta = sc->sc_msr_delta; 1907 sc->sc_msr_delta = 0; 1908 mutex_spin_exit(&sc->sc_lock); 1909 1910 if (ISSET(delta, sc->sc_msr_dcd)) { 1911 /* 1912 * Inform the tty layer that carrier detect changed. 1913 */ 1914 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1915 } 1916 1917 if (ISSET(delta, sc->sc_msr_cts)) { 1918 /* Block or unblock output according to flow control. */ 1919 if (ISSET(msr, sc->sc_msr_cts)) { 1920 sc->sc_tx_stopped = 0; 1921 (*tp->t_linesw->l_start)(tp); 1922 } else { 1923 sc->sc_tx_stopped = 1; 1924 } 1925 } 1926 1927 #ifdef COM_DEBUG 1928 if (com_debug) 1929 comstatus(sc, "com_stsoft"); 1930 #endif 1931 } 1932 1933 void 1934 comsoft(void *arg) 1935 { 1936 struct com_softc *sc = arg; 1937 struct tty *tp; 1938 1939 if (COM_ISALIVE(sc) == 0) 1940 return; 1941 1942 tp = sc->sc_tty; 1943 1944 if (sc->sc_rx_ready) { 1945 sc->sc_rx_ready = 0; 1946 com_rxsoft(sc, tp); 1947 } 1948 1949 if (sc->sc_st_check) { 1950 sc->sc_st_check = 0; 1951 com_stsoft(sc, tp); 1952 } 1953 1954 if (sc->sc_tx_done) { 1955 sc->sc_tx_done = 0; 1956 com_txsoft(sc, tp); 1957 } 1958 } 1959 1960 int 1961 comintr(void *arg) 1962 { 1963 struct com_softc *sc = arg; 1964 struct com_regs *regsp = &sc->sc_regs; 1965 1966 u_char *put, *end; 1967 u_int cc; 1968 u_char lsr, iir; 1969 1970 if (COM_ISALIVE(sc) == 0) 1971 return (0); 1972 1973 KASSERT(regsp != NULL); 1974 1975 mutex_spin_enter(&sc->sc_lock); 1976 iir = CSR_READ_1(regsp, COM_REG_IIR); 1977 1978 /* Handle ns16750-specific busy interrupt. */ 1979 #ifdef COM_16750 1980 int timeout; 1981 if ((iir & IIR_BUSY) == IIR_BUSY) { 1982 for (timeout = 10000; 1983 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 1984 if (timeout <= 0) { 1985 aprint_error_dev(sc->sc_dev, 1986 "timeout while waiting for BUSY interrupt " 1987 "acknowledge\n"); 1988 mutex_spin_exit(&sc->sc_lock); 1989 return (0); 1990 } 1991 1992 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1993 iir = CSR_READ_1(regsp, COM_REG_IIR); 1994 } 1995 #endif /* COM_16750 */ 1996 1997 1998 if (ISSET(iir, IIR_NOPEND)) { 1999 mutex_spin_exit(&sc->sc_lock); 2000 return (0); 2001 } 2002 2003 end = sc->sc_ebuf; 2004 put = sc->sc_rbput; 2005 cc = sc->sc_rbavail; 2006 2007 again: do { 2008 u_char msr, delta; 2009 2010 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2011 if (ISSET(lsr, LSR_BI)) { 2012 int cn_trapped = 0; /* see above: cn_trap() */ 2013 2014 cn_check_magic(sc->sc_tty->t_dev, 2015 CNC_BREAK, com_cnm_state); 2016 if (cn_trapped) 2017 continue; 2018 #if defined(KGDB) && !defined(DDB) 2019 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2020 kgdb_connect(1); 2021 continue; 2022 } 2023 #endif 2024 } 2025 2026 if (ISSET(lsr, LSR_RCV_MASK) && 2027 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2028 while (cc > 0) { 2029 int cn_trapped = 0; 2030 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2031 put[1] = lsr; 2032 cn_check_magic(sc->sc_tty->t_dev, 2033 put[0], com_cnm_state); 2034 if (cn_trapped) 2035 goto next; 2036 put += 2; 2037 if (put >= end) 2038 put = sc->sc_rbuf; 2039 cc--; 2040 next: 2041 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2042 if (!ISSET(lsr, LSR_RCV_MASK)) 2043 break; 2044 } 2045 2046 /* 2047 * Current string of incoming characters ended because 2048 * no more data was available or we ran out of space. 2049 * Schedule a receive event if any data was received. 2050 * If we're out of space, turn off receive interrupts. 2051 */ 2052 sc->sc_rbput = put; 2053 sc->sc_rbavail = cc; 2054 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2055 sc->sc_rx_ready = 1; 2056 2057 /* 2058 * See if we are in danger of overflowing a buffer. If 2059 * so, use hardware flow control to ease the pressure. 2060 */ 2061 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2062 cc < sc->sc_r_hiwat) { 2063 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2064 com_hwiflow(sc); 2065 } 2066 2067 /* 2068 * If we're out of space, disable receive interrupts 2069 * until the queue has drained a bit. 2070 */ 2071 if (!cc) { 2072 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2073 #ifdef COM_PXA2X0 2074 if (sc->sc_type == COM_TYPE_PXA2x0) 2075 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2076 else 2077 #endif 2078 CLR(sc->sc_ier, IER_ERXRDY); 2079 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2080 } 2081 } else { 2082 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2083 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2084 continue; 2085 } 2086 } 2087 2088 msr = CSR_READ_1(regsp, COM_REG_MSR); 2089 delta = msr ^ sc->sc_msr; 2090 sc->sc_msr = msr; 2091 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2092 (delta & MSR_DCD)) { 2093 mutex_spin_enter(&timecounter_lock); 2094 pps_capture(&sc->sc_pps_state); 2095 pps_event(&sc->sc_pps_state, 2096 (msr & MSR_DCD) ? 2097 PPS_CAPTUREASSERT : 2098 PPS_CAPTURECLEAR); 2099 mutex_spin_exit(&timecounter_lock); 2100 } 2101 2102 /* 2103 * Process normal status changes 2104 */ 2105 if (ISSET(delta, sc->sc_msr_mask)) { 2106 SET(sc->sc_msr_delta, delta); 2107 2108 /* 2109 * Stop output immediately if we lose the output 2110 * flow control signal or carrier detect. 2111 */ 2112 if (ISSET(~msr, sc->sc_msr_mask)) { 2113 sc->sc_tbc = 0; 2114 sc->sc_heldtbc = 0; 2115 #ifdef COM_DEBUG 2116 if (com_debug) 2117 comstatus(sc, "comintr "); 2118 #endif 2119 } 2120 2121 sc->sc_st_check = 1; 2122 } 2123 } while (!ISSET((iir = 2124 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2125 /* 2126 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2127 * by IIR read, so we can't do this way: `process all interrupts, 2128 * then do TX if possible'. 2129 */ 2130 (iir & IIR_IMASK) != IIR_TXRDY); 2131 2132 /* 2133 * Read LSR again, since there may be an interrupt between 2134 * the last LSR read and IIR read above. 2135 */ 2136 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2137 2138 /* 2139 * See if data can be transmitted as well. 2140 * Schedule tx done event if no data left 2141 * and tty was marked busy. 2142 */ 2143 if (ISSET(lsr, LSR_TXRDY)) { 2144 /* 2145 * If we've delayed a parameter change, do it now, and restart 2146 * output. 2147 */ 2148 if (sc->sc_heldchange) { 2149 com_loadchannelregs(sc); 2150 sc->sc_heldchange = 0; 2151 sc->sc_tbc = sc->sc_heldtbc; 2152 sc->sc_heldtbc = 0; 2153 } 2154 2155 /* Output the next chunk of the contiguous buffer, if any. */ 2156 if (sc->sc_tbc > 0) { 2157 u_int n; 2158 2159 n = sc->sc_tbc; 2160 if (n > sc->sc_fifolen) 2161 n = sc->sc_fifolen; 2162 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2163 sc->sc_tbc -= n; 2164 sc->sc_tba += n; 2165 } else { 2166 /* Disable transmit completion interrupts if necessary. */ 2167 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2168 CLR(sc->sc_ier, IER_ETXRDY); 2169 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2170 } 2171 if (sc->sc_tx_busy) { 2172 sc->sc_tx_busy = 0; 2173 sc->sc_tx_done = 1; 2174 } 2175 } 2176 } 2177 2178 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2179 goto again; 2180 2181 mutex_spin_exit(&sc->sc_lock); 2182 2183 /* Wake up the poller. */ 2184 softint_schedule(sc->sc_si); 2185 2186 #ifdef RND_COM 2187 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2188 #endif 2189 2190 return (1); 2191 } 2192 2193 /* 2194 * The following functions are polled getc and putc routines, shared 2195 * by the console and kgdb glue. 2196 * 2197 * The read-ahead code is so that you can detect pending in-band 2198 * cn_magic in polled mode while doing output rather than having to 2199 * wait until the kernel decides it needs input. 2200 */ 2201 2202 #define MAX_READAHEAD 20 2203 static int com_readahead[MAX_READAHEAD]; 2204 static int com_readaheadcount = 0; 2205 2206 int 2207 com_common_getc(dev_t dev, struct com_regs *regsp) 2208 { 2209 int s = splserial(); 2210 u_char stat, c; 2211 2212 /* got a character from reading things earlier */ 2213 if (com_readaheadcount > 0) { 2214 int i; 2215 2216 c = com_readahead[0]; 2217 for (i = 1; i < com_readaheadcount; i++) { 2218 com_readahead[i-1] = com_readahead[i]; 2219 } 2220 com_readaheadcount--; 2221 splx(s); 2222 return (c); 2223 } 2224 2225 /* don't block until a character becomes available */ 2226 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2227 splx(s); 2228 return -1; 2229 } 2230 2231 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2232 stat = CSR_READ_1(regsp, COM_REG_IIR); 2233 { 2234 int cn_trapped = 0; /* required by cn_trap, see above */ 2235 #ifdef DDB 2236 extern int db_active; 2237 if (!db_active) 2238 #endif 2239 cn_check_magic(dev, c, com_cnm_state); 2240 } 2241 splx(s); 2242 return (c); 2243 } 2244 2245 static void 2246 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2247 { 2248 int s = splserial(); 2249 int cin, stat, timo; 2250 2251 if (com_readaheadcount < MAX_READAHEAD 2252 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2253 int cn_trapped = 0; 2254 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2255 stat = CSR_READ_1(regsp, COM_REG_IIR); 2256 cn_check_magic(dev, cin, com_cnm_state); 2257 com_readahead[com_readaheadcount++] = cin; 2258 } 2259 2260 /* wait for any pending transmission to finish */ 2261 timo = 150000; 2262 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2263 continue; 2264 2265 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2266 COM_BARRIER(regsp, BR | BW); 2267 2268 splx(s); 2269 } 2270 2271 /* 2272 * Initialize UART for use as console or KGDB line. 2273 */ 2274 int 2275 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2276 tcflag_t cflag) 2277 { 2278 2279 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2280 ®sp->cr_ioh)) 2281 return (ENOMEM); /* ??? */ 2282 2283 if (type == COM_TYPE_OMAP) { 2284 /* disable before changing settings */ 2285 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2286 } 2287 2288 rate = comspeed(rate, frequency, type); 2289 if (__predict_true(rate != -1)) { 2290 if (type == COM_TYPE_AU1x00) { 2291 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2292 } else { 2293 /* no EFR on alchemy */ 2294 if (type != COM_TYPE_16550_NOERS) { 2295 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2296 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2297 } 2298 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2299 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2300 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2301 } 2302 } 2303 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2304 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2305 CSR_WRITE_1(regsp, COM_REG_FIFO, 2306 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 2307 2308 if (type == COM_TYPE_OMAP) { 2309 /* setup the fifos. the FCR value is not used as long 2310 as SCR[6] and SCR[7] are 0, which they are at reset 2311 and we never touch the SCR register */ 2312 uint8_t rx_fifo_trig = 40; 2313 uint8_t tx_fifo_trig = 60; 2314 uint8_t rx_start = 8; 2315 uint8_t rx_halt = 60; 2316 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2317 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2318 2319 /* enable access to TCR & TLR */ 2320 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2321 2322 /* write tcr and tlr values */ 2323 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2324 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2325 2326 /* disable access to TCR & TLR */ 2327 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2328 2329 /* enable again, but mode is based on speed */ 2330 if (rate > 230400) { 2331 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2332 } else { 2333 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2334 } 2335 } 2336 2337 #ifdef COM_PXA2X0 2338 if (type == COM_TYPE_PXA2x0) 2339 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2340 else 2341 #endif 2342 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2343 2344 return (0); 2345 } 2346 2347 int 2348 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2349 tcflag_t cflag) 2350 { 2351 int res; 2352 2353 comcons_info.regs = *regsp; 2354 2355 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2356 if (res) 2357 return (res); 2358 2359 cn_tab = &comcons; 2360 cn_init_magic(&com_cnm_state); 2361 cn_set_magic("\047\001"); /* default magic is BREAK */ 2362 2363 comcons_info.frequency = frequency; 2364 comcons_info.type = type; 2365 comcons_info.rate = rate; 2366 comcons_info.cflag = cflag; 2367 2368 return (0); 2369 } 2370 2371 int 2372 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2373 int type, tcflag_t cflag) 2374 { 2375 struct com_regs regs; 2376 2377 memset(®s, 0, sizeof regs); 2378 regs.cr_iot = iot; 2379 regs.cr_iobase = iobase; 2380 regs.cr_nports = COM_NPORTS; 2381 #ifdef COM_REGMAP 2382 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2383 #endif 2384 2385 return comcnattach1(®s, rate, frequency, type, cflag); 2386 } 2387 2388 static int 2389 comcnreattach(void) 2390 { 2391 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2392 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2393 } 2394 2395 int 2396 comcngetc(dev_t dev) 2397 { 2398 2399 return (com_common_getc(dev, &comcons_info.regs)); 2400 } 2401 2402 /* 2403 * Console kernel output character routine. 2404 */ 2405 void 2406 comcnputc(dev_t dev, int c) 2407 { 2408 2409 com_common_putc(dev, &comcons_info.regs, c); 2410 } 2411 2412 void 2413 comcnpollc(dev_t dev, int on) 2414 { 2415 2416 com_readaheadcount = 0; 2417 } 2418 2419 #ifdef KGDB 2420 int 2421 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2422 tcflag_t cflag) 2423 { 2424 int res; 2425 2426 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2427 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2428 #if !defined(DDB) 2429 return (EBUSY); /* cannot share with console */ 2430 #else 2431 comkgdbregs = *regsp; 2432 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2433 #endif 2434 } else { 2435 comkgdbregs = *regsp; 2436 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2437 if (res) 2438 return (res); 2439 2440 /* 2441 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2442 * expects this to be initialized 2443 */ 2444 cn_init_magic(&com_cnm_state); 2445 cn_set_magic("\047\001"); 2446 } 2447 2448 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2449 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2450 2451 return (0); 2452 } 2453 2454 int 2455 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2456 int frequency, int type, tcflag_t cflag) 2457 { 2458 struct com_regs regs; 2459 2460 regs.cr_iot = iot; 2461 regs.cr_nports = COM_NPORTS; 2462 regs.cr_iobase = iobase; 2463 #ifdef COM_REGMAP 2464 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2465 #endif 2466 2467 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2468 } 2469 2470 /* ARGSUSED */ 2471 int 2472 com_kgdb_getc(void *arg) 2473 { 2474 2475 return (com_common_getc(NODEV, &comkgdbregs)); 2476 } 2477 2478 /* ARGSUSED */ 2479 void 2480 com_kgdb_putc(void *arg, int c) 2481 { 2482 2483 com_common_putc(NODEV, &comkgdbregs, c); 2484 } 2485 #endif /* KGDB */ 2486 2487 /* helper function to identify the com ports used by 2488 console or KGDB (and not yet autoconf attached) */ 2489 int 2490 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2491 { 2492 bus_space_handle_t help; 2493 2494 if (!comconsattached && 2495 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2496 iobase == comcons_info.regs.cr_iobase) 2497 help = comcons_info.regs.cr_ioh; 2498 #ifdef KGDB 2499 else if (!com_kgdb_attached && 2500 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2501 iobase == comkgdbregs.cr_iobase) 2502 help = comkgdbregs.cr_ioh; 2503 #endif 2504 else 2505 return (0); 2506 2507 if (ioh) 2508 *ioh = help; 2509 return (1); 2510 } 2511 2512 /* 2513 * this routine exists to serve as a shutdown hook for systems that 2514 * have firmware which doesn't interact properly with a com device in 2515 * FIFO mode. 2516 */ 2517 bool 2518 com_cleanup(device_t self, int how) 2519 { 2520 struct com_softc *sc = device_private(self); 2521 2522 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2523 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2524 2525 return true; 2526 } 2527 2528 bool 2529 com_suspend(device_t self, const pmf_qual_t *qual) 2530 { 2531 struct com_softc *sc = device_private(self); 2532 2533 #if 0 2534 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2535 cn_tab = &comcons_suspend; 2536 #endif 2537 2538 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2539 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2540 2541 return true; 2542 } 2543 2544 bool 2545 com_resume(device_t self, const pmf_qual_t *qual) 2546 { 2547 struct com_softc *sc = device_private(self); 2548 2549 mutex_spin_enter(&sc->sc_lock); 2550 com_loadchannelregs(sc); 2551 mutex_spin_exit(&sc->sc_lock); 2552 2553 return true; 2554 } 2555
Indexes created Thu Sep 25 08:09:54 GMT 2025