com.c revision 1.329
1 /* $NetBSD: com.c,v 1.329 2014/11/22 15:14:35 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.329 2014/11/22 15:14:35 macallan Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 (void)cn_trapped; \ 96 } while (/* CONSTCOND */ 0) 97 98 #include <sys/param.h> 99 #include <sys/systm.h> 100 #include <sys/ioctl.h> 101 #include <sys/select.h> 102 #include <sys/poll.h> 103 #include <sys/tty.h> 104 #include <sys/proc.h> 105 #include <sys/conf.h> 106 #include <sys/file.h> 107 #include <sys/uio.h> 108 #include <sys/kernel.h> 109 #include <sys/syslog.h> 110 #include <sys/device.h> 111 #include <sys/malloc.h> 112 #include <sys/timepps.h> 113 #include <sys/vnode.h> 114 #include <sys/kauth.h> 115 #include <sys/intr.h> 116 #ifdef RND_COM 117 #include <sys/rnd.h> 118 #endif 119 120 121 #include <sys/bus.h> 122 123 #include <dev/ic/comreg.h> 124 #include <dev/ic/comvar.h> 125 #include <dev/ic/ns16550reg.h> 126 #include <dev/ic/st16650reg.h> 127 #ifdef COM_HAYESP 128 #include <dev/ic/hayespreg.h> 129 #endif 130 #define com_lcr com_cfcr 131 #include <dev/cons.h> 132 133 #ifdef COM_REGMAP 134 #define CSR_WRITE_1(r, o, v) \ 135 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 136 #define CSR_READ_1(r, o) \ 137 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 138 #define CSR_WRITE_2(r, o, v) \ 139 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 140 #define CSR_READ_2(r, o) \ 141 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 142 #define CSR_WRITE_MULTI(r, o, p, n) \ 143 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 144 #else 145 #define CSR_WRITE_1(r, o, v) \ 146 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 147 #define CSR_READ_1(r, o) \ 148 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 149 #define CSR_WRITE_2(r, o, v) \ 150 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 151 #define CSR_READ_2(r, o) \ 152 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 153 #define CSR_WRITE_MULTI(r, o, p, n) \ 154 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 155 #endif 156 157 158 static void com_enable_debugport(struct com_softc *); 159 160 void com_config(struct com_softc *); 161 void com_shutdown(struct com_softc *); 162 int comspeed(long, long, int); 163 static u_char cflag2lcr(tcflag_t); 164 int comparam(struct tty *, struct termios *); 165 void comstart(struct tty *); 166 int comhwiflow(struct tty *, int); 167 168 void com_loadchannelregs(struct com_softc *); 169 void com_hwiflow(struct com_softc *); 170 void com_break(struct com_softc *, int); 171 void com_modem(struct com_softc *, int); 172 void tiocm_to_com(struct com_softc *, u_long, int); 173 int com_to_tiocm(struct com_softc *); 174 void com_iflush(struct com_softc *); 175 176 int com_common_getc(dev_t, struct com_regs *); 177 static void com_common_putc(dev_t, struct com_regs *, int); 178 179 int cominit(struct com_regs *, int, int, int, tcflag_t); 180 181 static int comcnreattach(void); 182 183 int comcngetc(dev_t); 184 void comcnputc(dev_t, int); 185 void comcnpollc(dev_t, int); 186 187 #define integrate static inline 188 void comsoft(void *); 189 integrate void com_rxsoft(struct com_softc *, struct tty *); 190 integrate void com_txsoft(struct com_softc *, struct tty *); 191 integrate void com_stsoft(struct com_softc *, struct tty *); 192 integrate void com_schedrx(struct com_softc *); 193 void comdiag(void *); 194 195 extern struct cfdriver com_cd; 196 197 dev_type_open(comopen); 198 dev_type_close(comclose); 199 dev_type_read(comread); 200 dev_type_write(comwrite); 201 dev_type_ioctl(comioctl); 202 dev_type_stop(comstop); 203 dev_type_tty(comtty); 204 dev_type_poll(compoll); 205 206 static struct comcons_info comcons_info; 207 208 /* 209 * Following are all routines needed for COM to act as console 210 */ 211 static struct consdev comcons = { 212 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 213 NODEV, CN_NORMAL 214 }; 215 216 217 const struct cdevsw com_cdevsw = { 218 .d_open = comopen, 219 .d_close = comclose, 220 .d_read = comread, 221 .d_write = comwrite, 222 .d_ioctl = comioctl, 223 .d_stop = comstop, 224 .d_tty = comtty, 225 .d_poll = compoll, 226 .d_mmap = nommap, 227 .d_kqfilter = ttykqfilter, 228 .d_discard = nodiscard, 229 .d_flag = D_TTY 230 }; 231 232 /* 233 * Make this an option variable one can patch. 234 * But be warned: this must be a power of 2! 235 */ 236 u_int com_rbuf_size = COM_RING_SIZE; 237 238 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 239 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 240 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 241 242 static int comconsattached; 243 static struct cnm_state com_cnm_state; 244 245 #ifdef KGDB 246 #include <sys/kgdb.h> 247 248 static struct com_regs comkgdbregs; 249 static int com_kgdb_attached; 250 251 int com_kgdb_getc(void *); 252 void com_kgdb_putc(void *, int); 253 #endif /* KGDB */ 254 255 #ifdef COM_REGMAP 256 /* initializer for typical 16550-ish hardware */ 257 #define COM_REG_16550 { \ 258 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 259 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 260 /* 16750-specific register set, additional UART status register */ 261 #define COM_REG_16750 { \ 262 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 263 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } 265 266 #ifdef COM_16750 267 const bus_size_t com_std_map[32] = COM_REG_16750; 268 #else 269 const bus_size_t com_std_map[16] = COM_REG_16550; 270 #endif /* COM_16750 */ 271 #endif /* COM_REGMAP */ 272 273 #define COMDIALOUT_MASK TTDIALOUT_MASK 274 275 #define COMUNIT(x) TTUNIT(x) 276 #define COMDIALOUT(x) TTDIALOUT(x) 277 278 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 279 device_is_active((sc)->sc_dev)) 280 281 #define BR BUS_SPACE_BARRIER_READ 282 #define BW BUS_SPACE_BARRIER_WRITE 283 #define COM_BARRIER(r, f) \ 284 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 285 286 /*ARGSUSED*/ 287 int 288 comspeed(long speed, long frequency, int type) 289 { 290 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 291 292 int x, err; 293 int divisor = 16; 294 295 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 296 divisor = 13; 297 } 298 299 if (speed == 0) 300 return (0); 301 if (speed < 0) 302 return (-1); 303 x = divrnd(frequency / divisor, speed); 304 if (x <= 0) 305 return (-1); 306 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 307 if (err < 0) 308 err = -err; 309 if (err > COM_TOLERANCE) 310 return (-1); 311 return (x); 312 313 #undef divrnd 314 } 315 316 #ifdef COM_DEBUG 317 int com_debug = 0; 318 319 void comstatus(struct com_softc *, const char *); 320 void 321 comstatus(struct com_softc *sc, const char *str) 322 { 323 struct tty *tp = sc->sc_tty; 324 325 aprint_normal_dev(sc->sc_dev, 326 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 327 str, 328 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 329 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 330 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 331 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 332 sc->sc_tx_stopped ? '+' : '-'); 333 334 aprint_normal_dev(sc->sc_dev, 335 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 336 str, 337 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 338 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 339 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 340 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 341 sc->sc_rx_flags); 342 } 343 #endif 344 345 int 346 com_probe_subr(struct com_regs *regs) 347 { 348 349 /* force access to id reg */ 350 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 351 CSR_WRITE_1(regs, COM_REG_IIR, 0); 352 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 353 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 354 return (0); 355 356 return (1); 357 } 358 359 int 360 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 361 { 362 struct com_regs regs; 363 364 regs.cr_iot = iot; 365 regs.cr_ioh = ioh; 366 #ifdef COM_REGMAP 367 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 368 #endif 369 370 return com_probe_subr(®s); 371 } 372 373 /* 374 * No locking in this routine; it is only called during attach, 375 * or with the port already locked. 376 */ 377 static void 378 com_enable_debugport(struct com_softc *sc) 379 { 380 381 /* Turn on line break interrupt, set carrier. */ 382 sc->sc_ier = IER_ERXRDY; 383 if (sc->sc_type == COM_TYPE_PXA2x0) 384 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 385 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 386 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 387 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 388 } 389 390 void 391 com_attach_subr(struct com_softc *sc) 392 { 393 struct com_regs *regsp = &sc->sc_regs; 394 struct tty *tp; 395 #if defined(COM_16650) || defined(COM_16750) 396 u_int8_t lcr; 397 #endif 398 const char *fifo_msg = NULL; 399 prop_dictionary_t dict; 400 bool is_console = true; 401 402 aprint_naive("\n"); 403 404 dict = device_properties(sc->sc_dev); 405 prop_dictionary_get_bool(dict, "is_console", &is_console); 406 callout_init(&sc->sc_diag_callout, 0); 407 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 408 409 /* Disable interrupts before configuring the device. */ 410 if (sc->sc_type == COM_TYPE_PXA2x0) 411 sc->sc_ier = IER_EUART; 412 else 413 sc->sc_ier = 0; 414 415 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 416 417 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 418 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 419 comconsattached = 1; 420 421 if (cn_tab == NULL && comcnreattach() != 0) { 422 printf("can't re-init serial console @%lx\n", 423 (u_long)comcons_info.regs.cr_iobase); 424 } 425 426 #ifdef COM_16750 427 /* Use in comintr(). */ 428 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 429 #endif 430 431 /* Make sure the console is always "hardwired". */ 432 delay(10000); /* wait for output to finish */ 433 if (is_console) { 434 SET(sc->sc_hwflags, COM_HW_CONSOLE); 435 } 436 437 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 438 } 439 440 /* Probe for FIFO */ 441 switch (sc->sc_type) { 442 case COM_TYPE_HAYESP: 443 goto fifodone; 444 445 case COM_TYPE_AU1x00: 446 sc->sc_fifolen = 16; 447 fifo_msg = "Au1X00 UART, working fifo"; 448 SET(sc->sc_hwflags, COM_HW_FIFO); 449 goto fifodelay; 450 451 case COM_TYPE_16550_NOERS: 452 sc->sc_fifolen = 16; 453 fifo_msg = "ns16650, no ERS, working fifo"; 454 SET(sc->sc_hwflags, COM_HW_FIFO); 455 goto fifodelay; 456 457 case COM_TYPE_OMAP: 458 sc->sc_fifolen = 64; 459 fifo_msg = "OMAP UART, working fifo"; 460 SET(sc->sc_hwflags, COM_HW_FIFO); 461 goto fifodelay; 462 463 case COM_TYPE_INGENIC: 464 sc->sc_fifolen = 64; 465 fifo_msg = "Ingenic UART, working fifo"; 466 SET(sc->sc_hwflags, COM_HW_FIFO); 467 goto fifodelay; 468 } 469 470 sc->sc_fifolen = 1; 471 /* look for a NS 16550AF UART with FIFOs */ 472 CSR_WRITE_1(regsp, COM_REG_FIFO, 473 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 474 delay(100); 475 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 476 == IIR_FIFO_MASK) 477 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 478 == FIFO_TRIGGER_14) { 479 SET(sc->sc_hwflags, COM_HW_FIFO); 480 481 #ifdef COM_16650 482 /* 483 * IIR changes into the EFR if LCR is set to LCR_EERS 484 * on 16650s. We also know IIR != 0 at this point. 485 * Write 0 into the EFR, and read it. If the result 486 * is 0, we have a 16650. 487 * 488 * Older 16650s were broken; the test to detect them 489 * is taken from the Linux driver. Apparently 490 * setting DLAB enable gives access to the EFR on 491 * these chips. 492 */ 493 lcr = CSR_READ_1(regsp, COM_REG_LCR); 494 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 495 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 496 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 497 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 498 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 499 CLR(sc->sc_hwflags, COM_HW_FIFO); 500 sc->sc_fifolen = 0; 501 } else { 502 SET(sc->sc_hwflags, COM_HW_FLOW); 503 sc->sc_fifolen = 32; 504 } 505 } else 506 #endif 507 sc->sc_fifolen = 16; 508 509 #ifdef COM_16750 510 /* 511 * TL16C750 can enable 64byte FIFO, only when DLAB 512 * is 1. However, some 16750 may always enable. For 513 * example, restrictions according to DLAB in a data 514 * sheet for SC16C750 were not described. 515 * Please enable 'options COM_16650', supposing you 516 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 517 * should become effective. 518 */ 519 uint8_t iir1, iir2; 520 const uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 521 522 lcr = CSR_READ_1(regsp, COM_REG_LCR); 523 CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB); 524 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 525 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 526 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 527 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 528 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 529 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 530 531 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 532 533 if (!ISSET(iir1, IIR_64B_FIFO) && 534 ISSET(iir2, IIR_64B_FIFO)) { 535 /* It is TL16C750. */ 536 sc->sc_fifolen = 64; 537 SET(sc->sc_hwflags, COM_HW_AFE); 538 } else 539 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 540 #endif 541 542 #ifdef COM_16650 543 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 544 if (sc->sc_fifolen == 0) 545 fifo_msg = "st16650, broken fifo"; 546 else if (sc->sc_fifolen == 32) 547 fifo_msg = "st16650a, working fifo"; 548 else 549 #endif 550 #ifdef COM_16750 551 if (sc->sc_fifolen == 64) 552 fifo_msg = "tl16c750, working fifo"; 553 else 554 #endif 555 fifo_msg = "ns16550a, working fifo"; 556 } else 557 fifo_msg = "ns16550, broken fifo"; 558 else 559 fifo_msg = "ns8250 or ns16450, no fifo"; 560 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 561 fifodelay: 562 /* 563 * Some chips will clear down both Tx and Rx FIFOs when zero is 564 * written to com_fifo. If this chip is the console, writing zero 565 * results in some of the chip/FIFO description being lost, so delay 566 * printing it until now. 567 */ 568 delay(10); 569 aprint_normal(": %s\n", fifo_msg); 570 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 571 sc->sc_fifolen = 1; 572 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 573 } 574 575 fifodone: 576 577 tp = tty_alloc(); 578 tp->t_oproc = comstart; 579 tp->t_param = comparam; 580 tp->t_hwiflow = comhwiflow; 581 tp->t_softc = sc; 582 583 sc->sc_tty = tp; 584 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 585 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 586 sc->sc_rbavail = com_rbuf_size; 587 if (sc->sc_rbuf == NULL) { 588 aprint_error_dev(sc->sc_dev, 589 "unable to allocate ring buffer\n"); 590 return; 591 } 592 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 593 594 tty_attach(tp); 595 596 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 597 SET(sc->sc_mcr, MCR_IENABLE); 598 599 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 600 int maj; 601 602 /* locate the major number */ 603 maj = cdevsw_lookup_major(&com_cdevsw); 604 605 tp->t_dev = cn_tab->cn_dev = makedev(maj, 606 device_unit(sc->sc_dev)); 607 608 aprint_normal_dev(sc->sc_dev, "console\n"); 609 } 610 611 #ifdef KGDB 612 /* 613 * Allow kgdb to "take over" this port. If this is 614 * not the console and is the kgdb device, it has 615 * exclusive use. If it's the console _and_ the 616 * kgdb device, it doesn't. 617 */ 618 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 619 regsp->cr_iobase == comkgdbregs.cr_iobase) { 620 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 621 com_kgdb_attached = 1; 622 623 SET(sc->sc_hwflags, COM_HW_KGDB); 624 } 625 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 626 } 627 #endif 628 629 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 630 631 #ifdef RND_COM 632 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 633 RND_TYPE_TTY, RND_FLAG_DEFAULT); 634 #endif 635 636 /* if there are no enable/disable functions, assume the device 637 is always enabled */ 638 if (!sc->enable) 639 sc->enabled = 1; 640 641 com_config(sc); 642 643 SET(sc->sc_hwflags, COM_HW_DEV_OK); 644 } 645 646 void 647 com_config(struct com_softc *sc) 648 { 649 struct com_regs *regsp = &sc->sc_regs; 650 651 /* Disable interrupts before configuring the device. */ 652 if (sc->sc_type == COM_TYPE_PXA2x0) 653 sc->sc_ier = IER_EUART; 654 else 655 sc->sc_ier = 0; 656 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 657 (void) CSR_READ_1(regsp, COM_REG_IIR); 658 659 #ifdef COM_HAYESP 660 /* Look for a Hayes ESP board. */ 661 if (sc->sc_type == COM_TYPE_HAYESP) { 662 663 /* Set 16550 compatibility mode */ 664 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 665 HAYESP_SETMODE); 666 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 667 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 668 HAYESP_MODE_SCALE); 669 670 /* Set RTS/CTS flow control */ 671 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 672 HAYESP_SETFLOWTYPE); 673 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 674 HAYESP_FLOW_RTS); 675 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 676 HAYESP_FLOW_CTS); 677 678 /* Set flow control levels */ 679 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 680 HAYESP_SETRXFLOW); 681 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 682 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 683 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 684 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 685 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 686 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 687 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 688 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 689 } 690 #endif 691 692 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 693 com_enable_debugport(sc); 694 } 695 696 #if 0 697 static int 698 comcngetc_detached(dev_t dev) 699 { 700 return 0; 701 } 702 703 static void 704 comcnputc_detached(dev_t dev, int c) 705 { 706 } 707 #endif 708 709 int 710 com_detach(device_t self, int flags) 711 { 712 struct com_softc *sc = device_private(self); 713 int maj, mn; 714 715 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 716 return EBUSY; 717 718 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 719 (flags & DETACH_SHUTDOWN) != 0) 720 return EBUSY; 721 722 if (sc->disable != NULL && sc->enabled != 0) { 723 (*sc->disable)(sc); 724 sc->enabled = 0; 725 } 726 727 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 728 comconsattached = 0; 729 cn_tab = NULL; 730 } 731 732 /* locate the major number */ 733 maj = cdevsw_lookup_major(&com_cdevsw); 734 735 /* Nuke the vnodes for any open instances. */ 736 mn = device_unit(self); 737 vdevgone(maj, mn, mn, VCHR); 738 739 mn |= COMDIALOUT_MASK; 740 vdevgone(maj, mn, mn, VCHR); 741 742 if (sc->sc_rbuf == NULL) { 743 /* 744 * Ring buffer allocation failed in the com_attach_subr, 745 * only the tty is allocated, and nothing else. 746 */ 747 tty_free(sc->sc_tty); 748 return 0; 749 } 750 751 /* Free the receive buffer. */ 752 free(sc->sc_rbuf, M_DEVBUF); 753 754 /* Detach and free the tty. */ 755 tty_detach(sc->sc_tty); 756 tty_free(sc->sc_tty); 757 758 /* Unhook the soft interrupt handler. */ 759 softint_disestablish(sc->sc_si); 760 761 #ifdef RND_COM 762 /* Unhook the entropy source. */ 763 rnd_detach_source(&sc->rnd_source); 764 #endif 765 callout_destroy(&sc->sc_diag_callout); 766 767 /* Destroy the lock. */ 768 mutex_destroy(&sc->sc_lock); 769 770 return (0); 771 } 772 773 void 774 com_shutdown(struct com_softc *sc) 775 { 776 struct tty *tp = sc->sc_tty; 777 778 mutex_spin_enter(&sc->sc_lock); 779 780 /* If we were asserting flow control, then deassert it. */ 781 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 782 com_hwiflow(sc); 783 784 /* Clear any break condition set with TIOCSBRK. */ 785 com_break(sc, 0); 786 787 /* 788 * Hang up if necessary. Wait a bit, so the other side has time to 789 * notice even if we immediately open the port again. 790 * Avoid tsleeping above splhigh(). 791 */ 792 if (ISSET(tp->t_cflag, HUPCL)) { 793 com_modem(sc, 0); 794 mutex_spin_exit(&sc->sc_lock); 795 /* XXX will only timeout */ 796 (void) kpause(ttclos, false, hz, NULL); 797 mutex_spin_enter(&sc->sc_lock); 798 } 799 800 /* Turn off interrupts. */ 801 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 802 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 803 if (sc->sc_type == COM_TYPE_PXA2x0) 804 sc->sc_ier |= IER_ERXTOUT; 805 } else 806 sc->sc_ier = 0; 807 808 if (sc->sc_type == COM_TYPE_PXA2x0) 809 sc->sc_ier |= IER_EUART; 810 811 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 812 813 mutex_spin_exit(&sc->sc_lock); 814 815 if (sc->disable) { 816 #ifdef DIAGNOSTIC 817 if (!sc->enabled) 818 panic("com_shutdown: not enabled?"); 819 #endif 820 (*sc->disable)(sc); 821 sc->enabled = 0; 822 } 823 } 824 825 int 826 comopen(dev_t dev, int flag, int mode, struct lwp *l) 827 { 828 struct com_softc *sc; 829 struct tty *tp; 830 int s; 831 int error; 832 833 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 834 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 835 sc->sc_rbuf == NULL) 836 return (ENXIO); 837 838 if (!device_is_active(sc->sc_dev)) 839 return (ENXIO); 840 841 #ifdef KGDB 842 /* 843 * If this is the kgdb port, no other use is permitted. 844 */ 845 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 846 return (EBUSY); 847 #endif 848 849 tp = sc->sc_tty; 850 851 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 852 return (EBUSY); 853 854 s = spltty(); 855 856 /* 857 * Do the following iff this is a first open. 858 */ 859 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 860 struct termios t; 861 862 tp->t_dev = dev; 863 864 if (sc->enable) { 865 if ((*sc->enable)(sc)) { 866 splx(s); 867 aprint_error_dev(sc->sc_dev, 868 "device enable failed\n"); 869 return (EIO); 870 } 871 mutex_spin_enter(&sc->sc_lock); 872 sc->enabled = 1; 873 com_config(sc); 874 } else { 875 mutex_spin_enter(&sc->sc_lock); 876 } 877 878 /* Turn on interrupts. */ 879 sc->sc_ier = IER_ERXRDY | IER_ERLS; 880 if (!ISSET(tp->t_cflag, CLOCAL)) 881 sc->sc_ier |= IER_EMSC; 882 883 if (sc->sc_type == COM_TYPE_PXA2x0) 884 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 885 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 886 887 /* Fetch the current modem control status, needed later. */ 888 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 889 890 /* Clear PPS capture state on first open. */ 891 mutex_spin_enter(&timecounter_lock); 892 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 893 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 894 pps_init(&sc->sc_pps_state); 895 mutex_spin_exit(&timecounter_lock); 896 897 mutex_spin_exit(&sc->sc_lock); 898 899 /* 900 * Initialize the termios status to the defaults. Add in the 901 * sticky bits from TIOCSFLAGS. 902 */ 903 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 904 t.c_ospeed = comcons_info.rate; 905 t.c_cflag = comcons_info.cflag; 906 } else { 907 t.c_ospeed = TTYDEF_SPEED; 908 t.c_cflag = TTYDEF_CFLAG; 909 } 910 t.c_ispeed = t.c_ospeed; 911 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 912 SET(t.c_cflag, CLOCAL); 913 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 914 SET(t.c_cflag, CRTSCTS); 915 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 916 SET(t.c_cflag, MDMBUF); 917 /* Make sure comparam() will do something. */ 918 tp->t_ospeed = 0; 919 (void) comparam(tp, &t); 920 tp->t_iflag = TTYDEF_IFLAG; 921 tp->t_oflag = TTYDEF_OFLAG; 922 tp->t_lflag = TTYDEF_LFLAG; 923 ttychars(tp); 924 ttsetwater(tp); 925 926 mutex_spin_enter(&sc->sc_lock); 927 928 /* 929 * Turn on DTR. We must always do this, even if carrier is not 930 * present, because otherwise we'd have to use TIOCSDTR 931 * immediately after setting CLOCAL, which applications do not 932 * expect. We always assert DTR while the device is open 933 * unless explicitly requested to deassert it. 934 */ 935 com_modem(sc, 1); 936 937 /* Clear the input ring, and unblock. */ 938 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 939 sc->sc_rbavail = com_rbuf_size; 940 com_iflush(sc); 941 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 942 com_hwiflow(sc); 943 944 #ifdef COM_DEBUG 945 if (com_debug) 946 comstatus(sc, "comopen "); 947 #endif 948 949 mutex_spin_exit(&sc->sc_lock); 950 } 951 952 splx(s); 953 954 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 955 if (error) 956 goto bad; 957 958 error = (*tp->t_linesw->l_open)(dev, tp); 959 if (error) 960 goto bad; 961 962 return (0); 963 964 bad: 965 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 966 /* 967 * We failed to open the device, and nobody else had it opened. 968 * Clean up the state as appropriate. 969 */ 970 com_shutdown(sc); 971 } 972 973 return (error); 974 } 975 976 int 977 comclose(dev_t dev, int flag, int mode, struct lwp *l) 978 { 979 struct com_softc *sc = 980 device_lookup_private(&com_cd, COMUNIT(dev)); 981 struct tty *tp = sc->sc_tty; 982 983 /* XXX This is for cons.c. */ 984 if (!ISSET(tp->t_state, TS_ISOPEN)) 985 return (0); 986 987 (*tp->t_linesw->l_close)(tp, flag); 988 ttyclose(tp); 989 990 if (COM_ISALIVE(sc) == 0) 991 return (0); 992 993 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 994 /* 995 * Although we got a last close, the device may still be in 996 * use; e.g. if this was the dialout node, and there are still 997 * processes waiting for carrier on the non-dialout node. 998 */ 999 com_shutdown(sc); 1000 } 1001 1002 return (0); 1003 } 1004 1005 int 1006 comread(dev_t dev, struct uio *uio, int flag) 1007 { 1008 struct com_softc *sc = 1009 device_lookup_private(&com_cd, COMUNIT(dev)); 1010 struct tty *tp = sc->sc_tty; 1011 1012 if (COM_ISALIVE(sc) == 0) 1013 return (EIO); 1014 1015 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1016 } 1017 1018 int 1019 comwrite(dev_t dev, struct uio *uio, int flag) 1020 { 1021 struct com_softc *sc = 1022 device_lookup_private(&com_cd, COMUNIT(dev)); 1023 struct tty *tp = sc->sc_tty; 1024 1025 if (COM_ISALIVE(sc) == 0) 1026 return (EIO); 1027 1028 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1029 } 1030 1031 int 1032 compoll(dev_t dev, int events, struct lwp *l) 1033 { 1034 struct com_softc *sc = 1035 device_lookup_private(&com_cd, COMUNIT(dev)); 1036 struct tty *tp = sc->sc_tty; 1037 1038 if (COM_ISALIVE(sc) == 0) 1039 return (POLLHUP); 1040 1041 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1042 } 1043 1044 struct tty * 1045 comtty(dev_t dev) 1046 { 1047 struct com_softc *sc = 1048 device_lookup_private(&com_cd, COMUNIT(dev)); 1049 struct tty *tp = sc->sc_tty; 1050 1051 return (tp); 1052 } 1053 1054 int 1055 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1056 { 1057 struct com_softc *sc; 1058 struct tty *tp; 1059 int error; 1060 1061 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1062 if (sc == NULL) 1063 return ENXIO; 1064 if (COM_ISALIVE(sc) == 0) 1065 return (EIO); 1066 1067 tp = sc->sc_tty; 1068 1069 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1070 if (error != EPASSTHROUGH) 1071 return (error); 1072 1073 error = ttioctl(tp, cmd, data, flag, l); 1074 if (error != EPASSTHROUGH) 1075 return (error); 1076 1077 error = 0; 1078 switch (cmd) { 1079 case TIOCSFLAGS: 1080 error = kauth_authorize_device_tty(l->l_cred, 1081 KAUTH_DEVICE_TTY_PRIVSET, tp); 1082 break; 1083 default: 1084 /* nothing */ 1085 break; 1086 } 1087 if (error) { 1088 return error; 1089 } 1090 1091 mutex_spin_enter(&sc->sc_lock); 1092 1093 switch (cmd) { 1094 case TIOCSBRK: 1095 com_break(sc, 1); 1096 break; 1097 1098 case TIOCCBRK: 1099 com_break(sc, 0); 1100 break; 1101 1102 case TIOCSDTR: 1103 com_modem(sc, 1); 1104 break; 1105 1106 case TIOCCDTR: 1107 com_modem(sc, 0); 1108 break; 1109 1110 case TIOCGFLAGS: 1111 *(int *)data = sc->sc_swflags; 1112 break; 1113 1114 case TIOCSFLAGS: 1115 sc->sc_swflags = *(int *)data; 1116 break; 1117 1118 case TIOCMSET: 1119 case TIOCMBIS: 1120 case TIOCMBIC: 1121 tiocm_to_com(sc, cmd, *(int *)data); 1122 break; 1123 1124 case TIOCMGET: 1125 *(int *)data = com_to_tiocm(sc); 1126 break; 1127 1128 case PPS_IOC_CREATE: 1129 case PPS_IOC_DESTROY: 1130 case PPS_IOC_GETPARAMS: 1131 case PPS_IOC_SETPARAMS: 1132 case PPS_IOC_GETCAP: 1133 case PPS_IOC_FETCH: 1134 #ifdef PPS_SYNC 1135 case PPS_IOC_KCBIND: 1136 #endif 1137 mutex_spin_enter(&timecounter_lock); 1138 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1139 mutex_spin_exit(&timecounter_lock); 1140 break; 1141 1142 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1143 mutex_spin_enter(&timecounter_lock); 1144 #ifndef PPS_TRAILING_EDGE 1145 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1146 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1147 #else 1148 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1149 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1150 #endif 1151 mutex_spin_exit(&timecounter_lock); 1152 break; 1153 1154 default: 1155 error = EPASSTHROUGH; 1156 break; 1157 } 1158 1159 mutex_spin_exit(&sc->sc_lock); 1160 1161 #ifdef COM_DEBUG 1162 if (com_debug) 1163 comstatus(sc, "comioctl "); 1164 #endif 1165 1166 return (error); 1167 } 1168 1169 integrate void 1170 com_schedrx(struct com_softc *sc) 1171 { 1172 1173 sc->sc_rx_ready = 1; 1174 1175 /* Wake up the poller. */ 1176 softint_schedule(sc->sc_si); 1177 } 1178 1179 void 1180 com_break(struct com_softc *sc, int onoff) 1181 { 1182 1183 if (onoff) 1184 SET(sc->sc_lcr, LCR_SBREAK); 1185 else 1186 CLR(sc->sc_lcr, LCR_SBREAK); 1187 1188 if (!sc->sc_heldchange) { 1189 if (sc->sc_tx_busy) { 1190 sc->sc_heldtbc = sc->sc_tbc; 1191 sc->sc_tbc = 0; 1192 sc->sc_heldchange = 1; 1193 } else 1194 com_loadchannelregs(sc); 1195 } 1196 } 1197 1198 void 1199 com_modem(struct com_softc *sc, int onoff) 1200 { 1201 1202 if (sc->sc_mcr_dtr == 0) 1203 return; 1204 1205 if (onoff) 1206 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1207 else 1208 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1209 1210 if (!sc->sc_heldchange) { 1211 if (sc->sc_tx_busy) { 1212 sc->sc_heldtbc = sc->sc_tbc; 1213 sc->sc_tbc = 0; 1214 sc->sc_heldchange = 1; 1215 } else 1216 com_loadchannelregs(sc); 1217 } 1218 } 1219 1220 void 1221 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1222 { 1223 u_char combits; 1224 1225 combits = 0; 1226 if (ISSET(ttybits, TIOCM_DTR)) 1227 SET(combits, MCR_DTR); 1228 if (ISSET(ttybits, TIOCM_RTS)) 1229 SET(combits, MCR_RTS); 1230 1231 switch (how) { 1232 case TIOCMBIC: 1233 CLR(sc->sc_mcr, combits); 1234 break; 1235 1236 case TIOCMBIS: 1237 SET(sc->sc_mcr, combits); 1238 break; 1239 1240 case TIOCMSET: 1241 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1242 SET(sc->sc_mcr, combits); 1243 break; 1244 } 1245 1246 if (!sc->sc_heldchange) { 1247 if (sc->sc_tx_busy) { 1248 sc->sc_heldtbc = sc->sc_tbc; 1249 sc->sc_tbc = 0; 1250 sc->sc_heldchange = 1; 1251 } else 1252 com_loadchannelregs(sc); 1253 } 1254 } 1255 1256 int 1257 com_to_tiocm(struct com_softc *sc) 1258 { 1259 u_char combits; 1260 int ttybits = 0; 1261 1262 combits = sc->sc_mcr; 1263 if (ISSET(combits, MCR_DTR)) 1264 SET(ttybits, TIOCM_DTR); 1265 if (ISSET(combits, MCR_RTS)) 1266 SET(ttybits, TIOCM_RTS); 1267 1268 combits = sc->sc_msr; 1269 if (ISSET(combits, MSR_DCD)) 1270 SET(ttybits, TIOCM_CD); 1271 if (ISSET(combits, MSR_CTS)) 1272 SET(ttybits, TIOCM_CTS); 1273 if (ISSET(combits, MSR_DSR)) 1274 SET(ttybits, TIOCM_DSR); 1275 if (ISSET(combits, MSR_RI | MSR_TERI)) 1276 SET(ttybits, TIOCM_RI); 1277 1278 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1279 SET(ttybits, TIOCM_LE); 1280 1281 return (ttybits); 1282 } 1283 1284 static u_char 1285 cflag2lcr(tcflag_t cflag) 1286 { 1287 u_char lcr = 0; 1288 1289 switch (ISSET(cflag, CSIZE)) { 1290 case CS5: 1291 SET(lcr, LCR_5BITS); 1292 break; 1293 case CS6: 1294 SET(lcr, LCR_6BITS); 1295 break; 1296 case CS7: 1297 SET(lcr, LCR_7BITS); 1298 break; 1299 case CS8: 1300 SET(lcr, LCR_8BITS); 1301 break; 1302 } 1303 if (ISSET(cflag, PARENB)) { 1304 SET(lcr, LCR_PENAB); 1305 if (!ISSET(cflag, PARODD)) 1306 SET(lcr, LCR_PEVEN); 1307 } 1308 if (ISSET(cflag, CSTOPB)) 1309 SET(lcr, LCR_STOPB); 1310 1311 return (lcr); 1312 } 1313 1314 int 1315 comparam(struct tty *tp, struct termios *t) 1316 { 1317 struct com_softc *sc = 1318 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1319 int ospeed; 1320 u_char lcr; 1321 1322 if (COM_ISALIVE(sc) == 0) 1323 return (EIO); 1324 1325 #ifdef COM_HAYESP 1326 if (sc->sc_type == COM_TYPE_HAYESP) { 1327 int prescaler, speed; 1328 1329 /* 1330 * Calculate UART clock prescaler. It should be in 1331 * range of 0 .. 3. 1332 */ 1333 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1334 prescaler++, speed /= 2) 1335 if ((ospeed = comspeed(speed, sc->sc_frequency, 1336 sc->sc_type)) > 0) 1337 break; 1338 1339 if (prescaler == 4) 1340 return (EINVAL); 1341 sc->sc_prescaler = prescaler; 1342 } else 1343 #endif 1344 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1345 1346 /* Check requested parameters. */ 1347 if (ospeed < 0) 1348 return (EINVAL); 1349 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1350 return (EINVAL); 1351 1352 /* 1353 * For the console, always force CLOCAL and !HUPCL, so that the port 1354 * is always active. 1355 */ 1356 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1357 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1358 SET(t->c_cflag, CLOCAL); 1359 CLR(t->c_cflag, HUPCL); 1360 } 1361 1362 /* 1363 * If there were no changes, don't do anything. This avoids dropping 1364 * input and improves performance when all we did was frob things like 1365 * VMIN and VTIME. 1366 */ 1367 if (tp->t_ospeed == t->c_ospeed && 1368 tp->t_cflag == t->c_cflag) 1369 return (0); 1370 1371 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1372 1373 mutex_spin_enter(&sc->sc_lock); 1374 1375 sc->sc_lcr = lcr; 1376 1377 /* 1378 * If we're not in a mode that assumes a connection is present, then 1379 * ignore carrier changes. 1380 */ 1381 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1382 sc->sc_msr_dcd = 0; 1383 else 1384 sc->sc_msr_dcd = MSR_DCD; 1385 /* 1386 * Set the flow control pins depending on the current flow control 1387 * mode. 1388 */ 1389 if (ISSET(t->c_cflag, CRTSCTS)) { 1390 sc->sc_mcr_dtr = MCR_DTR; 1391 sc->sc_mcr_rts = MCR_RTS; 1392 sc->sc_msr_cts = MSR_CTS; 1393 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1394 SET(sc->sc_mcr, MCR_AFE); 1395 } else { 1396 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1397 } 1398 } else if (ISSET(t->c_cflag, MDMBUF)) { 1399 /* 1400 * For DTR/DCD flow control, make sure we don't toggle DTR for 1401 * carrier detection. 1402 */ 1403 sc->sc_mcr_dtr = 0; 1404 sc->sc_mcr_rts = MCR_DTR; 1405 sc->sc_msr_cts = MSR_DCD; 1406 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1407 CLR(sc->sc_mcr, MCR_AFE); 1408 } else { 1409 sc->sc_efr = 0; 1410 } 1411 } else { 1412 /* 1413 * If no flow control, then always set RTS. This will make 1414 * the other side happy if it mistakenly thinks we're doing 1415 * RTS/CTS flow control. 1416 */ 1417 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1418 sc->sc_mcr_rts = 0; 1419 sc->sc_msr_cts = 0; 1420 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1421 CLR(sc->sc_mcr, MCR_AFE); 1422 } else { 1423 sc->sc_efr = 0; 1424 } 1425 if (ISSET(sc->sc_mcr, MCR_DTR)) 1426 SET(sc->sc_mcr, MCR_RTS); 1427 else 1428 CLR(sc->sc_mcr, MCR_RTS); 1429 } 1430 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1431 1432 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1433 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1434 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1435 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1436 1437 sc->sc_dlbl = ospeed; 1438 sc->sc_dlbh = ospeed >> 8; 1439 1440 /* 1441 * Set the FIFO threshold based on the receive speed. 1442 * 1443 * * If it's a low speed, it's probably a mouse or some other 1444 * interactive device, so set the threshold low. 1445 * * If it's a high speed, trim the trigger level down to prevent 1446 * overflows. 1447 * * Otherwise set it a bit higher. 1448 */ 1449 if (sc->sc_type == COM_TYPE_HAYESP) 1450 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1451 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1452 if (t->c_ospeed <= 1200) 1453 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1454 else if (t->c_ospeed <= 38400) 1455 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1456 else 1457 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1458 } else 1459 sc->sc_fifo = 0; 1460 1461 /* And copy to tty. */ 1462 tp->t_ispeed = t->c_ospeed; 1463 tp->t_ospeed = t->c_ospeed; 1464 tp->t_cflag = t->c_cflag; 1465 1466 if (!sc->sc_heldchange) { 1467 if (sc->sc_tx_busy) { 1468 sc->sc_heldtbc = sc->sc_tbc; 1469 sc->sc_tbc = 0; 1470 sc->sc_heldchange = 1; 1471 } else 1472 com_loadchannelregs(sc); 1473 } 1474 1475 if (!ISSET(t->c_cflag, CHWFLOW)) { 1476 /* Disable the high water mark. */ 1477 sc->sc_r_hiwat = 0; 1478 sc->sc_r_lowat = 0; 1479 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1480 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1481 com_schedrx(sc); 1482 } 1483 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1484 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1485 com_hwiflow(sc); 1486 } 1487 } else { 1488 sc->sc_r_hiwat = com_rbuf_hiwat; 1489 sc->sc_r_lowat = com_rbuf_lowat; 1490 } 1491 1492 mutex_spin_exit(&sc->sc_lock); 1493 1494 /* 1495 * Update the tty layer's idea of the carrier bit, in case we changed 1496 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1497 * explicit request. 1498 */ 1499 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1500 1501 #ifdef COM_DEBUG 1502 if (com_debug) 1503 comstatus(sc, "comparam "); 1504 #endif 1505 1506 if (!ISSET(t->c_cflag, CHWFLOW)) { 1507 if (sc->sc_tx_stopped) { 1508 sc->sc_tx_stopped = 0; 1509 comstart(tp); 1510 } 1511 } 1512 1513 return (0); 1514 } 1515 1516 void 1517 com_iflush(struct com_softc *sc) 1518 { 1519 struct com_regs *regsp = &sc->sc_regs; 1520 #ifdef DIAGNOSTIC 1521 int reg; 1522 #endif 1523 int timo; 1524 1525 #ifdef DIAGNOSTIC 1526 reg = 0xffff; 1527 #endif 1528 timo = 50000; 1529 /* flush any pending I/O */ 1530 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1531 && --timo) 1532 #ifdef DIAGNOSTIC 1533 reg = 1534 #else 1535 (void) 1536 #endif 1537 CSR_READ_1(regsp, COM_REG_RXDATA); 1538 #ifdef DIAGNOSTIC 1539 if (!timo) 1540 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1541 #endif 1542 1543 #ifdef COM_16750 1544 uint8_t fifo; 1545 /* 1546 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1547 * This should prevent triggering busy interrupt while 1548 * manipulating divisors. 1549 */ 1550 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1551 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1552 CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST | 1553 FIFO_XMT_RST); 1554 delay(100); 1555 #endif 1556 } 1557 1558 void 1559 com_loadchannelregs(struct com_softc *sc) 1560 { 1561 struct com_regs *regsp = &sc->sc_regs; 1562 1563 /* XXXXX necessary? */ 1564 com_iflush(sc); 1565 1566 if (sc->sc_type == COM_TYPE_PXA2x0) 1567 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1568 else 1569 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1570 1571 if (sc->sc_type == COM_TYPE_OMAP) { 1572 /* disable before changing settings */ 1573 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1574 } 1575 1576 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1577 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1578 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1579 /* no EFR on alchemy */ 1580 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1581 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1582 } 1583 if (sc->sc_type == COM_TYPE_AU1x00) { 1584 /* alchemy has single separate 16-bit clock divisor register */ 1585 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1586 (sc->sc_dlbh << 8)); 1587 } else { 1588 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1589 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1590 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1591 } 1592 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1593 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1594 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1595 #ifdef COM_HAYESP 1596 if (sc->sc_type == COM_TYPE_HAYESP) { 1597 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1598 HAYESP_SETPRESCALER); 1599 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1600 sc->sc_prescaler); 1601 } 1602 #endif 1603 if (sc->sc_type == COM_TYPE_OMAP) { 1604 /* setup the fifos. the FCR value is not used as long 1605 as SCR[6] and SCR[7] are 0, which they are at reset 1606 and we never touch the SCR register */ 1607 uint8_t rx_fifo_trig = 40; 1608 uint8_t tx_fifo_trig = 60; 1609 uint8_t rx_start = 8; 1610 uint8_t rx_halt = 60; 1611 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1612 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1613 1614 /* enable access to TCR & TLR */ 1615 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1616 1617 /* write tcr and tlr values */ 1618 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1619 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1620 1621 /* disable access to TCR & TLR */ 1622 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1623 1624 /* enable again, but mode is based on speed */ 1625 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1626 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1627 } else { 1628 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1629 } 1630 } 1631 1632 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1633 } 1634 1635 int 1636 comhwiflow(struct tty *tp, int block) 1637 { 1638 struct com_softc *sc = 1639 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1640 1641 if (COM_ISALIVE(sc) == 0) 1642 return (0); 1643 1644 if (sc->sc_mcr_rts == 0) 1645 return (0); 1646 1647 mutex_spin_enter(&sc->sc_lock); 1648 1649 if (block) { 1650 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1651 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1652 com_hwiflow(sc); 1653 } 1654 } else { 1655 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1656 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1657 com_schedrx(sc); 1658 } 1659 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1660 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1661 com_hwiflow(sc); 1662 } 1663 } 1664 1665 mutex_spin_exit(&sc->sc_lock); 1666 return (1); 1667 } 1668 1669 /* 1670 * (un)block input via hw flowcontrol 1671 */ 1672 void 1673 com_hwiflow(struct com_softc *sc) 1674 { 1675 struct com_regs *regsp= &sc->sc_regs; 1676 1677 if (sc->sc_mcr_rts == 0) 1678 return; 1679 1680 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1681 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1682 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1683 } else { 1684 SET(sc->sc_mcr, sc->sc_mcr_rts); 1685 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1686 } 1687 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1688 } 1689 1690 1691 void 1692 comstart(struct tty *tp) 1693 { 1694 struct com_softc *sc = 1695 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1696 struct com_regs *regsp = &sc->sc_regs; 1697 int s; 1698 1699 if (COM_ISALIVE(sc) == 0) 1700 return; 1701 1702 s = spltty(); 1703 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1704 goto out; 1705 if (sc->sc_tx_stopped) 1706 goto out; 1707 if (!ttypull(tp)) 1708 goto out; 1709 1710 /* Grab the first contiguous region of buffer space. */ 1711 { 1712 u_char *tba; 1713 int tbc; 1714 1715 tba = tp->t_outq.c_cf; 1716 tbc = ndqb(&tp->t_outq, 0); 1717 1718 mutex_spin_enter(&sc->sc_lock); 1719 1720 sc->sc_tba = tba; 1721 sc->sc_tbc = tbc; 1722 } 1723 1724 SET(tp->t_state, TS_BUSY); 1725 sc->sc_tx_busy = 1; 1726 1727 /* Enable transmit completion interrupts if necessary. */ 1728 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1729 SET(sc->sc_ier, IER_ETXRDY); 1730 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1731 } 1732 1733 /* Output the first chunk of the contiguous buffer. */ 1734 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1735 u_int n; 1736 1737 n = sc->sc_tbc; 1738 if (n > sc->sc_fifolen) 1739 n = sc->sc_fifolen; 1740 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1741 sc->sc_tbc -= n; 1742 sc->sc_tba += n; 1743 } 1744 1745 mutex_spin_exit(&sc->sc_lock); 1746 out: 1747 splx(s); 1748 return; 1749 } 1750 1751 /* 1752 * Stop output on a line. 1753 */ 1754 void 1755 comstop(struct tty *tp, int flag) 1756 { 1757 struct com_softc *sc = 1758 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1759 1760 mutex_spin_enter(&sc->sc_lock); 1761 if (ISSET(tp->t_state, TS_BUSY)) { 1762 /* Stop transmitting at the next chunk. */ 1763 sc->sc_tbc = 0; 1764 sc->sc_heldtbc = 0; 1765 if (!ISSET(tp->t_state, TS_TTSTOP)) 1766 SET(tp->t_state, TS_FLUSH); 1767 } 1768 mutex_spin_exit(&sc->sc_lock); 1769 } 1770 1771 void 1772 comdiag(void *arg) 1773 { 1774 struct com_softc *sc = arg; 1775 int overflows, floods; 1776 1777 mutex_spin_enter(&sc->sc_lock); 1778 overflows = sc->sc_overflows; 1779 sc->sc_overflows = 0; 1780 floods = sc->sc_floods; 1781 sc->sc_floods = 0; 1782 sc->sc_errors = 0; 1783 mutex_spin_exit(&sc->sc_lock); 1784 1785 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1786 device_xname(sc->sc_dev), 1787 overflows, overflows == 1 ? "" : "s", 1788 floods, floods == 1 ? "" : "s"); 1789 } 1790 1791 integrate void 1792 com_rxsoft(struct com_softc *sc, struct tty *tp) 1793 { 1794 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1795 u_char *get, *end; 1796 u_int cc, scc; 1797 u_char lsr; 1798 int code; 1799 1800 end = sc->sc_ebuf; 1801 get = sc->sc_rbget; 1802 scc = cc = com_rbuf_size - sc->sc_rbavail; 1803 1804 if (cc == com_rbuf_size) { 1805 sc->sc_floods++; 1806 if (sc->sc_errors++ == 0) 1807 callout_reset(&sc->sc_diag_callout, 60 * hz, 1808 comdiag, sc); 1809 } 1810 1811 /* If not yet open, drop the entire buffer content here */ 1812 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1813 get += cc << 1; 1814 if (get >= end) 1815 get -= com_rbuf_size << 1; 1816 cc = 0; 1817 } 1818 while (cc) { 1819 code = get[0]; 1820 lsr = get[1]; 1821 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1822 if (ISSET(lsr, LSR_OE)) { 1823 sc->sc_overflows++; 1824 if (sc->sc_errors++ == 0) 1825 callout_reset(&sc->sc_diag_callout, 1826 60 * hz, comdiag, sc); 1827 } 1828 if (ISSET(lsr, LSR_BI | LSR_FE)) 1829 SET(code, TTY_FE); 1830 if (ISSET(lsr, LSR_PE)) 1831 SET(code, TTY_PE); 1832 } 1833 if ((*rint)(code, tp) == -1) { 1834 /* 1835 * The line discipline's buffer is out of space. 1836 */ 1837 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1838 /* 1839 * We're either not using flow control, or the 1840 * line discipline didn't tell us to block for 1841 * some reason. Either way, we have no way to 1842 * know when there's more space available, so 1843 * just drop the rest of the data. 1844 */ 1845 get += cc << 1; 1846 if (get >= end) 1847 get -= com_rbuf_size << 1; 1848 cc = 0; 1849 } else { 1850 /* 1851 * Don't schedule any more receive processing 1852 * until the line discipline tells us there's 1853 * space available (through comhwiflow()). 1854 * Leave the rest of the data in the input 1855 * buffer. 1856 */ 1857 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1858 } 1859 break; 1860 } 1861 get += 2; 1862 if (get >= end) 1863 get = sc->sc_rbuf; 1864 cc--; 1865 } 1866 1867 if (cc != scc) { 1868 sc->sc_rbget = get; 1869 mutex_spin_enter(&sc->sc_lock); 1870 1871 cc = sc->sc_rbavail += scc - cc; 1872 /* Buffers should be ok again, release possible block. */ 1873 if (cc >= sc->sc_r_lowat) { 1874 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1875 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1876 SET(sc->sc_ier, IER_ERXRDY); 1877 #ifdef COM_PXA2X0 1878 if (sc->sc_type == COM_TYPE_PXA2x0) 1879 SET(sc->sc_ier, IER_ERXTOUT); 1880 #endif 1881 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1882 } 1883 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1884 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1885 com_hwiflow(sc); 1886 } 1887 } 1888 mutex_spin_exit(&sc->sc_lock); 1889 } 1890 } 1891 1892 integrate void 1893 com_txsoft(struct com_softc *sc, struct tty *tp) 1894 { 1895 1896 CLR(tp->t_state, TS_BUSY); 1897 if (ISSET(tp->t_state, TS_FLUSH)) 1898 CLR(tp->t_state, TS_FLUSH); 1899 else 1900 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1901 (*tp->t_linesw->l_start)(tp); 1902 } 1903 1904 integrate void 1905 com_stsoft(struct com_softc *sc, struct tty *tp) 1906 { 1907 u_char msr, delta; 1908 1909 mutex_spin_enter(&sc->sc_lock); 1910 msr = sc->sc_msr; 1911 delta = sc->sc_msr_delta; 1912 sc->sc_msr_delta = 0; 1913 mutex_spin_exit(&sc->sc_lock); 1914 1915 if (ISSET(delta, sc->sc_msr_dcd)) { 1916 /* 1917 * Inform the tty layer that carrier detect changed. 1918 */ 1919 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1920 } 1921 1922 if (ISSET(delta, sc->sc_msr_cts)) { 1923 /* Block or unblock output according to flow control. */ 1924 if (ISSET(msr, sc->sc_msr_cts)) { 1925 sc->sc_tx_stopped = 0; 1926 (*tp->t_linesw->l_start)(tp); 1927 } else { 1928 sc->sc_tx_stopped = 1; 1929 } 1930 } 1931 1932 #ifdef COM_DEBUG 1933 if (com_debug) 1934 comstatus(sc, "com_stsoft"); 1935 #endif 1936 } 1937 1938 void 1939 comsoft(void *arg) 1940 { 1941 struct com_softc *sc = arg; 1942 struct tty *tp; 1943 1944 if (COM_ISALIVE(sc) == 0) 1945 return; 1946 1947 tp = sc->sc_tty; 1948 1949 if (sc->sc_rx_ready) { 1950 sc->sc_rx_ready = 0; 1951 com_rxsoft(sc, tp); 1952 } 1953 1954 if (sc->sc_st_check) { 1955 sc->sc_st_check = 0; 1956 com_stsoft(sc, tp); 1957 } 1958 1959 if (sc->sc_tx_done) { 1960 sc->sc_tx_done = 0; 1961 com_txsoft(sc, tp); 1962 } 1963 } 1964 1965 int 1966 comintr(void *arg) 1967 { 1968 struct com_softc *sc = arg; 1969 struct com_regs *regsp = &sc->sc_regs; 1970 1971 u_char *put, *end; 1972 u_int cc; 1973 u_char lsr, iir; 1974 1975 if (COM_ISALIVE(sc) == 0) 1976 return (0); 1977 1978 KASSERT(regsp != NULL); 1979 1980 mutex_spin_enter(&sc->sc_lock); 1981 iir = CSR_READ_1(regsp, COM_REG_IIR); 1982 1983 /* Handle ns16750-specific busy interrupt. */ 1984 #ifdef COM_16750 1985 int timeout; 1986 if ((iir & IIR_BUSY) == IIR_BUSY) { 1987 for (timeout = 10000; 1988 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 1989 if (timeout <= 0) { 1990 aprint_error_dev(sc->sc_dev, 1991 "timeout while waiting for BUSY interrupt " 1992 "acknowledge\n"); 1993 mutex_spin_exit(&sc->sc_lock); 1994 return (0); 1995 } 1996 1997 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1998 iir = CSR_READ_1(regsp, COM_REG_IIR); 1999 } 2000 #endif /* COM_16750 */ 2001 2002 2003 if (ISSET(iir, IIR_NOPEND)) { 2004 mutex_spin_exit(&sc->sc_lock); 2005 return (0); 2006 } 2007 2008 end = sc->sc_ebuf; 2009 put = sc->sc_rbput; 2010 cc = sc->sc_rbavail; 2011 2012 again: do { 2013 u_char msr, delta; 2014 2015 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2016 if (ISSET(lsr, LSR_BI)) { 2017 int cn_trapped = 0; /* see above: cn_trap() */ 2018 2019 cn_check_magic(sc->sc_tty->t_dev, 2020 CNC_BREAK, com_cnm_state); 2021 if (cn_trapped) 2022 continue; 2023 #if defined(KGDB) && !defined(DDB) 2024 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2025 kgdb_connect(1); 2026 continue; 2027 } 2028 #endif 2029 } 2030 2031 if (ISSET(lsr, LSR_RCV_MASK) && 2032 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2033 while (cc > 0) { 2034 int cn_trapped = 0; 2035 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2036 put[1] = lsr; 2037 cn_check_magic(sc->sc_tty->t_dev, 2038 put[0], com_cnm_state); 2039 if (cn_trapped) 2040 goto next; 2041 put += 2; 2042 if (put >= end) 2043 put = sc->sc_rbuf; 2044 cc--; 2045 next: 2046 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2047 if (!ISSET(lsr, LSR_RCV_MASK)) 2048 break; 2049 } 2050 2051 /* 2052 * Current string of incoming characters ended because 2053 * no more data was available or we ran out of space. 2054 * Schedule a receive event if any data was received. 2055 * If we're out of space, turn off receive interrupts. 2056 */ 2057 sc->sc_rbput = put; 2058 sc->sc_rbavail = cc; 2059 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2060 sc->sc_rx_ready = 1; 2061 2062 /* 2063 * See if we are in danger of overflowing a buffer. If 2064 * so, use hardware flow control to ease the pressure. 2065 */ 2066 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2067 cc < sc->sc_r_hiwat) { 2068 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2069 com_hwiflow(sc); 2070 } 2071 2072 /* 2073 * If we're out of space, disable receive interrupts 2074 * until the queue has drained a bit. 2075 */ 2076 if (!cc) { 2077 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2078 #ifdef COM_PXA2X0 2079 if (sc->sc_type == COM_TYPE_PXA2x0) 2080 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2081 else 2082 #endif 2083 CLR(sc->sc_ier, IER_ERXRDY); 2084 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2085 } 2086 } else { 2087 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2088 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2089 continue; 2090 } 2091 } 2092 2093 msr = CSR_READ_1(regsp, COM_REG_MSR); 2094 delta = msr ^ sc->sc_msr; 2095 sc->sc_msr = msr; 2096 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2097 (delta & MSR_DCD)) { 2098 mutex_spin_enter(&timecounter_lock); 2099 pps_capture(&sc->sc_pps_state); 2100 pps_event(&sc->sc_pps_state, 2101 (msr & MSR_DCD) ? 2102 PPS_CAPTUREASSERT : 2103 PPS_CAPTURECLEAR); 2104 mutex_spin_exit(&timecounter_lock); 2105 } 2106 2107 /* 2108 * Process normal status changes 2109 */ 2110 if (ISSET(delta, sc->sc_msr_mask)) { 2111 SET(sc->sc_msr_delta, delta); 2112 2113 /* 2114 * Stop output immediately if we lose the output 2115 * flow control signal or carrier detect. 2116 */ 2117 if (ISSET(~msr, sc->sc_msr_mask)) { 2118 sc->sc_tbc = 0; 2119 sc->sc_heldtbc = 0; 2120 #ifdef COM_DEBUG 2121 if (com_debug) 2122 comstatus(sc, "comintr "); 2123 #endif 2124 } 2125 2126 sc->sc_st_check = 1; 2127 } 2128 } while (!ISSET((iir = 2129 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2130 /* 2131 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2132 * by IIR read, so we can't do this way: `process all interrupts, 2133 * then do TX if possible'. 2134 */ 2135 (iir & IIR_IMASK) != IIR_TXRDY); 2136 2137 /* 2138 * Read LSR again, since there may be an interrupt between 2139 * the last LSR read and IIR read above. 2140 */ 2141 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2142 2143 /* 2144 * See if data can be transmitted as well. 2145 * Schedule tx done event if no data left 2146 * and tty was marked busy. 2147 */ 2148 if (ISSET(lsr, LSR_TXRDY)) { 2149 /* 2150 * If we've delayed a parameter change, do it now, and restart 2151 * output. 2152 */ 2153 if (sc->sc_heldchange) { 2154 com_loadchannelregs(sc); 2155 sc->sc_heldchange = 0; 2156 sc->sc_tbc = sc->sc_heldtbc; 2157 sc->sc_heldtbc = 0; 2158 } 2159 2160 /* Output the next chunk of the contiguous buffer, if any. */ 2161 if (sc->sc_tbc > 0) { 2162 u_int n; 2163 2164 n = sc->sc_tbc; 2165 if (n > sc->sc_fifolen) 2166 n = sc->sc_fifolen; 2167 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2168 sc->sc_tbc -= n; 2169 sc->sc_tba += n; 2170 } else { 2171 /* Disable transmit completion interrupts if necessary. */ 2172 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2173 CLR(sc->sc_ier, IER_ETXRDY); 2174 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2175 } 2176 if (sc->sc_tx_busy) { 2177 sc->sc_tx_busy = 0; 2178 sc->sc_tx_done = 1; 2179 } 2180 } 2181 } 2182 2183 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2184 goto again; 2185 2186 mutex_spin_exit(&sc->sc_lock); 2187 2188 /* Wake up the poller. */ 2189 softint_schedule(sc->sc_si); 2190 2191 #ifdef RND_COM 2192 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2193 #endif 2194 2195 return (1); 2196 } 2197 2198 /* 2199 * The following functions are polled getc and putc routines, shared 2200 * by the console and kgdb glue. 2201 * 2202 * The read-ahead code is so that you can detect pending in-band 2203 * cn_magic in polled mode while doing output rather than having to 2204 * wait until the kernel decides it needs input. 2205 */ 2206 2207 #define MAX_READAHEAD 20 2208 static int com_readahead[MAX_READAHEAD]; 2209 static int com_readaheadcount = 0; 2210 2211 int 2212 com_common_getc(dev_t dev, struct com_regs *regsp) 2213 { 2214 int s = splserial(); 2215 u_char stat, c; 2216 2217 /* got a character from reading things earlier */ 2218 if (com_readaheadcount > 0) { 2219 int i; 2220 2221 c = com_readahead[0]; 2222 for (i = 1; i < com_readaheadcount; i++) { 2223 com_readahead[i-1] = com_readahead[i]; 2224 } 2225 com_readaheadcount--; 2226 splx(s); 2227 return (c); 2228 } 2229 2230 /* don't block until a character becomes available */ 2231 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2232 splx(s); 2233 return -1; 2234 } 2235 2236 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2237 stat = CSR_READ_1(regsp, COM_REG_IIR); 2238 { 2239 int cn_trapped = 0; /* required by cn_trap, see above */ 2240 #ifdef DDB 2241 extern int db_active; 2242 if (!db_active) 2243 #endif 2244 cn_check_magic(dev, c, com_cnm_state); 2245 } 2246 splx(s); 2247 return (c); 2248 } 2249 2250 static void 2251 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2252 { 2253 int s = splserial(); 2254 int cin, stat, timo; 2255 2256 if (com_readaheadcount < MAX_READAHEAD 2257 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2258 int cn_trapped = 0; 2259 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2260 stat = CSR_READ_1(regsp, COM_REG_IIR); 2261 cn_check_magic(dev, cin, com_cnm_state); 2262 com_readahead[com_readaheadcount++] = cin; 2263 } 2264 2265 /* wait for any pending transmission to finish */ 2266 timo = 150000; 2267 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2268 continue; 2269 2270 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2271 COM_BARRIER(regsp, BR | BW); 2272 2273 splx(s); 2274 } 2275 2276 /* 2277 * Initialize UART for use as console or KGDB line. 2278 */ 2279 int 2280 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2281 tcflag_t cflag) 2282 { 2283 2284 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2285 ®sp->cr_ioh)) 2286 return (ENOMEM); /* ??? */ 2287 2288 if (type == COM_TYPE_OMAP) { 2289 /* disable before changing settings */ 2290 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2291 } 2292 2293 rate = comspeed(rate, frequency, type); 2294 if (__predict_true(rate != -1)) { 2295 if (type == COM_TYPE_AU1x00) { 2296 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2297 } else { 2298 /* no EFR on alchemy */ 2299 if (type != COM_TYPE_16550_NOERS) { 2300 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2301 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2302 } 2303 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2304 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2305 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2306 } 2307 } 2308 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2309 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2310 2311 if (type == COM_TYPE_INGENIC) { 2312 CSR_WRITE_1(regsp, COM_REG_FIFO, 2313 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2314 FIFO_TRIGGER_1 | FIFO_UART_ON); 2315 } else { 2316 CSR_WRITE_1(regsp, COM_REG_FIFO, 2317 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2318 FIFO_TRIGGER_1); 2319 } 2320 2321 if (type == COM_TYPE_OMAP) { 2322 /* setup the fifos. the FCR value is not used as long 2323 as SCR[6] and SCR[7] are 0, which they are at reset 2324 and we never touch the SCR register */ 2325 uint8_t rx_fifo_trig = 40; 2326 uint8_t tx_fifo_trig = 60; 2327 uint8_t rx_start = 8; 2328 uint8_t rx_halt = 60; 2329 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2330 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2331 2332 /* enable access to TCR & TLR */ 2333 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2334 2335 /* write tcr and tlr values */ 2336 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2337 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2338 2339 /* disable access to TCR & TLR */ 2340 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2341 2342 /* enable again, but mode is based on speed */ 2343 if (rate > 230400) { 2344 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2345 } else { 2346 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2347 } 2348 } 2349 2350 #ifdef COM_PXA2X0 2351 if (type == COM_TYPE_PXA2x0) 2352 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2353 else 2354 #endif 2355 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2356 2357 return (0); 2358 } 2359 2360 int 2361 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2362 tcflag_t cflag) 2363 { 2364 int res; 2365 2366 comcons_info.regs = *regsp; 2367 2368 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2369 if (res) 2370 return (res); 2371 2372 cn_tab = &comcons; 2373 cn_init_magic(&com_cnm_state); 2374 cn_set_magic("\047\001"); /* default magic is BREAK */ 2375 2376 comcons_info.frequency = frequency; 2377 comcons_info.type = type; 2378 comcons_info.rate = rate; 2379 comcons_info.cflag = cflag; 2380 2381 return (0); 2382 } 2383 2384 int 2385 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2386 int type, tcflag_t cflag) 2387 { 2388 struct com_regs regs; 2389 2390 memset(®s, 0, sizeof regs); 2391 regs.cr_iot = iot; 2392 regs.cr_iobase = iobase; 2393 regs.cr_nports = COM_NPORTS; 2394 #ifdef COM_REGMAP 2395 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2396 #endif 2397 2398 return comcnattach1(®s, rate, frequency, type, cflag); 2399 } 2400 2401 static int 2402 comcnreattach(void) 2403 { 2404 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2405 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2406 } 2407 2408 int 2409 comcngetc(dev_t dev) 2410 { 2411 2412 return (com_common_getc(dev, &comcons_info.regs)); 2413 } 2414 2415 /* 2416 * Console kernel output character routine. 2417 */ 2418 void 2419 comcnputc(dev_t dev, int c) 2420 { 2421 2422 com_common_putc(dev, &comcons_info.regs, c); 2423 } 2424 2425 void 2426 comcnpollc(dev_t dev, int on) 2427 { 2428 2429 com_readaheadcount = 0; 2430 } 2431 2432 #ifdef KGDB 2433 int 2434 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2435 tcflag_t cflag) 2436 { 2437 int res; 2438 2439 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2440 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2441 #if !defined(DDB) 2442 return (EBUSY); /* cannot share with console */ 2443 #else 2444 comkgdbregs = *regsp; 2445 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2446 #endif 2447 } else { 2448 comkgdbregs = *regsp; 2449 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2450 if (res) 2451 return (res); 2452 2453 /* 2454 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2455 * expects this to be initialized 2456 */ 2457 cn_init_magic(&com_cnm_state); 2458 cn_set_magic("\047\001"); 2459 } 2460 2461 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2462 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2463 2464 return (0); 2465 } 2466 2467 int 2468 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2469 int frequency, int type, tcflag_t cflag) 2470 { 2471 struct com_regs regs; 2472 2473 regs.cr_iot = iot; 2474 regs.cr_nports = COM_NPORTS; 2475 regs.cr_iobase = iobase; 2476 #ifdef COM_REGMAP 2477 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2478 #endif 2479 2480 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2481 } 2482 2483 /* ARGSUSED */ 2484 int 2485 com_kgdb_getc(void *arg) 2486 { 2487 2488 return (com_common_getc(NODEV, &comkgdbregs)); 2489 } 2490 2491 /* ARGSUSED */ 2492 void 2493 com_kgdb_putc(void *arg, int c) 2494 { 2495 2496 com_common_putc(NODEV, &comkgdbregs, c); 2497 } 2498 #endif /* KGDB */ 2499 2500 /* helper function to identify the com ports used by 2501 console or KGDB (and not yet autoconf attached) */ 2502 int 2503 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2504 { 2505 bus_space_handle_t help; 2506 2507 if (!comconsattached && 2508 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2509 iobase == comcons_info.regs.cr_iobase) 2510 help = comcons_info.regs.cr_ioh; 2511 #ifdef KGDB 2512 else if (!com_kgdb_attached && 2513 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2514 iobase == comkgdbregs.cr_iobase) 2515 help = comkgdbregs.cr_ioh; 2516 #endif 2517 else 2518 return (0); 2519 2520 if (ioh) 2521 *ioh = help; 2522 return (1); 2523 } 2524 2525 /* 2526 * this routine exists to serve as a shutdown hook for systems that 2527 * have firmware which doesn't interact properly with a com device in 2528 * FIFO mode. 2529 */ 2530 bool 2531 com_cleanup(device_t self, int how) 2532 { 2533 struct com_softc *sc = device_private(self); 2534 2535 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2536 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2537 2538 return true; 2539 } 2540 2541 bool 2542 com_suspend(device_t self, const pmf_qual_t *qual) 2543 { 2544 struct com_softc *sc = device_private(self); 2545 2546 #if 0 2547 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2548 cn_tab = &comcons_suspend; 2549 #endif 2550 2551 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2552 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2553 2554 return true; 2555 } 2556 2557 bool 2558 com_resume(device_t self, const pmf_qual_t *qual) 2559 { 2560 struct com_softc *sc = device_private(self); 2561 2562 mutex_spin_enter(&sc->sc_lock); 2563 com_loadchannelregs(sc); 2564 mutex_spin_exit(&sc->sc_lock); 2565 2566 return true; 2567 } 2568
Indexes created Wed Sep 24 15:09:51 GMT 2025