com.c revision 1.332
1 /* $NetBSD: com.c,v 1.332 2015/03/07 22:13:16 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.332 2015/03/07 22:13:16 skrll Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 #include "rnd.h" 79 80 /* The COM16650 option was renamed to COM_16650. */ 81 #ifdef COM16650 82 #error Obsolete COM16650 option; use COM_16650 instead. 83 #endif 84 85 /* 86 * Override cnmagic(9) macro before including <sys/systm.h>. 87 * We need to know if cn_check_magic triggered debugger, so set a flag. 88 * Callers of cn_check_magic must declare int cn_trapped = 0; 89 * XXX: this is *ugly*! 90 */ 91 #define cn_trap() \ 92 do { \ 93 console_debugger(); \ 94 cn_trapped = 1; \ 95 (void)cn_trapped; \ 96 } while (/* CONSTCOND */ 0) 97 98 #include <sys/param.h> 99 #include <sys/systm.h> 100 #include <sys/ioctl.h> 101 #include <sys/select.h> 102 #include <sys/poll.h> 103 #include <sys/tty.h> 104 #include <sys/proc.h> 105 #include <sys/conf.h> 106 #include <sys/file.h> 107 #include <sys/uio.h> 108 #include <sys/kernel.h> 109 #include <sys/syslog.h> 110 #include <sys/device.h> 111 #include <sys/malloc.h> 112 #include <sys/timepps.h> 113 #include <sys/vnode.h> 114 #include <sys/kauth.h> 115 #include <sys/intr.h> 116 #ifdef RND_COM 117 #include <sys/rnd.h> 118 #endif 119 120 121 #include <sys/bus.h> 122 123 #include <dev/ic/comreg.h> 124 #include <dev/ic/comvar.h> 125 #include <dev/ic/ns16550reg.h> 126 #include <dev/ic/st16650reg.h> 127 #ifdef COM_HAYESP 128 #include <dev/ic/hayespreg.h> 129 #endif 130 #define com_lcr com_cfcr 131 #include <dev/cons.h> 132 133 #ifdef COM_REGMAP 134 #define CSR_WRITE_1(r, o, v) \ 135 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 136 #define CSR_READ_1(r, o) \ 137 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 138 #define CSR_WRITE_2(r, o, v) \ 139 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 140 #define CSR_READ_2(r, o) \ 141 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 142 #define CSR_WRITE_MULTI(r, o, p, n) \ 143 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 144 #else 145 #define CSR_WRITE_1(r, o, v) \ 146 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 147 #define CSR_READ_1(r, o) \ 148 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 149 #define CSR_WRITE_2(r, o, v) \ 150 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 151 #define CSR_READ_2(r, o) \ 152 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 153 #define CSR_WRITE_MULTI(r, o, p, n) \ 154 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 155 #endif 156 157 158 static void com_enable_debugport(struct com_softc *); 159 160 void com_config(struct com_softc *); 161 void com_shutdown(struct com_softc *); 162 int comspeed(long, long, int); 163 static u_char cflag2lcr(tcflag_t); 164 int comparam(struct tty *, struct termios *); 165 void comstart(struct tty *); 166 int comhwiflow(struct tty *, int); 167 168 void com_loadchannelregs(struct com_softc *); 169 void com_hwiflow(struct com_softc *); 170 void com_break(struct com_softc *, int); 171 void com_modem(struct com_softc *, int); 172 void tiocm_to_com(struct com_softc *, u_long, int); 173 int com_to_tiocm(struct com_softc *); 174 void com_iflush(struct com_softc *); 175 176 int com_common_getc(dev_t, struct com_regs *); 177 static void com_common_putc(dev_t, struct com_regs *, int); 178 179 int cominit(struct com_regs *, int, int, int, tcflag_t); 180 181 static int comcnreattach(void); 182 183 int comcngetc(dev_t); 184 void comcnputc(dev_t, int); 185 void comcnpollc(dev_t, int); 186 187 #define integrate static inline 188 void comsoft(void *); 189 integrate void com_rxsoft(struct com_softc *, struct tty *); 190 integrate void com_txsoft(struct com_softc *, struct tty *); 191 integrate void com_stsoft(struct com_softc *, struct tty *); 192 integrate void com_schedrx(struct com_softc *); 193 void comdiag(void *); 194 195 extern struct cfdriver com_cd; 196 197 dev_type_open(comopen); 198 dev_type_close(comclose); 199 dev_type_read(comread); 200 dev_type_write(comwrite); 201 dev_type_ioctl(comioctl); 202 dev_type_stop(comstop); 203 dev_type_tty(comtty); 204 dev_type_poll(compoll); 205 206 static struct comcons_info comcons_info; 207 208 /* 209 * Following are all routines needed for COM to act as console 210 */ 211 static struct consdev comcons = { 212 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 213 NODEV, CN_NORMAL 214 }; 215 216 217 const struct cdevsw com_cdevsw = { 218 .d_open = comopen, 219 .d_close = comclose, 220 .d_read = comread, 221 .d_write = comwrite, 222 .d_ioctl = comioctl, 223 .d_stop = comstop, 224 .d_tty = comtty, 225 .d_poll = compoll, 226 .d_mmap = nommap, 227 .d_kqfilter = ttykqfilter, 228 .d_discard = nodiscard, 229 .d_flag = D_TTY 230 }; 231 232 /* 233 * Make this an option variable one can patch. 234 * But be warned: this must be a power of 2! 235 */ 236 u_int com_rbuf_size = COM_RING_SIZE; 237 238 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 239 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 240 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 241 242 static int comconsattached; 243 static struct cnm_state com_cnm_state; 244 245 #ifdef KGDB 246 #include <sys/kgdb.h> 247 248 static struct com_regs comkgdbregs; 249 static int com_kgdb_attached; 250 251 int com_kgdb_getc(void *); 252 void com_kgdb_putc(void *, int); 253 #endif /* KGDB */ 254 255 #ifdef COM_REGMAP 256 /* initializer for typical 16550-ish hardware */ 257 #define COM_REG_16550 { \ 258 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 259 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 260 /* 16750-specific register set, additional UART status register */ 261 #define COM_REG_16750 { \ 262 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 263 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 264 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } 265 266 #ifdef COM_16750 267 const bus_size_t com_std_map[32] = COM_REG_16750; 268 #else 269 const bus_size_t com_std_map[16] = COM_REG_16550; 270 #endif /* COM_16750 */ 271 #endif /* COM_REGMAP */ 272 273 #define COMDIALOUT_MASK TTDIALOUT_MASK 274 275 #define COMUNIT(x) TTUNIT(x) 276 #define COMDIALOUT(x) TTDIALOUT(x) 277 278 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 279 device_is_active((sc)->sc_dev)) 280 281 #define BR BUS_SPACE_BARRIER_READ 282 #define BW BUS_SPACE_BARRIER_WRITE 283 #define COM_BARRIER(r, f) \ 284 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 285 286 /*ARGSUSED*/ 287 int 288 comspeed(long speed, long frequency, int type) 289 { 290 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 291 292 int x, err; 293 int divisor = 16; 294 295 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 296 divisor = 13; 297 } 298 299 if (speed == 0) 300 return (0); 301 if (speed < 0) 302 return (-1); 303 x = divrnd(frequency / divisor, speed); 304 if (x <= 0) 305 return (-1); 306 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 307 if (err < 0) 308 err = -err; 309 if (err > COM_TOLERANCE) 310 return (-1); 311 return (x); 312 313 #undef divrnd 314 } 315 316 #ifdef COM_DEBUG 317 int com_debug = 0; 318 319 void comstatus(struct com_softc *, const char *); 320 void 321 comstatus(struct com_softc *sc, const char *str) 322 { 323 struct tty *tp = sc->sc_tty; 324 325 aprint_normal_dev(sc->sc_dev, 326 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 327 str, 328 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 329 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 330 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 331 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 332 sc->sc_tx_stopped ? '+' : '-'); 333 334 aprint_normal_dev(sc->sc_dev, 335 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 336 str, 337 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 338 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 339 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 340 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 341 sc->sc_rx_flags); 342 } 343 #endif 344 345 int 346 com_probe_subr(struct com_regs *regs) 347 { 348 349 /* force access to id reg */ 350 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 351 CSR_WRITE_1(regs, COM_REG_IIR, 0); 352 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 353 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 354 return (0); 355 356 return (1); 357 } 358 359 int 360 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 361 { 362 struct com_regs regs; 363 364 regs.cr_iot = iot; 365 regs.cr_ioh = ioh; 366 #ifdef COM_REGMAP 367 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 368 #endif 369 370 return com_probe_subr(®s); 371 } 372 373 /* 374 * No locking in this routine; it is only called during attach, 375 * or with the port already locked. 376 */ 377 static void 378 com_enable_debugport(struct com_softc *sc) 379 { 380 381 /* Turn on line break interrupt, set carrier. */ 382 sc->sc_ier = IER_ERXRDY; 383 if (sc->sc_type == COM_TYPE_PXA2x0) 384 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 385 if (sc->sc_type == COM_TYPE_INGENIC) 386 sc->sc_ier |= IER_ERXTOUT; 387 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 388 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 389 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 390 } 391 392 void 393 com_attach_subr(struct com_softc *sc) 394 { 395 struct com_regs *regsp = &sc->sc_regs; 396 struct tty *tp; 397 #if defined(COM_16650) || defined(COM_16750) 398 u_int8_t lcr; 399 #endif 400 const char *fifo_msg = NULL; 401 prop_dictionary_t dict; 402 bool is_console = true; 403 404 aprint_naive("\n"); 405 406 dict = device_properties(sc->sc_dev); 407 prop_dictionary_get_bool(dict, "is_console", &is_console); 408 callout_init(&sc->sc_diag_callout, 0); 409 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 410 411 /* Disable interrupts before configuring the device. */ 412 if (sc->sc_type == COM_TYPE_PXA2x0) 413 sc->sc_ier = IER_EUART; 414 else 415 sc->sc_ier = 0; 416 417 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 418 419 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 420 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 421 comconsattached = 1; 422 423 if (cn_tab == NULL && comcnreattach() != 0) { 424 printf("can't re-init serial console @%lx\n", 425 (u_long)comcons_info.regs.cr_iobase); 426 } 427 428 #ifdef COM_16750 429 /* Use in comintr(). */ 430 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 431 #endif 432 433 /* Make sure the console is always "hardwired". */ 434 delay(10000); /* wait for output to finish */ 435 if (is_console) { 436 SET(sc->sc_hwflags, COM_HW_CONSOLE); 437 } 438 439 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 440 } 441 442 /* Probe for FIFO */ 443 switch (sc->sc_type) { 444 case COM_TYPE_HAYESP: 445 goto fifodone; 446 447 case COM_TYPE_AU1x00: 448 sc->sc_fifolen = 16; 449 fifo_msg = "Au1X00 UART, working fifo"; 450 SET(sc->sc_hwflags, COM_HW_FIFO); 451 goto fifodelay; 452 453 case COM_TYPE_16550_NOERS: 454 sc->sc_fifolen = 16; 455 fifo_msg = "ns16650, no ERS, working fifo"; 456 SET(sc->sc_hwflags, COM_HW_FIFO); 457 goto fifodelay; 458 459 case COM_TYPE_OMAP: 460 sc->sc_fifolen = 64; 461 fifo_msg = "OMAP UART, working fifo"; 462 SET(sc->sc_hwflags, COM_HW_FIFO); 463 goto fifodelay; 464 465 case COM_TYPE_INGENIC: 466 sc->sc_fifolen = 16; 467 fifo_msg = "Ingenic UART, working fifo"; 468 SET(sc->sc_hwflags, COM_HW_FIFO); 469 SET(sc->sc_hwflags, COM_HW_NOIEN); 470 goto fifodelay; 471 } 472 473 sc->sc_fifolen = 1; 474 /* look for a NS 16550AF UART with FIFOs */ 475 if (sc->sc_type == COM_TYPE_INGENIC) { 476 CSR_WRITE_1(regsp, COM_REG_FIFO, 477 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 478 FIFO_TRIGGER_14 | FIFO_UART_ON); 479 } else 480 CSR_WRITE_1(regsp, COM_REG_FIFO, 481 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 482 delay(100); 483 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 484 == IIR_FIFO_MASK) 485 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 486 == FIFO_TRIGGER_14) { 487 SET(sc->sc_hwflags, COM_HW_FIFO); 488 489 #ifdef COM_16650 490 /* 491 * IIR changes into the EFR if LCR is set to LCR_EERS 492 * on 16650s. We also know IIR != 0 at this point. 493 * Write 0 into the EFR, and read it. If the result 494 * is 0, we have a 16650. 495 * 496 * Older 16650s were broken; the test to detect them 497 * is taken from the Linux driver. Apparently 498 * setting DLAB enable gives access to the EFR on 499 * these chips. 500 */ 501 lcr = CSR_READ_1(regsp, COM_REG_LCR); 502 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 503 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 504 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 505 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 506 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 507 CLR(sc->sc_hwflags, COM_HW_FIFO); 508 sc->sc_fifolen = 0; 509 } else { 510 SET(sc->sc_hwflags, COM_HW_FLOW); 511 sc->sc_fifolen = 32; 512 } 513 } else 514 #endif 515 sc->sc_fifolen = 16; 516 517 #ifdef COM_16750 518 /* 519 * TL16C750 can enable 64byte FIFO, only when DLAB 520 * is 1. However, some 16750 may always enable. For 521 * example, restrictions according to DLAB in a data 522 * sheet for SC16C750 were not described. 523 * Please enable 'options COM_16650', supposing you 524 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 525 * should become effective. 526 */ 527 uint8_t iir1, iir2; 528 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 529 530 if (sc->sc_type == COM_TYPE_INGENIC) 531 fcr |= FIFO_UART_ON; 532 533 lcr = CSR_READ_1(regsp, COM_REG_LCR); 534 CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB); 535 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 536 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 537 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 538 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 539 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 540 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 541 542 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 543 544 if (!ISSET(iir1, IIR_64B_FIFO) && 545 ISSET(iir2, IIR_64B_FIFO)) { 546 /* It is TL16C750. */ 547 sc->sc_fifolen = 64; 548 SET(sc->sc_hwflags, COM_HW_AFE); 549 } else 550 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 551 #endif 552 553 #ifdef COM_16650 554 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 555 if (sc->sc_fifolen == 0) 556 fifo_msg = "st16650, broken fifo"; 557 else if (sc->sc_fifolen == 32) 558 fifo_msg = "st16650a, working fifo"; 559 else 560 #endif 561 #ifdef COM_16750 562 if (sc->sc_fifolen == 64) 563 fifo_msg = "tl16c750, working fifo"; 564 else 565 #endif 566 fifo_msg = "ns16550a, working fifo"; 567 } else 568 fifo_msg = "ns16550, broken fifo"; 569 else 570 fifo_msg = "ns8250 or ns16450, no fifo"; 571 if (sc->sc_type == COM_TYPE_INGENIC) { 572 CSR_WRITE_1(regsp, COM_REG_FIFO, FIFO_UART_ON); 573 } else 574 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 575 fifodelay: 576 /* 577 * Some chips will clear down both Tx and Rx FIFOs when zero is 578 * written to com_fifo. If this chip is the console, writing zero 579 * results in some of the chip/FIFO description being lost, so delay 580 * printing it until now. 581 */ 582 delay(10); 583 aprint_normal(": %s\n", fifo_msg); 584 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 585 sc->sc_fifolen = 1; 586 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 587 } 588 589 fifodone: 590 591 tp = tty_alloc(); 592 tp->t_oproc = comstart; 593 tp->t_param = comparam; 594 tp->t_hwiflow = comhwiflow; 595 tp->t_softc = sc; 596 597 sc->sc_tty = tp; 598 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 599 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 600 sc->sc_rbavail = com_rbuf_size; 601 if (sc->sc_rbuf == NULL) { 602 aprint_error_dev(sc->sc_dev, 603 "unable to allocate ring buffer\n"); 604 return; 605 } 606 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 607 608 tty_attach(tp); 609 610 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 611 SET(sc->sc_mcr, MCR_IENABLE); 612 613 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 614 int maj; 615 616 /* locate the major number */ 617 maj = cdevsw_lookup_major(&com_cdevsw); 618 619 tp->t_dev = cn_tab->cn_dev = makedev(maj, 620 device_unit(sc->sc_dev)); 621 622 aprint_normal_dev(sc->sc_dev, "console\n"); 623 } 624 625 #ifdef KGDB 626 /* 627 * Allow kgdb to "take over" this port. If this is 628 * not the console and is the kgdb device, it has 629 * exclusive use. If it's the console _and_ the 630 * kgdb device, it doesn't. 631 */ 632 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 633 regsp->cr_iobase == comkgdbregs.cr_iobase) { 634 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 635 com_kgdb_attached = 1; 636 637 SET(sc->sc_hwflags, COM_HW_KGDB); 638 } 639 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 640 } 641 #endif 642 643 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 644 645 #ifdef RND_COM 646 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 647 RND_TYPE_TTY, RND_FLAG_DEFAULT); 648 #endif 649 650 /* if there are no enable/disable functions, assume the device 651 is always enabled */ 652 if (!sc->enable) 653 sc->enabled = 1; 654 655 com_config(sc); 656 657 SET(sc->sc_hwflags, COM_HW_DEV_OK); 658 } 659 660 void 661 com_config(struct com_softc *sc) 662 { 663 struct com_regs *regsp = &sc->sc_regs; 664 665 /* Disable interrupts before configuring the device. */ 666 if (sc->sc_type == COM_TYPE_PXA2x0) 667 sc->sc_ier = IER_EUART; 668 else 669 sc->sc_ier = 0; 670 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 671 (void) CSR_READ_1(regsp, COM_REG_IIR); 672 673 #ifdef COM_HAYESP 674 /* Look for a Hayes ESP board. */ 675 if (sc->sc_type == COM_TYPE_HAYESP) { 676 677 /* Set 16550 compatibility mode */ 678 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 679 HAYESP_SETMODE); 680 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 681 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 682 HAYESP_MODE_SCALE); 683 684 /* Set RTS/CTS flow control */ 685 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 686 HAYESP_SETFLOWTYPE); 687 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 688 HAYESP_FLOW_RTS); 689 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 690 HAYESP_FLOW_CTS); 691 692 /* Set flow control levels */ 693 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 694 HAYESP_SETRXFLOW); 695 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 696 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 697 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 698 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 699 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 700 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 701 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 702 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 703 } 704 #endif 705 706 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 707 com_enable_debugport(sc); 708 } 709 710 #if 0 711 static int 712 comcngetc_detached(dev_t dev) 713 { 714 return 0; 715 } 716 717 static void 718 comcnputc_detached(dev_t dev, int c) 719 { 720 } 721 #endif 722 723 int 724 com_detach(device_t self, int flags) 725 { 726 struct com_softc *sc = device_private(self); 727 int maj, mn; 728 729 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 730 return EBUSY; 731 732 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 733 (flags & DETACH_SHUTDOWN) != 0) 734 return EBUSY; 735 736 if (sc->disable != NULL && sc->enabled != 0) { 737 (*sc->disable)(sc); 738 sc->enabled = 0; 739 } 740 741 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 742 comconsattached = 0; 743 cn_tab = NULL; 744 } 745 746 /* locate the major number */ 747 maj = cdevsw_lookup_major(&com_cdevsw); 748 749 /* Nuke the vnodes for any open instances. */ 750 mn = device_unit(self); 751 vdevgone(maj, mn, mn, VCHR); 752 753 mn |= COMDIALOUT_MASK; 754 vdevgone(maj, mn, mn, VCHR); 755 756 if (sc->sc_rbuf == NULL) { 757 /* 758 * Ring buffer allocation failed in the com_attach_subr, 759 * only the tty is allocated, and nothing else. 760 */ 761 tty_free(sc->sc_tty); 762 return 0; 763 } 764 765 /* Free the receive buffer. */ 766 free(sc->sc_rbuf, M_DEVBUF); 767 768 /* Detach and free the tty. */ 769 tty_detach(sc->sc_tty); 770 tty_free(sc->sc_tty); 771 772 /* Unhook the soft interrupt handler. */ 773 softint_disestablish(sc->sc_si); 774 775 #ifdef RND_COM 776 /* Unhook the entropy source. */ 777 rnd_detach_source(&sc->rnd_source); 778 #endif 779 callout_destroy(&sc->sc_diag_callout); 780 781 /* Destroy the lock. */ 782 mutex_destroy(&sc->sc_lock); 783 784 return (0); 785 } 786 787 void 788 com_shutdown(struct com_softc *sc) 789 { 790 struct tty *tp = sc->sc_tty; 791 792 mutex_spin_enter(&sc->sc_lock); 793 794 /* If we were asserting flow control, then deassert it. */ 795 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 796 com_hwiflow(sc); 797 798 /* Clear any break condition set with TIOCSBRK. */ 799 com_break(sc, 0); 800 801 /* 802 * Hang up if necessary. Wait a bit, so the other side has time to 803 * notice even if we immediately open the port again. 804 * Avoid tsleeping above splhigh(). 805 */ 806 if (ISSET(tp->t_cflag, HUPCL)) { 807 com_modem(sc, 0); 808 mutex_spin_exit(&sc->sc_lock); 809 /* XXX will only timeout */ 810 (void) kpause(ttclos, false, hz, NULL); 811 mutex_spin_enter(&sc->sc_lock); 812 } 813 814 /* Turn off interrupts. */ 815 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 816 sc->sc_ier = IER_ERXRDY; /* interrupt on break */ 817 if ((sc->sc_type == COM_TYPE_PXA2x0) || 818 (sc->sc_type == COM_TYPE_INGENIC)) 819 sc->sc_ier |= IER_ERXTOUT; 820 } else 821 sc->sc_ier = 0; 822 823 if (sc->sc_type == COM_TYPE_PXA2x0) 824 sc->sc_ier |= IER_EUART; 825 826 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 827 828 mutex_spin_exit(&sc->sc_lock); 829 830 if (sc->disable) { 831 #ifdef DIAGNOSTIC 832 if (!sc->enabled) 833 panic("com_shutdown: not enabled?"); 834 #endif 835 (*sc->disable)(sc); 836 sc->enabled = 0; 837 } 838 } 839 840 int 841 comopen(dev_t dev, int flag, int mode, struct lwp *l) 842 { 843 struct com_softc *sc; 844 struct tty *tp; 845 int s; 846 int error; 847 848 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 849 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 850 sc->sc_rbuf == NULL) 851 return (ENXIO); 852 853 if (!device_is_active(sc->sc_dev)) 854 return (ENXIO); 855 856 #ifdef KGDB 857 /* 858 * If this is the kgdb port, no other use is permitted. 859 */ 860 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 861 return (EBUSY); 862 #endif 863 864 tp = sc->sc_tty; 865 866 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 867 return (EBUSY); 868 869 s = spltty(); 870 871 /* 872 * Do the following iff this is a first open. 873 */ 874 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 875 struct termios t; 876 877 tp->t_dev = dev; 878 879 if (sc->enable) { 880 if ((*sc->enable)(sc)) { 881 splx(s); 882 aprint_error_dev(sc->sc_dev, 883 "device enable failed\n"); 884 return (EIO); 885 } 886 mutex_spin_enter(&sc->sc_lock); 887 sc->enabled = 1; 888 com_config(sc); 889 } else { 890 mutex_spin_enter(&sc->sc_lock); 891 } 892 893 /* Turn on interrupts. */ 894 sc->sc_ier = IER_ERXRDY | IER_ERLS; 895 if (!ISSET(tp->t_cflag, CLOCAL)) 896 sc->sc_ier |= IER_EMSC; 897 898 if (sc->sc_type == COM_TYPE_PXA2x0) 899 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 900 else if (sc->sc_type == COM_TYPE_INGENIC) 901 sc->sc_ier |= IER_ERXTOUT; 902 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 903 904 /* Fetch the current modem control status, needed later. */ 905 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 906 907 /* Clear PPS capture state on first open. */ 908 mutex_spin_enter(&timecounter_lock); 909 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 910 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 911 pps_init(&sc->sc_pps_state); 912 mutex_spin_exit(&timecounter_lock); 913 914 mutex_spin_exit(&sc->sc_lock); 915 916 /* 917 * Initialize the termios status to the defaults. Add in the 918 * sticky bits from TIOCSFLAGS. 919 */ 920 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 921 t.c_ospeed = comcons_info.rate; 922 t.c_cflag = comcons_info.cflag; 923 } else { 924 t.c_ospeed = TTYDEF_SPEED; 925 t.c_cflag = TTYDEF_CFLAG; 926 } 927 t.c_ispeed = t.c_ospeed; 928 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 929 SET(t.c_cflag, CLOCAL); 930 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 931 SET(t.c_cflag, CRTSCTS); 932 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 933 SET(t.c_cflag, MDMBUF); 934 /* Make sure comparam() will do something. */ 935 tp->t_ospeed = 0; 936 (void) comparam(tp, &t); 937 tp->t_iflag = TTYDEF_IFLAG; 938 tp->t_oflag = TTYDEF_OFLAG; 939 tp->t_lflag = TTYDEF_LFLAG; 940 ttychars(tp); 941 ttsetwater(tp); 942 943 mutex_spin_enter(&sc->sc_lock); 944 945 /* 946 * Turn on DTR. We must always do this, even if carrier is not 947 * present, because otherwise we'd have to use TIOCSDTR 948 * immediately after setting CLOCAL, which applications do not 949 * expect. We always assert DTR while the device is open 950 * unless explicitly requested to deassert it. 951 */ 952 com_modem(sc, 1); 953 954 /* Clear the input ring, and unblock. */ 955 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 956 sc->sc_rbavail = com_rbuf_size; 957 com_iflush(sc); 958 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 959 com_hwiflow(sc); 960 961 #ifdef COM_DEBUG 962 if (com_debug) 963 comstatus(sc, "comopen "); 964 #endif 965 966 mutex_spin_exit(&sc->sc_lock); 967 } 968 969 splx(s); 970 971 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 972 if (error) 973 goto bad; 974 975 error = (*tp->t_linesw->l_open)(dev, tp); 976 if (error) 977 goto bad; 978 979 return (0); 980 981 bad: 982 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 983 /* 984 * We failed to open the device, and nobody else had it opened. 985 * Clean up the state as appropriate. 986 */ 987 com_shutdown(sc); 988 } 989 990 return (error); 991 } 992 993 int 994 comclose(dev_t dev, int flag, int mode, struct lwp *l) 995 { 996 struct com_softc *sc = 997 device_lookup_private(&com_cd, COMUNIT(dev)); 998 struct tty *tp = sc->sc_tty; 999 1000 /* XXX This is for cons.c. */ 1001 if (!ISSET(tp->t_state, TS_ISOPEN)) 1002 return (0); 1003 1004 (*tp->t_linesw->l_close)(tp, flag); 1005 ttyclose(tp); 1006 1007 if (COM_ISALIVE(sc) == 0) 1008 return (0); 1009 1010 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1011 /* 1012 * Although we got a last close, the device may still be in 1013 * use; e.g. if this was the dialout node, and there are still 1014 * processes waiting for carrier on the non-dialout node. 1015 */ 1016 com_shutdown(sc); 1017 } 1018 1019 return (0); 1020 } 1021 1022 int 1023 comread(dev_t dev, struct uio *uio, int flag) 1024 { 1025 struct com_softc *sc = 1026 device_lookup_private(&com_cd, COMUNIT(dev)); 1027 struct tty *tp = sc->sc_tty; 1028 1029 if (COM_ISALIVE(sc) == 0) 1030 return (EIO); 1031 1032 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1033 } 1034 1035 int 1036 comwrite(dev_t dev, struct uio *uio, int flag) 1037 { 1038 struct com_softc *sc = 1039 device_lookup_private(&com_cd, COMUNIT(dev)); 1040 struct tty *tp = sc->sc_tty; 1041 1042 if (COM_ISALIVE(sc) == 0) 1043 return (EIO); 1044 1045 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1046 } 1047 1048 int 1049 compoll(dev_t dev, int events, struct lwp *l) 1050 { 1051 struct com_softc *sc = 1052 device_lookup_private(&com_cd, COMUNIT(dev)); 1053 struct tty *tp = sc->sc_tty; 1054 1055 if (COM_ISALIVE(sc) == 0) 1056 return (POLLHUP); 1057 1058 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1059 } 1060 1061 struct tty * 1062 comtty(dev_t dev) 1063 { 1064 struct com_softc *sc = 1065 device_lookup_private(&com_cd, COMUNIT(dev)); 1066 struct tty *tp = sc->sc_tty; 1067 1068 return (tp); 1069 } 1070 1071 int 1072 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1073 { 1074 struct com_softc *sc; 1075 struct tty *tp; 1076 int error; 1077 1078 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1079 if (sc == NULL) 1080 return ENXIO; 1081 if (COM_ISALIVE(sc) == 0) 1082 return (EIO); 1083 1084 tp = sc->sc_tty; 1085 1086 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1087 if (error != EPASSTHROUGH) 1088 return (error); 1089 1090 error = ttioctl(tp, cmd, data, flag, l); 1091 if (error != EPASSTHROUGH) 1092 return (error); 1093 1094 error = 0; 1095 switch (cmd) { 1096 case TIOCSFLAGS: 1097 error = kauth_authorize_device_tty(l->l_cred, 1098 KAUTH_DEVICE_TTY_PRIVSET, tp); 1099 break; 1100 default: 1101 /* nothing */ 1102 break; 1103 } 1104 if (error) { 1105 return error; 1106 } 1107 1108 mutex_spin_enter(&sc->sc_lock); 1109 1110 switch (cmd) { 1111 case TIOCSBRK: 1112 com_break(sc, 1); 1113 break; 1114 1115 case TIOCCBRK: 1116 com_break(sc, 0); 1117 break; 1118 1119 case TIOCSDTR: 1120 com_modem(sc, 1); 1121 break; 1122 1123 case TIOCCDTR: 1124 com_modem(sc, 0); 1125 break; 1126 1127 case TIOCGFLAGS: 1128 *(int *)data = sc->sc_swflags; 1129 break; 1130 1131 case TIOCSFLAGS: 1132 sc->sc_swflags = *(int *)data; 1133 break; 1134 1135 case TIOCMSET: 1136 case TIOCMBIS: 1137 case TIOCMBIC: 1138 tiocm_to_com(sc, cmd, *(int *)data); 1139 break; 1140 1141 case TIOCMGET: 1142 *(int *)data = com_to_tiocm(sc); 1143 break; 1144 1145 case PPS_IOC_CREATE: 1146 case PPS_IOC_DESTROY: 1147 case PPS_IOC_GETPARAMS: 1148 case PPS_IOC_SETPARAMS: 1149 case PPS_IOC_GETCAP: 1150 case PPS_IOC_FETCH: 1151 #ifdef PPS_SYNC 1152 case PPS_IOC_KCBIND: 1153 #endif 1154 mutex_spin_enter(&timecounter_lock); 1155 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1156 mutex_spin_exit(&timecounter_lock); 1157 break; 1158 1159 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1160 mutex_spin_enter(&timecounter_lock); 1161 #ifndef PPS_TRAILING_EDGE 1162 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1163 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1164 #else 1165 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1166 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1167 #endif 1168 mutex_spin_exit(&timecounter_lock); 1169 break; 1170 1171 default: 1172 error = EPASSTHROUGH; 1173 break; 1174 } 1175 1176 mutex_spin_exit(&sc->sc_lock); 1177 1178 #ifdef COM_DEBUG 1179 if (com_debug) 1180 comstatus(sc, "comioctl "); 1181 #endif 1182 1183 return (error); 1184 } 1185 1186 integrate void 1187 com_schedrx(struct com_softc *sc) 1188 { 1189 1190 sc->sc_rx_ready = 1; 1191 1192 /* Wake up the poller. */ 1193 softint_schedule(sc->sc_si); 1194 } 1195 1196 void 1197 com_break(struct com_softc *sc, int onoff) 1198 { 1199 1200 if (onoff) 1201 SET(sc->sc_lcr, LCR_SBREAK); 1202 else 1203 CLR(sc->sc_lcr, LCR_SBREAK); 1204 1205 if (!sc->sc_heldchange) { 1206 if (sc->sc_tx_busy) { 1207 sc->sc_heldtbc = sc->sc_tbc; 1208 sc->sc_tbc = 0; 1209 sc->sc_heldchange = 1; 1210 } else 1211 com_loadchannelregs(sc); 1212 } 1213 } 1214 1215 void 1216 com_modem(struct com_softc *sc, int onoff) 1217 { 1218 1219 if (sc->sc_mcr_dtr == 0) 1220 return; 1221 1222 if (onoff) 1223 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1224 else 1225 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1226 1227 if (!sc->sc_heldchange) { 1228 if (sc->sc_tx_busy) { 1229 sc->sc_heldtbc = sc->sc_tbc; 1230 sc->sc_tbc = 0; 1231 sc->sc_heldchange = 1; 1232 } else 1233 com_loadchannelregs(sc); 1234 } 1235 } 1236 1237 void 1238 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1239 { 1240 u_char combits; 1241 1242 combits = 0; 1243 if (ISSET(ttybits, TIOCM_DTR)) 1244 SET(combits, MCR_DTR); 1245 if (ISSET(ttybits, TIOCM_RTS)) 1246 SET(combits, MCR_RTS); 1247 1248 switch (how) { 1249 case TIOCMBIC: 1250 CLR(sc->sc_mcr, combits); 1251 break; 1252 1253 case TIOCMBIS: 1254 SET(sc->sc_mcr, combits); 1255 break; 1256 1257 case TIOCMSET: 1258 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1259 SET(sc->sc_mcr, combits); 1260 break; 1261 } 1262 1263 if (!sc->sc_heldchange) { 1264 if (sc->sc_tx_busy) { 1265 sc->sc_heldtbc = sc->sc_tbc; 1266 sc->sc_tbc = 0; 1267 sc->sc_heldchange = 1; 1268 } else 1269 com_loadchannelregs(sc); 1270 } 1271 } 1272 1273 int 1274 com_to_tiocm(struct com_softc *sc) 1275 { 1276 u_char combits; 1277 int ttybits = 0; 1278 1279 combits = sc->sc_mcr; 1280 if (ISSET(combits, MCR_DTR)) 1281 SET(ttybits, TIOCM_DTR); 1282 if (ISSET(combits, MCR_RTS)) 1283 SET(ttybits, TIOCM_RTS); 1284 1285 combits = sc->sc_msr; 1286 if (sc->sc_type == COM_TYPE_INGENIC) { 1287 SET(ttybits, TIOCM_CD); 1288 } else { 1289 if (ISSET(combits, MSR_DCD)) 1290 SET(ttybits, TIOCM_CD); 1291 } 1292 if (ISSET(combits, MSR_CTS)) 1293 SET(ttybits, TIOCM_CTS); 1294 if (ISSET(combits, MSR_DSR)) 1295 SET(ttybits, TIOCM_DSR); 1296 if (ISSET(combits, MSR_RI | MSR_TERI)) 1297 SET(ttybits, TIOCM_RI); 1298 1299 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1300 SET(ttybits, TIOCM_LE); 1301 1302 return (ttybits); 1303 } 1304 1305 static u_char 1306 cflag2lcr(tcflag_t cflag) 1307 { 1308 u_char lcr = 0; 1309 1310 switch (ISSET(cflag, CSIZE)) { 1311 case CS5: 1312 SET(lcr, LCR_5BITS); 1313 break; 1314 case CS6: 1315 SET(lcr, LCR_6BITS); 1316 break; 1317 case CS7: 1318 SET(lcr, LCR_7BITS); 1319 break; 1320 case CS8: 1321 SET(lcr, LCR_8BITS); 1322 break; 1323 } 1324 if (ISSET(cflag, PARENB)) { 1325 SET(lcr, LCR_PENAB); 1326 if (!ISSET(cflag, PARODD)) 1327 SET(lcr, LCR_PEVEN); 1328 } 1329 if (ISSET(cflag, CSTOPB)) 1330 SET(lcr, LCR_STOPB); 1331 1332 return (lcr); 1333 } 1334 1335 int 1336 comparam(struct tty *tp, struct termios *t) 1337 { 1338 struct com_softc *sc = 1339 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1340 int ospeed; 1341 u_char lcr; 1342 1343 if (COM_ISALIVE(sc) == 0) 1344 return (EIO); 1345 1346 #ifdef COM_HAYESP 1347 if (sc->sc_type == COM_TYPE_HAYESP) { 1348 int prescaler, speed; 1349 1350 /* 1351 * Calculate UART clock prescaler. It should be in 1352 * range of 0 .. 3. 1353 */ 1354 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1355 prescaler++, speed /= 2) 1356 if ((ospeed = comspeed(speed, sc->sc_frequency, 1357 sc->sc_type)) > 0) 1358 break; 1359 1360 if (prescaler == 4) 1361 return (EINVAL); 1362 sc->sc_prescaler = prescaler; 1363 } else 1364 #endif 1365 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1366 1367 /* Check requested parameters. */ 1368 if (ospeed < 0) 1369 return (EINVAL); 1370 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1371 return (EINVAL); 1372 1373 /* 1374 * For the console, always force CLOCAL and !HUPCL, so that the port 1375 * is always active. 1376 */ 1377 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1378 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1379 SET(t->c_cflag, CLOCAL); 1380 CLR(t->c_cflag, HUPCL); 1381 } 1382 1383 /* 1384 * If there were no changes, don't do anything. This avoids dropping 1385 * input and improves performance when all we did was frob things like 1386 * VMIN and VTIME. 1387 */ 1388 if (tp->t_ospeed == t->c_ospeed && 1389 tp->t_cflag == t->c_cflag) 1390 return (0); 1391 1392 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1393 1394 mutex_spin_enter(&sc->sc_lock); 1395 1396 sc->sc_lcr = lcr; 1397 1398 /* 1399 * If we're not in a mode that assumes a connection is present, then 1400 * ignore carrier changes. 1401 */ 1402 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1403 sc->sc_msr_dcd = 0; 1404 else 1405 sc->sc_msr_dcd = MSR_DCD; 1406 /* 1407 * Set the flow control pins depending on the current flow control 1408 * mode. 1409 */ 1410 if (ISSET(t->c_cflag, CRTSCTS)) { 1411 sc->sc_mcr_dtr = MCR_DTR; 1412 sc->sc_mcr_rts = MCR_RTS; 1413 sc->sc_msr_cts = MSR_CTS; 1414 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1415 SET(sc->sc_mcr, MCR_AFE); 1416 } else { 1417 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1418 } 1419 } else if (ISSET(t->c_cflag, MDMBUF)) { 1420 /* 1421 * For DTR/DCD flow control, make sure we don't toggle DTR for 1422 * carrier detection. 1423 */ 1424 sc->sc_mcr_dtr = 0; 1425 sc->sc_mcr_rts = MCR_DTR; 1426 sc->sc_msr_cts = MSR_DCD; 1427 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1428 CLR(sc->sc_mcr, MCR_AFE); 1429 } else { 1430 sc->sc_efr = 0; 1431 } 1432 } else { 1433 /* 1434 * If no flow control, then always set RTS. This will make 1435 * the other side happy if it mistakenly thinks we're doing 1436 * RTS/CTS flow control. 1437 */ 1438 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1439 sc->sc_mcr_rts = 0; 1440 sc->sc_msr_cts = 0; 1441 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1442 CLR(sc->sc_mcr, MCR_AFE); 1443 } else { 1444 sc->sc_efr = 0; 1445 } 1446 if (ISSET(sc->sc_mcr, MCR_DTR)) 1447 SET(sc->sc_mcr, MCR_RTS); 1448 else 1449 CLR(sc->sc_mcr, MCR_RTS); 1450 } 1451 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1452 1453 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1454 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1455 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1456 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1457 1458 sc->sc_dlbl = ospeed; 1459 sc->sc_dlbh = ospeed >> 8; 1460 1461 /* 1462 * Set the FIFO threshold based on the receive speed. 1463 * 1464 * * If it's a low speed, it's probably a mouse or some other 1465 * interactive device, so set the threshold low. 1466 * * If it's a high speed, trim the trigger level down to prevent 1467 * overflows. 1468 * * Otherwise set it a bit higher. 1469 */ 1470 if (sc->sc_type == COM_TYPE_HAYESP) 1471 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1472 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1473 if (t->c_ospeed <= 1200) 1474 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1475 else if (t->c_ospeed <= 38400) 1476 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1477 else 1478 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1479 } else 1480 sc->sc_fifo = 0; 1481 1482 if (sc->sc_type == COM_TYPE_INGENIC) 1483 sc->sc_fifo |= FIFO_UART_ON; 1484 1485 /* And copy to tty. */ 1486 tp->t_ispeed = t->c_ospeed; 1487 tp->t_ospeed = t->c_ospeed; 1488 tp->t_cflag = t->c_cflag; 1489 1490 if (!sc->sc_heldchange) { 1491 if (sc->sc_tx_busy) { 1492 sc->sc_heldtbc = sc->sc_tbc; 1493 sc->sc_tbc = 0; 1494 sc->sc_heldchange = 1; 1495 } else 1496 com_loadchannelregs(sc); 1497 } 1498 1499 if (!ISSET(t->c_cflag, CHWFLOW)) { 1500 /* Disable the high water mark. */ 1501 sc->sc_r_hiwat = 0; 1502 sc->sc_r_lowat = 0; 1503 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1504 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1505 com_schedrx(sc); 1506 } 1507 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1508 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1509 com_hwiflow(sc); 1510 } 1511 } else { 1512 sc->sc_r_hiwat = com_rbuf_hiwat; 1513 sc->sc_r_lowat = com_rbuf_lowat; 1514 } 1515 1516 mutex_spin_exit(&sc->sc_lock); 1517 1518 /* 1519 * Update the tty layer's idea of the carrier bit, in case we changed 1520 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1521 * explicit request. 1522 */ 1523 if (sc->sc_type == COM_TYPE_INGENIC) { 1524 /* no DCD here */ 1525 (void) (*tp->t_linesw->l_modem)(tp, 1); 1526 } else 1527 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1528 1529 #ifdef COM_DEBUG 1530 if (com_debug) 1531 comstatus(sc, "comparam "); 1532 #endif 1533 1534 if (!ISSET(t->c_cflag, CHWFLOW)) { 1535 if (sc->sc_tx_stopped) { 1536 sc->sc_tx_stopped = 0; 1537 comstart(tp); 1538 } 1539 } 1540 1541 return (0); 1542 } 1543 1544 void 1545 com_iflush(struct com_softc *sc) 1546 { 1547 struct com_regs *regsp = &sc->sc_regs; 1548 #ifdef DIAGNOSTIC 1549 int reg; 1550 #endif 1551 int timo; 1552 1553 #ifdef DIAGNOSTIC 1554 reg = 0xffff; 1555 #endif 1556 timo = 50000; 1557 /* flush any pending I/O */ 1558 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1559 && --timo) 1560 #ifdef DIAGNOSTIC 1561 reg = 1562 #else 1563 (void) 1564 #endif 1565 CSR_READ_1(regsp, COM_REG_RXDATA); 1566 #ifdef DIAGNOSTIC 1567 if (!timo) 1568 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1569 #endif 1570 1571 #ifdef COM_16750 1572 uint8_t fifo; 1573 /* 1574 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1575 * This should prevent triggering busy interrupt while 1576 * manipulating divisors. 1577 */ 1578 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1579 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1580 CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST | 1581 FIFO_XMT_RST); 1582 delay(100); 1583 #endif 1584 } 1585 1586 void 1587 com_loadchannelregs(struct com_softc *sc) 1588 { 1589 struct com_regs *regsp = &sc->sc_regs; 1590 1591 /* XXXXX necessary? */ 1592 com_iflush(sc); 1593 1594 if (sc->sc_type == COM_TYPE_PXA2x0) 1595 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1596 else 1597 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1598 1599 if (sc->sc_type == COM_TYPE_OMAP) { 1600 /* disable before changing settings */ 1601 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1602 } 1603 1604 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1605 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1606 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1607 /* no EFR on alchemy */ 1608 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1609 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1610 } 1611 if (sc->sc_type == COM_TYPE_AU1x00) { 1612 /* alchemy has single separate 16-bit clock divisor register */ 1613 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1614 (sc->sc_dlbh << 8)); 1615 } else { 1616 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1617 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1618 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1619 } 1620 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1621 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1622 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1623 #ifdef COM_HAYESP 1624 if (sc->sc_type == COM_TYPE_HAYESP) { 1625 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1626 HAYESP_SETPRESCALER); 1627 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1628 sc->sc_prescaler); 1629 } 1630 #endif 1631 if (sc->sc_type == COM_TYPE_OMAP) { 1632 /* setup the fifos. the FCR value is not used as long 1633 as SCR[6] and SCR[7] are 0, which they are at reset 1634 and we never touch the SCR register */ 1635 uint8_t rx_fifo_trig = 40; 1636 uint8_t tx_fifo_trig = 60; 1637 uint8_t rx_start = 8; 1638 uint8_t rx_halt = 60; 1639 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1640 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1641 1642 /* enable access to TCR & TLR */ 1643 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1644 1645 /* write tcr and tlr values */ 1646 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1647 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1648 1649 /* disable access to TCR & TLR */ 1650 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1651 1652 /* enable again, but mode is based on speed */ 1653 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1654 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1655 } else { 1656 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1657 } 1658 } 1659 1660 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1661 } 1662 1663 int 1664 comhwiflow(struct tty *tp, int block) 1665 { 1666 struct com_softc *sc = 1667 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1668 1669 if (COM_ISALIVE(sc) == 0) 1670 return (0); 1671 1672 if (sc->sc_mcr_rts == 0) 1673 return (0); 1674 1675 mutex_spin_enter(&sc->sc_lock); 1676 1677 if (block) { 1678 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1679 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1680 com_hwiflow(sc); 1681 } 1682 } else { 1683 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1684 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1685 com_schedrx(sc); 1686 } 1687 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1688 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1689 com_hwiflow(sc); 1690 } 1691 } 1692 1693 mutex_spin_exit(&sc->sc_lock); 1694 return (1); 1695 } 1696 1697 /* 1698 * (un)block input via hw flowcontrol 1699 */ 1700 void 1701 com_hwiflow(struct com_softc *sc) 1702 { 1703 struct com_regs *regsp= &sc->sc_regs; 1704 1705 if (sc->sc_mcr_rts == 0) 1706 return; 1707 1708 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1709 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1710 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1711 } else { 1712 SET(sc->sc_mcr, sc->sc_mcr_rts); 1713 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1714 } 1715 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1716 } 1717 1718 1719 void 1720 comstart(struct tty *tp) 1721 { 1722 struct com_softc *sc = 1723 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1724 struct com_regs *regsp = &sc->sc_regs; 1725 int s; 1726 1727 if (COM_ISALIVE(sc) == 0) 1728 return; 1729 1730 s = spltty(); 1731 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1732 goto out; 1733 if (sc->sc_tx_stopped) 1734 goto out; 1735 if (!ttypull(tp)) 1736 goto out; 1737 1738 /* Grab the first contiguous region of buffer space. */ 1739 { 1740 u_char *tba; 1741 int tbc; 1742 1743 tba = tp->t_outq.c_cf; 1744 tbc = ndqb(&tp->t_outq, 0); 1745 1746 mutex_spin_enter(&sc->sc_lock); 1747 1748 sc->sc_tba = tba; 1749 sc->sc_tbc = tbc; 1750 } 1751 1752 SET(tp->t_state, TS_BUSY); 1753 sc->sc_tx_busy = 1; 1754 1755 /* Enable transmit completion interrupts if necessary. */ 1756 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1757 SET(sc->sc_ier, IER_ETXRDY); 1758 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1759 } 1760 1761 /* Output the first chunk of the contiguous buffer. */ 1762 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1763 u_int n; 1764 1765 n = sc->sc_tbc; 1766 if (n > sc->sc_fifolen) 1767 n = sc->sc_fifolen; 1768 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1769 sc->sc_tbc -= n; 1770 sc->sc_tba += n; 1771 } 1772 1773 mutex_spin_exit(&sc->sc_lock); 1774 out: 1775 splx(s); 1776 return; 1777 } 1778 1779 /* 1780 * Stop output on a line. 1781 */ 1782 void 1783 comstop(struct tty *tp, int flag) 1784 { 1785 struct com_softc *sc = 1786 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1787 1788 mutex_spin_enter(&sc->sc_lock); 1789 if (ISSET(tp->t_state, TS_BUSY)) { 1790 /* Stop transmitting at the next chunk. */ 1791 sc->sc_tbc = 0; 1792 sc->sc_heldtbc = 0; 1793 if (!ISSET(tp->t_state, TS_TTSTOP)) 1794 SET(tp->t_state, TS_FLUSH); 1795 } 1796 mutex_spin_exit(&sc->sc_lock); 1797 } 1798 1799 void 1800 comdiag(void *arg) 1801 { 1802 struct com_softc *sc = arg; 1803 int overflows, floods; 1804 1805 mutex_spin_enter(&sc->sc_lock); 1806 overflows = sc->sc_overflows; 1807 sc->sc_overflows = 0; 1808 floods = sc->sc_floods; 1809 sc->sc_floods = 0; 1810 sc->sc_errors = 0; 1811 mutex_spin_exit(&sc->sc_lock); 1812 1813 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1814 device_xname(sc->sc_dev), 1815 overflows, overflows == 1 ? "" : "s", 1816 floods, floods == 1 ? "" : "s"); 1817 } 1818 1819 integrate void 1820 com_rxsoft(struct com_softc *sc, struct tty *tp) 1821 { 1822 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1823 u_char *get, *end; 1824 u_int cc, scc; 1825 u_char lsr; 1826 int code; 1827 1828 end = sc->sc_ebuf; 1829 get = sc->sc_rbget; 1830 scc = cc = com_rbuf_size - sc->sc_rbavail; 1831 1832 if (cc == com_rbuf_size) { 1833 sc->sc_floods++; 1834 if (sc->sc_errors++ == 0) 1835 callout_reset(&sc->sc_diag_callout, 60 * hz, 1836 comdiag, sc); 1837 } 1838 1839 /* If not yet open, drop the entire buffer content here */ 1840 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1841 get += cc << 1; 1842 if (get >= end) 1843 get -= com_rbuf_size << 1; 1844 cc = 0; 1845 } 1846 while (cc) { 1847 code = get[0]; 1848 lsr = get[1]; 1849 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1850 if (ISSET(lsr, LSR_OE)) { 1851 sc->sc_overflows++; 1852 if (sc->sc_errors++ == 0) 1853 callout_reset(&sc->sc_diag_callout, 1854 60 * hz, comdiag, sc); 1855 } 1856 if (ISSET(lsr, LSR_BI | LSR_FE)) 1857 SET(code, TTY_FE); 1858 if (ISSET(lsr, LSR_PE)) 1859 SET(code, TTY_PE); 1860 } 1861 if ((*rint)(code, tp) == -1) { 1862 /* 1863 * The line discipline's buffer is out of space. 1864 */ 1865 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1866 /* 1867 * We're either not using flow control, or the 1868 * line discipline didn't tell us to block for 1869 * some reason. Either way, we have no way to 1870 * know when there's more space available, so 1871 * just drop the rest of the data. 1872 */ 1873 get += cc << 1; 1874 if (get >= end) 1875 get -= com_rbuf_size << 1; 1876 cc = 0; 1877 } else { 1878 /* 1879 * Don't schedule any more receive processing 1880 * until the line discipline tells us there's 1881 * space available (through comhwiflow()). 1882 * Leave the rest of the data in the input 1883 * buffer. 1884 */ 1885 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1886 } 1887 break; 1888 } 1889 get += 2; 1890 if (get >= end) 1891 get = sc->sc_rbuf; 1892 cc--; 1893 } 1894 1895 if (cc != scc) { 1896 sc->sc_rbget = get; 1897 mutex_spin_enter(&sc->sc_lock); 1898 1899 cc = sc->sc_rbavail += scc - cc; 1900 /* Buffers should be ok again, release possible block. */ 1901 if (cc >= sc->sc_r_lowat) { 1902 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1903 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1904 SET(sc->sc_ier, IER_ERXRDY); 1905 #ifdef COM_PXA2X0 1906 if (sc->sc_type == COM_TYPE_PXA2x0) 1907 SET(sc->sc_ier, IER_ERXTOUT); 1908 #endif 1909 if (sc->sc_type == COM_TYPE_INGENIC) 1910 sc->sc_ier |= IER_ERXTOUT; 1911 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 1912 sc->sc_ier); 1913 } 1914 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1915 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1916 com_hwiflow(sc); 1917 } 1918 } 1919 mutex_spin_exit(&sc->sc_lock); 1920 } 1921 } 1922 1923 integrate void 1924 com_txsoft(struct com_softc *sc, struct tty *tp) 1925 { 1926 1927 CLR(tp->t_state, TS_BUSY); 1928 if (ISSET(tp->t_state, TS_FLUSH)) 1929 CLR(tp->t_state, TS_FLUSH); 1930 else 1931 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1932 (*tp->t_linesw->l_start)(tp); 1933 } 1934 1935 integrate void 1936 com_stsoft(struct com_softc *sc, struct tty *tp) 1937 { 1938 u_char msr, delta; 1939 1940 mutex_spin_enter(&sc->sc_lock); 1941 msr = sc->sc_msr; 1942 delta = sc->sc_msr_delta; 1943 sc->sc_msr_delta = 0; 1944 mutex_spin_exit(&sc->sc_lock); 1945 1946 if (ISSET(delta, sc->sc_msr_dcd)) { 1947 /* 1948 * Inform the tty layer that carrier detect changed. 1949 */ 1950 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1951 } 1952 1953 if (ISSET(delta, sc->sc_msr_cts)) { 1954 /* Block or unblock output according to flow control. */ 1955 if (ISSET(msr, sc->sc_msr_cts)) { 1956 sc->sc_tx_stopped = 0; 1957 (*tp->t_linesw->l_start)(tp); 1958 } else { 1959 sc->sc_tx_stopped = 1; 1960 } 1961 } 1962 1963 #ifdef COM_DEBUG 1964 if (com_debug) 1965 comstatus(sc, "com_stsoft"); 1966 #endif 1967 } 1968 1969 void 1970 comsoft(void *arg) 1971 { 1972 struct com_softc *sc = arg; 1973 struct tty *tp; 1974 1975 if (COM_ISALIVE(sc) == 0) 1976 return; 1977 1978 tp = sc->sc_tty; 1979 1980 if (sc->sc_rx_ready) { 1981 sc->sc_rx_ready = 0; 1982 com_rxsoft(sc, tp); 1983 } 1984 1985 if (sc->sc_st_check) { 1986 sc->sc_st_check = 0; 1987 com_stsoft(sc, tp); 1988 } 1989 1990 if (sc->sc_tx_done) { 1991 sc->sc_tx_done = 0; 1992 com_txsoft(sc, tp); 1993 } 1994 } 1995 1996 int 1997 comintr(void *arg) 1998 { 1999 struct com_softc *sc = arg; 2000 struct com_regs *regsp = &sc->sc_regs; 2001 2002 u_char *put, *end; 2003 u_int cc; 2004 u_char lsr, iir; 2005 2006 if (COM_ISALIVE(sc) == 0) 2007 return (0); 2008 2009 KASSERT(regsp != NULL); 2010 2011 mutex_spin_enter(&sc->sc_lock); 2012 iir = CSR_READ_1(regsp, COM_REG_IIR); 2013 2014 /* Handle ns16750-specific busy interrupt. */ 2015 #ifdef COM_16750 2016 int timeout; 2017 if ((iir & IIR_BUSY) == IIR_BUSY) { 2018 for (timeout = 10000; 2019 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2020 if (timeout <= 0) { 2021 aprint_error_dev(sc->sc_dev, 2022 "timeout while waiting for BUSY interrupt " 2023 "acknowledge\n"); 2024 mutex_spin_exit(&sc->sc_lock); 2025 return (0); 2026 } 2027 2028 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2029 iir = CSR_READ_1(regsp, COM_REG_IIR); 2030 } 2031 #endif /* COM_16750 */ 2032 2033 2034 if (ISSET(iir, IIR_NOPEND)) { 2035 mutex_spin_exit(&sc->sc_lock); 2036 return (0); 2037 } 2038 2039 end = sc->sc_ebuf; 2040 put = sc->sc_rbput; 2041 cc = sc->sc_rbavail; 2042 2043 again: do { 2044 u_char msr, delta; 2045 2046 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2047 if (ISSET(lsr, LSR_BI)) { 2048 int cn_trapped = 0; /* see above: cn_trap() */ 2049 2050 cn_check_magic(sc->sc_tty->t_dev, 2051 CNC_BREAK, com_cnm_state); 2052 if (cn_trapped) 2053 continue; 2054 #if defined(KGDB) && !defined(DDB) 2055 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2056 kgdb_connect(1); 2057 continue; 2058 } 2059 #endif 2060 } 2061 2062 if (ISSET(lsr, LSR_RCV_MASK) && 2063 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2064 while (cc > 0) { 2065 int cn_trapped = 0; 2066 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2067 put[1] = lsr; 2068 cn_check_magic(sc->sc_tty->t_dev, 2069 put[0], com_cnm_state); 2070 if (cn_trapped) 2071 goto next; 2072 put += 2; 2073 if (put >= end) 2074 put = sc->sc_rbuf; 2075 cc--; 2076 next: 2077 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2078 if (!ISSET(lsr, LSR_RCV_MASK)) 2079 break; 2080 } 2081 2082 /* 2083 * Current string of incoming characters ended because 2084 * no more data was available or we ran out of space. 2085 * Schedule a receive event if any data was received. 2086 * If we're out of space, turn off receive interrupts. 2087 */ 2088 sc->sc_rbput = put; 2089 sc->sc_rbavail = cc; 2090 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2091 sc->sc_rx_ready = 1; 2092 2093 /* 2094 * See if we are in danger of overflowing a buffer. If 2095 * so, use hardware flow control to ease the pressure. 2096 */ 2097 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2098 cc < sc->sc_r_hiwat) { 2099 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2100 com_hwiflow(sc); 2101 } 2102 2103 /* 2104 * If we're out of space, disable receive interrupts 2105 * until the queue has drained a bit. 2106 */ 2107 if (!cc) { 2108 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2109 #ifdef COM_PXA2X0 2110 if (sc->sc_type == COM_TYPE_PXA2x0) 2111 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2112 else 2113 #endif 2114 if (sc->sc_type == COM_TYPE_INGENIC) 2115 sc->sc_ier |= IER_ERXRDY|IER_ERXTOUT; 2116 else 2117 CLR(sc->sc_ier, IER_ERXRDY); 2118 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2119 } 2120 } else { 2121 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2122 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2123 continue; 2124 } 2125 } 2126 2127 msr = CSR_READ_1(regsp, COM_REG_MSR); 2128 delta = msr ^ sc->sc_msr; 2129 sc->sc_msr = msr; 2130 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2131 (delta & MSR_DCD)) { 2132 mutex_spin_enter(&timecounter_lock); 2133 pps_capture(&sc->sc_pps_state); 2134 pps_event(&sc->sc_pps_state, 2135 (msr & MSR_DCD) ? 2136 PPS_CAPTUREASSERT : 2137 PPS_CAPTURECLEAR); 2138 mutex_spin_exit(&timecounter_lock); 2139 } 2140 2141 /* 2142 * Process normal status changes 2143 */ 2144 if (ISSET(delta, sc->sc_msr_mask)) { 2145 SET(sc->sc_msr_delta, delta); 2146 2147 /* 2148 * Stop output immediately if we lose the output 2149 * flow control signal or carrier detect. 2150 */ 2151 if (ISSET(~msr, sc->sc_msr_mask)) { 2152 sc->sc_tbc = 0; 2153 sc->sc_heldtbc = 0; 2154 #ifdef COM_DEBUG 2155 if (com_debug) 2156 comstatus(sc, "comintr "); 2157 #endif 2158 } 2159 2160 sc->sc_st_check = 1; 2161 } 2162 } while (!ISSET((iir = 2163 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2164 /* 2165 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2166 * by IIR read, so we can't do this way: `process all interrupts, 2167 * then do TX if possible'. 2168 */ 2169 (iir & IIR_IMASK) != IIR_TXRDY); 2170 2171 /* 2172 * Read LSR again, since there may be an interrupt between 2173 * the last LSR read and IIR read above. 2174 */ 2175 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2176 2177 /* 2178 * See if data can be transmitted as well. 2179 * Schedule tx done event if no data left 2180 * and tty was marked busy. 2181 */ 2182 if (ISSET(lsr, LSR_TXRDY)) { 2183 /* 2184 * If we've delayed a parameter change, do it now, and restart 2185 * output. 2186 */ 2187 if (sc->sc_heldchange) { 2188 com_loadchannelregs(sc); 2189 sc->sc_heldchange = 0; 2190 sc->sc_tbc = sc->sc_heldtbc; 2191 sc->sc_heldtbc = 0; 2192 } 2193 2194 /* Output the next chunk of the contiguous buffer, if any. */ 2195 if (sc->sc_tbc > 0) { 2196 u_int n; 2197 2198 n = sc->sc_tbc; 2199 if (n > sc->sc_fifolen) 2200 n = sc->sc_fifolen; 2201 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2202 sc->sc_tbc -= n; 2203 sc->sc_tba += n; 2204 } else { 2205 /* Disable transmit completion interrupts if necessary. */ 2206 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2207 CLR(sc->sc_ier, IER_ETXRDY); 2208 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2209 } 2210 if (sc->sc_tx_busy) { 2211 sc->sc_tx_busy = 0; 2212 sc->sc_tx_done = 1; 2213 } 2214 } 2215 } 2216 2217 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2218 goto again; 2219 2220 mutex_spin_exit(&sc->sc_lock); 2221 2222 /* Wake up the poller. */ 2223 softint_schedule(sc->sc_si); 2224 2225 #ifdef RND_COM 2226 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2227 #endif 2228 2229 return (1); 2230 } 2231 2232 /* 2233 * The following functions are polled getc and putc routines, shared 2234 * by the console and kgdb glue. 2235 * 2236 * The read-ahead code is so that you can detect pending in-band 2237 * cn_magic in polled mode while doing output rather than having to 2238 * wait until the kernel decides it needs input. 2239 */ 2240 2241 #define MAX_READAHEAD 20 2242 static int com_readahead[MAX_READAHEAD]; 2243 static int com_readaheadcount = 0; 2244 2245 int 2246 com_common_getc(dev_t dev, struct com_regs *regsp) 2247 { 2248 int s = splserial(); 2249 u_char stat, c; 2250 2251 /* got a character from reading things earlier */ 2252 if (com_readaheadcount > 0) { 2253 int i; 2254 2255 c = com_readahead[0]; 2256 for (i = 1; i < com_readaheadcount; i++) { 2257 com_readahead[i-1] = com_readahead[i]; 2258 } 2259 com_readaheadcount--; 2260 splx(s); 2261 return (c); 2262 } 2263 2264 /* don't block until a character becomes available */ 2265 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2266 splx(s); 2267 return -1; 2268 } 2269 2270 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2271 stat = CSR_READ_1(regsp, COM_REG_IIR); 2272 { 2273 int cn_trapped = 0; /* required by cn_trap, see above */ 2274 #ifdef DDB 2275 extern int db_active; 2276 if (!db_active) 2277 #endif 2278 cn_check_magic(dev, c, com_cnm_state); 2279 } 2280 splx(s); 2281 return (c); 2282 } 2283 2284 static void 2285 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2286 { 2287 int s = splserial(); 2288 int cin, stat, timo; 2289 2290 if (com_readaheadcount < MAX_READAHEAD 2291 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2292 int cn_trapped = 0; 2293 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2294 stat = CSR_READ_1(regsp, COM_REG_IIR); 2295 cn_check_magic(dev, cin, com_cnm_state); 2296 com_readahead[com_readaheadcount++] = cin; 2297 } 2298 2299 /* wait for any pending transmission to finish */ 2300 timo = 150000; 2301 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2302 continue; 2303 2304 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2305 COM_BARRIER(regsp, BR | BW); 2306 2307 splx(s); 2308 } 2309 2310 /* 2311 * Initialize UART for use as console or KGDB line. 2312 */ 2313 int 2314 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2315 tcflag_t cflag) 2316 { 2317 2318 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2319 ®sp->cr_ioh)) 2320 return (ENOMEM); /* ??? */ 2321 2322 if (type == COM_TYPE_OMAP) { 2323 /* disable before changing settings */ 2324 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2325 } 2326 2327 rate = comspeed(rate, frequency, type); 2328 if (__predict_true(rate != -1)) { 2329 if (type == COM_TYPE_AU1x00) { 2330 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2331 } else { 2332 /* no EFR on alchemy */ 2333 if ((type != COM_TYPE_16550_NOERS) && 2334 (type != COM_TYPE_INGENIC)) { 2335 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2336 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2337 } 2338 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2339 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2340 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2341 } 2342 } 2343 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2344 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2345 2346 if (type == COM_TYPE_INGENIC) { 2347 CSR_WRITE_1(regsp, COM_REG_FIFO, 2348 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2349 FIFO_TRIGGER_1 | FIFO_UART_ON); 2350 } else { 2351 CSR_WRITE_1(regsp, COM_REG_FIFO, 2352 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2353 FIFO_TRIGGER_1); 2354 } 2355 2356 if (type == COM_TYPE_OMAP) { 2357 /* setup the fifos. the FCR value is not used as long 2358 as SCR[6] and SCR[7] are 0, which they are at reset 2359 and we never touch the SCR register */ 2360 uint8_t rx_fifo_trig = 40; 2361 uint8_t tx_fifo_trig = 60; 2362 uint8_t rx_start = 8; 2363 uint8_t rx_halt = 60; 2364 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2365 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2366 2367 /* enable access to TCR & TLR */ 2368 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2369 2370 /* write tcr and tlr values */ 2371 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2372 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2373 2374 /* disable access to TCR & TLR */ 2375 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2376 2377 /* enable again, but mode is based on speed */ 2378 if (rate > 230400) { 2379 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2380 } else { 2381 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2382 } 2383 } 2384 2385 #ifdef COM_PXA2X0 2386 if (type == COM_TYPE_PXA2x0) 2387 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2388 else 2389 #endif 2390 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2391 2392 return (0); 2393 } 2394 2395 int 2396 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2397 tcflag_t cflag) 2398 { 2399 int res; 2400 2401 comcons_info.regs = *regsp; 2402 2403 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2404 if (res) 2405 return (res); 2406 2407 cn_tab = &comcons; 2408 cn_init_magic(&com_cnm_state); 2409 cn_set_magic("\047\001"); /* default magic is BREAK */ 2410 2411 comcons_info.frequency = frequency; 2412 comcons_info.type = type; 2413 comcons_info.rate = rate; 2414 comcons_info.cflag = cflag; 2415 2416 return (0); 2417 } 2418 2419 int 2420 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2421 int type, tcflag_t cflag) 2422 { 2423 struct com_regs regs; 2424 2425 memset(®s, 0, sizeof regs); 2426 regs.cr_iot = iot; 2427 regs.cr_iobase = iobase; 2428 regs.cr_nports = COM_NPORTS; 2429 #ifdef COM_REGMAP 2430 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2431 #endif 2432 2433 return comcnattach1(®s, rate, frequency, type, cflag); 2434 } 2435 2436 static int 2437 comcnreattach(void) 2438 { 2439 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2440 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2441 } 2442 2443 int 2444 comcngetc(dev_t dev) 2445 { 2446 2447 return (com_common_getc(dev, &comcons_info.regs)); 2448 } 2449 2450 /* 2451 * Console kernel output character routine. 2452 */ 2453 void 2454 comcnputc(dev_t dev, int c) 2455 { 2456 2457 com_common_putc(dev, &comcons_info.regs, c); 2458 } 2459 2460 void 2461 comcnpollc(dev_t dev, int on) 2462 { 2463 2464 com_readaheadcount = 0; 2465 } 2466 2467 #ifdef KGDB 2468 int 2469 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2470 tcflag_t cflag) 2471 { 2472 int res; 2473 2474 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2475 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2476 #if !defined(DDB) 2477 return (EBUSY); /* cannot share with console */ 2478 #else 2479 comkgdbregs = *regsp; 2480 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2481 #endif 2482 } else { 2483 comkgdbregs = *regsp; 2484 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2485 if (res) 2486 return (res); 2487 2488 /* 2489 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2490 * expects this to be initialized 2491 */ 2492 cn_init_magic(&com_cnm_state); 2493 cn_set_magic("\047\001"); 2494 } 2495 2496 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2497 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2498 2499 return (0); 2500 } 2501 2502 int 2503 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2504 int frequency, int type, tcflag_t cflag) 2505 { 2506 struct com_regs regs; 2507 2508 regs.cr_iot = iot; 2509 regs.cr_nports = COM_NPORTS; 2510 regs.cr_iobase = iobase; 2511 #ifdef COM_REGMAP 2512 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2513 #endif 2514 2515 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2516 } 2517 2518 /* ARGSUSED */ 2519 int 2520 com_kgdb_getc(void *arg) 2521 { 2522 2523 return (com_common_getc(NODEV, &comkgdbregs)); 2524 } 2525 2526 /* ARGSUSED */ 2527 void 2528 com_kgdb_putc(void *arg, int c) 2529 { 2530 2531 com_common_putc(NODEV, &comkgdbregs, c); 2532 } 2533 #endif /* KGDB */ 2534 2535 /* helper function to identify the com ports used by 2536 console or KGDB (and not yet autoconf attached) */ 2537 int 2538 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2539 { 2540 bus_space_handle_t help; 2541 2542 if (!comconsattached && 2543 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2544 iobase == comcons_info.regs.cr_iobase) 2545 help = comcons_info.regs.cr_ioh; 2546 #ifdef KGDB 2547 else if (!com_kgdb_attached && 2548 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2549 iobase == comkgdbregs.cr_iobase) 2550 help = comkgdbregs.cr_ioh; 2551 #endif 2552 else 2553 return (0); 2554 2555 if (ioh) 2556 *ioh = help; 2557 return (1); 2558 } 2559 2560 /* 2561 * this routine exists to serve as a shutdown hook for systems that 2562 * have firmware which doesn't interact properly with a com device in 2563 * FIFO mode. 2564 */ 2565 bool 2566 com_cleanup(device_t self, int how) 2567 { 2568 struct com_softc *sc = device_private(self); 2569 2570 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2571 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2572 2573 return true; 2574 } 2575 2576 bool 2577 com_suspend(device_t self, const pmf_qual_t *qual) 2578 { 2579 struct com_softc *sc = device_private(self); 2580 2581 #if 0 2582 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2583 cn_tab = &comcons_suspend; 2584 #endif 2585 2586 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2587 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2588 2589 return true; 2590 } 2591 2592 bool 2593 com_resume(device_t self, const pmf_qual_t *qual) 2594 { 2595 struct com_softc *sc = device_private(self); 2596 2597 mutex_spin_enter(&sc->sc_lock); 2598 com_loadchannelregs(sc); 2599 mutex_spin_exit(&sc->sc_lock); 2600 2601 return true; 2602 } 2603
Indexes created Wed Sep 24 05:09:52 GMT 2025