com.c revision 1.340
1 /* $NetBSD: com.c,v 1.340 2017/07/31 09:25:14 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.340 2017/07/31 09:25:14 jmcneill Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #ifdef COM_HAYESP 126 #include <dev/ic/hayespreg.h> 127 #endif 128 #define com_lcr com_cfcr 129 #include <dev/cons.h> 130 131 #ifdef COM_REGMAP 132 #define CSR_WRITE_1(r, o, v) \ 133 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 134 #define CSR_READ_1(r, o) \ 135 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 136 #define CSR_WRITE_2(r, o, v) \ 137 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 138 #define CSR_READ_2(r, o) \ 139 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 140 #define CSR_WRITE_MULTI(r, o, p, n) \ 141 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 142 #else 143 #define CSR_WRITE_1(r, o, v) \ 144 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 145 #define CSR_READ_1(r, o) \ 146 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 147 #define CSR_WRITE_2(r, o, v) \ 148 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 149 #define CSR_READ_2(r, o) \ 150 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 151 #define CSR_WRITE_MULTI(r, o, p, n) \ 152 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 153 #endif 154 155 156 static void com_enable_debugport(struct com_softc *); 157 158 void com_config(struct com_softc *); 159 void com_shutdown(struct com_softc *); 160 int comspeed(long, long, int); 161 static u_char cflag2lcr(tcflag_t); 162 int comparam(struct tty *, struct termios *); 163 void comstart(struct tty *); 164 int comhwiflow(struct tty *, int); 165 166 void com_loadchannelregs(struct com_softc *); 167 void com_hwiflow(struct com_softc *); 168 void com_break(struct com_softc *, int); 169 void com_modem(struct com_softc *, int); 170 void tiocm_to_com(struct com_softc *, u_long, int); 171 int com_to_tiocm(struct com_softc *); 172 void com_iflush(struct com_softc *); 173 174 int com_common_getc(dev_t, struct com_regs *); 175 static void com_common_putc(dev_t, struct com_regs *, int); 176 177 int cominit(struct com_regs *, int, int, int, tcflag_t); 178 179 static int comcnreattach(void); 180 181 int comcngetc(dev_t); 182 void comcnputc(dev_t, int); 183 void comcnpollc(dev_t, int); 184 185 #define integrate static inline 186 void comsoft(void *); 187 integrate void com_rxsoft(struct com_softc *, struct tty *); 188 integrate void com_txsoft(struct com_softc *, struct tty *); 189 integrate void com_stsoft(struct com_softc *, struct tty *); 190 integrate void com_schedrx(struct com_softc *); 191 void comdiag(void *); 192 193 extern struct cfdriver com_cd; 194 195 dev_type_open(comopen); 196 dev_type_close(comclose); 197 dev_type_read(comread); 198 dev_type_write(comwrite); 199 dev_type_ioctl(comioctl); 200 dev_type_stop(comstop); 201 dev_type_tty(comtty); 202 dev_type_poll(compoll); 203 204 static struct comcons_info comcons_info; 205 206 /* 207 * Following are all routines needed for COM to act as console 208 */ 209 static struct consdev comcons = { 210 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 211 NODEV, CN_NORMAL 212 }; 213 214 215 const struct cdevsw com_cdevsw = { 216 .d_open = comopen, 217 .d_close = comclose, 218 .d_read = comread, 219 .d_write = comwrite, 220 .d_ioctl = comioctl, 221 .d_stop = comstop, 222 .d_tty = comtty, 223 .d_poll = compoll, 224 .d_mmap = nommap, 225 .d_kqfilter = ttykqfilter, 226 .d_discard = nodiscard, 227 .d_flag = D_TTY 228 }; 229 230 /* 231 * Make this an option variable one can patch. 232 * But be warned: this must be a power of 2! 233 */ 234 u_int com_rbuf_size = COM_RING_SIZE; 235 236 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 237 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 238 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 239 240 static int comconsattached; 241 static struct cnm_state com_cnm_state; 242 243 #ifdef KGDB 244 #include <sys/kgdb.h> 245 246 static struct com_regs comkgdbregs; 247 static int com_kgdb_attached; 248 249 int com_kgdb_getc(void *); 250 void com_kgdb_putc(void *, int); 251 #endif /* KGDB */ 252 253 #ifdef COM_REGMAP 254 /* initializer for typical 16550-ish hardware */ 255 #define COM_REG_16550 { \ 256 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 257 com_efr, com_lcr, com_mcr, com_lsr, com_msr } 258 /* 16750-specific register set, additional UART status register */ 259 #define COM_REG_16750 { \ 260 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 261 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 262 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } 263 264 #ifdef COM_16750 265 const bus_size_t com_std_map[32] = COM_REG_16750; 266 #else 267 const bus_size_t com_std_map[16] = COM_REG_16550; 268 #endif /* COM_16750 */ 269 #endif /* COM_REGMAP */ 270 271 #define COMDIALOUT_MASK TTDIALOUT_MASK 272 273 #define COMUNIT(x) TTUNIT(x) 274 #define COMDIALOUT(x) TTDIALOUT(x) 275 276 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 277 device_is_active((sc)->sc_dev)) 278 279 #define BR BUS_SPACE_BARRIER_READ 280 #define BW BUS_SPACE_BARRIER_WRITE 281 #define COM_BARRIER(r, f) \ 282 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 283 284 /*ARGSUSED*/ 285 int 286 comspeed(long speed, long frequency, int type) 287 { 288 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 289 290 int x, err; 291 int divisor = 16; 292 293 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 294 divisor = 13; 295 } 296 297 if (speed == 0) 298 return (0); 299 if (speed < 0) 300 return (-1); 301 x = divrnd(frequency / divisor, speed); 302 if (x <= 0) 303 return (-1); 304 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 305 if (err < 0) 306 err = -err; 307 if (err > COM_TOLERANCE) 308 return (-1); 309 return (x); 310 311 #undef divrnd 312 } 313 314 #ifdef COM_DEBUG 315 int com_debug = 0; 316 317 void comstatus(struct com_softc *, const char *); 318 void 319 comstatus(struct com_softc *sc, const char *str) 320 { 321 struct tty *tp = sc->sc_tty; 322 323 aprint_normal_dev(sc->sc_dev, 324 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 325 str, 326 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 327 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 328 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 329 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 330 sc->sc_tx_stopped ? '+' : '-'); 331 332 aprint_normal_dev(sc->sc_dev, 333 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 334 str, 335 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 336 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 337 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 338 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 339 sc->sc_rx_flags); 340 } 341 #endif 342 343 int 344 com_probe_subr(struct com_regs *regs) 345 { 346 347 /* force access to id reg */ 348 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 349 CSR_WRITE_1(regs, COM_REG_IIR, 0); 350 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 351 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 352 return (0); 353 354 return (1); 355 } 356 357 int 358 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 359 { 360 struct com_regs regs; 361 362 regs.cr_iot = iot; 363 regs.cr_ioh = ioh; 364 #ifdef COM_REGMAP 365 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 366 #endif 367 368 return com_probe_subr(®s); 369 } 370 371 /* 372 * No locking in this routine; it is only called during attach, 373 * or with the port already locked. 374 */ 375 static void 376 com_enable_debugport(struct com_softc *sc) 377 { 378 379 /* Turn on line break interrupt, set carrier. */ 380 sc->sc_ier = IER_ERLS; 381 if (sc->sc_type == COM_TYPE_PXA2x0) 382 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 383 if (sc->sc_type == COM_TYPE_INGENIC || 384 sc->sc_type == COM_TYPE_TEGRA) 385 sc->sc_ier |= IER_ERXTOUT; 386 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 387 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 388 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 389 } 390 391 void 392 com_attach_subr(struct com_softc *sc) 393 { 394 struct com_regs *regsp = &sc->sc_regs; 395 struct tty *tp; 396 #if defined(COM_16650) || defined(COM_16750) 397 u_int8_t lcr; 398 #endif 399 const char *fifo_msg = NULL; 400 prop_dictionary_t dict; 401 bool is_console = true; 402 403 aprint_naive("\n"); 404 405 dict = device_properties(sc->sc_dev); 406 prop_dictionary_get_bool(dict, "is_console", &is_console); 407 callout_init(&sc->sc_diag_callout, 0); 408 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 409 410 /* Disable interrupts before configuring the device. */ 411 if (sc->sc_type == COM_TYPE_PXA2x0) 412 sc->sc_ier = IER_EUART; 413 else 414 sc->sc_ier = 0; 415 416 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 417 418 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 419 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 420 comconsattached = 1; 421 422 if (cn_tab == NULL && comcnreattach() != 0) { 423 printf("can't re-init serial console @%lx\n", 424 (u_long)comcons_info.regs.cr_iobase); 425 } 426 427 #if defined(COM_16750) || defined(COM_AWIN) 428 /* Use in comintr(). */ 429 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 430 #endif 431 432 /* Make sure the console is always "hardwired". */ 433 delay(10000); /* wait for output to finish */ 434 if (is_console) { 435 SET(sc->sc_hwflags, COM_HW_CONSOLE); 436 } 437 438 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 439 } 440 441 /* Probe for FIFO */ 442 switch (sc->sc_type) { 443 case COM_TYPE_HAYESP: 444 goto fifodone; 445 446 case COM_TYPE_AU1x00: 447 sc->sc_fifolen = 16; 448 fifo_msg = "Au1X00 UART, working fifo"; 449 SET(sc->sc_hwflags, COM_HW_FIFO); 450 goto fifodelay; 451 452 case COM_TYPE_16550_NOERS: 453 sc->sc_fifolen = 16; 454 fifo_msg = "ns16650, no ERS, working fifo"; 455 SET(sc->sc_hwflags, COM_HW_FIFO); 456 goto fifodelay; 457 458 case COM_TYPE_OMAP: 459 sc->sc_fifolen = 64; 460 fifo_msg = "OMAP UART, working fifo"; 461 SET(sc->sc_hwflags, COM_HW_FIFO); 462 goto fifodelay; 463 464 case COM_TYPE_INGENIC: 465 sc->sc_fifolen = 16; 466 fifo_msg = "Ingenic UART, working fifo"; 467 SET(sc->sc_hwflags, COM_HW_FIFO); 468 SET(sc->sc_hwflags, COM_HW_NOIEN); 469 goto fifodelay; 470 471 case COM_TYPE_TEGRA: 472 sc->sc_fifolen = 8; 473 fifo_msg = "Tegra UART, working fifo"; 474 SET(sc->sc_hwflags, COM_HW_FIFO); 475 CSR_WRITE_1(regsp, COM_REG_FIFO, 476 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 477 goto fifodelay; 478 479 case COM_TYPE_BCMAUXUART: 480 sc->sc_fifolen = 8; 481 fifo_msg = "BCM AUX UART, working fifo"; 482 SET(sc->sc_hwflags, COM_HW_FIFO); 483 CSR_WRITE_1(regsp, COM_REG_FIFO, 484 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 485 goto fifodelay; 486 } 487 488 sc->sc_fifolen = 1; 489 /* look for a NS 16550AF UART with FIFOs */ 490 if (sc->sc_type == COM_TYPE_INGENIC) { 491 CSR_WRITE_1(regsp, COM_REG_FIFO, 492 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 493 FIFO_TRIGGER_14 | FIFO_UART_ON); 494 } else 495 CSR_WRITE_1(regsp, COM_REG_FIFO, 496 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 497 delay(100); 498 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 499 == IIR_FIFO_MASK) 500 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 501 == FIFO_TRIGGER_14) { 502 SET(sc->sc_hwflags, COM_HW_FIFO); 503 504 #ifdef COM_16650 505 /* 506 * IIR changes into the EFR if LCR is set to LCR_EERS 507 * on 16650s. We also know IIR != 0 at this point. 508 * Write 0 into the EFR, and read it. If the result 509 * is 0, we have a 16650. 510 * 511 * Older 16650s were broken; the test to detect them 512 * is taken from the Linux driver. Apparently 513 * setting DLAB enable gives access to the EFR on 514 * these chips. 515 */ 516 lcr = CSR_READ_1(regsp, COM_REG_LCR); 517 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 518 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 519 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 520 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 521 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 522 CLR(sc->sc_hwflags, COM_HW_FIFO); 523 sc->sc_fifolen = 0; 524 } else { 525 SET(sc->sc_hwflags, COM_HW_FLOW); 526 sc->sc_fifolen = 32; 527 } 528 } else 529 #endif 530 sc->sc_fifolen = 16; 531 532 #ifdef COM_16750 533 /* 534 * TL16C750 can enable 64byte FIFO, only when DLAB 535 * is 1. However, some 16750 may always enable. For 536 * example, restrictions according to DLAB in a data 537 * sheet for SC16C750 were not described. 538 * Please enable 'options COM_16650', supposing you 539 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 540 * should become effective. 541 */ 542 uint8_t iir1, iir2; 543 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 544 545 if (sc->sc_type == COM_TYPE_INGENIC) 546 fcr |= FIFO_UART_ON; 547 548 lcr = CSR_READ_1(regsp, COM_REG_LCR); 549 CSR_WRITE_1(regsp, COM_REG_LCR, lcr & ~LCR_DLAB); 550 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 551 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 552 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 553 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 554 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr | FIFO_64B_ENABLE); 555 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 556 557 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 558 559 if (!ISSET(iir1, IIR_64B_FIFO) && 560 ISSET(iir2, IIR_64B_FIFO)) { 561 /* It is TL16C750. */ 562 sc->sc_fifolen = 64; 563 SET(sc->sc_hwflags, COM_HW_AFE); 564 } else 565 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 566 #endif 567 568 #ifdef COM_16650 569 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 570 if (sc->sc_fifolen == 0) 571 fifo_msg = "st16650, broken fifo"; 572 else if (sc->sc_fifolen == 32) 573 fifo_msg = "st16650a, working fifo"; 574 else 575 #endif 576 #ifdef COM_16750 577 if (sc->sc_fifolen == 64) 578 fifo_msg = "tl16c750, working fifo"; 579 else 580 #endif 581 fifo_msg = "ns16550a, working fifo"; 582 } else 583 fifo_msg = "ns16550, broken fifo"; 584 else 585 fifo_msg = "ns8250 or ns16450, no fifo"; 586 if (sc->sc_type == COM_TYPE_INGENIC) { 587 CSR_WRITE_1(regsp, COM_REG_FIFO, FIFO_UART_ON); 588 } else 589 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 590 fifodelay: 591 /* 592 * Some chips will clear down both Tx and Rx FIFOs when zero is 593 * written to com_fifo. If this chip is the console, writing zero 594 * results in some of the chip/FIFO description being lost, so delay 595 * printing it until now. 596 */ 597 delay(10); 598 aprint_normal(": %s\n", fifo_msg); 599 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 600 sc->sc_fifolen = 1; 601 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 602 } 603 604 fifodone: 605 606 tp = tty_alloc(); 607 tp->t_oproc = comstart; 608 tp->t_param = comparam; 609 tp->t_hwiflow = comhwiflow; 610 tp->t_softc = sc; 611 612 sc->sc_tty = tp; 613 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 614 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 615 sc->sc_rbavail = com_rbuf_size; 616 if (sc->sc_rbuf == NULL) { 617 aprint_error_dev(sc->sc_dev, 618 "unable to allocate ring buffer\n"); 619 return; 620 } 621 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 622 623 tty_attach(tp); 624 625 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 626 SET(sc->sc_mcr, MCR_IENABLE); 627 628 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 629 int maj; 630 631 /* locate the major number */ 632 maj = cdevsw_lookup_major(&com_cdevsw); 633 634 tp->t_dev = cn_tab->cn_dev = makedev(maj, 635 device_unit(sc->sc_dev)); 636 637 aprint_normal_dev(sc->sc_dev, "console\n"); 638 } 639 640 #ifdef KGDB 641 /* 642 * Allow kgdb to "take over" this port. If this is 643 * not the console and is the kgdb device, it has 644 * exclusive use. If it's the console _and_ the 645 * kgdb device, it doesn't. 646 */ 647 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 648 regsp->cr_iobase == comkgdbregs.cr_iobase) { 649 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 650 com_kgdb_attached = 1; 651 652 SET(sc->sc_hwflags, COM_HW_KGDB); 653 } 654 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 655 } 656 #endif 657 658 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 659 660 #ifdef RND_COM 661 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 662 RND_TYPE_TTY, RND_FLAG_DEFAULT); 663 #endif 664 665 /* if there are no enable/disable functions, assume the device 666 is always enabled */ 667 if (!sc->enable) 668 sc->enabled = 1; 669 670 com_config(sc); 671 672 SET(sc->sc_hwflags, COM_HW_DEV_OK); 673 } 674 675 void 676 com_config(struct com_softc *sc) 677 { 678 struct com_regs *regsp = &sc->sc_regs; 679 680 /* Disable interrupts before configuring the device. */ 681 if (sc->sc_type == COM_TYPE_PXA2x0) 682 sc->sc_ier = IER_EUART; 683 else 684 sc->sc_ier = 0; 685 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 686 (void) CSR_READ_1(regsp, COM_REG_IIR); 687 688 #ifdef COM_HAYESP 689 /* Look for a Hayes ESP board. */ 690 if (sc->sc_type == COM_TYPE_HAYESP) { 691 692 /* Set 16550 compatibility mode */ 693 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 694 HAYESP_SETMODE); 695 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 696 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 697 HAYESP_MODE_SCALE); 698 699 /* Set RTS/CTS flow control */ 700 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 701 HAYESP_SETFLOWTYPE); 702 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 703 HAYESP_FLOW_RTS); 704 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 705 HAYESP_FLOW_CTS); 706 707 /* Set flow control levels */ 708 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 709 HAYESP_SETRXFLOW); 710 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 711 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 712 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 713 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 714 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 715 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 716 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 717 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 718 } 719 #endif 720 721 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 722 com_enable_debugport(sc); 723 } 724 725 #if 0 726 static int 727 comcngetc_detached(dev_t dev) 728 { 729 return 0; 730 } 731 732 static void 733 comcnputc_detached(dev_t dev, int c) 734 { 735 } 736 #endif 737 738 int 739 com_detach(device_t self, int flags) 740 { 741 struct com_softc *sc = device_private(self); 742 int maj, mn; 743 744 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 745 return EBUSY; 746 747 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 748 (flags & DETACH_SHUTDOWN) != 0) 749 return EBUSY; 750 751 if (sc->disable != NULL && sc->enabled != 0) { 752 (*sc->disable)(sc); 753 sc->enabled = 0; 754 } 755 756 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 757 comconsattached = 0; 758 cn_tab = NULL; 759 } 760 761 /* locate the major number */ 762 maj = cdevsw_lookup_major(&com_cdevsw); 763 764 /* Nuke the vnodes for any open instances. */ 765 mn = device_unit(self); 766 vdevgone(maj, mn, mn, VCHR); 767 768 mn |= COMDIALOUT_MASK; 769 vdevgone(maj, mn, mn, VCHR); 770 771 if (sc->sc_rbuf == NULL) { 772 /* 773 * Ring buffer allocation failed in the com_attach_subr, 774 * only the tty is allocated, and nothing else. 775 */ 776 tty_free(sc->sc_tty); 777 return 0; 778 } 779 780 /* Free the receive buffer. */ 781 free(sc->sc_rbuf, M_DEVBUF); 782 783 /* Detach and free the tty. */ 784 tty_detach(sc->sc_tty); 785 tty_free(sc->sc_tty); 786 787 /* Unhook the soft interrupt handler. */ 788 softint_disestablish(sc->sc_si); 789 790 #ifdef RND_COM 791 /* Unhook the entropy source. */ 792 rnd_detach_source(&sc->rnd_source); 793 #endif 794 callout_destroy(&sc->sc_diag_callout); 795 796 /* Destroy the lock. */ 797 mutex_destroy(&sc->sc_lock); 798 799 return (0); 800 } 801 802 void 803 com_shutdown(struct com_softc *sc) 804 { 805 struct tty *tp = sc->sc_tty; 806 807 mutex_spin_enter(&sc->sc_lock); 808 809 /* If we were asserting flow control, then deassert it. */ 810 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 811 com_hwiflow(sc); 812 813 /* Clear any break condition set with TIOCSBRK. */ 814 com_break(sc, 0); 815 816 /* 817 * Hang up if necessary. Wait a bit, so the other side has time to 818 * notice even if we immediately open the port again. 819 * Avoid tsleeping above splhigh(). 820 */ 821 if (ISSET(tp->t_cflag, HUPCL)) { 822 com_modem(sc, 0); 823 mutex_spin_exit(&sc->sc_lock); 824 /* XXX will only timeout */ 825 (void) kpause(ttclos, false, hz, NULL); 826 mutex_spin_enter(&sc->sc_lock); 827 } 828 829 /* Turn off interrupts. */ 830 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 831 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 832 if ((sc->sc_type == COM_TYPE_PXA2x0) || 833 (sc->sc_type == COM_TYPE_INGENIC) || 834 (sc->sc_type == COM_TYPE_TEGRA)) 835 sc->sc_ier |= IER_ERXTOUT; 836 } else 837 sc->sc_ier = 0; 838 839 if (sc->sc_type == COM_TYPE_PXA2x0) 840 sc->sc_ier |= IER_EUART; 841 842 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 843 844 mutex_spin_exit(&sc->sc_lock); 845 846 if (sc->disable) { 847 #ifdef DIAGNOSTIC 848 if (!sc->enabled) 849 panic("com_shutdown: not enabled?"); 850 #endif 851 (*sc->disable)(sc); 852 sc->enabled = 0; 853 } 854 } 855 856 int 857 comopen(dev_t dev, int flag, int mode, struct lwp *l) 858 { 859 struct com_softc *sc; 860 struct tty *tp; 861 int s; 862 int error; 863 864 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 865 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 866 sc->sc_rbuf == NULL) 867 return (ENXIO); 868 869 if (!device_is_active(sc->sc_dev)) 870 return (ENXIO); 871 872 #ifdef KGDB 873 /* 874 * If this is the kgdb port, no other use is permitted. 875 */ 876 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 877 return (EBUSY); 878 #endif 879 880 tp = sc->sc_tty; 881 882 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 883 return (EBUSY); 884 885 s = spltty(); 886 887 /* 888 * Do the following iff this is a first open. 889 */ 890 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 891 struct termios t; 892 893 tp->t_dev = dev; 894 895 if (sc->enable) { 896 if ((*sc->enable)(sc)) { 897 splx(s); 898 aprint_error_dev(sc->sc_dev, 899 "device enable failed\n"); 900 return (EIO); 901 } 902 mutex_spin_enter(&sc->sc_lock); 903 sc->enabled = 1; 904 com_config(sc); 905 } else { 906 mutex_spin_enter(&sc->sc_lock); 907 } 908 909 /* Turn on interrupts. */ 910 sc->sc_ier = IER_ERXRDY | IER_ERLS; 911 if (!ISSET(tp->t_cflag, CLOCAL)) 912 sc->sc_ier |= IER_EMSC; 913 914 if (sc->sc_type == COM_TYPE_PXA2x0) 915 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 916 else if (sc->sc_type == COM_TYPE_INGENIC || 917 sc->sc_type == COM_TYPE_TEGRA) 918 sc->sc_ier |= IER_ERXTOUT; 919 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 920 921 /* Fetch the current modem control status, needed later. */ 922 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 923 924 /* Clear PPS capture state on first open. */ 925 mutex_spin_enter(&timecounter_lock); 926 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 927 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 928 pps_init(&sc->sc_pps_state); 929 mutex_spin_exit(&timecounter_lock); 930 931 mutex_spin_exit(&sc->sc_lock); 932 933 /* 934 * Initialize the termios status to the defaults. Add in the 935 * sticky bits from TIOCSFLAGS. 936 */ 937 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 938 t.c_ospeed = comcons_info.rate; 939 t.c_cflag = comcons_info.cflag; 940 } else { 941 t.c_ospeed = TTYDEF_SPEED; 942 t.c_cflag = TTYDEF_CFLAG; 943 } 944 t.c_ispeed = t.c_ospeed; 945 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 946 SET(t.c_cflag, CLOCAL); 947 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 948 SET(t.c_cflag, CRTSCTS); 949 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 950 SET(t.c_cflag, MDMBUF); 951 /* Make sure comparam() will do something. */ 952 tp->t_ospeed = 0; 953 (void) comparam(tp, &t); 954 tp->t_iflag = TTYDEF_IFLAG; 955 tp->t_oflag = TTYDEF_OFLAG; 956 tp->t_lflag = TTYDEF_LFLAG; 957 ttychars(tp); 958 ttsetwater(tp); 959 960 mutex_spin_enter(&sc->sc_lock); 961 962 /* 963 * Turn on DTR. We must always do this, even if carrier is not 964 * present, because otherwise we'd have to use TIOCSDTR 965 * immediately after setting CLOCAL, which applications do not 966 * expect. We always assert DTR while the device is open 967 * unless explicitly requested to deassert it. 968 */ 969 com_modem(sc, 1); 970 971 /* Clear the input ring, and unblock. */ 972 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 973 sc->sc_rbavail = com_rbuf_size; 974 com_iflush(sc); 975 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 976 com_hwiflow(sc); 977 978 #ifdef COM_DEBUG 979 if (com_debug) 980 comstatus(sc, "comopen "); 981 #endif 982 983 mutex_spin_exit(&sc->sc_lock); 984 } 985 986 splx(s); 987 988 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 989 if (error) 990 goto bad; 991 992 error = (*tp->t_linesw->l_open)(dev, tp); 993 if (error) 994 goto bad; 995 996 return (0); 997 998 bad: 999 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1000 /* 1001 * We failed to open the device, and nobody else had it opened. 1002 * Clean up the state as appropriate. 1003 */ 1004 com_shutdown(sc); 1005 } 1006 1007 return (error); 1008 } 1009 1010 int 1011 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1012 { 1013 struct com_softc *sc = 1014 device_lookup_private(&com_cd, COMUNIT(dev)); 1015 struct tty *tp = sc->sc_tty; 1016 1017 /* XXX This is for cons.c. */ 1018 if (!ISSET(tp->t_state, TS_ISOPEN)) 1019 return (0); 1020 1021 (*tp->t_linesw->l_close)(tp, flag); 1022 ttyclose(tp); 1023 1024 if (COM_ISALIVE(sc) == 0) 1025 return (0); 1026 1027 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1028 /* 1029 * Although we got a last close, the device may still be in 1030 * use; e.g. if this was the dialout node, and there are still 1031 * processes waiting for carrier on the non-dialout node. 1032 */ 1033 com_shutdown(sc); 1034 } 1035 1036 return (0); 1037 } 1038 1039 int 1040 comread(dev_t dev, struct uio *uio, int flag) 1041 { 1042 struct com_softc *sc = 1043 device_lookup_private(&com_cd, COMUNIT(dev)); 1044 struct tty *tp = sc->sc_tty; 1045 1046 if (COM_ISALIVE(sc) == 0) 1047 return (EIO); 1048 1049 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1050 } 1051 1052 int 1053 comwrite(dev_t dev, struct uio *uio, int flag) 1054 { 1055 struct com_softc *sc = 1056 device_lookup_private(&com_cd, COMUNIT(dev)); 1057 struct tty *tp = sc->sc_tty; 1058 1059 if (COM_ISALIVE(sc) == 0) 1060 return (EIO); 1061 1062 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1063 } 1064 1065 int 1066 compoll(dev_t dev, int events, struct lwp *l) 1067 { 1068 struct com_softc *sc = 1069 device_lookup_private(&com_cd, COMUNIT(dev)); 1070 struct tty *tp = sc->sc_tty; 1071 1072 if (COM_ISALIVE(sc) == 0) 1073 return (POLLHUP); 1074 1075 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1076 } 1077 1078 struct tty * 1079 comtty(dev_t dev) 1080 { 1081 struct com_softc *sc = 1082 device_lookup_private(&com_cd, COMUNIT(dev)); 1083 struct tty *tp = sc->sc_tty; 1084 1085 return (tp); 1086 } 1087 1088 int 1089 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1090 { 1091 struct com_softc *sc; 1092 struct tty *tp; 1093 int error; 1094 1095 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1096 if (sc == NULL) 1097 return ENXIO; 1098 if (COM_ISALIVE(sc) == 0) 1099 return (EIO); 1100 1101 tp = sc->sc_tty; 1102 1103 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1104 if (error != EPASSTHROUGH) 1105 return (error); 1106 1107 error = ttioctl(tp, cmd, data, flag, l); 1108 if (error != EPASSTHROUGH) 1109 return (error); 1110 1111 error = 0; 1112 switch (cmd) { 1113 case TIOCSFLAGS: 1114 error = kauth_authorize_device_tty(l->l_cred, 1115 KAUTH_DEVICE_TTY_PRIVSET, tp); 1116 break; 1117 default: 1118 /* nothing */ 1119 break; 1120 } 1121 if (error) { 1122 return error; 1123 } 1124 1125 mutex_spin_enter(&sc->sc_lock); 1126 1127 switch (cmd) { 1128 case TIOCSBRK: 1129 com_break(sc, 1); 1130 break; 1131 1132 case TIOCCBRK: 1133 com_break(sc, 0); 1134 break; 1135 1136 case TIOCSDTR: 1137 com_modem(sc, 1); 1138 break; 1139 1140 case TIOCCDTR: 1141 com_modem(sc, 0); 1142 break; 1143 1144 case TIOCGFLAGS: 1145 *(int *)data = sc->sc_swflags; 1146 break; 1147 1148 case TIOCSFLAGS: 1149 sc->sc_swflags = *(int *)data; 1150 break; 1151 1152 case TIOCMSET: 1153 case TIOCMBIS: 1154 case TIOCMBIC: 1155 tiocm_to_com(sc, cmd, *(int *)data); 1156 break; 1157 1158 case TIOCMGET: 1159 *(int *)data = com_to_tiocm(sc); 1160 break; 1161 1162 case PPS_IOC_CREATE: 1163 case PPS_IOC_DESTROY: 1164 case PPS_IOC_GETPARAMS: 1165 case PPS_IOC_SETPARAMS: 1166 case PPS_IOC_GETCAP: 1167 case PPS_IOC_FETCH: 1168 #ifdef PPS_SYNC 1169 case PPS_IOC_KCBIND: 1170 #endif 1171 mutex_spin_enter(&timecounter_lock); 1172 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1173 mutex_spin_exit(&timecounter_lock); 1174 break; 1175 1176 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1177 mutex_spin_enter(&timecounter_lock); 1178 #ifndef PPS_TRAILING_EDGE 1179 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1180 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1181 #else 1182 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1183 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1184 #endif 1185 mutex_spin_exit(&timecounter_lock); 1186 break; 1187 1188 default: 1189 error = EPASSTHROUGH; 1190 break; 1191 } 1192 1193 mutex_spin_exit(&sc->sc_lock); 1194 1195 #ifdef COM_DEBUG 1196 if (com_debug) 1197 comstatus(sc, "comioctl "); 1198 #endif 1199 1200 return (error); 1201 } 1202 1203 integrate void 1204 com_schedrx(struct com_softc *sc) 1205 { 1206 1207 sc->sc_rx_ready = 1; 1208 1209 /* Wake up the poller. */ 1210 softint_schedule(sc->sc_si); 1211 } 1212 1213 void 1214 com_break(struct com_softc *sc, int onoff) 1215 { 1216 1217 if (onoff) 1218 SET(sc->sc_lcr, LCR_SBREAK); 1219 else 1220 CLR(sc->sc_lcr, LCR_SBREAK); 1221 1222 if (!sc->sc_heldchange) { 1223 if (sc->sc_tx_busy) { 1224 sc->sc_heldtbc = sc->sc_tbc; 1225 sc->sc_tbc = 0; 1226 sc->sc_heldchange = 1; 1227 } else 1228 com_loadchannelregs(sc); 1229 } 1230 } 1231 1232 void 1233 com_modem(struct com_softc *sc, int onoff) 1234 { 1235 1236 if (sc->sc_mcr_dtr == 0) 1237 return; 1238 1239 if (onoff) 1240 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1241 else 1242 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1243 1244 if (!sc->sc_heldchange) { 1245 if (sc->sc_tx_busy) { 1246 sc->sc_heldtbc = sc->sc_tbc; 1247 sc->sc_tbc = 0; 1248 sc->sc_heldchange = 1; 1249 } else 1250 com_loadchannelregs(sc); 1251 } 1252 } 1253 1254 void 1255 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1256 { 1257 u_char combits; 1258 1259 combits = 0; 1260 if (ISSET(ttybits, TIOCM_DTR)) 1261 SET(combits, MCR_DTR); 1262 if (ISSET(ttybits, TIOCM_RTS)) 1263 SET(combits, MCR_RTS); 1264 1265 switch (how) { 1266 case TIOCMBIC: 1267 CLR(sc->sc_mcr, combits); 1268 break; 1269 1270 case TIOCMBIS: 1271 SET(sc->sc_mcr, combits); 1272 break; 1273 1274 case TIOCMSET: 1275 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1276 SET(sc->sc_mcr, combits); 1277 break; 1278 } 1279 1280 if (!sc->sc_heldchange) { 1281 if (sc->sc_tx_busy) { 1282 sc->sc_heldtbc = sc->sc_tbc; 1283 sc->sc_tbc = 0; 1284 sc->sc_heldchange = 1; 1285 } else 1286 com_loadchannelregs(sc); 1287 } 1288 } 1289 1290 int 1291 com_to_tiocm(struct com_softc *sc) 1292 { 1293 u_char combits; 1294 int ttybits = 0; 1295 1296 combits = sc->sc_mcr; 1297 if (ISSET(combits, MCR_DTR)) 1298 SET(ttybits, TIOCM_DTR); 1299 if (ISSET(combits, MCR_RTS)) 1300 SET(ttybits, TIOCM_RTS); 1301 1302 combits = sc->sc_msr; 1303 if (sc->sc_type == COM_TYPE_INGENIC) { 1304 SET(ttybits, TIOCM_CD); 1305 } else { 1306 if (ISSET(combits, MSR_DCD)) 1307 SET(ttybits, TIOCM_CD); 1308 } 1309 if (ISSET(combits, MSR_CTS)) 1310 SET(ttybits, TIOCM_CTS); 1311 if (ISSET(combits, MSR_DSR)) 1312 SET(ttybits, TIOCM_DSR); 1313 if (ISSET(combits, MSR_RI | MSR_TERI)) 1314 SET(ttybits, TIOCM_RI); 1315 1316 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1317 SET(ttybits, TIOCM_LE); 1318 1319 return (ttybits); 1320 } 1321 1322 static u_char 1323 cflag2lcr(tcflag_t cflag) 1324 { 1325 u_char lcr = 0; 1326 1327 switch (ISSET(cflag, CSIZE)) { 1328 case CS5: 1329 SET(lcr, LCR_5BITS); 1330 break; 1331 case CS6: 1332 SET(lcr, LCR_6BITS); 1333 break; 1334 case CS7: 1335 SET(lcr, LCR_7BITS); 1336 break; 1337 case CS8: 1338 SET(lcr, LCR_8BITS); 1339 break; 1340 } 1341 if (ISSET(cflag, PARENB)) { 1342 SET(lcr, LCR_PENAB); 1343 if (!ISSET(cflag, PARODD)) 1344 SET(lcr, LCR_PEVEN); 1345 } 1346 if (ISSET(cflag, CSTOPB)) 1347 SET(lcr, LCR_STOPB); 1348 1349 return (lcr); 1350 } 1351 1352 int 1353 comparam(struct tty *tp, struct termios *t) 1354 { 1355 struct com_softc *sc = 1356 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1357 int ospeed; 1358 u_char lcr; 1359 1360 if (COM_ISALIVE(sc) == 0) 1361 return (EIO); 1362 1363 #ifdef COM_HAYESP 1364 if (sc->sc_type == COM_TYPE_HAYESP) { 1365 int prescaler, speed; 1366 1367 /* 1368 * Calculate UART clock prescaler. It should be in 1369 * range of 0 .. 3. 1370 */ 1371 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1372 prescaler++, speed /= 2) 1373 if ((ospeed = comspeed(speed, sc->sc_frequency, 1374 sc->sc_type)) > 0) 1375 break; 1376 1377 if (prescaler == 4) 1378 return (EINVAL); 1379 sc->sc_prescaler = prescaler; 1380 } else 1381 #endif 1382 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1383 1384 /* Check requested parameters. */ 1385 if (ospeed < 0) 1386 return (EINVAL); 1387 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1388 return (EINVAL); 1389 1390 /* 1391 * For the console, always force CLOCAL and !HUPCL, so that the port 1392 * is always active. 1393 */ 1394 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1395 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1396 SET(t->c_cflag, CLOCAL); 1397 CLR(t->c_cflag, HUPCL); 1398 } 1399 1400 /* 1401 * If there were no changes, don't do anything. This avoids dropping 1402 * input and improves performance when all we did was frob things like 1403 * VMIN and VTIME. 1404 */ 1405 if (tp->t_ospeed == t->c_ospeed && 1406 tp->t_cflag == t->c_cflag) 1407 return (0); 1408 1409 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1410 1411 mutex_spin_enter(&sc->sc_lock); 1412 1413 sc->sc_lcr = lcr; 1414 1415 /* 1416 * If we're not in a mode that assumes a connection is present, then 1417 * ignore carrier changes. 1418 */ 1419 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1420 sc->sc_msr_dcd = 0; 1421 else 1422 sc->sc_msr_dcd = MSR_DCD; 1423 /* 1424 * Set the flow control pins depending on the current flow control 1425 * mode. 1426 */ 1427 if (ISSET(t->c_cflag, CRTSCTS)) { 1428 sc->sc_mcr_dtr = MCR_DTR; 1429 sc->sc_mcr_rts = MCR_RTS; 1430 sc->sc_msr_cts = MSR_CTS; 1431 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1432 SET(sc->sc_mcr, MCR_AFE); 1433 } else { 1434 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1435 } 1436 } else if (ISSET(t->c_cflag, MDMBUF)) { 1437 /* 1438 * For DTR/DCD flow control, make sure we don't toggle DTR for 1439 * carrier detection. 1440 */ 1441 sc->sc_mcr_dtr = 0; 1442 sc->sc_mcr_rts = MCR_DTR; 1443 sc->sc_msr_cts = MSR_DCD; 1444 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1445 CLR(sc->sc_mcr, MCR_AFE); 1446 } else { 1447 sc->sc_efr = 0; 1448 } 1449 } else { 1450 /* 1451 * If no flow control, then always set RTS. This will make 1452 * the other side happy if it mistakenly thinks we're doing 1453 * RTS/CTS flow control. 1454 */ 1455 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1456 sc->sc_mcr_rts = 0; 1457 sc->sc_msr_cts = 0; 1458 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1459 CLR(sc->sc_mcr, MCR_AFE); 1460 } else { 1461 sc->sc_efr = 0; 1462 } 1463 if (ISSET(sc->sc_mcr, MCR_DTR)) 1464 SET(sc->sc_mcr, MCR_RTS); 1465 else 1466 CLR(sc->sc_mcr, MCR_RTS); 1467 } 1468 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1469 1470 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1471 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1472 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1473 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1474 1475 sc->sc_dlbl = ospeed; 1476 sc->sc_dlbh = ospeed >> 8; 1477 1478 /* 1479 * Set the FIFO threshold based on the receive speed. 1480 * 1481 * * If it's a low speed, it's probably a mouse or some other 1482 * interactive device, so set the threshold low. 1483 * * If it's a high speed, trim the trigger level down to prevent 1484 * overflows. 1485 * * Otherwise set it a bit higher. 1486 */ 1487 if (sc->sc_type == COM_TYPE_HAYESP) { 1488 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1489 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1490 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1491 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1492 if (t->c_ospeed <= 1200) 1493 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1494 else if (t->c_ospeed <= 38400) 1495 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1496 else 1497 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1498 } else { 1499 sc->sc_fifo = 0; 1500 } 1501 1502 if (sc->sc_type == COM_TYPE_INGENIC) 1503 sc->sc_fifo |= FIFO_UART_ON; 1504 1505 /* And copy to tty. */ 1506 tp->t_ispeed = t->c_ospeed; 1507 tp->t_ospeed = t->c_ospeed; 1508 tp->t_cflag = t->c_cflag; 1509 1510 if (!sc->sc_heldchange) { 1511 if (sc->sc_tx_busy) { 1512 sc->sc_heldtbc = sc->sc_tbc; 1513 sc->sc_tbc = 0; 1514 sc->sc_heldchange = 1; 1515 } else 1516 com_loadchannelregs(sc); 1517 } 1518 1519 if (!ISSET(t->c_cflag, CHWFLOW)) { 1520 /* Disable the high water mark. */ 1521 sc->sc_r_hiwat = 0; 1522 sc->sc_r_lowat = 0; 1523 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1524 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1525 com_schedrx(sc); 1526 } 1527 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1528 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1529 com_hwiflow(sc); 1530 } 1531 } else { 1532 sc->sc_r_hiwat = com_rbuf_hiwat; 1533 sc->sc_r_lowat = com_rbuf_lowat; 1534 } 1535 1536 mutex_spin_exit(&sc->sc_lock); 1537 1538 /* 1539 * Update the tty layer's idea of the carrier bit, in case we changed 1540 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1541 * explicit request. 1542 */ 1543 if (sc->sc_type == COM_TYPE_INGENIC) { 1544 /* no DCD here */ 1545 (void) (*tp->t_linesw->l_modem)(tp, 1); 1546 } else 1547 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1548 1549 #ifdef COM_DEBUG 1550 if (com_debug) 1551 comstatus(sc, "comparam "); 1552 #endif 1553 1554 if (!ISSET(t->c_cflag, CHWFLOW)) { 1555 if (sc->sc_tx_stopped) { 1556 sc->sc_tx_stopped = 0; 1557 comstart(tp); 1558 } 1559 } 1560 1561 return (0); 1562 } 1563 1564 void 1565 com_iflush(struct com_softc *sc) 1566 { 1567 struct com_regs *regsp = &sc->sc_regs; 1568 #ifdef DIAGNOSTIC 1569 int reg; 1570 #endif 1571 int timo; 1572 1573 #ifdef DIAGNOSTIC 1574 reg = 0xffff; 1575 #endif 1576 timo = 50000; 1577 /* flush any pending I/O */ 1578 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1579 && --timo) 1580 #ifdef DIAGNOSTIC 1581 reg = 1582 #else 1583 (void) 1584 #endif 1585 CSR_READ_1(regsp, COM_REG_RXDATA); 1586 #ifdef DIAGNOSTIC 1587 if (!timo) 1588 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1589 #endif 1590 1591 #if defined(COM_16750) || defined(COM_AWIN) 1592 uint8_t fifo; 1593 /* 1594 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1595 * This should prevent triggering busy interrupt while 1596 * manipulating divisors. 1597 */ 1598 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1599 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1600 CSR_WRITE_1(regsp, COM_REG_FIFO, fifo | FIFO_ENABLE | FIFO_RCV_RST | 1601 FIFO_XMT_RST); 1602 delay(100); 1603 #endif 1604 } 1605 1606 void 1607 com_loadchannelregs(struct com_softc *sc) 1608 { 1609 struct com_regs *regsp = &sc->sc_regs; 1610 1611 /* XXXXX necessary? */ 1612 com_iflush(sc); 1613 1614 if (sc->sc_type == COM_TYPE_PXA2x0) 1615 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1616 else 1617 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1618 1619 if (sc->sc_type == COM_TYPE_OMAP) { 1620 /* disable before changing settings */ 1621 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1622 } 1623 1624 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1625 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1626 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1627 /* no EFR on alchemy */ 1628 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1629 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1630 } 1631 if (sc->sc_type == COM_TYPE_AU1x00) { 1632 /* alchemy has single separate 16-bit clock divisor register */ 1633 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1634 (sc->sc_dlbh << 8)); 1635 } else { 1636 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1637 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1638 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1639 } 1640 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1641 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1642 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1643 #ifdef COM_HAYESP 1644 if (sc->sc_type == COM_TYPE_HAYESP) { 1645 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1646 HAYESP_SETPRESCALER); 1647 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1648 sc->sc_prescaler); 1649 } 1650 #endif 1651 if (sc->sc_type == COM_TYPE_OMAP) { 1652 /* setup the fifos. the FCR value is not used as long 1653 as SCR[6] and SCR[7] are 0, which they are at reset 1654 and we never touch the SCR register */ 1655 uint8_t rx_fifo_trig = 40; 1656 uint8_t tx_fifo_trig = 60; 1657 uint8_t rx_start = 8; 1658 uint8_t rx_halt = 60; 1659 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1660 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1661 1662 /* enable access to TCR & TLR */ 1663 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1664 1665 /* write tcr and tlr values */ 1666 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1667 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1668 1669 /* disable access to TCR & TLR */ 1670 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1671 1672 /* enable again, but mode is based on speed */ 1673 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1674 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1675 } else { 1676 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1677 } 1678 } 1679 1680 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1681 } 1682 1683 int 1684 comhwiflow(struct tty *tp, int block) 1685 { 1686 struct com_softc *sc = 1687 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1688 1689 if (COM_ISALIVE(sc) == 0) 1690 return (0); 1691 1692 if (sc->sc_mcr_rts == 0) 1693 return (0); 1694 1695 mutex_spin_enter(&sc->sc_lock); 1696 1697 if (block) { 1698 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1699 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1700 com_hwiflow(sc); 1701 } 1702 } else { 1703 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1704 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1705 com_schedrx(sc); 1706 } 1707 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1708 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1709 com_hwiflow(sc); 1710 } 1711 } 1712 1713 mutex_spin_exit(&sc->sc_lock); 1714 return (1); 1715 } 1716 1717 /* 1718 * (un)block input via hw flowcontrol 1719 */ 1720 void 1721 com_hwiflow(struct com_softc *sc) 1722 { 1723 struct com_regs *regsp= &sc->sc_regs; 1724 1725 if (sc->sc_mcr_rts == 0) 1726 return; 1727 1728 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1729 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1730 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1731 } else { 1732 SET(sc->sc_mcr, sc->sc_mcr_rts); 1733 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1734 } 1735 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1736 } 1737 1738 1739 void 1740 comstart(struct tty *tp) 1741 { 1742 struct com_softc *sc = 1743 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1744 struct com_regs *regsp = &sc->sc_regs; 1745 int s; 1746 1747 if (COM_ISALIVE(sc) == 0) 1748 return; 1749 1750 s = spltty(); 1751 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1752 goto out; 1753 if (sc->sc_tx_stopped) 1754 goto out; 1755 if (!ttypull(tp)) 1756 goto out; 1757 1758 /* Grab the first contiguous region of buffer space. */ 1759 { 1760 u_char *tba; 1761 int tbc; 1762 1763 tba = tp->t_outq.c_cf; 1764 tbc = ndqb(&tp->t_outq, 0); 1765 1766 mutex_spin_enter(&sc->sc_lock); 1767 1768 sc->sc_tba = tba; 1769 sc->sc_tbc = tbc; 1770 } 1771 1772 SET(tp->t_state, TS_BUSY); 1773 sc->sc_tx_busy = 1; 1774 1775 /* Enable transmit completion interrupts if necessary. */ 1776 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1777 SET(sc->sc_ier, IER_ETXRDY); 1778 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1779 } 1780 1781 /* Output the first chunk of the contiguous buffer. */ 1782 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1783 u_int n; 1784 1785 n = sc->sc_tbc; 1786 if (n > sc->sc_fifolen) 1787 n = sc->sc_fifolen; 1788 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1789 sc->sc_tbc -= n; 1790 sc->sc_tba += n; 1791 } 1792 1793 mutex_spin_exit(&sc->sc_lock); 1794 out: 1795 splx(s); 1796 return; 1797 } 1798 1799 /* 1800 * Stop output on a line. 1801 */ 1802 void 1803 comstop(struct tty *tp, int flag) 1804 { 1805 struct com_softc *sc = 1806 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1807 1808 mutex_spin_enter(&sc->sc_lock); 1809 if (ISSET(tp->t_state, TS_BUSY)) { 1810 /* Stop transmitting at the next chunk. */ 1811 sc->sc_tbc = 0; 1812 sc->sc_heldtbc = 0; 1813 if (!ISSET(tp->t_state, TS_TTSTOP)) 1814 SET(tp->t_state, TS_FLUSH); 1815 } 1816 mutex_spin_exit(&sc->sc_lock); 1817 } 1818 1819 void 1820 comdiag(void *arg) 1821 { 1822 struct com_softc *sc = arg; 1823 int overflows, floods; 1824 1825 mutex_spin_enter(&sc->sc_lock); 1826 overflows = sc->sc_overflows; 1827 sc->sc_overflows = 0; 1828 floods = sc->sc_floods; 1829 sc->sc_floods = 0; 1830 sc->sc_errors = 0; 1831 mutex_spin_exit(&sc->sc_lock); 1832 1833 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1834 device_xname(sc->sc_dev), 1835 overflows, overflows == 1 ? "" : "s", 1836 floods, floods == 1 ? "" : "s"); 1837 } 1838 1839 integrate void 1840 com_rxsoft(struct com_softc *sc, struct tty *tp) 1841 { 1842 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1843 u_char *get, *end; 1844 u_int cc, scc; 1845 u_char lsr; 1846 int code; 1847 1848 end = sc->sc_ebuf; 1849 get = sc->sc_rbget; 1850 scc = cc = com_rbuf_size - sc->sc_rbavail; 1851 1852 if (cc == com_rbuf_size) { 1853 sc->sc_floods++; 1854 if (sc->sc_errors++ == 0) 1855 callout_reset(&sc->sc_diag_callout, 60 * hz, 1856 comdiag, sc); 1857 } 1858 1859 /* If not yet open, drop the entire buffer content here */ 1860 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1861 get += cc << 1; 1862 if (get >= end) 1863 get -= com_rbuf_size << 1; 1864 cc = 0; 1865 } 1866 while (cc) { 1867 code = get[0]; 1868 lsr = get[1]; 1869 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1870 if (ISSET(lsr, LSR_OE)) { 1871 sc->sc_overflows++; 1872 if (sc->sc_errors++ == 0) 1873 callout_reset(&sc->sc_diag_callout, 1874 60 * hz, comdiag, sc); 1875 } 1876 if (ISSET(lsr, LSR_BI | LSR_FE)) 1877 SET(code, TTY_FE); 1878 if (ISSET(lsr, LSR_PE)) 1879 SET(code, TTY_PE); 1880 } 1881 if ((*rint)(code, tp) == -1) { 1882 /* 1883 * The line discipline's buffer is out of space. 1884 */ 1885 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1886 /* 1887 * We're either not using flow control, or the 1888 * line discipline didn't tell us to block for 1889 * some reason. Either way, we have no way to 1890 * know when there's more space available, so 1891 * just drop the rest of the data. 1892 */ 1893 get += cc << 1; 1894 if (get >= end) 1895 get -= com_rbuf_size << 1; 1896 cc = 0; 1897 } else { 1898 /* 1899 * Don't schedule any more receive processing 1900 * until the line discipline tells us there's 1901 * space available (through comhwiflow()). 1902 * Leave the rest of the data in the input 1903 * buffer. 1904 */ 1905 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1906 } 1907 break; 1908 } 1909 get += 2; 1910 if (get >= end) 1911 get = sc->sc_rbuf; 1912 cc--; 1913 } 1914 1915 if (cc != scc) { 1916 sc->sc_rbget = get; 1917 mutex_spin_enter(&sc->sc_lock); 1918 1919 cc = sc->sc_rbavail += scc - cc; 1920 /* Buffers should be ok again, release possible block. */ 1921 if (cc >= sc->sc_r_lowat) { 1922 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1923 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1924 SET(sc->sc_ier, IER_ERXRDY); 1925 #ifdef COM_PXA2X0 1926 if (sc->sc_type == COM_TYPE_PXA2x0) 1927 SET(sc->sc_ier, IER_ERXTOUT); 1928 #endif 1929 if (sc->sc_type == COM_TYPE_INGENIC || 1930 sc->sc_type == COM_TYPE_TEGRA) 1931 SET(sc->sc_ier, IER_ERXTOUT); 1932 1933 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 1934 sc->sc_ier); 1935 } 1936 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1937 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1938 com_hwiflow(sc); 1939 } 1940 } 1941 mutex_spin_exit(&sc->sc_lock); 1942 } 1943 } 1944 1945 integrate void 1946 com_txsoft(struct com_softc *sc, struct tty *tp) 1947 { 1948 1949 CLR(tp->t_state, TS_BUSY); 1950 if (ISSET(tp->t_state, TS_FLUSH)) 1951 CLR(tp->t_state, TS_FLUSH); 1952 else 1953 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1954 (*tp->t_linesw->l_start)(tp); 1955 } 1956 1957 integrate void 1958 com_stsoft(struct com_softc *sc, struct tty *tp) 1959 { 1960 u_char msr, delta; 1961 1962 mutex_spin_enter(&sc->sc_lock); 1963 msr = sc->sc_msr; 1964 delta = sc->sc_msr_delta; 1965 sc->sc_msr_delta = 0; 1966 mutex_spin_exit(&sc->sc_lock); 1967 1968 if (ISSET(delta, sc->sc_msr_dcd)) { 1969 /* 1970 * Inform the tty layer that carrier detect changed. 1971 */ 1972 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1973 } 1974 1975 if (ISSET(delta, sc->sc_msr_cts)) { 1976 /* Block or unblock output according to flow control. */ 1977 if (ISSET(msr, sc->sc_msr_cts)) { 1978 sc->sc_tx_stopped = 0; 1979 (*tp->t_linesw->l_start)(tp); 1980 } else { 1981 sc->sc_tx_stopped = 1; 1982 } 1983 } 1984 1985 #ifdef COM_DEBUG 1986 if (com_debug) 1987 comstatus(sc, "com_stsoft"); 1988 #endif 1989 } 1990 1991 void 1992 comsoft(void *arg) 1993 { 1994 struct com_softc *sc = arg; 1995 struct tty *tp; 1996 1997 if (COM_ISALIVE(sc) == 0) 1998 return; 1999 2000 tp = sc->sc_tty; 2001 2002 if (sc->sc_rx_ready) { 2003 sc->sc_rx_ready = 0; 2004 com_rxsoft(sc, tp); 2005 } 2006 2007 if (sc->sc_st_check) { 2008 sc->sc_st_check = 0; 2009 com_stsoft(sc, tp); 2010 } 2011 2012 if (sc->sc_tx_done) { 2013 sc->sc_tx_done = 0; 2014 com_txsoft(sc, tp); 2015 } 2016 } 2017 2018 int 2019 comintr(void *arg) 2020 { 2021 struct com_softc *sc = arg; 2022 struct com_regs *regsp = &sc->sc_regs; 2023 2024 u_char *put, *end; 2025 u_int cc; 2026 u_char lsr, iir; 2027 2028 if (COM_ISALIVE(sc) == 0) 2029 return (0); 2030 2031 KASSERT(regsp != NULL); 2032 2033 mutex_spin_enter(&sc->sc_lock); 2034 iir = CSR_READ_1(regsp, COM_REG_IIR); 2035 2036 /* Handle ns16750-specific busy interrupt. */ 2037 #ifdef COM_16750 2038 #ifdef COM_AWIN 2039 #error "COM_16750 and COM_AWIN are exclusive" 2040 #endif 2041 int timeout; 2042 if ((iir & IIR_BUSY) == IIR_BUSY) { 2043 for (timeout = 10000; 2044 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2045 if (timeout <= 0) { 2046 aprint_error_dev(sc->sc_dev, 2047 "timeout while waiting for BUSY interrupt " 2048 "acknowledge\n"); 2049 mutex_spin_exit(&sc->sc_lock); 2050 return (0); 2051 } 2052 2053 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2054 iir = CSR_READ_1(regsp, COM_REG_IIR); 2055 } 2056 #endif /* COM_16750 */ 2057 #ifdef COM_AWIN 2058 /* Allwinner BUSY interrupt */ 2059 if ((iir & IIR_BUSY) == IIR_BUSY) { 2060 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2061 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2062 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2063 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2064 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2065 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2066 CSR_WRITE_1(regsp, COM_REG_HALT, 2067 HALT_CHCFG_EN | HALT_CHCFG_UD); 2068 for (int timeout = 10000000; 2069 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2070 timeout--) { 2071 if (timeout <= 0) { 2072 aprint_error_dev(sc->sc_dev, 2073 "timeout while waiting for HALT " 2074 "update acknowledge 0x%x 0x%x\n", 2075 CSR_READ_1(regsp, COM_REG_HALT), 2076 CSR_READ_1(regsp, COM_REG_USR)); 2077 break; 2078 } 2079 } 2080 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2081 (void)CSR_READ_1(regsp, COM_REG_USR); 2082 } else { 2083 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2084 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2085 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2086 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2087 } 2088 } 2089 #endif /* COM_AWIN */ 2090 2091 if (ISSET(iir, IIR_NOPEND)) { 2092 mutex_spin_exit(&sc->sc_lock); 2093 return (0); 2094 } 2095 2096 end = sc->sc_ebuf; 2097 put = sc->sc_rbput; 2098 cc = sc->sc_rbavail; 2099 2100 again: do { 2101 u_char msr, delta; 2102 2103 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2104 if (ISSET(lsr, LSR_BI)) { 2105 int cn_trapped = 0; /* see above: cn_trap() */ 2106 2107 cn_check_magic(sc->sc_tty->t_dev, 2108 CNC_BREAK, com_cnm_state); 2109 if (cn_trapped) 2110 continue; 2111 #if defined(KGDB) && !defined(DDB) 2112 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2113 kgdb_connect(1); 2114 continue; 2115 } 2116 #endif 2117 } 2118 2119 if (ISSET(lsr, LSR_RCV_MASK) && 2120 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2121 while (cc > 0) { 2122 int cn_trapped = 0; 2123 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2124 put[1] = lsr; 2125 cn_check_magic(sc->sc_tty->t_dev, 2126 put[0], com_cnm_state); 2127 if (cn_trapped) 2128 goto next; 2129 put += 2; 2130 if (put >= end) 2131 put = sc->sc_rbuf; 2132 cc--; 2133 next: 2134 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2135 if (!ISSET(lsr, LSR_RCV_MASK)) 2136 break; 2137 } 2138 2139 /* 2140 * Current string of incoming characters ended because 2141 * no more data was available or we ran out of space. 2142 * Schedule a receive event if any data was received. 2143 * If we're out of space, turn off receive interrupts. 2144 */ 2145 sc->sc_rbput = put; 2146 sc->sc_rbavail = cc; 2147 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2148 sc->sc_rx_ready = 1; 2149 2150 /* 2151 * See if we are in danger of overflowing a buffer. If 2152 * so, use hardware flow control to ease the pressure. 2153 */ 2154 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2155 cc < sc->sc_r_hiwat) { 2156 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2157 com_hwiflow(sc); 2158 } 2159 2160 /* 2161 * If we're out of space, disable receive interrupts 2162 * until the queue has drained a bit. 2163 */ 2164 if (!cc) { 2165 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2166 #ifdef COM_PXA2X0 2167 if (sc->sc_type == COM_TYPE_PXA2x0) 2168 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2169 else 2170 #endif 2171 if (sc->sc_type == COM_TYPE_INGENIC || 2172 sc->sc_type == COM_TYPE_TEGRA) 2173 CLR(sc->sc_ier, 2174 IER_ERXRDY | IER_ERXTOUT); 2175 else 2176 CLR(sc->sc_ier, IER_ERXRDY); 2177 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2178 } 2179 } else { 2180 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2181 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2182 continue; 2183 } 2184 } 2185 2186 msr = CSR_READ_1(regsp, COM_REG_MSR); 2187 delta = msr ^ sc->sc_msr; 2188 sc->sc_msr = msr; 2189 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2190 (delta & MSR_DCD)) { 2191 mutex_spin_enter(&timecounter_lock); 2192 pps_capture(&sc->sc_pps_state); 2193 pps_event(&sc->sc_pps_state, 2194 (msr & MSR_DCD) ? 2195 PPS_CAPTUREASSERT : 2196 PPS_CAPTURECLEAR); 2197 mutex_spin_exit(&timecounter_lock); 2198 } 2199 2200 /* 2201 * Process normal status changes 2202 */ 2203 if (ISSET(delta, sc->sc_msr_mask)) { 2204 SET(sc->sc_msr_delta, delta); 2205 2206 /* 2207 * Stop output immediately if we lose the output 2208 * flow control signal or carrier detect. 2209 */ 2210 if (ISSET(~msr, sc->sc_msr_mask)) { 2211 sc->sc_tbc = 0; 2212 sc->sc_heldtbc = 0; 2213 #ifdef COM_DEBUG 2214 if (com_debug) 2215 comstatus(sc, "comintr "); 2216 #endif 2217 } 2218 2219 sc->sc_st_check = 1; 2220 } 2221 } while (!ISSET((iir = 2222 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2223 /* 2224 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2225 * by IIR read, so we can't do this way: `process all interrupts, 2226 * then do TX if possible'. 2227 */ 2228 (iir & IIR_IMASK) != IIR_TXRDY); 2229 2230 /* 2231 * Read LSR again, since there may be an interrupt between 2232 * the last LSR read and IIR read above. 2233 */ 2234 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2235 2236 /* 2237 * See if data can be transmitted as well. 2238 * Schedule tx done event if no data left 2239 * and tty was marked busy. 2240 */ 2241 if (ISSET(lsr, LSR_TXRDY)) { 2242 /* 2243 * If we've delayed a parameter change, do it now, and restart 2244 * output. 2245 */ 2246 if (sc->sc_heldchange) { 2247 com_loadchannelregs(sc); 2248 sc->sc_heldchange = 0; 2249 sc->sc_tbc = sc->sc_heldtbc; 2250 sc->sc_heldtbc = 0; 2251 } 2252 2253 /* Output the next chunk of the contiguous buffer, if any. */ 2254 if (sc->sc_tbc > 0) { 2255 u_int n; 2256 2257 n = sc->sc_tbc; 2258 if (n > sc->sc_fifolen) 2259 n = sc->sc_fifolen; 2260 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2261 sc->sc_tbc -= n; 2262 sc->sc_tba += n; 2263 } else { 2264 /* Disable transmit completion interrupts if necessary. */ 2265 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2266 CLR(sc->sc_ier, IER_ETXRDY); 2267 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2268 } 2269 if (sc->sc_tx_busy) { 2270 sc->sc_tx_busy = 0; 2271 sc->sc_tx_done = 1; 2272 } 2273 } 2274 } 2275 2276 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2277 goto again; 2278 2279 mutex_spin_exit(&sc->sc_lock); 2280 2281 /* Wake up the poller. */ 2282 softint_schedule(sc->sc_si); 2283 2284 #ifdef RND_COM 2285 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2286 #endif 2287 2288 return (1); 2289 } 2290 2291 /* 2292 * The following functions are polled getc and putc routines, shared 2293 * by the console and kgdb glue. 2294 * 2295 * The read-ahead code is so that you can detect pending in-band 2296 * cn_magic in polled mode while doing output rather than having to 2297 * wait until the kernel decides it needs input. 2298 */ 2299 2300 #define MAX_READAHEAD 20 2301 static int com_readahead[MAX_READAHEAD]; 2302 static int com_readaheadcount = 0; 2303 2304 int 2305 com_common_getc(dev_t dev, struct com_regs *regsp) 2306 { 2307 int s = splserial(); 2308 u_char stat, c; 2309 2310 /* got a character from reading things earlier */ 2311 if (com_readaheadcount > 0) { 2312 int i; 2313 2314 c = com_readahead[0]; 2315 for (i = 1; i < com_readaheadcount; i++) { 2316 com_readahead[i-1] = com_readahead[i]; 2317 } 2318 com_readaheadcount--; 2319 splx(s); 2320 return (c); 2321 } 2322 2323 /* don't block until a character becomes available */ 2324 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2325 splx(s); 2326 return -1; 2327 } 2328 2329 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2330 stat = CSR_READ_1(regsp, COM_REG_IIR); 2331 { 2332 int cn_trapped = 0; /* required by cn_trap, see above */ 2333 #ifdef DDB 2334 extern int db_active; 2335 if (!db_active) 2336 #endif 2337 cn_check_magic(dev, c, com_cnm_state); 2338 } 2339 splx(s); 2340 return (c); 2341 } 2342 2343 static void 2344 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2345 { 2346 int s = splserial(); 2347 int cin, stat, timo; 2348 2349 if (com_readaheadcount < MAX_READAHEAD 2350 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2351 int cn_trapped = 0; 2352 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2353 stat = CSR_READ_1(regsp, COM_REG_IIR); 2354 cn_check_magic(dev, cin, com_cnm_state); 2355 com_readahead[com_readaheadcount++] = cin; 2356 } 2357 2358 /* wait for any pending transmission to finish */ 2359 timo = 150000; 2360 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2361 continue; 2362 2363 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2364 COM_BARRIER(regsp, BR | BW); 2365 2366 splx(s); 2367 } 2368 2369 /* 2370 * Initialize UART for use as console or KGDB line. 2371 */ 2372 int 2373 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2374 tcflag_t cflag) 2375 { 2376 2377 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2378 ®sp->cr_ioh)) 2379 return (ENOMEM); /* ??? */ 2380 2381 if (type == COM_TYPE_OMAP) { 2382 /* disable before changing settings */ 2383 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2384 } 2385 2386 rate = comspeed(rate, frequency, type); 2387 if (__predict_true(rate != -1)) { 2388 if (type == COM_TYPE_AU1x00) { 2389 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2390 } else { 2391 /* no EFR on alchemy */ 2392 if ((type != COM_TYPE_16550_NOERS) && 2393 (type != COM_TYPE_INGENIC)) { 2394 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2395 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2396 } 2397 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2398 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2399 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2400 } 2401 } 2402 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2403 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2404 2405 if (type == COM_TYPE_INGENIC) { 2406 CSR_WRITE_1(regsp, COM_REG_FIFO, 2407 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2408 FIFO_TRIGGER_1 | FIFO_UART_ON); 2409 } else { 2410 CSR_WRITE_1(regsp, COM_REG_FIFO, 2411 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2412 FIFO_TRIGGER_1); 2413 } 2414 2415 if (type == COM_TYPE_OMAP) { 2416 /* setup the fifos. the FCR value is not used as long 2417 as SCR[6] and SCR[7] are 0, which they are at reset 2418 and we never touch the SCR register */ 2419 uint8_t rx_fifo_trig = 40; 2420 uint8_t tx_fifo_trig = 60; 2421 uint8_t rx_start = 8; 2422 uint8_t rx_halt = 60; 2423 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2424 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2425 2426 /* enable access to TCR & TLR */ 2427 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2428 2429 /* write tcr and tlr values */ 2430 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2431 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2432 2433 /* disable access to TCR & TLR */ 2434 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2435 2436 /* enable again, but mode is based on speed */ 2437 if (rate > 230400) { 2438 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2439 } else { 2440 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2441 } 2442 } 2443 2444 #ifdef COM_PXA2X0 2445 if (type == COM_TYPE_PXA2x0) 2446 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2447 else 2448 #endif 2449 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2450 2451 return (0); 2452 } 2453 2454 int 2455 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2456 tcflag_t cflag) 2457 { 2458 int res; 2459 2460 comcons_info.regs = *regsp; 2461 2462 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2463 if (res) 2464 return (res); 2465 2466 cn_tab = &comcons; 2467 cn_init_magic(&com_cnm_state); 2468 cn_set_magic("\047\001"); /* default magic is BREAK */ 2469 2470 comcons_info.frequency = frequency; 2471 comcons_info.type = type; 2472 comcons_info.rate = rate; 2473 comcons_info.cflag = cflag; 2474 2475 return (0); 2476 } 2477 2478 int 2479 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2480 int type, tcflag_t cflag) 2481 { 2482 struct com_regs regs; 2483 2484 memset(®s, 0, sizeof regs); 2485 regs.cr_iot = iot; 2486 regs.cr_iobase = iobase; 2487 regs.cr_nports = COM_NPORTS; 2488 #ifdef COM_REGMAP 2489 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2490 #endif 2491 2492 return comcnattach1(®s, rate, frequency, type, cflag); 2493 } 2494 2495 static int 2496 comcnreattach(void) 2497 { 2498 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2499 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2500 } 2501 2502 int 2503 comcngetc(dev_t dev) 2504 { 2505 2506 return (com_common_getc(dev, &comcons_info.regs)); 2507 } 2508 2509 /* 2510 * Console kernel output character routine. 2511 */ 2512 void 2513 comcnputc(dev_t dev, int c) 2514 { 2515 2516 com_common_putc(dev, &comcons_info.regs, c); 2517 } 2518 2519 void 2520 comcnpollc(dev_t dev, int on) 2521 { 2522 2523 com_readaheadcount = 0; 2524 } 2525 2526 #ifdef KGDB 2527 int 2528 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2529 tcflag_t cflag) 2530 { 2531 int res; 2532 2533 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2534 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2535 #if !defined(DDB) 2536 return (EBUSY); /* cannot share with console */ 2537 #else 2538 comkgdbregs = *regsp; 2539 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2540 #endif 2541 } else { 2542 comkgdbregs = *regsp; 2543 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2544 if (res) 2545 return (res); 2546 2547 /* 2548 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2549 * expects this to be initialized 2550 */ 2551 cn_init_magic(&com_cnm_state); 2552 cn_set_magic("\047\001"); 2553 } 2554 2555 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2556 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2557 2558 return (0); 2559 } 2560 2561 int 2562 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2563 int frequency, int type, tcflag_t cflag) 2564 { 2565 struct com_regs regs; 2566 2567 regs.cr_iot = iot; 2568 regs.cr_nports = COM_NPORTS; 2569 regs.cr_iobase = iobase; 2570 #ifdef COM_REGMAP 2571 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2572 #endif 2573 2574 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2575 } 2576 2577 /* ARGSUSED */ 2578 int 2579 com_kgdb_getc(void *arg) 2580 { 2581 2582 return (com_common_getc(NODEV, &comkgdbregs)); 2583 } 2584 2585 /* ARGSUSED */ 2586 void 2587 com_kgdb_putc(void *arg, int c) 2588 { 2589 2590 com_common_putc(NODEV, &comkgdbregs, c); 2591 } 2592 #endif /* KGDB */ 2593 2594 /* helper function to identify the com ports used by 2595 console or KGDB (and not yet autoconf attached) */ 2596 int 2597 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2598 { 2599 bus_space_handle_t help; 2600 2601 if (!comconsattached && 2602 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2603 iobase == comcons_info.regs.cr_iobase) 2604 help = comcons_info.regs.cr_ioh; 2605 #ifdef KGDB 2606 else if (!com_kgdb_attached && 2607 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2608 iobase == comkgdbregs.cr_iobase) 2609 help = comkgdbregs.cr_ioh; 2610 #endif 2611 else 2612 return (0); 2613 2614 if (ioh) 2615 *ioh = help; 2616 return (1); 2617 } 2618 2619 /* 2620 * this routine exists to serve as a shutdown hook for systems that 2621 * have firmware which doesn't interact properly with a com device in 2622 * FIFO mode. 2623 */ 2624 bool 2625 com_cleanup(device_t self, int how) 2626 { 2627 struct com_softc *sc = device_private(self); 2628 2629 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2630 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2631 2632 return true; 2633 } 2634 2635 bool 2636 com_suspend(device_t self, const pmf_qual_t *qual) 2637 { 2638 struct com_softc *sc = device_private(self); 2639 2640 #if 0 2641 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2642 cn_tab = &comcons_suspend; 2643 #endif 2644 2645 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2646 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2647 2648 return true; 2649 } 2650 2651 bool 2652 com_resume(device_t self, const pmf_qual_t *qual) 2653 { 2654 struct com_softc *sc = device_private(self); 2655 2656 mutex_spin_enter(&sc->sc_lock); 2657 com_loadchannelregs(sc); 2658 mutex_spin_exit(&sc->sc_lock); 2659 2660 return true; 2661 } 2662
Indexes created Tue Sep 23 21:09:50 GMT 2025