com.c revision 1.344
1 /* $NetBSD: com.c,v 1.344 2017/10/29 14:06:08 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.344 2017/10/29 14:06:08 jmcneill Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #ifdef COM_REGMAP 132 #define CSR_WRITE_1(r, o, v) \ 133 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 134 #define CSR_READ_1(r, o) \ 135 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 136 #define CSR_WRITE_2(r, o, v) \ 137 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 138 #define CSR_READ_2(r, o) \ 139 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 140 #define CSR_WRITE_MULTI(r, o, p, n) \ 141 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 142 #else 143 #define CSR_WRITE_1(r, o, v) \ 144 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 145 #define CSR_READ_1(r, o) \ 146 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 147 #define CSR_WRITE_2(r, o, v) \ 148 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 149 #define CSR_READ_2(r, o) \ 150 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 151 #define CSR_WRITE_MULTI(r, o, p, n) \ 152 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 153 #endif 154 155 156 static void com_enable_debugport(struct com_softc *); 157 158 void com_config(struct com_softc *); 159 void com_shutdown(struct com_softc *); 160 int comspeed(long, long, int); 161 static u_char cflag2lcr(tcflag_t); 162 int comparam(struct tty *, struct termios *); 163 void comstart(struct tty *); 164 int comhwiflow(struct tty *, int); 165 166 void com_loadchannelregs(struct com_softc *); 167 void com_hwiflow(struct com_softc *); 168 void com_break(struct com_softc *, int); 169 void com_modem(struct com_softc *, int); 170 void tiocm_to_com(struct com_softc *, u_long, int); 171 int com_to_tiocm(struct com_softc *); 172 void com_iflush(struct com_softc *); 173 174 int com_common_getc(dev_t, struct com_regs *); 175 static void com_common_putc(dev_t, struct com_regs *, int); 176 177 int cominit(struct com_regs *, int, int, int, tcflag_t); 178 179 static int comcnreattach(void); 180 181 int comcngetc(dev_t); 182 void comcnputc(dev_t, int); 183 void comcnpollc(dev_t, int); 184 185 #define integrate static inline 186 void comsoft(void *); 187 integrate void com_rxsoft(struct com_softc *, struct tty *); 188 integrate void com_txsoft(struct com_softc *, struct tty *); 189 integrate void com_stsoft(struct com_softc *, struct tty *); 190 integrate void com_schedrx(struct com_softc *); 191 void comdiag(void *); 192 193 dev_type_open(comopen); 194 dev_type_close(comclose); 195 dev_type_read(comread); 196 dev_type_write(comwrite); 197 dev_type_ioctl(comioctl); 198 dev_type_stop(comstop); 199 dev_type_tty(comtty); 200 dev_type_poll(compoll); 201 202 static struct comcons_info comcons_info; 203 204 /* 205 * Following are all routines needed for COM to act as console 206 */ 207 static struct consdev comcons = { 208 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 209 NODEV, CN_NORMAL 210 }; 211 212 213 const struct cdevsw com_cdevsw = { 214 .d_open = comopen, 215 .d_close = comclose, 216 .d_read = comread, 217 .d_write = comwrite, 218 .d_ioctl = comioctl, 219 .d_stop = comstop, 220 .d_tty = comtty, 221 .d_poll = compoll, 222 .d_mmap = nommap, 223 .d_kqfilter = ttykqfilter, 224 .d_discard = nodiscard, 225 .d_flag = D_TTY 226 }; 227 228 /* 229 * Make this an option variable one can patch. 230 * But be warned: this must be a power of 2! 231 */ 232 u_int com_rbuf_size = COM_RING_SIZE; 233 234 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 235 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 236 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 237 238 static int comconsattached; 239 static struct cnm_state com_cnm_state; 240 241 #ifdef KGDB 242 #include <sys/kgdb.h> 243 244 static struct com_regs comkgdbregs; 245 static int com_kgdb_attached; 246 247 int com_kgdb_getc(void *); 248 void com_kgdb_putc(void *, int); 249 #endif /* KGDB */ 250 251 #ifdef COM_REGMAP 252 /* initializer for typical 16550-ish hardware */ 253 #define COM_REG_STD { \ 254 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 255 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 256 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr } 257 258 const bus_size_t com_std_map[32] = COM_REG_STD; 259 #endif /* COM_REGMAP */ 260 261 #define COMDIALOUT_MASK TTDIALOUT_MASK 262 263 #define COMUNIT(x) TTUNIT(x) 264 #define COMDIALOUT(x) TTDIALOUT(x) 265 266 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 267 device_is_active((sc)->sc_dev)) 268 269 #define BR BUS_SPACE_BARRIER_READ 270 #define BW BUS_SPACE_BARRIER_WRITE 271 #define COM_BARRIER(r, f) \ 272 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 273 274 /*ARGSUSED*/ 275 int 276 comspeed(long speed, long frequency, int type) 277 { 278 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 279 280 int x, err; 281 int divisor = 16; 282 283 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 284 divisor = 13; 285 } 286 287 if (speed == 0) 288 return (0); 289 if (speed < 0) 290 return (-1); 291 x = divrnd(frequency / divisor, speed); 292 if (x <= 0) 293 return (-1); 294 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 295 if (err < 0) 296 err = -err; 297 if (err > COM_TOLERANCE) 298 return (-1); 299 return (x); 300 301 #undef divrnd 302 } 303 304 #ifdef COM_DEBUG 305 int com_debug = 0; 306 307 void comstatus(struct com_softc *, const char *); 308 void 309 comstatus(struct com_softc *sc, const char *str) 310 { 311 struct tty *tp = sc->sc_tty; 312 313 aprint_normal_dev(sc->sc_dev, 314 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 315 str, 316 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 317 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 318 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 319 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 320 sc->sc_tx_stopped ? '+' : '-'); 321 322 aprint_normal_dev(sc->sc_dev, 323 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 324 str, 325 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 326 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 327 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 328 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 329 sc->sc_rx_flags); 330 } 331 #endif 332 333 int 334 com_probe_subr(struct com_regs *regs) 335 { 336 337 /* force access to id reg */ 338 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 339 CSR_WRITE_1(regs, COM_REG_IIR, 0); 340 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 341 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 342 return (0); 343 344 return (1); 345 } 346 347 int 348 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 349 { 350 struct com_regs regs; 351 352 regs.cr_iot = iot; 353 regs.cr_ioh = ioh; 354 #ifdef COM_REGMAP 355 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 356 #endif 357 358 return com_probe_subr(®s); 359 } 360 361 /* 362 * No locking in this routine; it is only called during attach, 363 * or with the port already locked. 364 */ 365 static void 366 com_enable_debugport(struct com_softc *sc) 367 { 368 369 /* Turn on line break interrupt, set carrier. */ 370 sc->sc_ier = IER_ERLS; 371 if (sc->sc_type == COM_TYPE_PXA2x0) 372 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 373 if (sc->sc_type == COM_TYPE_INGENIC || 374 sc->sc_type == COM_TYPE_TEGRA) 375 sc->sc_ier |= IER_ERXTOUT; 376 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 377 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 378 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 379 } 380 381 void 382 com_attach_subr(struct com_softc *sc) 383 { 384 struct com_regs *regsp = &sc->sc_regs; 385 struct tty *tp; 386 u_int8_t lcr; 387 const char *fifo_msg = NULL; 388 prop_dictionary_t dict; 389 bool is_console = true; 390 391 aprint_naive("\n"); 392 393 dict = device_properties(sc->sc_dev); 394 prop_dictionary_get_bool(dict, "is_console", &is_console); 395 callout_init(&sc->sc_diag_callout, 0); 396 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 397 398 #if defined(COM_16650) 399 sc->sc_type = COM_TYPE_16650; 400 #elif defined(COM_16750) 401 sc->sc_type = COM_TYPE_16750; 402 #elif defined(COM_AWIN) 403 sc->sc_type = COM_TYPE_SUNXI; 404 #elif defined(COM_HAYESP) 405 sc->sc_type = COM_TYPE_HAYESP; 406 #elif defined(COM_PXA2X0) 407 sc->sc_type = COM_TYPE_PXA2x0; 408 #endif 409 410 /* Disable interrupts before configuring the device. */ 411 if (sc->sc_type == COM_TYPE_PXA2x0) 412 sc->sc_ier = IER_EUART; 413 else 414 sc->sc_ier = 0; 415 416 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 417 418 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 419 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 420 comconsattached = 1; 421 422 if (cn_tab == NULL && comcnreattach() != 0) { 423 printf("can't re-init serial console @%lx\n", 424 (u_long)comcons_info.regs.cr_iobase); 425 } 426 427 switch (sc->sc_type) { 428 case COM_TYPE_16750: 429 case COM_TYPE_SUNXI: 430 /* Use in comintr(). */ 431 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 432 break; 433 } 434 435 /* Make sure the console is always "hardwired". */ 436 delay(10000); /* wait for output to finish */ 437 if (is_console) { 438 SET(sc->sc_hwflags, COM_HW_CONSOLE); 439 } 440 441 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 442 } 443 444 /* Probe for FIFO */ 445 switch (sc->sc_type) { 446 case COM_TYPE_HAYESP: 447 goto fifodone; 448 449 case COM_TYPE_AU1x00: 450 sc->sc_fifolen = 16; 451 fifo_msg = "Au1X00 UART, working fifo"; 452 SET(sc->sc_hwflags, COM_HW_FIFO); 453 goto fifodelay; 454 455 case COM_TYPE_16550_NOERS: 456 sc->sc_fifolen = 16; 457 fifo_msg = "ns16650, no ERS, working fifo"; 458 SET(sc->sc_hwflags, COM_HW_FIFO); 459 goto fifodelay; 460 461 case COM_TYPE_OMAP: 462 sc->sc_fifolen = 64; 463 fifo_msg = "OMAP UART, working fifo"; 464 SET(sc->sc_hwflags, COM_HW_FIFO); 465 goto fifodelay; 466 467 case COM_TYPE_INGENIC: 468 sc->sc_fifolen = 16; 469 fifo_msg = "Ingenic UART, working fifo"; 470 SET(sc->sc_hwflags, COM_HW_FIFO); 471 SET(sc->sc_hwflags, COM_HW_NOIEN); 472 goto fifodelay; 473 474 case COM_TYPE_TEGRA: 475 sc->sc_fifolen = 8; 476 fifo_msg = "Tegra UART, working fifo"; 477 SET(sc->sc_hwflags, COM_HW_FIFO); 478 CSR_WRITE_1(regsp, COM_REG_FIFO, 479 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 480 goto fifodelay; 481 482 case COM_TYPE_BCMAUXUART: 483 sc->sc_fifolen = 1; 484 fifo_msg = "BCM AUX UART, working fifo"; 485 SET(sc->sc_hwflags, COM_HW_FIFO); 486 CSR_WRITE_1(regsp, COM_REG_FIFO, 487 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 488 goto fifodelay; 489 } 490 491 sc->sc_fifolen = 1; 492 /* look for a NS 16550AF UART with FIFOs */ 493 if (sc->sc_type == COM_TYPE_INGENIC) { 494 CSR_WRITE_1(regsp, COM_REG_FIFO, 495 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 496 FIFO_TRIGGER_14 | FIFO_UART_ON); 497 } else 498 CSR_WRITE_1(regsp, COM_REG_FIFO, 499 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 500 delay(100); 501 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 502 == IIR_FIFO_MASK) 503 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 504 == FIFO_TRIGGER_14) { 505 SET(sc->sc_hwflags, COM_HW_FIFO); 506 507 fifo_msg = "ns16550a, working fifo"; 508 509 /* 510 * IIR changes into the EFR if LCR is set to LCR_EERS 511 * on 16650s. We also know IIR != 0 at this point. 512 * Write 0 into the EFR, and read it. If the result 513 * is 0, we have a 16650. 514 * 515 * Older 16650s were broken; the test to detect them 516 * is taken from the Linux driver. Apparently 517 * setting DLAB enable gives access to the EFR on 518 * these chips. 519 */ 520 if (sc->sc_type == COM_TYPE_16650) { 521 lcr = CSR_READ_1(regsp, COM_REG_LCR); 522 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 523 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 524 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 525 CSR_WRITE_1(regsp, COM_REG_LCR, 526 lcr | LCR_DLAB); 527 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 528 CLR(sc->sc_hwflags, COM_HW_FIFO); 529 sc->sc_fifolen = 0; 530 } else { 531 SET(sc->sc_hwflags, COM_HW_FLOW); 532 sc->sc_fifolen = 32; 533 } 534 } else 535 sc->sc_fifolen = 16; 536 537 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 538 if (sc->sc_fifolen == 0) 539 fifo_msg = "st16650, broken fifo"; 540 else if (sc->sc_fifolen == 32) 541 fifo_msg = "st16650a, working fifo"; 542 else 543 fifo_msg = "ns16550a, working fifo"; 544 } 545 546 /* 547 * TL16C750 can enable 64byte FIFO, only when DLAB 548 * is 1. However, some 16750 may always enable. For 549 * example, restrictions according to DLAB in a data 550 * sheet for SC16C750 were not described. 551 * Please enable 'options COM_16650', supposing you 552 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 553 * should become effective. 554 */ 555 if (sc->sc_type == COM_TYPE_16750) { 556 uint8_t iir1, iir2; 557 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 558 559 lcr = CSR_READ_1(regsp, COM_REG_LCR); 560 CSR_WRITE_1(regsp, COM_REG_LCR, 561 lcr & ~LCR_DLAB); 562 CSR_WRITE_1(regsp, COM_REG_FIFO, 563 fcr | FIFO_64B_ENABLE); 564 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 565 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 566 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 567 CSR_WRITE_1(regsp, COM_REG_FIFO, 568 fcr | FIFO_64B_ENABLE); 569 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 570 571 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 572 573 if (!ISSET(iir1, IIR_64B_FIFO) && 574 ISSET(iir2, IIR_64B_FIFO)) { 575 /* It is TL16C750. */ 576 sc->sc_fifolen = 64; 577 SET(sc->sc_hwflags, COM_HW_AFE); 578 } else 579 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 580 581 if (sc->sc_fifolen == 64) 582 fifo_msg = "tl16c750, working fifo"; 583 else 584 fifo_msg = "ns16750, working fifo"; 585 } 586 } else 587 fifo_msg = "ns16550, broken fifo"; 588 else 589 fifo_msg = "ns8250 or ns16450, no fifo"; 590 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 591 592 fifodelay: 593 /* 594 * Some chips will clear down both Tx and Rx FIFOs when zero is 595 * written to com_fifo. If this chip is the console, writing zero 596 * results in some of the chip/FIFO description being lost, so delay 597 * printing it until now. 598 */ 599 delay(10); 600 aprint_normal(": %s\n", fifo_msg); 601 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 602 sc->sc_fifolen = 1; 603 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 604 } 605 606 fifodone: 607 608 tp = tty_alloc(); 609 tp->t_oproc = comstart; 610 tp->t_param = comparam; 611 tp->t_hwiflow = comhwiflow; 612 tp->t_softc = sc; 613 614 sc->sc_tty = tp; 615 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 616 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 617 sc->sc_rbavail = com_rbuf_size; 618 if (sc->sc_rbuf == NULL) { 619 aprint_error_dev(sc->sc_dev, 620 "unable to allocate ring buffer\n"); 621 return; 622 } 623 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 624 625 tty_attach(tp); 626 627 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 628 SET(sc->sc_mcr, MCR_IENABLE); 629 630 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 631 int maj; 632 633 /* locate the major number */ 634 maj = cdevsw_lookup_major(&com_cdevsw); 635 636 tp->t_dev = cn_tab->cn_dev = makedev(maj, 637 device_unit(sc->sc_dev)); 638 639 aprint_normal_dev(sc->sc_dev, "console\n"); 640 } 641 642 #ifdef KGDB 643 /* 644 * Allow kgdb to "take over" this port. If this is 645 * not the console and is the kgdb device, it has 646 * exclusive use. If it's the console _and_ the 647 * kgdb device, it doesn't. 648 */ 649 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 650 regsp->cr_iobase == comkgdbregs.cr_iobase) { 651 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 652 com_kgdb_attached = 1; 653 654 SET(sc->sc_hwflags, COM_HW_KGDB); 655 } 656 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 657 } 658 #endif 659 660 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 661 662 #ifdef RND_COM 663 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 664 RND_TYPE_TTY, RND_FLAG_DEFAULT); 665 #endif 666 667 /* if there are no enable/disable functions, assume the device 668 is always enabled */ 669 if (!sc->enable) 670 sc->enabled = 1; 671 672 com_config(sc); 673 674 SET(sc->sc_hwflags, COM_HW_DEV_OK); 675 } 676 677 void 678 com_config(struct com_softc *sc) 679 { 680 struct com_regs *regsp = &sc->sc_regs; 681 682 /* Disable interrupts before configuring the device. */ 683 if (sc->sc_type == COM_TYPE_PXA2x0) 684 sc->sc_ier = IER_EUART; 685 else 686 sc->sc_ier = 0; 687 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 688 (void) CSR_READ_1(regsp, COM_REG_IIR); 689 690 /* Look for a Hayes ESP board. */ 691 if (sc->sc_type == COM_TYPE_HAYESP) { 692 693 /* Set 16550 compatibility mode */ 694 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 695 HAYESP_SETMODE); 696 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 697 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 698 HAYESP_MODE_SCALE); 699 700 /* Set RTS/CTS flow control */ 701 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 702 HAYESP_SETFLOWTYPE); 703 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 704 HAYESP_FLOW_RTS); 705 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 706 HAYESP_FLOW_CTS); 707 708 /* Set flow control levels */ 709 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 710 HAYESP_SETRXFLOW); 711 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 712 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 713 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 714 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 715 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 716 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 717 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 718 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 719 } 720 721 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 722 com_enable_debugport(sc); 723 } 724 725 #if 0 726 static int 727 comcngetc_detached(dev_t dev) 728 { 729 return 0; 730 } 731 732 static void 733 comcnputc_detached(dev_t dev, int c) 734 { 735 } 736 #endif 737 738 int 739 com_detach(device_t self, int flags) 740 { 741 struct com_softc *sc = device_private(self); 742 int maj, mn; 743 744 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 745 return EBUSY; 746 747 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 748 (flags & DETACH_SHUTDOWN) != 0) 749 return EBUSY; 750 751 if (sc->disable != NULL && sc->enabled != 0) { 752 (*sc->disable)(sc); 753 sc->enabled = 0; 754 } 755 756 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 757 comconsattached = 0; 758 cn_tab = NULL; 759 } 760 761 /* locate the major number */ 762 maj = cdevsw_lookup_major(&com_cdevsw); 763 764 /* Nuke the vnodes for any open instances. */ 765 mn = device_unit(self); 766 vdevgone(maj, mn, mn, VCHR); 767 768 mn |= COMDIALOUT_MASK; 769 vdevgone(maj, mn, mn, VCHR); 770 771 if (sc->sc_rbuf == NULL) { 772 /* 773 * Ring buffer allocation failed in the com_attach_subr, 774 * only the tty is allocated, and nothing else. 775 */ 776 tty_free(sc->sc_tty); 777 return 0; 778 } 779 780 /* Free the receive buffer. */ 781 free(sc->sc_rbuf, M_DEVBUF); 782 783 /* Detach and free the tty. */ 784 tty_detach(sc->sc_tty); 785 tty_free(sc->sc_tty); 786 787 /* Unhook the soft interrupt handler. */ 788 softint_disestablish(sc->sc_si); 789 790 #ifdef RND_COM 791 /* Unhook the entropy source. */ 792 rnd_detach_source(&sc->rnd_source); 793 #endif 794 callout_destroy(&sc->sc_diag_callout); 795 796 /* Destroy the lock. */ 797 mutex_destroy(&sc->sc_lock); 798 799 return (0); 800 } 801 802 void 803 com_shutdown(struct com_softc *sc) 804 { 805 struct tty *tp = sc->sc_tty; 806 807 mutex_spin_enter(&sc->sc_lock); 808 809 /* If we were asserting flow control, then deassert it. */ 810 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 811 com_hwiflow(sc); 812 813 /* Clear any break condition set with TIOCSBRK. */ 814 com_break(sc, 0); 815 816 /* 817 * Hang up if necessary. Wait a bit, so the other side has time to 818 * notice even if we immediately open the port again. 819 * Avoid tsleeping above splhigh(). 820 */ 821 if (ISSET(tp->t_cflag, HUPCL)) { 822 com_modem(sc, 0); 823 mutex_spin_exit(&sc->sc_lock); 824 /* XXX will only timeout */ 825 (void) kpause(ttclos, false, hz, NULL); 826 mutex_spin_enter(&sc->sc_lock); 827 } 828 829 /* Turn off interrupts. */ 830 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 831 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 832 if ((sc->sc_type == COM_TYPE_PXA2x0) || 833 (sc->sc_type == COM_TYPE_INGENIC) || 834 (sc->sc_type == COM_TYPE_TEGRA)) 835 sc->sc_ier |= IER_ERXTOUT; 836 } else 837 sc->sc_ier = 0; 838 839 if (sc->sc_type == COM_TYPE_PXA2x0) 840 sc->sc_ier |= IER_EUART; 841 842 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 843 844 mutex_spin_exit(&sc->sc_lock); 845 846 if (sc->disable) { 847 #ifdef DIAGNOSTIC 848 if (!sc->enabled) 849 panic("com_shutdown: not enabled?"); 850 #endif 851 (*sc->disable)(sc); 852 sc->enabled = 0; 853 } 854 } 855 856 int 857 comopen(dev_t dev, int flag, int mode, struct lwp *l) 858 { 859 struct com_softc *sc; 860 struct tty *tp; 861 int s; 862 int error; 863 864 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 865 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 866 sc->sc_rbuf == NULL) 867 return (ENXIO); 868 869 if (!device_is_active(sc->sc_dev)) 870 return (ENXIO); 871 872 #ifdef KGDB 873 /* 874 * If this is the kgdb port, no other use is permitted. 875 */ 876 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 877 return (EBUSY); 878 #endif 879 880 tp = sc->sc_tty; 881 882 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 883 return (EBUSY); 884 885 s = spltty(); 886 887 /* 888 * Do the following iff this is a first open. 889 */ 890 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 891 struct termios t; 892 893 tp->t_dev = dev; 894 895 if (sc->enable) { 896 if ((*sc->enable)(sc)) { 897 splx(s); 898 aprint_error_dev(sc->sc_dev, 899 "device enable failed\n"); 900 return (EIO); 901 } 902 mutex_spin_enter(&sc->sc_lock); 903 sc->enabled = 1; 904 com_config(sc); 905 } else { 906 mutex_spin_enter(&sc->sc_lock); 907 } 908 909 /* Turn on interrupts. */ 910 sc->sc_ier = IER_ERXRDY | IER_ERLS; 911 if (!ISSET(tp->t_cflag, CLOCAL)) 912 sc->sc_ier |= IER_EMSC; 913 914 if (sc->sc_type == COM_TYPE_PXA2x0) 915 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 916 else if (sc->sc_type == COM_TYPE_INGENIC || 917 sc->sc_type == COM_TYPE_TEGRA) 918 sc->sc_ier |= IER_ERXTOUT; 919 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 920 921 /* Fetch the current modem control status, needed later. */ 922 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 923 924 /* Clear PPS capture state on first open. */ 925 mutex_spin_enter(&timecounter_lock); 926 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 927 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 928 pps_init(&sc->sc_pps_state); 929 mutex_spin_exit(&timecounter_lock); 930 931 mutex_spin_exit(&sc->sc_lock); 932 933 /* 934 * Initialize the termios status to the defaults. Add in the 935 * sticky bits from TIOCSFLAGS. 936 */ 937 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 938 t.c_ospeed = comcons_info.rate; 939 t.c_cflag = comcons_info.cflag; 940 } else { 941 t.c_ospeed = TTYDEF_SPEED; 942 t.c_cflag = TTYDEF_CFLAG; 943 } 944 t.c_ispeed = t.c_ospeed; 945 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 946 SET(t.c_cflag, CLOCAL); 947 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 948 SET(t.c_cflag, CRTSCTS); 949 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 950 SET(t.c_cflag, MDMBUF); 951 /* Make sure comparam() will do something. */ 952 tp->t_ospeed = 0; 953 (void) comparam(tp, &t); 954 tp->t_iflag = TTYDEF_IFLAG; 955 tp->t_oflag = TTYDEF_OFLAG; 956 tp->t_lflag = TTYDEF_LFLAG; 957 ttychars(tp); 958 ttsetwater(tp); 959 960 mutex_spin_enter(&sc->sc_lock); 961 962 /* 963 * Turn on DTR. We must always do this, even if carrier is not 964 * present, because otherwise we'd have to use TIOCSDTR 965 * immediately after setting CLOCAL, which applications do not 966 * expect. We always assert DTR while the device is open 967 * unless explicitly requested to deassert it. 968 */ 969 com_modem(sc, 1); 970 971 /* Clear the input ring, and unblock. */ 972 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 973 sc->sc_rbavail = com_rbuf_size; 974 com_iflush(sc); 975 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 976 com_hwiflow(sc); 977 978 #ifdef COM_DEBUG 979 if (com_debug) 980 comstatus(sc, "comopen "); 981 #endif 982 983 mutex_spin_exit(&sc->sc_lock); 984 } 985 986 splx(s); 987 988 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 989 if (error) 990 goto bad; 991 992 error = (*tp->t_linesw->l_open)(dev, tp); 993 if (error) 994 goto bad; 995 996 return (0); 997 998 bad: 999 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1000 /* 1001 * We failed to open the device, and nobody else had it opened. 1002 * Clean up the state as appropriate. 1003 */ 1004 com_shutdown(sc); 1005 } 1006 1007 return (error); 1008 } 1009 1010 int 1011 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1012 { 1013 struct com_softc *sc = 1014 device_lookup_private(&com_cd, COMUNIT(dev)); 1015 struct tty *tp = sc->sc_tty; 1016 1017 /* XXX This is for cons.c. */ 1018 if (!ISSET(tp->t_state, TS_ISOPEN)) 1019 return (0); 1020 1021 (*tp->t_linesw->l_close)(tp, flag); 1022 ttyclose(tp); 1023 1024 if (COM_ISALIVE(sc) == 0) 1025 return (0); 1026 1027 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1028 /* 1029 * Although we got a last close, the device may still be in 1030 * use; e.g. if this was the dialout node, and there are still 1031 * processes waiting for carrier on the non-dialout node. 1032 */ 1033 com_shutdown(sc); 1034 } 1035 1036 return (0); 1037 } 1038 1039 int 1040 comread(dev_t dev, struct uio *uio, int flag) 1041 { 1042 struct com_softc *sc = 1043 device_lookup_private(&com_cd, COMUNIT(dev)); 1044 struct tty *tp = sc->sc_tty; 1045 1046 if (COM_ISALIVE(sc) == 0) 1047 return (EIO); 1048 1049 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1050 } 1051 1052 int 1053 comwrite(dev_t dev, struct uio *uio, int flag) 1054 { 1055 struct com_softc *sc = 1056 device_lookup_private(&com_cd, COMUNIT(dev)); 1057 struct tty *tp = sc->sc_tty; 1058 1059 if (COM_ISALIVE(sc) == 0) 1060 return (EIO); 1061 1062 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1063 } 1064 1065 int 1066 compoll(dev_t dev, int events, struct lwp *l) 1067 { 1068 struct com_softc *sc = 1069 device_lookup_private(&com_cd, COMUNIT(dev)); 1070 struct tty *tp = sc->sc_tty; 1071 1072 if (COM_ISALIVE(sc) == 0) 1073 return (POLLHUP); 1074 1075 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1076 } 1077 1078 struct tty * 1079 comtty(dev_t dev) 1080 { 1081 struct com_softc *sc = 1082 device_lookup_private(&com_cd, COMUNIT(dev)); 1083 struct tty *tp = sc->sc_tty; 1084 1085 return (tp); 1086 } 1087 1088 int 1089 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1090 { 1091 struct com_softc *sc; 1092 struct tty *tp; 1093 int error; 1094 1095 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1096 if (sc == NULL) 1097 return ENXIO; 1098 if (COM_ISALIVE(sc) == 0) 1099 return (EIO); 1100 1101 tp = sc->sc_tty; 1102 1103 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1104 if (error != EPASSTHROUGH) 1105 return (error); 1106 1107 error = ttioctl(tp, cmd, data, flag, l); 1108 if (error != EPASSTHROUGH) 1109 return (error); 1110 1111 error = 0; 1112 switch (cmd) { 1113 case TIOCSFLAGS: 1114 error = kauth_authorize_device_tty(l->l_cred, 1115 KAUTH_DEVICE_TTY_PRIVSET, tp); 1116 break; 1117 default: 1118 /* nothing */ 1119 break; 1120 } 1121 if (error) { 1122 return error; 1123 } 1124 1125 mutex_spin_enter(&sc->sc_lock); 1126 1127 switch (cmd) { 1128 case TIOCSBRK: 1129 com_break(sc, 1); 1130 break; 1131 1132 case TIOCCBRK: 1133 com_break(sc, 0); 1134 break; 1135 1136 case TIOCSDTR: 1137 com_modem(sc, 1); 1138 break; 1139 1140 case TIOCCDTR: 1141 com_modem(sc, 0); 1142 break; 1143 1144 case TIOCGFLAGS: 1145 *(int *)data = sc->sc_swflags; 1146 break; 1147 1148 case TIOCSFLAGS: 1149 sc->sc_swflags = *(int *)data; 1150 break; 1151 1152 case TIOCMSET: 1153 case TIOCMBIS: 1154 case TIOCMBIC: 1155 tiocm_to_com(sc, cmd, *(int *)data); 1156 break; 1157 1158 case TIOCMGET: 1159 *(int *)data = com_to_tiocm(sc); 1160 break; 1161 1162 case PPS_IOC_CREATE: 1163 case PPS_IOC_DESTROY: 1164 case PPS_IOC_GETPARAMS: 1165 case PPS_IOC_SETPARAMS: 1166 case PPS_IOC_GETCAP: 1167 case PPS_IOC_FETCH: 1168 #ifdef PPS_SYNC 1169 case PPS_IOC_KCBIND: 1170 #endif 1171 mutex_spin_enter(&timecounter_lock); 1172 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1173 mutex_spin_exit(&timecounter_lock); 1174 break; 1175 1176 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1177 mutex_spin_enter(&timecounter_lock); 1178 #ifndef PPS_TRAILING_EDGE 1179 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1180 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1181 #else 1182 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1183 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1184 #endif 1185 mutex_spin_exit(&timecounter_lock); 1186 break; 1187 1188 default: 1189 error = EPASSTHROUGH; 1190 break; 1191 } 1192 1193 mutex_spin_exit(&sc->sc_lock); 1194 1195 #ifdef COM_DEBUG 1196 if (com_debug) 1197 comstatus(sc, "comioctl "); 1198 #endif 1199 1200 return (error); 1201 } 1202 1203 integrate void 1204 com_schedrx(struct com_softc *sc) 1205 { 1206 1207 sc->sc_rx_ready = 1; 1208 1209 /* Wake up the poller. */ 1210 softint_schedule(sc->sc_si); 1211 } 1212 1213 void 1214 com_break(struct com_softc *sc, int onoff) 1215 { 1216 1217 if (onoff) 1218 SET(sc->sc_lcr, LCR_SBREAK); 1219 else 1220 CLR(sc->sc_lcr, LCR_SBREAK); 1221 1222 if (!sc->sc_heldchange) { 1223 if (sc->sc_tx_busy) { 1224 sc->sc_heldtbc = sc->sc_tbc; 1225 sc->sc_tbc = 0; 1226 sc->sc_heldchange = 1; 1227 } else 1228 com_loadchannelregs(sc); 1229 } 1230 } 1231 1232 void 1233 com_modem(struct com_softc *sc, int onoff) 1234 { 1235 1236 if (sc->sc_mcr_dtr == 0) 1237 return; 1238 1239 if (onoff) 1240 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1241 else 1242 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1243 1244 if (!sc->sc_heldchange) { 1245 if (sc->sc_tx_busy) { 1246 sc->sc_heldtbc = sc->sc_tbc; 1247 sc->sc_tbc = 0; 1248 sc->sc_heldchange = 1; 1249 } else 1250 com_loadchannelregs(sc); 1251 } 1252 } 1253 1254 void 1255 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1256 { 1257 u_char combits; 1258 1259 combits = 0; 1260 if (ISSET(ttybits, TIOCM_DTR)) 1261 SET(combits, MCR_DTR); 1262 if (ISSET(ttybits, TIOCM_RTS)) 1263 SET(combits, MCR_RTS); 1264 1265 switch (how) { 1266 case TIOCMBIC: 1267 CLR(sc->sc_mcr, combits); 1268 break; 1269 1270 case TIOCMBIS: 1271 SET(sc->sc_mcr, combits); 1272 break; 1273 1274 case TIOCMSET: 1275 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1276 SET(sc->sc_mcr, combits); 1277 break; 1278 } 1279 1280 if (!sc->sc_heldchange) { 1281 if (sc->sc_tx_busy) { 1282 sc->sc_heldtbc = sc->sc_tbc; 1283 sc->sc_tbc = 0; 1284 sc->sc_heldchange = 1; 1285 } else 1286 com_loadchannelregs(sc); 1287 } 1288 } 1289 1290 int 1291 com_to_tiocm(struct com_softc *sc) 1292 { 1293 u_char combits; 1294 int ttybits = 0; 1295 1296 combits = sc->sc_mcr; 1297 if (ISSET(combits, MCR_DTR)) 1298 SET(ttybits, TIOCM_DTR); 1299 if (ISSET(combits, MCR_RTS)) 1300 SET(ttybits, TIOCM_RTS); 1301 1302 combits = sc->sc_msr; 1303 if (sc->sc_type == COM_TYPE_INGENIC) { 1304 SET(ttybits, TIOCM_CD); 1305 } else { 1306 if (ISSET(combits, MSR_DCD)) 1307 SET(ttybits, TIOCM_CD); 1308 } 1309 if (ISSET(combits, MSR_CTS)) 1310 SET(ttybits, TIOCM_CTS); 1311 if (ISSET(combits, MSR_DSR)) 1312 SET(ttybits, TIOCM_DSR); 1313 if (ISSET(combits, MSR_RI | MSR_TERI)) 1314 SET(ttybits, TIOCM_RI); 1315 1316 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1317 SET(ttybits, TIOCM_LE); 1318 1319 return (ttybits); 1320 } 1321 1322 static u_char 1323 cflag2lcr(tcflag_t cflag) 1324 { 1325 u_char lcr = 0; 1326 1327 switch (ISSET(cflag, CSIZE)) { 1328 case CS5: 1329 SET(lcr, LCR_5BITS); 1330 break; 1331 case CS6: 1332 SET(lcr, LCR_6BITS); 1333 break; 1334 case CS7: 1335 SET(lcr, LCR_7BITS); 1336 break; 1337 case CS8: 1338 SET(lcr, LCR_8BITS); 1339 break; 1340 } 1341 if (ISSET(cflag, PARENB)) { 1342 SET(lcr, LCR_PENAB); 1343 if (!ISSET(cflag, PARODD)) 1344 SET(lcr, LCR_PEVEN); 1345 } 1346 if (ISSET(cflag, CSTOPB)) 1347 SET(lcr, LCR_STOPB); 1348 1349 return (lcr); 1350 } 1351 1352 int 1353 comparam(struct tty *tp, struct termios *t) 1354 { 1355 struct com_softc *sc = 1356 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1357 int ospeed; 1358 u_char lcr; 1359 1360 if (COM_ISALIVE(sc) == 0) 1361 return (EIO); 1362 1363 if (sc->sc_type == COM_TYPE_HAYESP) { 1364 int prescaler, speed; 1365 1366 /* 1367 * Calculate UART clock prescaler. It should be in 1368 * range of 0 .. 3. 1369 */ 1370 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1371 prescaler++, speed /= 2) 1372 if ((ospeed = comspeed(speed, sc->sc_frequency, 1373 sc->sc_type)) > 0) 1374 break; 1375 1376 if (prescaler == 4) 1377 return (EINVAL); 1378 sc->sc_prescaler = prescaler; 1379 } else 1380 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1381 1382 /* Check requested parameters. */ 1383 if (ospeed < 0) 1384 return (EINVAL); 1385 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1386 return (EINVAL); 1387 1388 /* 1389 * For the console, always force CLOCAL and !HUPCL, so that the port 1390 * is always active. 1391 */ 1392 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1393 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1394 SET(t->c_cflag, CLOCAL); 1395 CLR(t->c_cflag, HUPCL); 1396 } 1397 1398 /* 1399 * If there were no changes, don't do anything. This avoids dropping 1400 * input and improves performance when all we did was frob things like 1401 * VMIN and VTIME. 1402 */ 1403 if (tp->t_ospeed == t->c_ospeed && 1404 tp->t_cflag == t->c_cflag) 1405 return (0); 1406 1407 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1408 1409 mutex_spin_enter(&sc->sc_lock); 1410 1411 sc->sc_lcr = lcr; 1412 1413 /* 1414 * If we're not in a mode that assumes a connection is present, then 1415 * ignore carrier changes. 1416 */ 1417 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1418 sc->sc_msr_dcd = 0; 1419 else 1420 sc->sc_msr_dcd = MSR_DCD; 1421 /* 1422 * Set the flow control pins depending on the current flow control 1423 * mode. 1424 */ 1425 if (ISSET(t->c_cflag, CRTSCTS)) { 1426 sc->sc_mcr_dtr = MCR_DTR; 1427 sc->sc_mcr_rts = MCR_RTS; 1428 sc->sc_msr_cts = MSR_CTS; 1429 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1430 SET(sc->sc_mcr, MCR_AFE); 1431 } else { 1432 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1433 } 1434 } else if (ISSET(t->c_cflag, MDMBUF)) { 1435 /* 1436 * For DTR/DCD flow control, make sure we don't toggle DTR for 1437 * carrier detection. 1438 */ 1439 sc->sc_mcr_dtr = 0; 1440 sc->sc_mcr_rts = MCR_DTR; 1441 sc->sc_msr_cts = MSR_DCD; 1442 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1443 CLR(sc->sc_mcr, MCR_AFE); 1444 } else { 1445 sc->sc_efr = 0; 1446 } 1447 } else { 1448 /* 1449 * If no flow control, then always set RTS. This will make 1450 * the other side happy if it mistakenly thinks we're doing 1451 * RTS/CTS flow control. 1452 */ 1453 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1454 sc->sc_mcr_rts = 0; 1455 sc->sc_msr_cts = 0; 1456 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1457 CLR(sc->sc_mcr, MCR_AFE); 1458 } else { 1459 sc->sc_efr = 0; 1460 } 1461 if (ISSET(sc->sc_mcr, MCR_DTR)) 1462 SET(sc->sc_mcr, MCR_RTS); 1463 else 1464 CLR(sc->sc_mcr, MCR_RTS); 1465 } 1466 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1467 1468 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1469 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1470 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1471 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1472 1473 sc->sc_dlbl = ospeed; 1474 sc->sc_dlbh = ospeed >> 8; 1475 1476 /* 1477 * Set the FIFO threshold based on the receive speed. 1478 * 1479 * * If it's a low speed, it's probably a mouse or some other 1480 * interactive device, so set the threshold low. 1481 * * If it's a high speed, trim the trigger level down to prevent 1482 * overflows. 1483 * * Otherwise set it a bit higher. 1484 */ 1485 if (sc->sc_type == COM_TYPE_HAYESP) { 1486 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1487 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1488 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1489 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1490 if (t->c_ospeed <= 1200) 1491 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1492 else if (t->c_ospeed <= 38400) 1493 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1494 else 1495 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1496 } else { 1497 sc->sc_fifo = 0; 1498 } 1499 1500 if (sc->sc_type == COM_TYPE_INGENIC) 1501 sc->sc_fifo |= FIFO_UART_ON; 1502 1503 /* And copy to tty. */ 1504 tp->t_ispeed = t->c_ospeed; 1505 tp->t_ospeed = t->c_ospeed; 1506 tp->t_cflag = t->c_cflag; 1507 1508 if (!sc->sc_heldchange) { 1509 if (sc->sc_tx_busy) { 1510 sc->sc_heldtbc = sc->sc_tbc; 1511 sc->sc_tbc = 0; 1512 sc->sc_heldchange = 1; 1513 } else 1514 com_loadchannelregs(sc); 1515 } 1516 1517 if (!ISSET(t->c_cflag, CHWFLOW)) { 1518 /* Disable the high water mark. */ 1519 sc->sc_r_hiwat = 0; 1520 sc->sc_r_lowat = 0; 1521 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1522 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1523 com_schedrx(sc); 1524 } 1525 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1526 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1527 com_hwiflow(sc); 1528 } 1529 } else { 1530 sc->sc_r_hiwat = com_rbuf_hiwat; 1531 sc->sc_r_lowat = com_rbuf_lowat; 1532 } 1533 1534 mutex_spin_exit(&sc->sc_lock); 1535 1536 /* 1537 * Update the tty layer's idea of the carrier bit, in case we changed 1538 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1539 * explicit request. 1540 */ 1541 if (sc->sc_type == COM_TYPE_INGENIC) { 1542 /* no DCD here */ 1543 (void) (*tp->t_linesw->l_modem)(tp, 1); 1544 } else 1545 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1546 1547 #ifdef COM_DEBUG 1548 if (com_debug) 1549 comstatus(sc, "comparam "); 1550 #endif 1551 1552 if (!ISSET(t->c_cflag, CHWFLOW)) { 1553 if (sc->sc_tx_stopped) { 1554 sc->sc_tx_stopped = 0; 1555 comstart(tp); 1556 } 1557 } 1558 1559 return (0); 1560 } 1561 1562 void 1563 com_iflush(struct com_softc *sc) 1564 { 1565 struct com_regs *regsp = &sc->sc_regs; 1566 uint8_t fifo; 1567 #ifdef DIAGNOSTIC 1568 int reg; 1569 #endif 1570 int timo; 1571 1572 #ifdef DIAGNOSTIC 1573 reg = 0xffff; 1574 #endif 1575 timo = 50000; 1576 /* flush any pending I/O */ 1577 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1578 && --timo) 1579 #ifdef DIAGNOSTIC 1580 reg = 1581 #else 1582 (void) 1583 #endif 1584 CSR_READ_1(regsp, COM_REG_RXDATA); 1585 #ifdef DIAGNOSTIC 1586 if (!timo) 1587 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1588 #endif 1589 1590 switch (sc->sc_type) { 1591 case COM_TYPE_16750: 1592 case COM_TYPE_SUNXI: 1593 /* 1594 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1595 * This should prevent triggering busy interrupt while 1596 * manipulating divisors. 1597 */ 1598 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1599 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1600 CSR_WRITE_1(regsp, COM_REG_FIFO, 1601 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1602 delay(100); 1603 break; 1604 } 1605 } 1606 1607 void 1608 com_loadchannelregs(struct com_softc *sc) 1609 { 1610 struct com_regs *regsp = &sc->sc_regs; 1611 1612 /* XXXXX necessary? */ 1613 com_iflush(sc); 1614 1615 if (sc->sc_type == COM_TYPE_PXA2x0) 1616 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1617 else 1618 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1619 1620 if (sc->sc_type == COM_TYPE_OMAP) { 1621 /* disable before changing settings */ 1622 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1623 } 1624 1625 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1626 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1627 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1628 /* no EFR on alchemy */ 1629 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1630 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1631 } 1632 if (sc->sc_type == COM_TYPE_AU1x00) { 1633 /* alchemy has single separate 16-bit clock divisor register */ 1634 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1635 (sc->sc_dlbh << 8)); 1636 } else { 1637 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1638 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1639 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1640 } 1641 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1642 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1643 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1644 if (sc->sc_type == COM_TYPE_HAYESP) { 1645 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1646 HAYESP_SETPRESCALER); 1647 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1648 sc->sc_prescaler); 1649 } 1650 if (sc->sc_type == COM_TYPE_OMAP) { 1651 /* setup the fifos. the FCR value is not used as long 1652 as SCR[6] and SCR[7] are 0, which they are at reset 1653 and we never touch the SCR register */ 1654 uint8_t rx_fifo_trig = 40; 1655 uint8_t tx_fifo_trig = 60; 1656 uint8_t rx_start = 8; 1657 uint8_t rx_halt = 60; 1658 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1659 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1660 1661 /* enable access to TCR & TLR */ 1662 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1663 1664 /* write tcr and tlr values */ 1665 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1666 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1667 1668 /* disable access to TCR & TLR */ 1669 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1670 1671 /* enable again, but mode is based on speed */ 1672 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1673 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1674 } else { 1675 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1676 } 1677 } 1678 1679 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1680 } 1681 1682 int 1683 comhwiflow(struct tty *tp, int block) 1684 { 1685 struct com_softc *sc = 1686 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1687 1688 if (COM_ISALIVE(sc) == 0) 1689 return (0); 1690 1691 if (sc->sc_mcr_rts == 0) 1692 return (0); 1693 1694 mutex_spin_enter(&sc->sc_lock); 1695 1696 if (block) { 1697 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1698 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1699 com_hwiflow(sc); 1700 } 1701 } else { 1702 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1703 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1704 com_schedrx(sc); 1705 } 1706 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1707 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1708 com_hwiflow(sc); 1709 } 1710 } 1711 1712 mutex_spin_exit(&sc->sc_lock); 1713 return (1); 1714 } 1715 1716 /* 1717 * (un)block input via hw flowcontrol 1718 */ 1719 void 1720 com_hwiflow(struct com_softc *sc) 1721 { 1722 struct com_regs *regsp= &sc->sc_regs; 1723 1724 if (sc->sc_mcr_rts == 0) 1725 return; 1726 1727 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1728 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1729 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1730 } else { 1731 SET(sc->sc_mcr, sc->sc_mcr_rts); 1732 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1733 } 1734 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1735 } 1736 1737 1738 void 1739 comstart(struct tty *tp) 1740 { 1741 struct com_softc *sc = 1742 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1743 struct com_regs *regsp = &sc->sc_regs; 1744 int s; 1745 1746 if (COM_ISALIVE(sc) == 0) 1747 return; 1748 1749 s = spltty(); 1750 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1751 goto out; 1752 if (sc->sc_tx_stopped) 1753 goto out; 1754 if (!ttypull(tp)) 1755 goto out; 1756 1757 /* Grab the first contiguous region of buffer space. */ 1758 { 1759 u_char *tba; 1760 int tbc; 1761 1762 tba = tp->t_outq.c_cf; 1763 tbc = ndqb(&tp->t_outq, 0); 1764 1765 mutex_spin_enter(&sc->sc_lock); 1766 1767 sc->sc_tba = tba; 1768 sc->sc_tbc = tbc; 1769 } 1770 1771 SET(tp->t_state, TS_BUSY); 1772 sc->sc_tx_busy = 1; 1773 1774 /* Enable transmit completion interrupts if necessary. */ 1775 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1776 SET(sc->sc_ier, IER_ETXRDY); 1777 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1778 } 1779 1780 /* Output the first chunk of the contiguous buffer. */ 1781 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1782 u_int n; 1783 1784 n = sc->sc_tbc; 1785 if (n > sc->sc_fifolen) 1786 n = sc->sc_fifolen; 1787 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1788 sc->sc_tbc -= n; 1789 sc->sc_tba += n; 1790 } 1791 1792 mutex_spin_exit(&sc->sc_lock); 1793 out: 1794 splx(s); 1795 return; 1796 } 1797 1798 /* 1799 * Stop output on a line. 1800 */ 1801 void 1802 comstop(struct tty *tp, int flag) 1803 { 1804 struct com_softc *sc = 1805 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1806 1807 mutex_spin_enter(&sc->sc_lock); 1808 if (ISSET(tp->t_state, TS_BUSY)) { 1809 /* Stop transmitting at the next chunk. */ 1810 sc->sc_tbc = 0; 1811 sc->sc_heldtbc = 0; 1812 if (!ISSET(tp->t_state, TS_TTSTOP)) 1813 SET(tp->t_state, TS_FLUSH); 1814 } 1815 mutex_spin_exit(&sc->sc_lock); 1816 } 1817 1818 void 1819 comdiag(void *arg) 1820 { 1821 struct com_softc *sc = arg; 1822 int overflows, floods; 1823 1824 mutex_spin_enter(&sc->sc_lock); 1825 overflows = sc->sc_overflows; 1826 sc->sc_overflows = 0; 1827 floods = sc->sc_floods; 1828 sc->sc_floods = 0; 1829 sc->sc_errors = 0; 1830 mutex_spin_exit(&sc->sc_lock); 1831 1832 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1833 device_xname(sc->sc_dev), 1834 overflows, overflows == 1 ? "" : "s", 1835 floods, floods == 1 ? "" : "s"); 1836 } 1837 1838 integrate void 1839 com_rxsoft(struct com_softc *sc, struct tty *tp) 1840 { 1841 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1842 u_char *get, *end; 1843 u_int cc, scc; 1844 u_char lsr; 1845 int code; 1846 1847 end = sc->sc_ebuf; 1848 get = sc->sc_rbget; 1849 scc = cc = com_rbuf_size - sc->sc_rbavail; 1850 1851 if (cc == com_rbuf_size) { 1852 sc->sc_floods++; 1853 if (sc->sc_errors++ == 0) 1854 callout_reset(&sc->sc_diag_callout, 60 * hz, 1855 comdiag, sc); 1856 } 1857 1858 /* If not yet open, drop the entire buffer content here */ 1859 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1860 get += cc << 1; 1861 if (get >= end) 1862 get -= com_rbuf_size << 1; 1863 cc = 0; 1864 } 1865 while (cc) { 1866 code = get[0]; 1867 lsr = get[1]; 1868 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1869 if (ISSET(lsr, LSR_OE)) { 1870 sc->sc_overflows++; 1871 if (sc->sc_errors++ == 0) 1872 callout_reset(&sc->sc_diag_callout, 1873 60 * hz, comdiag, sc); 1874 } 1875 if (ISSET(lsr, LSR_BI | LSR_FE)) 1876 SET(code, TTY_FE); 1877 if (ISSET(lsr, LSR_PE)) 1878 SET(code, TTY_PE); 1879 } 1880 if ((*rint)(code, tp) == -1) { 1881 /* 1882 * The line discipline's buffer is out of space. 1883 */ 1884 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1885 /* 1886 * We're either not using flow control, or the 1887 * line discipline didn't tell us to block for 1888 * some reason. Either way, we have no way to 1889 * know when there's more space available, so 1890 * just drop the rest of the data. 1891 */ 1892 get += cc << 1; 1893 if (get >= end) 1894 get -= com_rbuf_size << 1; 1895 cc = 0; 1896 } else { 1897 /* 1898 * Don't schedule any more receive processing 1899 * until the line discipline tells us there's 1900 * space available (through comhwiflow()). 1901 * Leave the rest of the data in the input 1902 * buffer. 1903 */ 1904 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1905 } 1906 break; 1907 } 1908 get += 2; 1909 if (get >= end) 1910 get = sc->sc_rbuf; 1911 cc--; 1912 } 1913 1914 if (cc != scc) { 1915 sc->sc_rbget = get; 1916 mutex_spin_enter(&sc->sc_lock); 1917 1918 cc = sc->sc_rbavail += scc - cc; 1919 /* Buffers should be ok again, release possible block. */ 1920 if (cc >= sc->sc_r_lowat) { 1921 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1922 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1923 SET(sc->sc_ier, IER_ERXRDY); 1924 if (sc->sc_type == COM_TYPE_PXA2x0) 1925 SET(sc->sc_ier, IER_ERXTOUT); 1926 if (sc->sc_type == COM_TYPE_INGENIC || 1927 sc->sc_type == COM_TYPE_TEGRA) 1928 SET(sc->sc_ier, IER_ERXTOUT); 1929 1930 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 1931 sc->sc_ier); 1932 } 1933 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1934 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1935 com_hwiflow(sc); 1936 } 1937 } 1938 mutex_spin_exit(&sc->sc_lock); 1939 } 1940 } 1941 1942 integrate void 1943 com_txsoft(struct com_softc *sc, struct tty *tp) 1944 { 1945 1946 CLR(tp->t_state, TS_BUSY); 1947 if (ISSET(tp->t_state, TS_FLUSH)) 1948 CLR(tp->t_state, TS_FLUSH); 1949 else 1950 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1951 (*tp->t_linesw->l_start)(tp); 1952 } 1953 1954 integrate void 1955 com_stsoft(struct com_softc *sc, struct tty *tp) 1956 { 1957 u_char msr, delta; 1958 1959 mutex_spin_enter(&sc->sc_lock); 1960 msr = sc->sc_msr; 1961 delta = sc->sc_msr_delta; 1962 sc->sc_msr_delta = 0; 1963 mutex_spin_exit(&sc->sc_lock); 1964 1965 if (ISSET(delta, sc->sc_msr_dcd)) { 1966 /* 1967 * Inform the tty layer that carrier detect changed. 1968 */ 1969 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1970 } 1971 1972 if (ISSET(delta, sc->sc_msr_cts)) { 1973 /* Block or unblock output according to flow control. */ 1974 if (ISSET(msr, sc->sc_msr_cts)) { 1975 sc->sc_tx_stopped = 0; 1976 (*tp->t_linesw->l_start)(tp); 1977 } else { 1978 sc->sc_tx_stopped = 1; 1979 } 1980 } 1981 1982 #ifdef COM_DEBUG 1983 if (com_debug) 1984 comstatus(sc, "com_stsoft"); 1985 #endif 1986 } 1987 1988 void 1989 comsoft(void *arg) 1990 { 1991 struct com_softc *sc = arg; 1992 struct tty *tp; 1993 1994 if (COM_ISALIVE(sc) == 0) 1995 return; 1996 1997 tp = sc->sc_tty; 1998 1999 if (sc->sc_rx_ready) { 2000 sc->sc_rx_ready = 0; 2001 com_rxsoft(sc, tp); 2002 } 2003 2004 if (sc->sc_st_check) { 2005 sc->sc_st_check = 0; 2006 com_stsoft(sc, tp); 2007 } 2008 2009 if (sc->sc_tx_done) { 2010 sc->sc_tx_done = 0; 2011 com_txsoft(sc, tp); 2012 } 2013 } 2014 2015 int 2016 comintr(void *arg) 2017 { 2018 struct com_softc *sc = arg; 2019 struct com_regs *regsp = &sc->sc_regs; 2020 2021 u_char *put, *end; 2022 u_int cc; 2023 u_char lsr, iir; 2024 2025 if (COM_ISALIVE(sc) == 0) 2026 return (0); 2027 2028 KASSERT(regsp != NULL); 2029 2030 mutex_spin_enter(&sc->sc_lock); 2031 iir = CSR_READ_1(regsp, COM_REG_IIR); 2032 2033 /* Handle ns16750-specific busy interrupt. */ 2034 if (sc->sc_type == COM_TYPE_16750 && 2035 (iir & IIR_BUSY) == IIR_BUSY) { 2036 for (int timeout = 10000; 2037 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2038 if (timeout <= 0) { 2039 aprint_error_dev(sc->sc_dev, 2040 "timeout while waiting for BUSY interrupt " 2041 "acknowledge\n"); 2042 mutex_spin_exit(&sc->sc_lock); 2043 return (0); 2044 } 2045 2046 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2047 iir = CSR_READ_1(regsp, COM_REG_IIR); 2048 } 2049 2050 /* Allwinner BUSY interrupt */ 2051 if (sc->sc_type == COM_TYPE_SUNXI && 2052 (iir & IIR_BUSY) == IIR_BUSY) { 2053 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2054 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2055 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2056 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2057 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2058 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2059 CSR_WRITE_1(regsp, COM_REG_HALT, 2060 HALT_CHCFG_EN | HALT_CHCFG_UD); 2061 for (int timeout = 10000000; 2062 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2063 timeout--) { 2064 if (timeout <= 0) { 2065 aprint_error_dev(sc->sc_dev, 2066 "timeout while waiting for HALT " 2067 "update acknowledge 0x%x 0x%x\n", 2068 CSR_READ_1(regsp, COM_REG_HALT), 2069 CSR_READ_1(regsp, COM_REG_USR)); 2070 break; 2071 } 2072 } 2073 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2074 (void)CSR_READ_1(regsp, COM_REG_USR); 2075 } else { 2076 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2077 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2078 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2079 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2080 } 2081 } 2082 2083 if (ISSET(iir, IIR_NOPEND)) { 2084 mutex_spin_exit(&sc->sc_lock); 2085 return (0); 2086 } 2087 2088 end = sc->sc_ebuf; 2089 put = sc->sc_rbput; 2090 cc = sc->sc_rbavail; 2091 2092 again: do { 2093 u_char msr, delta; 2094 2095 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2096 if (ISSET(lsr, LSR_BI)) { 2097 int cn_trapped = 0; /* see above: cn_trap() */ 2098 2099 cn_check_magic(sc->sc_tty->t_dev, 2100 CNC_BREAK, com_cnm_state); 2101 if (cn_trapped) 2102 continue; 2103 #if defined(KGDB) && !defined(DDB) 2104 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2105 kgdb_connect(1); 2106 continue; 2107 } 2108 #endif 2109 } 2110 2111 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2112 lsr |= LSR_RXRDY; 2113 2114 if (ISSET(lsr, LSR_RCV_MASK) && 2115 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2116 while (cc > 0) { 2117 int cn_trapped = 0; 2118 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2119 put[1] = lsr; 2120 cn_check_magic(sc->sc_tty->t_dev, 2121 put[0], com_cnm_state); 2122 if (cn_trapped) 2123 goto next; 2124 put += 2; 2125 if (put >= end) 2126 put = sc->sc_rbuf; 2127 cc--; 2128 next: 2129 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2130 if (!ISSET(lsr, LSR_RCV_MASK)) 2131 break; 2132 } 2133 2134 /* 2135 * Current string of incoming characters ended because 2136 * no more data was available or we ran out of space. 2137 * Schedule a receive event if any data was received. 2138 * If we're out of space, turn off receive interrupts. 2139 */ 2140 sc->sc_rbput = put; 2141 sc->sc_rbavail = cc; 2142 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2143 sc->sc_rx_ready = 1; 2144 2145 /* 2146 * See if we are in danger of overflowing a buffer. If 2147 * so, use hardware flow control to ease the pressure. 2148 */ 2149 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2150 cc < sc->sc_r_hiwat) { 2151 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2152 com_hwiflow(sc); 2153 } 2154 2155 /* 2156 * If we're out of space, disable receive interrupts 2157 * until the queue has drained a bit. 2158 */ 2159 if (!cc) { 2160 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2161 switch (sc->sc_type) { 2162 case COM_TYPE_PXA2x0: 2163 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2164 break; 2165 case COM_TYPE_INGENIC: 2166 case COM_TYPE_TEGRA: 2167 CLR(sc->sc_ier, 2168 IER_ERXRDY | IER_ERXTOUT); 2169 break; 2170 default: 2171 CLR(sc->sc_ier, IER_ERXRDY); 2172 break; 2173 } 2174 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2175 } 2176 } else { 2177 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2178 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2179 continue; 2180 } 2181 } 2182 2183 msr = CSR_READ_1(regsp, COM_REG_MSR); 2184 delta = msr ^ sc->sc_msr; 2185 sc->sc_msr = msr; 2186 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2187 (delta & MSR_DCD)) { 2188 mutex_spin_enter(&timecounter_lock); 2189 pps_capture(&sc->sc_pps_state); 2190 pps_event(&sc->sc_pps_state, 2191 (msr & MSR_DCD) ? 2192 PPS_CAPTUREASSERT : 2193 PPS_CAPTURECLEAR); 2194 mutex_spin_exit(&timecounter_lock); 2195 } 2196 2197 /* 2198 * Process normal status changes 2199 */ 2200 if (ISSET(delta, sc->sc_msr_mask)) { 2201 SET(sc->sc_msr_delta, delta); 2202 2203 /* 2204 * Stop output immediately if we lose the output 2205 * flow control signal or carrier detect. 2206 */ 2207 if (ISSET(~msr, sc->sc_msr_mask)) { 2208 sc->sc_tbc = 0; 2209 sc->sc_heldtbc = 0; 2210 #ifdef COM_DEBUG 2211 if (com_debug) 2212 comstatus(sc, "comintr "); 2213 #endif 2214 } 2215 2216 sc->sc_st_check = 1; 2217 } 2218 } while (!ISSET((iir = 2219 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2220 /* 2221 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2222 * by IIR read, so we can't do this way: `process all interrupts, 2223 * then do TX if possible'. 2224 */ 2225 (iir & IIR_IMASK) != IIR_TXRDY); 2226 2227 /* 2228 * Read LSR again, since there may be an interrupt between 2229 * the last LSR read and IIR read above. 2230 */ 2231 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2232 2233 /* 2234 * See if data can be transmitted as well. 2235 * Schedule tx done event if no data left 2236 * and tty was marked busy. 2237 */ 2238 if (ISSET(lsr, LSR_TXRDY)) { 2239 /* 2240 * If we've delayed a parameter change, do it now, and restart 2241 * output. 2242 */ 2243 if (sc->sc_heldchange) { 2244 com_loadchannelregs(sc); 2245 sc->sc_heldchange = 0; 2246 sc->sc_tbc = sc->sc_heldtbc; 2247 sc->sc_heldtbc = 0; 2248 } 2249 2250 /* Output the next chunk of the contiguous buffer, if any. */ 2251 if (sc->sc_tbc > 0) { 2252 u_int n; 2253 2254 n = sc->sc_tbc; 2255 if (n > sc->sc_fifolen) 2256 n = sc->sc_fifolen; 2257 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2258 sc->sc_tbc -= n; 2259 sc->sc_tba += n; 2260 } else { 2261 /* Disable transmit completion interrupts if necessary. */ 2262 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2263 CLR(sc->sc_ier, IER_ETXRDY); 2264 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2265 } 2266 if (sc->sc_tx_busy) { 2267 sc->sc_tx_busy = 0; 2268 sc->sc_tx_done = 1; 2269 } 2270 } 2271 } 2272 2273 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2274 goto again; 2275 2276 mutex_spin_exit(&sc->sc_lock); 2277 2278 /* Wake up the poller. */ 2279 softint_schedule(sc->sc_si); 2280 2281 #ifdef RND_COM 2282 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2283 #endif 2284 2285 return (1); 2286 } 2287 2288 /* 2289 * The following functions are polled getc and putc routines, shared 2290 * by the console and kgdb glue. 2291 * 2292 * The read-ahead code is so that you can detect pending in-band 2293 * cn_magic in polled mode while doing output rather than having to 2294 * wait until the kernel decides it needs input. 2295 */ 2296 2297 #define MAX_READAHEAD 20 2298 static int com_readahead[MAX_READAHEAD]; 2299 static int com_readaheadcount = 0; 2300 2301 int 2302 com_common_getc(dev_t dev, struct com_regs *regsp) 2303 { 2304 int s = splserial(); 2305 u_char stat, c; 2306 2307 /* got a character from reading things earlier */ 2308 if (com_readaheadcount > 0) { 2309 int i; 2310 2311 c = com_readahead[0]; 2312 for (i = 1; i < com_readaheadcount; i++) { 2313 com_readahead[i-1] = com_readahead[i]; 2314 } 2315 com_readaheadcount--; 2316 splx(s); 2317 return (c); 2318 } 2319 2320 /* don't block until a character becomes available */ 2321 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2322 splx(s); 2323 return -1; 2324 } 2325 2326 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2327 stat = CSR_READ_1(regsp, COM_REG_IIR); 2328 { 2329 int cn_trapped = 0; /* required by cn_trap, see above */ 2330 #ifdef DDB 2331 extern int db_active; 2332 if (!db_active) 2333 #endif 2334 cn_check_magic(dev, c, com_cnm_state); 2335 } 2336 splx(s); 2337 return (c); 2338 } 2339 2340 static void 2341 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2342 { 2343 int s = splserial(); 2344 int cin, stat, timo; 2345 2346 if (com_readaheadcount < MAX_READAHEAD 2347 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2348 int cn_trapped = 0; 2349 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2350 stat = CSR_READ_1(regsp, COM_REG_IIR); 2351 cn_check_magic(dev, cin, com_cnm_state); 2352 com_readahead[com_readaheadcount++] = cin; 2353 } 2354 2355 /* wait for any pending transmission to finish */ 2356 timo = 150000; 2357 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2358 continue; 2359 2360 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2361 COM_BARRIER(regsp, BR | BW); 2362 2363 splx(s); 2364 } 2365 2366 /* 2367 * Initialize UART for use as console or KGDB line. 2368 */ 2369 int 2370 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2371 tcflag_t cflag) 2372 { 2373 2374 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2375 ®sp->cr_ioh)) 2376 return (ENOMEM); /* ??? */ 2377 2378 if (type == COM_TYPE_OMAP) { 2379 /* disable before changing settings */ 2380 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2381 } 2382 2383 rate = comspeed(rate, frequency, type); 2384 if (__predict_true(rate != -1)) { 2385 if (type == COM_TYPE_AU1x00) { 2386 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2387 } else { 2388 /* no EFR on alchemy */ 2389 if ((type != COM_TYPE_16550_NOERS) && 2390 (type != COM_TYPE_INGENIC)) { 2391 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2392 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2393 } 2394 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2395 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2396 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2397 } 2398 } 2399 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2400 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2401 2402 if (type == COM_TYPE_INGENIC) { 2403 CSR_WRITE_1(regsp, COM_REG_FIFO, 2404 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2405 FIFO_TRIGGER_1 | FIFO_UART_ON); 2406 } else { 2407 CSR_WRITE_1(regsp, COM_REG_FIFO, 2408 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2409 FIFO_TRIGGER_1); 2410 } 2411 2412 if (type == COM_TYPE_OMAP) { 2413 /* setup the fifos. the FCR value is not used as long 2414 as SCR[6] and SCR[7] are 0, which they are at reset 2415 and we never touch the SCR register */ 2416 uint8_t rx_fifo_trig = 40; 2417 uint8_t tx_fifo_trig = 60; 2418 uint8_t rx_start = 8; 2419 uint8_t rx_halt = 60; 2420 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2421 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2422 2423 /* enable access to TCR & TLR */ 2424 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2425 2426 /* write tcr and tlr values */ 2427 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2428 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2429 2430 /* disable access to TCR & TLR */ 2431 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2432 2433 /* enable again, but mode is based on speed */ 2434 if (rate > 230400) { 2435 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2436 } else { 2437 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2438 } 2439 } 2440 2441 if (type == COM_TYPE_PXA2x0) 2442 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2443 else 2444 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2445 2446 return (0); 2447 } 2448 2449 int 2450 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2451 tcflag_t cflag) 2452 { 2453 int res; 2454 2455 comcons_info.regs = *regsp; 2456 2457 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2458 if (res) 2459 return (res); 2460 2461 cn_tab = &comcons; 2462 cn_init_magic(&com_cnm_state); 2463 cn_set_magic("\047\001"); /* default magic is BREAK */ 2464 2465 comcons_info.frequency = frequency; 2466 comcons_info.type = type; 2467 comcons_info.rate = rate; 2468 comcons_info.cflag = cflag; 2469 2470 return (0); 2471 } 2472 2473 int 2474 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2475 int type, tcflag_t cflag) 2476 { 2477 struct com_regs regs; 2478 2479 memset(®s, 0, sizeof regs); 2480 regs.cr_iot = iot; 2481 regs.cr_iobase = iobase; 2482 regs.cr_nports = COM_NPORTS; 2483 #ifdef COM_REGMAP 2484 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2485 #endif 2486 2487 return comcnattach1(®s, rate, frequency, type, cflag); 2488 } 2489 2490 static int 2491 comcnreattach(void) 2492 { 2493 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2494 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2495 } 2496 2497 int 2498 comcngetc(dev_t dev) 2499 { 2500 2501 return (com_common_getc(dev, &comcons_info.regs)); 2502 } 2503 2504 /* 2505 * Console kernel output character routine. 2506 */ 2507 void 2508 comcnputc(dev_t dev, int c) 2509 { 2510 2511 com_common_putc(dev, &comcons_info.regs, c); 2512 } 2513 2514 void 2515 comcnpollc(dev_t dev, int on) 2516 { 2517 2518 com_readaheadcount = 0; 2519 } 2520 2521 #ifdef KGDB 2522 int 2523 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2524 tcflag_t cflag) 2525 { 2526 int res; 2527 2528 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2529 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2530 #if !defined(DDB) 2531 return (EBUSY); /* cannot share with console */ 2532 #else 2533 comkgdbregs = *regsp; 2534 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2535 #endif 2536 } else { 2537 comkgdbregs = *regsp; 2538 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2539 if (res) 2540 return (res); 2541 2542 /* 2543 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2544 * expects this to be initialized 2545 */ 2546 cn_init_magic(&com_cnm_state); 2547 cn_set_magic("\047\001"); 2548 } 2549 2550 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2551 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2552 2553 return (0); 2554 } 2555 2556 int 2557 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2558 int frequency, int type, tcflag_t cflag) 2559 { 2560 struct com_regs regs; 2561 2562 regs.cr_iot = iot; 2563 regs.cr_nports = COM_NPORTS; 2564 regs.cr_iobase = iobase; 2565 #ifdef COM_REGMAP 2566 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2567 #endif 2568 2569 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2570 } 2571 2572 /* ARGSUSED */ 2573 int 2574 com_kgdb_getc(void *arg) 2575 { 2576 2577 return (com_common_getc(NODEV, &comkgdbregs)); 2578 } 2579 2580 /* ARGSUSED */ 2581 void 2582 com_kgdb_putc(void *arg, int c) 2583 { 2584 2585 com_common_putc(NODEV, &comkgdbregs, c); 2586 } 2587 #endif /* KGDB */ 2588 2589 /* helper function to identify the com ports used by 2590 console or KGDB (and not yet autoconf attached) */ 2591 int 2592 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2593 { 2594 bus_space_handle_t help; 2595 2596 if (!comconsattached && 2597 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2598 iobase == comcons_info.regs.cr_iobase) 2599 help = comcons_info.regs.cr_ioh; 2600 #ifdef KGDB 2601 else if (!com_kgdb_attached && 2602 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2603 iobase == comkgdbregs.cr_iobase) 2604 help = comkgdbregs.cr_ioh; 2605 #endif 2606 else 2607 return (0); 2608 2609 if (ioh) 2610 *ioh = help; 2611 return (1); 2612 } 2613 2614 /* 2615 * this routine exists to serve as a shutdown hook for systems that 2616 * have firmware which doesn't interact properly with a com device in 2617 * FIFO mode. 2618 */ 2619 bool 2620 com_cleanup(device_t self, int how) 2621 { 2622 struct com_softc *sc = device_private(self); 2623 2624 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2625 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2626 2627 return true; 2628 } 2629 2630 bool 2631 com_suspend(device_t self, const pmf_qual_t *qual) 2632 { 2633 struct com_softc *sc = device_private(self); 2634 2635 #if 0 2636 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2637 cn_tab = &comcons_suspend; 2638 #endif 2639 2640 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2641 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2642 2643 return true; 2644 } 2645 2646 bool 2647 com_resume(device_t self, const pmf_qual_t *qual) 2648 { 2649 struct com_softc *sc = device_private(self); 2650 2651 mutex_spin_enter(&sc->sc_lock); 2652 com_loadchannelregs(sc); 2653 mutex_spin_exit(&sc->sc_lock); 2654 2655 return true; 2656 } 2657
Indexes created Thu Sep 25 08:09:54 GMT 2025