com.c revision 1.346.2.4
1 /* $NetBSD: com.c,v 1.346.2.4 2019/01/18 08:50:26 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.346.2.4 2019/01/18 08:50:26 pgoyette Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #define CSR_WRITE_1(r, o, v) \ 132 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 133 #define CSR_READ_1(r, o) \ 134 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 135 #define CSR_WRITE_2(r, o, v) \ 136 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 137 #define CSR_READ_2(r, o) \ 138 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 139 #define CSR_WRITE_MULTI(r, o, p, n) \ 140 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 141 142 143 static void com_enable_debugport(struct com_softc *); 144 145 void com_config(struct com_softc *); 146 void com_shutdown(struct com_softc *); 147 int comspeed(long, long, int); 148 static u_char cflag2lcr(tcflag_t); 149 int comparam(struct tty *, struct termios *); 150 void comstart(struct tty *); 151 int comhwiflow(struct tty *, int); 152 153 void com_loadchannelregs(struct com_softc *); 154 void com_hwiflow(struct com_softc *); 155 void com_break(struct com_softc *, int); 156 void com_modem(struct com_softc *, int); 157 void tiocm_to_com(struct com_softc *, u_long, int); 158 int com_to_tiocm(struct com_softc *); 159 void com_iflush(struct com_softc *); 160 161 int com_common_getc(dev_t, struct com_regs *); 162 static void com_common_putc(dev_t, struct com_regs *, int); 163 164 int cominit(struct com_regs *, int, int, int, tcflag_t); 165 166 static int comcnreattach(void); 167 168 int comcngetc(dev_t); 169 void comcnputc(dev_t, int); 170 void comcnpollc(dev_t, int); 171 172 #define integrate static inline 173 void comsoft(void *); 174 integrate void com_rxsoft(struct com_softc *, struct tty *); 175 integrate void com_txsoft(struct com_softc *, struct tty *); 176 integrate void com_stsoft(struct com_softc *, struct tty *); 177 integrate void com_schedrx(struct com_softc *); 178 void comdiag(void *); 179 180 dev_type_open(comopen); 181 dev_type_close(comclose); 182 dev_type_read(comread); 183 dev_type_write(comwrite); 184 dev_type_ioctl(comioctl); 185 dev_type_stop(comstop); 186 dev_type_tty(comtty); 187 dev_type_poll(compoll); 188 189 static struct comcons_info comcons_info; 190 191 /* 192 * Following are all routines needed for COM to act as console 193 */ 194 static struct consdev comcons = { 195 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 196 NODEV, CN_NORMAL 197 }; 198 199 200 const struct cdevsw com_cdevsw = { 201 .d_open = comopen, 202 .d_close = comclose, 203 .d_read = comread, 204 .d_write = comwrite, 205 .d_ioctl = comioctl, 206 .d_stop = comstop, 207 .d_tty = comtty, 208 .d_poll = compoll, 209 .d_mmap = nommap, 210 .d_kqfilter = ttykqfilter, 211 .d_discard = nodiscard, 212 .d_flag = D_TTY 213 }; 214 215 /* 216 * Make this an option variable one can patch. 217 * But be warned: this must be a power of 2! 218 */ 219 u_int com_rbuf_size = COM_RING_SIZE; 220 221 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 222 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 223 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 224 225 static int comconsattached; 226 static struct cnm_state com_cnm_state; 227 228 #ifdef KGDB 229 #include <sys/kgdb.h> 230 231 static struct com_regs comkgdbregs; 232 static int com_kgdb_attached; 233 234 int com_kgdb_getc(void *); 235 void com_kgdb_putc(void *, int); 236 #endif /* KGDB */ 237 238 /* initializer for typical 16550-ish hardware */ 239 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 240 [COM_REG_RXDATA] = com_data, 241 [COM_REG_TXDATA] = com_data, 242 [COM_REG_DLBL] = com_dlbl, 243 [COM_REG_DLBH] = com_dlbh, 244 [COM_REG_IER] = com_ier, 245 [COM_REG_IIR] = com_iir, 246 [COM_REG_FIFO] = com_fifo, 247 [COM_REG_TCR] = com_fifo, 248 [COM_REG_EFR] = com_efr, 249 [COM_REG_TLR] = com_efr, 250 [COM_REG_LCR] = com_lcr, 251 [COM_REG_MCR] = com_mcr, 252 [COM_REG_LSR] = com_lsr, 253 [COM_REG_MSR] = com_msr, 254 [COM_REG_USR] = com_usr, 255 [COM_REG_TFL] = com_tfl, 256 [COM_REG_RFL] = com_rfl, 257 [COM_REG_HALT] = com_halt, 258 [COM_REG_MDR1] = com_mdr1, 259 }; 260 261 #define COMDIALOUT_MASK TTDIALOUT_MASK 262 263 #define COMUNIT(x) TTUNIT(x) 264 #define COMDIALOUT(x) TTDIALOUT(x) 265 266 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 267 device_is_active((sc)->sc_dev)) 268 269 #define BR BUS_SPACE_BARRIER_READ 270 #define BW BUS_SPACE_BARRIER_WRITE 271 #define COM_BARRIER(r, f) \ 272 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 273 274 /* 275 * com_init_regs -- 276 * Driver front-ends use this to initialize our register map 277 * in the standard fashion. They may then tailor the map to 278 * their own particular requirements. 279 */ 280 void 281 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 282 bus_addr_t addr) 283 { 284 285 memset(regs, 0, sizeof(*regs)); 286 regs->cr_iot = st; 287 regs->cr_ioh = sh; 288 regs->cr_iobase = addr; 289 regs->cr_nports = COM_NPORTS; 290 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 291 } 292 293 /* 294 * com_init_regs_stride -- 295 * Convenience function for front-ends that have a stride between 296 * registers. 297 */ 298 void 299 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 300 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 301 { 302 303 com_init_regs(regs, st, sh, addr); 304 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 305 regs->cr_map[i] <<= regshift; 306 } 307 regs->cr_nports <<= regshift; 308 } 309 310 /*ARGSUSED*/ 311 int 312 comspeed(long speed, long frequency, int type) 313 { 314 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 315 316 int x, err; 317 int divisor = 16; 318 319 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 320 divisor = 13; 321 } 322 323 if (speed == 0) 324 return (0); 325 if (speed < 0) 326 return (-1); 327 x = divrnd(frequency / divisor, speed); 328 if (x <= 0) 329 return (-1); 330 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 331 if (err < 0) 332 err = -err; 333 if (err > COM_TOLERANCE) 334 return (-1); 335 return (x); 336 337 #undef divrnd 338 } 339 340 #ifdef COM_DEBUG 341 int com_debug = 0; 342 343 void comstatus(struct com_softc *, const char *); 344 void 345 comstatus(struct com_softc *sc, const char *str) 346 { 347 struct tty *tp = sc->sc_tty; 348 349 aprint_normal_dev(sc->sc_dev, 350 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 351 str, 352 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 353 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 354 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 355 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 356 sc->sc_tx_stopped ? '+' : '-'); 357 358 aprint_normal_dev(sc->sc_dev, 359 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 360 str, 361 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 362 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 363 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 364 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 365 sc->sc_rx_flags); 366 } 367 #endif 368 369 int 370 com_probe_subr(struct com_regs *regs) 371 { 372 373 /* force access to id reg */ 374 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 375 CSR_WRITE_1(regs, COM_REG_IIR, 0); 376 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 377 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 378 return (0); 379 380 return (1); 381 } 382 383 int 384 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 385 { 386 struct com_regs regs; 387 388 com_init_regs(®s, iot, ioh, 0/*XXX*/); 389 390 return com_probe_subr(®s); 391 } 392 393 /* 394 * No locking in this routine; it is only called during attach, 395 * or with the port already locked. 396 */ 397 static void 398 com_enable_debugport(struct com_softc *sc) 399 { 400 401 /* Turn on line break interrupt, set carrier. */ 402 sc->sc_ier = IER_ERLS; 403 if (sc->sc_type == COM_TYPE_PXA2x0) 404 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 405 if (sc->sc_type == COM_TYPE_INGENIC || 406 sc->sc_type == COM_TYPE_TEGRA) 407 sc->sc_ier |= IER_ERXTOUT; 408 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 409 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 410 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 411 } 412 413 static void 414 com_intr_poll(void *arg) 415 { 416 struct com_softc * const sc = arg; 417 418 comintr(sc); 419 420 callout_schedule(&sc->sc_poll_callout, 1); 421 } 422 423 void 424 com_attach_subr(struct com_softc *sc) 425 { 426 struct com_regs *regsp = &sc->sc_regs; 427 struct tty *tp; 428 u_int8_t lcr; 429 const char *fifo_msg = NULL; 430 prop_dictionary_t dict; 431 bool is_console = true; 432 bool force_console = false; 433 434 aprint_naive("\n"); 435 436 dict = device_properties(sc->sc_dev); 437 prop_dictionary_get_bool(dict, "is_console", &is_console); 438 prop_dictionary_get_bool(dict, "force_console", &force_console); 439 callout_init(&sc->sc_diag_callout, 0); 440 callout_init(&sc->sc_poll_callout, 0); 441 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 442 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 443 444 #if defined(COM_16650) 445 sc->sc_type = COM_TYPE_16650; 446 #elif defined(COM_16750) 447 sc->sc_type = COM_TYPE_16750; 448 #elif defined(COM_HAYESP) 449 sc->sc_type = COM_TYPE_HAYESP; 450 #elif defined(COM_PXA2X0) 451 sc->sc_type = COM_TYPE_PXA2x0; 452 #endif 453 454 /* Disable interrupts before configuring the device. */ 455 if (sc->sc_type == COM_TYPE_PXA2x0) 456 sc->sc_ier = IER_EUART; 457 else 458 sc->sc_ier = 0; 459 460 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 461 462 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 463 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 464 comconsattached = 1; 465 466 if (force_console) 467 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 468 469 if (cn_tab == NULL && comcnreattach() != 0) { 470 printf("can't re-init serial console @%lx\n", 471 (u_long)comcons_info.regs.cr_iobase); 472 } 473 474 switch (sc->sc_type) { 475 case COM_TYPE_16750: 476 case COM_TYPE_DW_APB: 477 /* Use in comintr(). */ 478 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 479 break; 480 } 481 482 /* Make sure the console is always "hardwired". */ 483 delay(10000); /* wait for output to finish */ 484 if (is_console) { 485 SET(sc->sc_hwflags, COM_HW_CONSOLE); 486 } 487 488 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 489 } 490 491 /* Probe for FIFO */ 492 switch (sc->sc_type) { 493 case COM_TYPE_HAYESP: 494 goto fifodone; 495 496 case COM_TYPE_AU1x00: 497 sc->sc_fifolen = 16; 498 fifo_msg = "Au1X00 UART, working fifo"; 499 SET(sc->sc_hwflags, COM_HW_FIFO); 500 goto fifodelay; 501 502 case COM_TYPE_16550_NOERS: 503 sc->sc_fifolen = 16; 504 fifo_msg = "ns16650, no ERS, working fifo"; 505 SET(sc->sc_hwflags, COM_HW_FIFO); 506 goto fifodelay; 507 508 case COM_TYPE_OMAP: 509 sc->sc_fifolen = 64; 510 fifo_msg = "OMAP UART, working fifo"; 511 SET(sc->sc_hwflags, COM_HW_FIFO); 512 goto fifodelay; 513 514 case COM_TYPE_INGENIC: 515 sc->sc_fifolen = 16; 516 fifo_msg = "Ingenic UART, working fifo"; 517 SET(sc->sc_hwflags, COM_HW_FIFO); 518 SET(sc->sc_hwflags, COM_HW_NOIEN); 519 goto fifodelay; 520 521 case COM_TYPE_TEGRA: 522 sc->sc_fifolen = 8; 523 fifo_msg = "Tegra UART, working fifo"; 524 SET(sc->sc_hwflags, COM_HW_FIFO); 525 CSR_WRITE_1(regsp, COM_REG_FIFO, 526 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 527 goto fifodelay; 528 529 case COM_TYPE_BCMAUXUART: 530 sc->sc_fifolen = 1; 531 fifo_msg = "BCM AUX UART, working fifo"; 532 SET(sc->sc_hwflags, COM_HW_FIFO); 533 CSR_WRITE_1(regsp, COM_REG_FIFO, 534 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 535 goto fifodelay; 536 } 537 538 sc->sc_fifolen = 1; 539 /* look for a NS 16550AF UART with FIFOs */ 540 if (sc->sc_type == COM_TYPE_INGENIC) { 541 CSR_WRITE_1(regsp, COM_REG_FIFO, 542 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 543 FIFO_TRIGGER_14 | FIFO_UART_ON); 544 } else 545 CSR_WRITE_1(regsp, COM_REG_FIFO, 546 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 547 delay(100); 548 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 549 == IIR_FIFO_MASK) 550 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 551 == FIFO_TRIGGER_14) { 552 SET(sc->sc_hwflags, COM_HW_FIFO); 553 554 fifo_msg = "ns16550a, working fifo"; 555 556 /* 557 * IIR changes into the EFR if LCR is set to LCR_EERS 558 * on 16650s. We also know IIR != 0 at this point. 559 * Write 0 into the EFR, and read it. If the result 560 * is 0, we have a 16650. 561 * 562 * Older 16650s were broken; the test to detect them 563 * is taken from the Linux driver. Apparently 564 * setting DLAB enable gives access to the EFR on 565 * these chips. 566 */ 567 if (sc->sc_type == COM_TYPE_16650) { 568 lcr = CSR_READ_1(regsp, COM_REG_LCR); 569 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 570 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 571 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 572 CSR_WRITE_1(regsp, COM_REG_LCR, 573 lcr | LCR_DLAB); 574 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 575 CLR(sc->sc_hwflags, COM_HW_FIFO); 576 sc->sc_fifolen = 0; 577 } else { 578 SET(sc->sc_hwflags, COM_HW_FLOW); 579 sc->sc_fifolen = 32; 580 } 581 } else 582 sc->sc_fifolen = 16; 583 584 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 585 if (sc->sc_fifolen == 0) 586 fifo_msg = "st16650, broken fifo"; 587 else if (sc->sc_fifolen == 32) 588 fifo_msg = "st16650a, working fifo"; 589 else 590 fifo_msg = "ns16550a, working fifo"; 591 } 592 593 /* 594 * TL16C750 can enable 64byte FIFO, only when DLAB 595 * is 1. However, some 16750 may always enable. For 596 * example, restrictions according to DLAB in a data 597 * sheet for SC16C750 were not described. 598 * Please enable 'options COM_16650', supposing you 599 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 600 * should become effective. 601 */ 602 if (sc->sc_type == COM_TYPE_16750) { 603 uint8_t iir1, iir2; 604 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 605 606 lcr = CSR_READ_1(regsp, COM_REG_LCR); 607 CSR_WRITE_1(regsp, COM_REG_LCR, 608 lcr & ~LCR_DLAB); 609 CSR_WRITE_1(regsp, COM_REG_FIFO, 610 fcr | FIFO_64B_ENABLE); 611 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 612 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 613 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 614 CSR_WRITE_1(regsp, COM_REG_FIFO, 615 fcr | FIFO_64B_ENABLE); 616 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 617 618 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 619 620 if (!ISSET(iir1, IIR_64B_FIFO) && 621 ISSET(iir2, IIR_64B_FIFO)) { 622 /* It is TL16C750. */ 623 sc->sc_fifolen = 64; 624 SET(sc->sc_hwflags, COM_HW_AFE); 625 } else 626 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 627 628 if (sc->sc_fifolen == 64) 629 fifo_msg = "tl16c750, working fifo"; 630 else 631 fifo_msg = "ns16750, working fifo"; 632 } 633 } else 634 fifo_msg = "ns16550, broken fifo"; 635 else 636 fifo_msg = "ns8250 or ns16450, no fifo"; 637 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 638 639 fifodelay: 640 /* 641 * Some chips will clear down both Tx and Rx FIFOs when zero is 642 * written to com_fifo. If this chip is the console, writing zero 643 * results in some of the chip/FIFO description being lost, so delay 644 * printing it until now. 645 */ 646 delay(10); 647 aprint_normal(": %s\n", fifo_msg); 648 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 649 sc->sc_fifolen = 1; 650 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 651 } 652 653 fifodone: 654 655 tp = tty_alloc(); 656 tp->t_oproc = comstart; 657 tp->t_param = comparam; 658 tp->t_hwiflow = comhwiflow; 659 tp->t_softc = sc; 660 661 sc->sc_tty = tp; 662 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 663 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 664 sc->sc_rbavail = com_rbuf_size; 665 if (sc->sc_rbuf == NULL) { 666 aprint_error_dev(sc->sc_dev, 667 "unable to allocate ring buffer\n"); 668 return; 669 } 670 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 671 672 tty_attach(tp); 673 674 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 675 SET(sc->sc_mcr, MCR_IENABLE); 676 677 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 678 int maj; 679 680 /* locate the major number */ 681 maj = cdevsw_lookup_major(&com_cdevsw); 682 683 tp->t_dev = cn_tab->cn_dev = makedev(maj, 684 device_unit(sc->sc_dev)); 685 686 aprint_normal_dev(sc->sc_dev, "console\n"); 687 } 688 689 #ifdef KGDB 690 /* 691 * Allow kgdb to "take over" this port. If this is 692 * not the console and is the kgdb device, it has 693 * exclusive use. If it's the console _and_ the 694 * kgdb device, it doesn't. 695 */ 696 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 697 regsp->cr_iobase == comkgdbregs.cr_iobase) { 698 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 699 com_kgdb_attached = 1; 700 701 SET(sc->sc_hwflags, COM_HW_KGDB); 702 } 703 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 704 } 705 #endif 706 707 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 708 709 #ifdef RND_COM 710 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 711 RND_TYPE_TTY, RND_FLAG_DEFAULT); 712 #endif 713 714 /* if there are no enable/disable functions, assume the device 715 is always enabled */ 716 if (!sc->enable) 717 sc->enabled = 1; 718 719 com_config(sc); 720 721 SET(sc->sc_hwflags, COM_HW_DEV_OK); 722 723 if (ISSET(sc->sc_hwflags, COM_HW_POLL)) 724 callout_schedule(&sc->sc_poll_callout, 1); 725 } 726 727 void 728 com_config(struct com_softc *sc) 729 { 730 struct com_regs *regsp = &sc->sc_regs; 731 732 /* Disable interrupts before configuring the device. */ 733 if (sc->sc_type == COM_TYPE_PXA2x0) 734 sc->sc_ier = IER_EUART; 735 else 736 sc->sc_ier = 0; 737 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 738 (void) CSR_READ_1(regsp, COM_REG_IIR); 739 740 /* Look for a Hayes ESP board. */ 741 if (sc->sc_type == COM_TYPE_HAYESP) { 742 743 /* Set 16550 compatibility mode */ 744 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 745 HAYESP_SETMODE); 746 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 747 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 748 HAYESP_MODE_SCALE); 749 750 /* Set RTS/CTS flow control */ 751 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 752 HAYESP_SETFLOWTYPE); 753 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 754 HAYESP_FLOW_RTS); 755 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 756 HAYESP_FLOW_CTS); 757 758 /* Set flow control levels */ 759 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 760 HAYESP_SETRXFLOW); 761 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 762 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 763 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 764 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 765 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 766 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 767 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 768 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 769 } 770 771 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 772 com_enable_debugport(sc); 773 } 774 775 #if 0 776 static int 777 comcngetc_detached(dev_t dev) 778 { 779 return 0; 780 } 781 782 static void 783 comcnputc_detached(dev_t dev, int c) 784 { 785 } 786 #endif 787 788 int 789 com_detach(device_t self, int flags) 790 { 791 struct com_softc *sc = device_private(self); 792 int maj, mn; 793 794 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 795 return EBUSY; 796 797 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 798 (flags & DETACH_SHUTDOWN) != 0) 799 return EBUSY; 800 801 if (sc->disable != NULL && sc->enabled != 0) { 802 (*sc->disable)(sc); 803 sc->enabled = 0; 804 } 805 806 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 807 comconsattached = 0; 808 cn_tab = NULL; 809 } 810 811 /* locate the major number */ 812 maj = cdevsw_lookup_major(&com_cdevsw); 813 814 /* Nuke the vnodes for any open instances. */ 815 mn = device_unit(self); 816 vdevgone(maj, mn, mn, VCHR); 817 818 mn |= COMDIALOUT_MASK; 819 vdevgone(maj, mn, mn, VCHR); 820 821 if (sc->sc_rbuf == NULL) { 822 /* 823 * Ring buffer allocation failed in the com_attach_subr, 824 * only the tty is allocated, and nothing else. 825 */ 826 tty_free(sc->sc_tty); 827 return 0; 828 } 829 830 /* Free the receive buffer. */ 831 free(sc->sc_rbuf, M_DEVBUF); 832 833 /* Detach and free the tty. */ 834 tty_detach(sc->sc_tty); 835 tty_free(sc->sc_tty); 836 837 /* Unhook the soft interrupt handler. */ 838 softint_disestablish(sc->sc_si); 839 840 #ifdef RND_COM 841 /* Unhook the entropy source. */ 842 rnd_detach_source(&sc->rnd_source); 843 #endif 844 callout_destroy(&sc->sc_diag_callout); 845 846 /* Destroy the lock. */ 847 mutex_destroy(&sc->sc_lock); 848 849 return (0); 850 } 851 852 void 853 com_shutdown(struct com_softc *sc) 854 { 855 struct tty *tp = sc->sc_tty; 856 857 mutex_spin_enter(&sc->sc_lock); 858 859 /* If we were asserting flow control, then deassert it. */ 860 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 861 com_hwiflow(sc); 862 863 /* Clear any break condition set with TIOCSBRK. */ 864 com_break(sc, 0); 865 866 /* 867 * Hang up if necessary. Wait a bit, so the other side has time to 868 * notice even if we immediately open the port again. 869 * Avoid tsleeping above splhigh(). 870 */ 871 if (ISSET(tp->t_cflag, HUPCL)) { 872 com_modem(sc, 0); 873 mutex_spin_exit(&sc->sc_lock); 874 /* XXX will only timeout */ 875 (void) kpause(ttclos, false, hz, NULL); 876 mutex_spin_enter(&sc->sc_lock); 877 } 878 879 /* Turn off interrupts. */ 880 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 881 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 882 if ((sc->sc_type == COM_TYPE_PXA2x0) || 883 (sc->sc_type == COM_TYPE_INGENIC) || 884 (sc->sc_type == COM_TYPE_TEGRA)) 885 sc->sc_ier |= IER_ERXTOUT; 886 } else 887 sc->sc_ier = 0; 888 889 if (sc->sc_type == COM_TYPE_PXA2x0) 890 sc->sc_ier |= IER_EUART; 891 892 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 893 894 mutex_spin_exit(&sc->sc_lock); 895 896 if (sc->disable) { 897 #ifdef DIAGNOSTIC 898 if (!sc->enabled) 899 panic("com_shutdown: not enabled?"); 900 #endif 901 (*sc->disable)(sc); 902 sc->enabled = 0; 903 } 904 } 905 906 int 907 comopen(dev_t dev, int flag, int mode, struct lwp *l) 908 { 909 struct com_softc *sc; 910 struct tty *tp; 911 int s; 912 int error; 913 914 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 915 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 916 sc->sc_rbuf == NULL) 917 return (ENXIO); 918 919 if (!device_is_active(sc->sc_dev)) 920 return (ENXIO); 921 922 #ifdef KGDB 923 /* 924 * If this is the kgdb port, no other use is permitted. 925 */ 926 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 927 return (EBUSY); 928 #endif 929 930 tp = sc->sc_tty; 931 932 /* 933 * If the device is exclusively for kernel use, deny userland 934 * open. 935 */ 936 if (ISSET(tp->t_state, TS_KERN_ONLY)) 937 return (EBUSY); 938 939 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 940 return (EBUSY); 941 942 s = spltty(); 943 944 /* 945 * Do the following iff this is a first open. 946 */ 947 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 948 struct termios t; 949 950 tp->t_dev = dev; 951 952 if (sc->enable) { 953 if ((*sc->enable)(sc)) { 954 splx(s); 955 aprint_error_dev(sc->sc_dev, 956 "device enable failed\n"); 957 return (EIO); 958 } 959 mutex_spin_enter(&sc->sc_lock); 960 sc->enabled = 1; 961 com_config(sc); 962 } else { 963 mutex_spin_enter(&sc->sc_lock); 964 } 965 966 /* Turn on interrupts. */ 967 sc->sc_ier = IER_ERXRDY | IER_ERLS; 968 if (!ISSET(tp->t_cflag, CLOCAL)) 969 sc->sc_ier |= IER_EMSC; 970 971 if (sc->sc_type == COM_TYPE_PXA2x0) 972 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 973 else if (sc->sc_type == COM_TYPE_INGENIC || 974 sc->sc_type == COM_TYPE_TEGRA) 975 sc->sc_ier |= IER_ERXTOUT; 976 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 977 978 /* Fetch the current modem control status, needed later. */ 979 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 980 981 /* Clear PPS capture state on first open. */ 982 mutex_spin_enter(&timecounter_lock); 983 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 984 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 985 pps_init(&sc->sc_pps_state); 986 mutex_spin_exit(&timecounter_lock); 987 988 mutex_spin_exit(&sc->sc_lock); 989 990 /* 991 * Initialize the termios status to the defaults. Add in the 992 * sticky bits from TIOCSFLAGS. 993 */ 994 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 995 t.c_ospeed = comcons_info.rate; 996 t.c_cflag = comcons_info.cflag; 997 } else { 998 t.c_ospeed = TTYDEF_SPEED; 999 t.c_cflag = TTYDEF_CFLAG; 1000 } 1001 t.c_ispeed = t.c_ospeed; 1002 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1003 SET(t.c_cflag, CLOCAL); 1004 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1005 SET(t.c_cflag, CRTSCTS); 1006 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1007 SET(t.c_cflag, MDMBUF); 1008 /* Make sure comparam() will do something. */ 1009 tp->t_ospeed = 0; 1010 (void) comparam(tp, &t); 1011 tp->t_iflag = TTYDEF_IFLAG; 1012 tp->t_oflag = TTYDEF_OFLAG; 1013 tp->t_lflag = TTYDEF_LFLAG; 1014 ttychars(tp); 1015 ttsetwater(tp); 1016 1017 mutex_spin_enter(&sc->sc_lock); 1018 1019 /* 1020 * Turn on DTR. We must always do this, even if carrier is not 1021 * present, because otherwise we'd have to use TIOCSDTR 1022 * immediately after setting CLOCAL, which applications do not 1023 * expect. We always assert DTR while the device is open 1024 * unless explicitly requested to deassert it. 1025 */ 1026 com_modem(sc, 1); 1027 1028 /* Clear the input ring, and unblock. */ 1029 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1030 sc->sc_rbavail = com_rbuf_size; 1031 com_iflush(sc); 1032 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1033 com_hwiflow(sc); 1034 1035 #ifdef COM_DEBUG 1036 if (com_debug) 1037 comstatus(sc, "comopen "); 1038 #endif 1039 1040 mutex_spin_exit(&sc->sc_lock); 1041 } 1042 1043 splx(s); 1044 1045 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1046 if (error) 1047 goto bad; 1048 1049 error = (*tp->t_linesw->l_open)(dev, tp); 1050 if (error) 1051 goto bad; 1052 1053 return (0); 1054 1055 bad: 1056 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1057 /* 1058 * We failed to open the device, and nobody else had it opened. 1059 * Clean up the state as appropriate. 1060 */ 1061 com_shutdown(sc); 1062 } 1063 1064 return (error); 1065 } 1066 1067 int 1068 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1069 { 1070 struct com_softc *sc = 1071 device_lookup_private(&com_cd, COMUNIT(dev)); 1072 struct tty *tp = sc->sc_tty; 1073 1074 /* XXX This is for cons.c. */ 1075 if (!ISSET(tp->t_state, TS_ISOPEN)) 1076 return (0); 1077 /* 1078 * If the device is exclusively for kernel use, deny userland 1079 * close. 1080 */ 1081 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1082 return (0); 1083 1084 (*tp->t_linesw->l_close)(tp, flag); 1085 ttyclose(tp); 1086 1087 if (COM_ISALIVE(sc) == 0) 1088 return (0); 1089 1090 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1091 /* 1092 * Although we got a last close, the device may still be in 1093 * use; e.g. if this was the dialout node, and there are still 1094 * processes waiting for carrier on the non-dialout node. 1095 */ 1096 com_shutdown(sc); 1097 } 1098 1099 return (0); 1100 } 1101 1102 int 1103 comread(dev_t dev, struct uio *uio, int flag) 1104 { 1105 struct com_softc *sc = 1106 device_lookup_private(&com_cd, COMUNIT(dev)); 1107 struct tty *tp = sc->sc_tty; 1108 1109 if (COM_ISALIVE(sc) == 0) 1110 return (EIO); 1111 1112 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1113 } 1114 1115 int 1116 comwrite(dev_t dev, struct uio *uio, int flag) 1117 { 1118 struct com_softc *sc = 1119 device_lookup_private(&com_cd, COMUNIT(dev)); 1120 struct tty *tp = sc->sc_tty; 1121 1122 if (COM_ISALIVE(sc) == 0) 1123 return (EIO); 1124 1125 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1126 } 1127 1128 int 1129 compoll(dev_t dev, int events, struct lwp *l) 1130 { 1131 struct com_softc *sc = 1132 device_lookup_private(&com_cd, COMUNIT(dev)); 1133 struct tty *tp = sc->sc_tty; 1134 1135 if (COM_ISALIVE(sc) == 0) 1136 return (POLLHUP); 1137 1138 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1139 } 1140 1141 struct tty * 1142 comtty(dev_t dev) 1143 { 1144 struct com_softc *sc = 1145 device_lookup_private(&com_cd, COMUNIT(dev)); 1146 struct tty *tp = sc->sc_tty; 1147 1148 return (tp); 1149 } 1150 1151 int 1152 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1153 { 1154 struct com_softc *sc; 1155 struct tty *tp; 1156 int error; 1157 1158 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1159 if (sc == NULL) 1160 return ENXIO; 1161 if (COM_ISALIVE(sc) == 0) 1162 return (EIO); 1163 1164 tp = sc->sc_tty; 1165 1166 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1167 if (error != EPASSTHROUGH) 1168 return (error); 1169 1170 error = ttioctl(tp, cmd, data, flag, l); 1171 if (error != EPASSTHROUGH) 1172 return (error); 1173 1174 error = 0; 1175 switch (cmd) { 1176 case TIOCSFLAGS: 1177 error = kauth_authorize_device_tty(l->l_cred, 1178 KAUTH_DEVICE_TTY_PRIVSET, tp); 1179 break; 1180 default: 1181 /* nothing */ 1182 break; 1183 } 1184 if (error) { 1185 return error; 1186 } 1187 1188 mutex_spin_enter(&sc->sc_lock); 1189 1190 switch (cmd) { 1191 case TIOCSBRK: 1192 com_break(sc, 1); 1193 break; 1194 1195 case TIOCCBRK: 1196 com_break(sc, 0); 1197 break; 1198 1199 case TIOCSDTR: 1200 com_modem(sc, 1); 1201 break; 1202 1203 case TIOCCDTR: 1204 com_modem(sc, 0); 1205 break; 1206 1207 case TIOCGFLAGS: 1208 *(int *)data = sc->sc_swflags; 1209 break; 1210 1211 case TIOCSFLAGS: 1212 sc->sc_swflags = *(int *)data; 1213 break; 1214 1215 case TIOCMSET: 1216 case TIOCMBIS: 1217 case TIOCMBIC: 1218 tiocm_to_com(sc, cmd, *(int *)data); 1219 break; 1220 1221 case TIOCMGET: 1222 *(int *)data = com_to_tiocm(sc); 1223 break; 1224 1225 case PPS_IOC_CREATE: 1226 case PPS_IOC_DESTROY: 1227 case PPS_IOC_GETPARAMS: 1228 case PPS_IOC_SETPARAMS: 1229 case PPS_IOC_GETCAP: 1230 case PPS_IOC_FETCH: 1231 #ifdef PPS_SYNC 1232 case PPS_IOC_KCBIND: 1233 #endif 1234 mutex_spin_enter(&timecounter_lock); 1235 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1236 mutex_spin_exit(&timecounter_lock); 1237 break; 1238 1239 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1240 mutex_spin_enter(&timecounter_lock); 1241 #ifndef PPS_TRAILING_EDGE 1242 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1243 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1244 #else 1245 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1246 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1247 #endif 1248 mutex_spin_exit(&timecounter_lock); 1249 break; 1250 1251 default: 1252 error = EPASSTHROUGH; 1253 break; 1254 } 1255 1256 mutex_spin_exit(&sc->sc_lock); 1257 1258 #ifdef COM_DEBUG 1259 if (com_debug) 1260 comstatus(sc, "comioctl "); 1261 #endif 1262 1263 return (error); 1264 } 1265 1266 integrate void 1267 com_schedrx(struct com_softc *sc) 1268 { 1269 1270 sc->sc_rx_ready = 1; 1271 1272 /* Wake up the poller. */ 1273 softint_schedule(sc->sc_si); 1274 } 1275 1276 void 1277 com_break(struct com_softc *sc, int onoff) 1278 { 1279 1280 if (onoff) 1281 SET(sc->sc_lcr, LCR_SBREAK); 1282 else 1283 CLR(sc->sc_lcr, LCR_SBREAK); 1284 1285 if (!sc->sc_heldchange) { 1286 if (sc->sc_tx_busy) { 1287 sc->sc_heldtbc = sc->sc_tbc; 1288 sc->sc_tbc = 0; 1289 sc->sc_heldchange = 1; 1290 } else 1291 com_loadchannelregs(sc); 1292 } 1293 } 1294 1295 void 1296 com_modem(struct com_softc *sc, int onoff) 1297 { 1298 1299 if (sc->sc_mcr_dtr == 0) 1300 return; 1301 1302 if (onoff) 1303 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1304 else 1305 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1306 1307 if (!sc->sc_heldchange) { 1308 if (sc->sc_tx_busy) { 1309 sc->sc_heldtbc = sc->sc_tbc; 1310 sc->sc_tbc = 0; 1311 sc->sc_heldchange = 1; 1312 } else 1313 com_loadchannelregs(sc); 1314 } 1315 } 1316 1317 void 1318 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1319 { 1320 u_char combits; 1321 1322 combits = 0; 1323 if (ISSET(ttybits, TIOCM_DTR)) 1324 SET(combits, MCR_DTR); 1325 if (ISSET(ttybits, TIOCM_RTS)) 1326 SET(combits, MCR_RTS); 1327 1328 switch (how) { 1329 case TIOCMBIC: 1330 CLR(sc->sc_mcr, combits); 1331 break; 1332 1333 case TIOCMBIS: 1334 SET(sc->sc_mcr, combits); 1335 break; 1336 1337 case TIOCMSET: 1338 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1339 SET(sc->sc_mcr, combits); 1340 break; 1341 } 1342 1343 if (!sc->sc_heldchange) { 1344 if (sc->sc_tx_busy) { 1345 sc->sc_heldtbc = sc->sc_tbc; 1346 sc->sc_tbc = 0; 1347 sc->sc_heldchange = 1; 1348 } else 1349 com_loadchannelregs(sc); 1350 } 1351 } 1352 1353 int 1354 com_to_tiocm(struct com_softc *sc) 1355 { 1356 u_char combits; 1357 int ttybits = 0; 1358 1359 combits = sc->sc_mcr; 1360 if (ISSET(combits, MCR_DTR)) 1361 SET(ttybits, TIOCM_DTR); 1362 if (ISSET(combits, MCR_RTS)) 1363 SET(ttybits, TIOCM_RTS); 1364 1365 combits = sc->sc_msr; 1366 if (sc->sc_type == COM_TYPE_INGENIC) { 1367 SET(ttybits, TIOCM_CD); 1368 } else { 1369 if (ISSET(combits, MSR_DCD)) 1370 SET(ttybits, TIOCM_CD); 1371 } 1372 if (ISSET(combits, MSR_CTS)) 1373 SET(ttybits, TIOCM_CTS); 1374 if (ISSET(combits, MSR_DSR)) 1375 SET(ttybits, TIOCM_DSR); 1376 if (ISSET(combits, MSR_RI | MSR_TERI)) 1377 SET(ttybits, TIOCM_RI); 1378 1379 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1380 SET(ttybits, TIOCM_LE); 1381 1382 return (ttybits); 1383 } 1384 1385 static u_char 1386 cflag2lcr(tcflag_t cflag) 1387 { 1388 u_char lcr = 0; 1389 1390 switch (ISSET(cflag, CSIZE)) { 1391 case CS5: 1392 SET(lcr, LCR_5BITS); 1393 break; 1394 case CS6: 1395 SET(lcr, LCR_6BITS); 1396 break; 1397 case CS7: 1398 SET(lcr, LCR_7BITS); 1399 break; 1400 case CS8: 1401 SET(lcr, LCR_8BITS); 1402 break; 1403 } 1404 if (ISSET(cflag, PARENB)) { 1405 SET(lcr, LCR_PENAB); 1406 if (!ISSET(cflag, PARODD)) 1407 SET(lcr, LCR_PEVEN); 1408 } 1409 if (ISSET(cflag, CSTOPB)) 1410 SET(lcr, LCR_STOPB); 1411 1412 return (lcr); 1413 } 1414 1415 int 1416 comparam(struct tty *tp, struct termios *t) 1417 { 1418 struct com_softc *sc = 1419 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1420 int ospeed; 1421 u_char lcr; 1422 1423 if (COM_ISALIVE(sc) == 0) 1424 return (EIO); 1425 1426 if (sc->sc_type == COM_TYPE_HAYESP) { 1427 int prescaler, speed; 1428 1429 /* 1430 * Calculate UART clock prescaler. It should be in 1431 * range of 0 .. 3. 1432 */ 1433 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1434 prescaler++, speed /= 2) 1435 if ((ospeed = comspeed(speed, sc->sc_frequency, 1436 sc->sc_type)) > 0) 1437 break; 1438 1439 if (prescaler == 4) 1440 return (EINVAL); 1441 sc->sc_prescaler = prescaler; 1442 } else 1443 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1444 1445 /* Check requested parameters. */ 1446 if (ospeed < 0) 1447 return (EINVAL); 1448 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1449 return (EINVAL); 1450 1451 /* 1452 * For the console, always force CLOCAL and !HUPCL, so that the port 1453 * is always active. 1454 */ 1455 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1456 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1457 SET(t->c_cflag, CLOCAL); 1458 CLR(t->c_cflag, HUPCL); 1459 } 1460 1461 /* 1462 * If there were no changes, don't do anything. This avoids dropping 1463 * input and improves performance when all we did was frob things like 1464 * VMIN and VTIME. 1465 */ 1466 if (tp->t_ospeed == t->c_ospeed && 1467 tp->t_cflag == t->c_cflag) 1468 return (0); 1469 1470 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1471 1472 mutex_spin_enter(&sc->sc_lock); 1473 1474 sc->sc_lcr = lcr; 1475 1476 /* 1477 * If we're not in a mode that assumes a connection is present, then 1478 * ignore carrier changes. 1479 */ 1480 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1481 sc->sc_msr_dcd = 0; 1482 else 1483 sc->sc_msr_dcd = MSR_DCD; 1484 /* 1485 * Set the flow control pins depending on the current flow control 1486 * mode. 1487 */ 1488 if (ISSET(t->c_cflag, CRTSCTS)) { 1489 sc->sc_mcr_dtr = MCR_DTR; 1490 sc->sc_mcr_rts = MCR_RTS; 1491 sc->sc_msr_cts = MSR_CTS; 1492 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1493 SET(sc->sc_mcr, MCR_AFE); 1494 } else { 1495 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1496 } 1497 } else if (ISSET(t->c_cflag, MDMBUF)) { 1498 /* 1499 * For DTR/DCD flow control, make sure we don't toggle DTR for 1500 * carrier detection. 1501 */ 1502 sc->sc_mcr_dtr = 0; 1503 sc->sc_mcr_rts = MCR_DTR; 1504 sc->sc_msr_cts = MSR_DCD; 1505 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1506 CLR(sc->sc_mcr, MCR_AFE); 1507 } else { 1508 sc->sc_efr = 0; 1509 } 1510 } else { 1511 /* 1512 * If no flow control, then always set RTS. This will make 1513 * the other side happy if it mistakenly thinks we're doing 1514 * RTS/CTS flow control. 1515 */ 1516 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1517 sc->sc_mcr_rts = 0; 1518 sc->sc_msr_cts = 0; 1519 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1520 CLR(sc->sc_mcr, MCR_AFE); 1521 } else { 1522 sc->sc_efr = 0; 1523 } 1524 if (ISSET(sc->sc_mcr, MCR_DTR)) 1525 SET(sc->sc_mcr, MCR_RTS); 1526 else 1527 CLR(sc->sc_mcr, MCR_RTS); 1528 } 1529 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1530 1531 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1532 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1533 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1534 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1535 1536 sc->sc_dlbl = ospeed; 1537 sc->sc_dlbh = ospeed >> 8; 1538 1539 /* 1540 * Set the FIFO threshold based on the receive speed. 1541 * 1542 * * If it's a low speed, it's probably a mouse or some other 1543 * interactive device, so set the threshold low. 1544 * * If it's a high speed, trim the trigger level down to prevent 1545 * overflows. 1546 * * Otherwise set it a bit higher. 1547 */ 1548 if (sc->sc_type == COM_TYPE_HAYESP) { 1549 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1550 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1551 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1552 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1553 if (t->c_ospeed <= 1200) 1554 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1555 else if (t->c_ospeed <= 38400) 1556 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1557 else 1558 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1559 } else { 1560 sc->sc_fifo = 0; 1561 } 1562 1563 if (sc->sc_type == COM_TYPE_INGENIC) 1564 sc->sc_fifo |= FIFO_UART_ON; 1565 1566 /* And copy to tty. */ 1567 tp->t_ispeed = t->c_ospeed; 1568 tp->t_ospeed = t->c_ospeed; 1569 tp->t_cflag = t->c_cflag; 1570 1571 if (!sc->sc_heldchange) { 1572 if (sc->sc_tx_busy) { 1573 sc->sc_heldtbc = sc->sc_tbc; 1574 sc->sc_tbc = 0; 1575 sc->sc_heldchange = 1; 1576 } else 1577 com_loadchannelregs(sc); 1578 } 1579 1580 if (!ISSET(t->c_cflag, CHWFLOW)) { 1581 /* Disable the high water mark. */ 1582 sc->sc_r_hiwat = 0; 1583 sc->sc_r_lowat = 0; 1584 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1585 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1586 com_schedrx(sc); 1587 } 1588 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1589 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1590 com_hwiflow(sc); 1591 } 1592 } else { 1593 sc->sc_r_hiwat = com_rbuf_hiwat; 1594 sc->sc_r_lowat = com_rbuf_lowat; 1595 } 1596 1597 mutex_spin_exit(&sc->sc_lock); 1598 1599 /* 1600 * Update the tty layer's idea of the carrier bit, in case we changed 1601 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1602 * explicit request. 1603 */ 1604 if (sc->sc_type == COM_TYPE_INGENIC) { 1605 /* no DCD here */ 1606 (void) (*tp->t_linesw->l_modem)(tp, 1); 1607 } else 1608 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1609 1610 #ifdef COM_DEBUG 1611 if (com_debug) 1612 comstatus(sc, "comparam "); 1613 #endif 1614 1615 if (!ISSET(t->c_cflag, CHWFLOW)) { 1616 if (sc->sc_tx_stopped) { 1617 sc->sc_tx_stopped = 0; 1618 comstart(tp); 1619 } 1620 } 1621 1622 return (0); 1623 } 1624 1625 void 1626 com_iflush(struct com_softc *sc) 1627 { 1628 struct com_regs *regsp = &sc->sc_regs; 1629 uint8_t fifo; 1630 #ifdef DIAGNOSTIC 1631 int reg; 1632 #endif 1633 int timo; 1634 1635 #ifdef DIAGNOSTIC 1636 reg = 0xffff; 1637 #endif 1638 timo = 50000; 1639 /* flush any pending I/O */ 1640 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1641 && --timo) 1642 #ifdef DIAGNOSTIC 1643 reg = 1644 #else 1645 (void) 1646 #endif 1647 CSR_READ_1(regsp, COM_REG_RXDATA); 1648 #ifdef DIAGNOSTIC 1649 if (!timo) 1650 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1651 #endif 1652 1653 switch (sc->sc_type) { 1654 case COM_TYPE_16750: 1655 case COM_TYPE_DW_APB: 1656 /* 1657 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1658 * This should prevent triggering busy interrupt while 1659 * manipulating divisors. 1660 */ 1661 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1662 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1663 CSR_WRITE_1(regsp, COM_REG_FIFO, 1664 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1665 delay(100); 1666 break; 1667 } 1668 } 1669 1670 void 1671 com_loadchannelregs(struct com_softc *sc) 1672 { 1673 struct com_regs *regsp = &sc->sc_regs; 1674 1675 /* XXXXX necessary? */ 1676 com_iflush(sc); 1677 1678 if (sc->sc_type == COM_TYPE_PXA2x0) 1679 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1680 else 1681 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1682 1683 if (sc->sc_type == COM_TYPE_OMAP) { 1684 /* disable before changing settings */ 1685 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1686 } 1687 1688 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1689 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1690 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1691 /* no EFR on alchemy */ 1692 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1693 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1694 } 1695 if (sc->sc_type == COM_TYPE_AU1x00) { 1696 /* alchemy has single separate 16-bit clock divisor register */ 1697 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1698 (sc->sc_dlbh << 8)); 1699 } else { 1700 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1701 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1702 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1703 } 1704 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1705 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1706 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1707 if (sc->sc_type == COM_TYPE_HAYESP) { 1708 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1709 HAYESP_SETPRESCALER); 1710 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1711 sc->sc_prescaler); 1712 } 1713 if (sc->sc_type == COM_TYPE_OMAP) { 1714 /* setup the fifos. the FCR value is not used as long 1715 as SCR[6] and SCR[7] are 0, which they are at reset 1716 and we never touch the SCR register */ 1717 uint8_t rx_fifo_trig = 40; 1718 uint8_t tx_fifo_trig = 60; 1719 uint8_t rx_start = 8; 1720 uint8_t rx_halt = 60; 1721 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1722 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1723 1724 /* enable access to TCR & TLR */ 1725 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1726 1727 /* write tcr and tlr values */ 1728 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1729 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1730 1731 /* disable access to TCR & TLR */ 1732 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1733 1734 /* enable again, but mode is based on speed */ 1735 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1736 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1737 } else { 1738 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1739 } 1740 } 1741 1742 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1743 } 1744 1745 int 1746 comhwiflow(struct tty *tp, int block) 1747 { 1748 struct com_softc *sc = 1749 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1750 1751 if (COM_ISALIVE(sc) == 0) 1752 return (0); 1753 1754 if (sc->sc_mcr_rts == 0) 1755 return (0); 1756 1757 mutex_spin_enter(&sc->sc_lock); 1758 1759 if (block) { 1760 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1761 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1762 com_hwiflow(sc); 1763 } 1764 } else { 1765 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1766 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1767 com_schedrx(sc); 1768 } 1769 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1770 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1771 com_hwiflow(sc); 1772 } 1773 } 1774 1775 mutex_spin_exit(&sc->sc_lock); 1776 return (1); 1777 } 1778 1779 /* 1780 * (un)block input via hw flowcontrol 1781 */ 1782 void 1783 com_hwiflow(struct com_softc *sc) 1784 { 1785 struct com_regs *regsp= &sc->sc_regs; 1786 1787 if (sc->sc_mcr_rts == 0) 1788 return; 1789 1790 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1791 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1792 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1793 } else { 1794 SET(sc->sc_mcr, sc->sc_mcr_rts); 1795 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1796 } 1797 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1798 } 1799 1800 1801 void 1802 comstart(struct tty *tp) 1803 { 1804 struct com_softc *sc = 1805 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1806 struct com_regs *regsp = &sc->sc_regs; 1807 int s; 1808 1809 if (COM_ISALIVE(sc) == 0) 1810 return; 1811 1812 s = spltty(); 1813 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1814 goto out; 1815 if (sc->sc_tx_stopped) 1816 goto out; 1817 if (!ttypull(tp)) 1818 goto out; 1819 1820 /* Grab the first contiguous region of buffer space. */ 1821 { 1822 u_char *tba; 1823 int tbc; 1824 1825 tba = tp->t_outq.c_cf; 1826 tbc = ndqb(&tp->t_outq, 0); 1827 1828 mutex_spin_enter(&sc->sc_lock); 1829 1830 sc->sc_tba = tba; 1831 sc->sc_tbc = tbc; 1832 } 1833 1834 SET(tp->t_state, TS_BUSY); 1835 sc->sc_tx_busy = 1; 1836 1837 /* Enable transmit completion interrupts if necessary. */ 1838 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1839 SET(sc->sc_ier, IER_ETXRDY); 1840 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1841 } 1842 1843 /* Output the first chunk of the contiguous buffer. */ 1844 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1845 u_int n; 1846 1847 n = sc->sc_tbc; 1848 if (n > sc->sc_fifolen) 1849 n = sc->sc_fifolen; 1850 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1851 sc->sc_tbc -= n; 1852 sc->sc_tba += n; 1853 } 1854 1855 mutex_spin_exit(&sc->sc_lock); 1856 out: 1857 splx(s); 1858 return; 1859 } 1860 1861 /* 1862 * Stop output on a line. 1863 */ 1864 void 1865 comstop(struct tty *tp, int flag) 1866 { 1867 struct com_softc *sc = 1868 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1869 1870 mutex_spin_enter(&sc->sc_lock); 1871 if (ISSET(tp->t_state, TS_BUSY)) { 1872 /* Stop transmitting at the next chunk. */ 1873 sc->sc_tbc = 0; 1874 sc->sc_heldtbc = 0; 1875 if (!ISSET(tp->t_state, TS_TTSTOP)) 1876 SET(tp->t_state, TS_FLUSH); 1877 } 1878 mutex_spin_exit(&sc->sc_lock); 1879 } 1880 1881 void 1882 comdiag(void *arg) 1883 { 1884 struct com_softc *sc = arg; 1885 int overflows, floods; 1886 1887 mutex_spin_enter(&sc->sc_lock); 1888 overflows = sc->sc_overflows; 1889 sc->sc_overflows = 0; 1890 floods = sc->sc_floods; 1891 sc->sc_floods = 0; 1892 sc->sc_errors = 0; 1893 mutex_spin_exit(&sc->sc_lock); 1894 1895 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1896 device_xname(sc->sc_dev), 1897 overflows, overflows == 1 ? "" : "s", 1898 floods, floods == 1 ? "" : "s"); 1899 } 1900 1901 integrate void 1902 com_rxsoft(struct com_softc *sc, struct tty *tp) 1903 { 1904 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1905 u_char *get, *end; 1906 u_int cc, scc; 1907 u_char lsr; 1908 int code; 1909 1910 end = sc->sc_ebuf; 1911 get = sc->sc_rbget; 1912 scc = cc = com_rbuf_size - sc->sc_rbavail; 1913 1914 if (cc == com_rbuf_size) { 1915 sc->sc_floods++; 1916 if (sc->sc_errors++ == 0) 1917 callout_reset(&sc->sc_diag_callout, 60 * hz, 1918 comdiag, sc); 1919 } 1920 1921 /* If not yet open, drop the entire buffer content here */ 1922 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1923 get += cc << 1; 1924 if (get >= end) 1925 get -= com_rbuf_size << 1; 1926 cc = 0; 1927 } 1928 while (cc) { 1929 code = get[0]; 1930 lsr = get[1]; 1931 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1932 if (ISSET(lsr, LSR_OE)) { 1933 sc->sc_overflows++; 1934 if (sc->sc_errors++ == 0) 1935 callout_reset(&sc->sc_diag_callout, 1936 60 * hz, comdiag, sc); 1937 } 1938 if (ISSET(lsr, LSR_BI | LSR_FE)) 1939 SET(code, TTY_FE); 1940 if (ISSET(lsr, LSR_PE)) 1941 SET(code, TTY_PE); 1942 } 1943 if ((*rint)(code, tp) == -1) { 1944 /* 1945 * The line discipline's buffer is out of space. 1946 */ 1947 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1948 /* 1949 * We're either not using flow control, or the 1950 * line discipline didn't tell us to block for 1951 * some reason. Either way, we have no way to 1952 * know when there's more space available, so 1953 * just drop the rest of the data. 1954 */ 1955 get += cc << 1; 1956 if (get >= end) 1957 get -= com_rbuf_size << 1; 1958 cc = 0; 1959 } else { 1960 /* 1961 * Don't schedule any more receive processing 1962 * until the line discipline tells us there's 1963 * space available (through comhwiflow()). 1964 * Leave the rest of the data in the input 1965 * buffer. 1966 */ 1967 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1968 } 1969 break; 1970 } 1971 get += 2; 1972 if (get >= end) 1973 get = sc->sc_rbuf; 1974 cc--; 1975 } 1976 1977 if (cc != scc) { 1978 sc->sc_rbget = get; 1979 mutex_spin_enter(&sc->sc_lock); 1980 1981 cc = sc->sc_rbavail += scc - cc; 1982 /* Buffers should be ok again, release possible block. */ 1983 if (cc >= sc->sc_r_lowat) { 1984 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1985 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1986 SET(sc->sc_ier, IER_ERXRDY); 1987 if (sc->sc_type == COM_TYPE_PXA2x0) 1988 SET(sc->sc_ier, IER_ERXTOUT); 1989 if (sc->sc_type == COM_TYPE_INGENIC || 1990 sc->sc_type == COM_TYPE_TEGRA) 1991 SET(sc->sc_ier, IER_ERXTOUT); 1992 1993 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 1994 sc->sc_ier); 1995 } 1996 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1997 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1998 com_hwiflow(sc); 1999 } 2000 } 2001 mutex_spin_exit(&sc->sc_lock); 2002 } 2003 } 2004 2005 integrate void 2006 com_txsoft(struct com_softc *sc, struct tty *tp) 2007 { 2008 2009 CLR(tp->t_state, TS_BUSY); 2010 if (ISSET(tp->t_state, TS_FLUSH)) 2011 CLR(tp->t_state, TS_FLUSH); 2012 else 2013 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2014 (*tp->t_linesw->l_start)(tp); 2015 } 2016 2017 integrate void 2018 com_stsoft(struct com_softc *sc, struct tty *tp) 2019 { 2020 u_char msr, delta; 2021 2022 mutex_spin_enter(&sc->sc_lock); 2023 msr = sc->sc_msr; 2024 delta = sc->sc_msr_delta; 2025 sc->sc_msr_delta = 0; 2026 mutex_spin_exit(&sc->sc_lock); 2027 2028 if (ISSET(delta, sc->sc_msr_dcd)) { 2029 /* 2030 * Inform the tty layer that carrier detect changed. 2031 */ 2032 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2033 } 2034 2035 if (ISSET(delta, sc->sc_msr_cts)) { 2036 /* Block or unblock output according to flow control. */ 2037 if (ISSET(msr, sc->sc_msr_cts)) { 2038 sc->sc_tx_stopped = 0; 2039 (*tp->t_linesw->l_start)(tp); 2040 } else { 2041 sc->sc_tx_stopped = 1; 2042 } 2043 } 2044 2045 #ifdef COM_DEBUG 2046 if (com_debug) 2047 comstatus(sc, "com_stsoft"); 2048 #endif 2049 } 2050 2051 void 2052 comsoft(void *arg) 2053 { 2054 struct com_softc *sc = arg; 2055 struct tty *tp; 2056 2057 if (COM_ISALIVE(sc) == 0) 2058 return; 2059 2060 tp = sc->sc_tty; 2061 2062 if (sc->sc_rx_ready) { 2063 sc->sc_rx_ready = 0; 2064 com_rxsoft(sc, tp); 2065 } 2066 2067 if (sc->sc_st_check) { 2068 sc->sc_st_check = 0; 2069 com_stsoft(sc, tp); 2070 } 2071 2072 if (sc->sc_tx_done) { 2073 sc->sc_tx_done = 0; 2074 com_txsoft(sc, tp); 2075 } 2076 } 2077 2078 int 2079 comintr(void *arg) 2080 { 2081 struct com_softc *sc = arg; 2082 struct com_regs *regsp = &sc->sc_regs; 2083 2084 u_char *put, *end; 2085 u_int cc; 2086 u_char lsr, iir; 2087 2088 if (COM_ISALIVE(sc) == 0) 2089 return (0); 2090 2091 KASSERT(regsp != NULL); 2092 2093 mutex_spin_enter(&sc->sc_lock); 2094 iir = CSR_READ_1(regsp, COM_REG_IIR); 2095 2096 /* Handle ns16750-specific busy interrupt. */ 2097 if (sc->sc_type == COM_TYPE_16750 && 2098 (iir & IIR_BUSY) == IIR_BUSY) { 2099 for (int timeout = 10000; 2100 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2101 if (timeout <= 0) { 2102 aprint_error_dev(sc->sc_dev, 2103 "timeout while waiting for BUSY interrupt " 2104 "acknowledge\n"); 2105 mutex_spin_exit(&sc->sc_lock); 2106 return (0); 2107 } 2108 2109 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2110 iir = CSR_READ_1(regsp, COM_REG_IIR); 2111 } 2112 2113 /* DesignWare APB UART BUSY interrupt */ 2114 if (sc->sc_type == COM_TYPE_DW_APB && 2115 (iir & IIR_BUSY) == IIR_BUSY) { 2116 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2117 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2118 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2119 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2120 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2121 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2122 CSR_WRITE_1(regsp, COM_REG_HALT, 2123 HALT_CHCFG_EN | HALT_CHCFG_UD); 2124 for (int timeout = 10000000; 2125 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2126 timeout--) { 2127 if (timeout <= 0) { 2128 aprint_error_dev(sc->sc_dev, 2129 "timeout while waiting for HALT " 2130 "update acknowledge 0x%x 0x%x\n", 2131 CSR_READ_1(regsp, COM_REG_HALT), 2132 CSR_READ_1(regsp, COM_REG_USR)); 2133 break; 2134 } 2135 } 2136 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2137 (void)CSR_READ_1(regsp, COM_REG_USR); 2138 } else { 2139 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2140 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2141 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2142 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2143 } 2144 } 2145 2146 if (ISSET(iir, IIR_NOPEND)) { 2147 mutex_spin_exit(&sc->sc_lock); 2148 return (0); 2149 } 2150 2151 end = sc->sc_ebuf; 2152 put = sc->sc_rbput; 2153 cc = sc->sc_rbavail; 2154 2155 again: do { 2156 u_char msr, delta; 2157 2158 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2159 if (ISSET(lsr, LSR_BI)) { 2160 int cn_trapped = 0; /* see above: cn_trap() */ 2161 2162 cn_check_magic(sc->sc_tty->t_dev, 2163 CNC_BREAK, com_cnm_state); 2164 if (cn_trapped) 2165 continue; 2166 #if defined(KGDB) && !defined(DDB) 2167 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2168 kgdb_connect(1); 2169 continue; 2170 } 2171 #endif 2172 } 2173 2174 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2175 lsr |= LSR_RXRDY; 2176 2177 if (ISSET(lsr, LSR_RCV_MASK) && 2178 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2179 while (cc > 0) { 2180 int cn_trapped = 0; 2181 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2182 put[1] = lsr; 2183 cn_check_magic(sc->sc_tty->t_dev, 2184 put[0], com_cnm_state); 2185 if (cn_trapped) 2186 goto next; 2187 put += 2; 2188 if (put >= end) 2189 put = sc->sc_rbuf; 2190 cc--; 2191 next: 2192 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2193 if (!ISSET(lsr, LSR_RCV_MASK)) 2194 break; 2195 } 2196 2197 /* 2198 * Current string of incoming characters ended because 2199 * no more data was available or we ran out of space. 2200 * Schedule a receive event if any data was received. 2201 * If we're out of space, turn off receive interrupts. 2202 */ 2203 sc->sc_rbput = put; 2204 sc->sc_rbavail = cc; 2205 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2206 sc->sc_rx_ready = 1; 2207 2208 /* 2209 * See if we are in danger of overflowing a buffer. If 2210 * so, use hardware flow control to ease the pressure. 2211 */ 2212 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2213 cc < sc->sc_r_hiwat) { 2214 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2215 com_hwiflow(sc); 2216 } 2217 2218 /* 2219 * If we're out of space, disable receive interrupts 2220 * until the queue has drained a bit. 2221 */ 2222 if (!cc) { 2223 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2224 switch (sc->sc_type) { 2225 case COM_TYPE_PXA2x0: 2226 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2227 break; 2228 case COM_TYPE_INGENIC: 2229 case COM_TYPE_TEGRA: 2230 CLR(sc->sc_ier, 2231 IER_ERXRDY | IER_ERXTOUT); 2232 break; 2233 default: 2234 CLR(sc->sc_ier, IER_ERXRDY); 2235 break; 2236 } 2237 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2238 } 2239 } else { 2240 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2241 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2242 continue; 2243 } 2244 } 2245 2246 msr = CSR_READ_1(regsp, COM_REG_MSR); 2247 delta = msr ^ sc->sc_msr; 2248 sc->sc_msr = msr; 2249 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2250 (delta & MSR_DCD)) { 2251 mutex_spin_enter(&timecounter_lock); 2252 pps_capture(&sc->sc_pps_state); 2253 pps_event(&sc->sc_pps_state, 2254 (msr & MSR_DCD) ? 2255 PPS_CAPTUREASSERT : 2256 PPS_CAPTURECLEAR); 2257 mutex_spin_exit(&timecounter_lock); 2258 } 2259 2260 /* 2261 * Process normal status changes 2262 */ 2263 if (ISSET(delta, sc->sc_msr_mask)) { 2264 SET(sc->sc_msr_delta, delta); 2265 2266 /* 2267 * Stop output immediately if we lose the output 2268 * flow control signal or carrier detect. 2269 */ 2270 if (ISSET(~msr, sc->sc_msr_mask)) { 2271 sc->sc_tbc = 0; 2272 sc->sc_heldtbc = 0; 2273 #ifdef COM_DEBUG 2274 if (com_debug) 2275 comstatus(sc, "comintr "); 2276 #endif 2277 } 2278 2279 sc->sc_st_check = 1; 2280 } 2281 } while (!ISSET((iir = 2282 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2283 /* 2284 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2285 * by IIR read, so we can't do this way: `process all interrupts, 2286 * then do TX if possible'. 2287 */ 2288 (iir & IIR_IMASK) != IIR_TXRDY); 2289 2290 /* 2291 * Read LSR again, since there may be an interrupt between 2292 * the last LSR read and IIR read above. 2293 */ 2294 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2295 2296 /* 2297 * See if data can be transmitted as well. 2298 * Schedule tx done event if no data left 2299 * and tty was marked busy. 2300 */ 2301 if (ISSET(lsr, LSR_TXRDY)) { 2302 /* 2303 * If we've delayed a parameter change, do it now, and restart 2304 * output. 2305 */ 2306 if (sc->sc_heldchange) { 2307 com_loadchannelregs(sc); 2308 sc->sc_heldchange = 0; 2309 sc->sc_tbc = sc->sc_heldtbc; 2310 sc->sc_heldtbc = 0; 2311 } 2312 2313 /* Output the next chunk of the contiguous buffer, if any. */ 2314 if (sc->sc_tbc > 0) { 2315 u_int n; 2316 2317 n = sc->sc_tbc; 2318 if (n > sc->sc_fifolen) 2319 n = sc->sc_fifolen; 2320 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2321 sc->sc_tbc -= n; 2322 sc->sc_tba += n; 2323 } else { 2324 /* Disable transmit completion interrupts if necessary. */ 2325 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2326 CLR(sc->sc_ier, IER_ETXRDY); 2327 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2328 } 2329 if (sc->sc_tx_busy) { 2330 sc->sc_tx_busy = 0; 2331 sc->sc_tx_done = 1; 2332 } 2333 } 2334 } 2335 2336 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2337 goto again; 2338 2339 mutex_spin_exit(&sc->sc_lock); 2340 2341 /* Wake up the poller. */ 2342 softint_schedule(sc->sc_si); 2343 2344 #ifdef RND_COM 2345 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2346 #endif 2347 2348 return (1); 2349 } 2350 2351 /* 2352 * The following functions are polled getc and putc routines, shared 2353 * by the console and kgdb glue. 2354 * 2355 * The read-ahead code is so that you can detect pending in-band 2356 * cn_magic in polled mode while doing output rather than having to 2357 * wait until the kernel decides it needs input. 2358 */ 2359 2360 #define MAX_READAHEAD 20 2361 static int com_readahead[MAX_READAHEAD]; 2362 static int com_readaheadcount = 0; 2363 2364 int 2365 com_common_getc(dev_t dev, struct com_regs *regsp) 2366 { 2367 int s = splserial(); 2368 u_char stat, c; 2369 2370 /* got a character from reading things earlier */ 2371 if (com_readaheadcount > 0) { 2372 int i; 2373 2374 c = com_readahead[0]; 2375 for (i = 1; i < com_readaheadcount; i++) { 2376 com_readahead[i-1] = com_readahead[i]; 2377 } 2378 com_readaheadcount--; 2379 splx(s); 2380 return (c); 2381 } 2382 2383 /* don't block until a character becomes available */ 2384 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2385 splx(s); 2386 return -1; 2387 } 2388 2389 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2390 stat = CSR_READ_1(regsp, COM_REG_IIR); 2391 { 2392 int cn_trapped = 0; /* required by cn_trap, see above */ 2393 #ifdef DDB 2394 extern int db_active; 2395 if (!db_active) 2396 #endif 2397 cn_check_magic(dev, c, com_cnm_state); 2398 } 2399 splx(s); 2400 return (c); 2401 } 2402 2403 static void 2404 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2405 { 2406 int s = splserial(); 2407 int cin, stat, timo; 2408 2409 if (com_readaheadcount < MAX_READAHEAD 2410 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2411 int cn_trapped = 0; 2412 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2413 stat = CSR_READ_1(regsp, COM_REG_IIR); 2414 cn_check_magic(dev, cin, com_cnm_state); 2415 com_readahead[com_readaheadcount++] = cin; 2416 } 2417 2418 /* wait for any pending transmission to finish */ 2419 timo = 150000; 2420 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2421 continue; 2422 2423 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2424 COM_BARRIER(regsp, BR | BW); 2425 2426 splx(s); 2427 } 2428 2429 /* 2430 * Initialize UART for use as console or KGDB line. 2431 */ 2432 int 2433 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2434 tcflag_t cflag) 2435 { 2436 2437 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2438 ®sp->cr_ioh)) 2439 return (ENOMEM); /* ??? */ 2440 2441 if (type == COM_TYPE_OMAP) { 2442 /* disable before changing settings */ 2443 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2444 } 2445 2446 rate = comspeed(rate, frequency, type); 2447 if (__predict_true(rate != -1)) { 2448 if (type == COM_TYPE_AU1x00) { 2449 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2450 } else { 2451 /* no EFR on alchemy */ 2452 if ((type != COM_TYPE_16550_NOERS) && 2453 (type != COM_TYPE_INGENIC)) { 2454 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2455 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2456 } 2457 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2458 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2459 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2460 } 2461 } 2462 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2463 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2464 2465 if (type == COM_TYPE_INGENIC) { 2466 CSR_WRITE_1(regsp, COM_REG_FIFO, 2467 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2468 FIFO_TRIGGER_1 | FIFO_UART_ON); 2469 } else { 2470 CSR_WRITE_1(regsp, COM_REG_FIFO, 2471 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2472 FIFO_TRIGGER_1); 2473 } 2474 2475 if (type == COM_TYPE_OMAP) { 2476 /* setup the fifos. the FCR value is not used as long 2477 as SCR[6] and SCR[7] are 0, which they are at reset 2478 and we never touch the SCR register */ 2479 uint8_t rx_fifo_trig = 40; 2480 uint8_t tx_fifo_trig = 60; 2481 uint8_t rx_start = 8; 2482 uint8_t rx_halt = 60; 2483 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2484 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2485 2486 /* enable access to TCR & TLR */ 2487 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2488 2489 /* write tcr and tlr values */ 2490 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2491 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2492 2493 /* disable access to TCR & TLR */ 2494 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2495 2496 /* enable again, but mode is based on speed */ 2497 if (rate > 230400) { 2498 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2499 } else { 2500 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2501 } 2502 } 2503 2504 if (type == COM_TYPE_PXA2x0) 2505 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2506 else 2507 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2508 2509 return (0); 2510 } 2511 2512 int 2513 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2514 tcflag_t cflag) 2515 { 2516 int res; 2517 2518 comcons_info.regs = *regsp; 2519 2520 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2521 if (res) 2522 return (res); 2523 2524 cn_tab = &comcons; 2525 cn_init_magic(&com_cnm_state); 2526 cn_set_magic("\047\001"); /* default magic is BREAK */ 2527 2528 comcons_info.frequency = frequency; 2529 comcons_info.type = type; 2530 comcons_info.rate = rate; 2531 comcons_info.cflag = cflag; 2532 2533 return (0); 2534 } 2535 2536 int 2537 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2538 int type, tcflag_t cflag) 2539 { 2540 struct com_regs regs; 2541 2542 /*XXX*/ 2543 bus_space_handle_t dummy_bsh; 2544 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2545 2546 /* 2547 * dummy_bsh required because com_init_regs() wants it. A 2548 * real bus_space_handle will be filled in by cominit() later. 2549 * XXXJRT Detangle this mess eventually, plz. 2550 */ 2551 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2552 2553 return comcnattach1(®s, rate, frequency, type, cflag); 2554 } 2555 2556 static int 2557 comcnreattach(void) 2558 { 2559 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2560 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2561 } 2562 2563 int 2564 comcngetc(dev_t dev) 2565 { 2566 2567 return (com_common_getc(dev, &comcons_info.regs)); 2568 } 2569 2570 /* 2571 * Console kernel output character routine. 2572 */ 2573 void 2574 comcnputc(dev_t dev, int c) 2575 { 2576 2577 com_common_putc(dev, &comcons_info.regs, c); 2578 } 2579 2580 void 2581 comcnpollc(dev_t dev, int on) 2582 { 2583 2584 com_readaheadcount = 0; 2585 } 2586 2587 #ifdef KGDB 2588 int 2589 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2590 tcflag_t cflag) 2591 { 2592 int res; 2593 2594 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2595 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2596 #if !defined(DDB) 2597 return (EBUSY); /* cannot share with console */ 2598 #else 2599 comkgdbregs = *regsp; 2600 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2601 #endif 2602 } else { 2603 comkgdbregs = *regsp; 2604 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2605 if (res) 2606 return (res); 2607 2608 /* 2609 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2610 * expects this to be initialized 2611 */ 2612 cn_init_magic(&com_cnm_state); 2613 cn_set_magic("\047\001"); 2614 } 2615 2616 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2617 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2618 2619 return (0); 2620 } 2621 2622 int 2623 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2624 int frequency, int type, tcflag_t cflag) 2625 { 2626 struct com_regs regs; 2627 2628 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2629 2630 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2631 } 2632 2633 /* ARGSUSED */ 2634 int 2635 com_kgdb_getc(void *arg) 2636 { 2637 2638 return (com_common_getc(NODEV, &comkgdbregs)); 2639 } 2640 2641 /* ARGSUSED */ 2642 void 2643 com_kgdb_putc(void *arg, int c) 2644 { 2645 2646 com_common_putc(NODEV, &comkgdbregs, c); 2647 } 2648 #endif /* KGDB */ 2649 2650 /* helper function to identify the com ports used by 2651 console or KGDB (and not yet autoconf attached) */ 2652 int 2653 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2654 { 2655 bus_space_handle_t help; 2656 2657 if (!comconsattached && 2658 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2659 iobase == comcons_info.regs.cr_iobase) 2660 help = comcons_info.regs.cr_ioh; 2661 #ifdef KGDB 2662 else if (!com_kgdb_attached && 2663 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2664 iobase == comkgdbregs.cr_iobase) 2665 help = comkgdbregs.cr_ioh; 2666 #endif 2667 else 2668 return (0); 2669 2670 if (ioh) 2671 *ioh = help; 2672 return (1); 2673 } 2674 2675 /* 2676 * this routine exists to serve as a shutdown hook for systems that 2677 * have firmware which doesn't interact properly with a com device in 2678 * FIFO mode. 2679 */ 2680 bool 2681 com_cleanup(device_t self, int how) 2682 { 2683 struct com_softc *sc = device_private(self); 2684 2685 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2686 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2687 2688 return true; 2689 } 2690 2691 bool 2692 com_suspend(device_t self, const pmf_qual_t *qual) 2693 { 2694 struct com_softc *sc = device_private(self); 2695 2696 #if 0 2697 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2698 cn_tab = &comcons_suspend; 2699 #endif 2700 2701 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2702 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2703 2704 return true; 2705 } 2706 2707 bool 2708 com_resume(device_t self, const pmf_qual_t *qual) 2709 { 2710 struct com_softc *sc = device_private(self); 2711 2712 mutex_spin_enter(&sc->sc_lock); 2713 com_loadchannelregs(sc); 2714 mutex_spin_exit(&sc->sc_lock); 2715 2716 return true; 2717 } 2718
Indexes created Mon Oct 20 11:09:49 GMT 2025