com.c revision 1.348
1 /* $NetBSD: com.c,v 1.348 2018/05/27 17:05:06 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.348 2018/05/27 17:05:06 jmcneill Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #ifdef COM_REGMAP 132 #define CSR_WRITE_1(r, o, v) \ 133 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 134 #define CSR_READ_1(r, o) \ 135 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 136 #define CSR_WRITE_2(r, o, v) \ 137 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 138 #define CSR_READ_2(r, o) \ 139 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 140 #define CSR_WRITE_MULTI(r, o, p, n) \ 141 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 142 #else 143 #define CSR_WRITE_1(r, o, v) \ 144 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 145 #define CSR_READ_1(r, o) \ 146 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 147 #define CSR_WRITE_2(r, o, v) \ 148 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 149 #define CSR_READ_2(r, o) \ 150 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 151 #define CSR_WRITE_MULTI(r, o, p, n) \ 152 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 153 #endif 154 155 156 static void com_enable_debugport(struct com_softc *); 157 158 void com_config(struct com_softc *); 159 void com_shutdown(struct com_softc *); 160 int comspeed(long, long, int); 161 static u_char cflag2lcr(tcflag_t); 162 int comparam(struct tty *, struct termios *); 163 void comstart(struct tty *); 164 int comhwiflow(struct tty *, int); 165 166 void com_loadchannelregs(struct com_softc *); 167 void com_hwiflow(struct com_softc *); 168 void com_break(struct com_softc *, int); 169 void com_modem(struct com_softc *, int); 170 void tiocm_to_com(struct com_softc *, u_long, int); 171 int com_to_tiocm(struct com_softc *); 172 void com_iflush(struct com_softc *); 173 174 int com_common_getc(dev_t, struct com_regs *); 175 static void com_common_putc(dev_t, struct com_regs *, int); 176 177 int cominit(struct com_regs *, int, int, int, tcflag_t); 178 179 static int comcnreattach(void); 180 181 int comcngetc(dev_t); 182 void comcnputc(dev_t, int); 183 void comcnpollc(dev_t, int); 184 185 #define integrate static inline 186 void comsoft(void *); 187 integrate void com_rxsoft(struct com_softc *, struct tty *); 188 integrate void com_txsoft(struct com_softc *, struct tty *); 189 integrate void com_stsoft(struct com_softc *, struct tty *); 190 integrate void com_schedrx(struct com_softc *); 191 void comdiag(void *); 192 193 dev_type_open(comopen); 194 dev_type_close(comclose); 195 dev_type_read(comread); 196 dev_type_write(comwrite); 197 dev_type_ioctl(comioctl); 198 dev_type_stop(comstop); 199 dev_type_tty(comtty); 200 dev_type_poll(compoll); 201 202 static struct comcons_info comcons_info; 203 204 /* 205 * Following are all routines needed for COM to act as console 206 */ 207 static struct consdev comcons = { 208 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 209 NODEV, CN_NORMAL 210 }; 211 212 213 const struct cdevsw com_cdevsw = { 214 .d_open = comopen, 215 .d_close = comclose, 216 .d_read = comread, 217 .d_write = comwrite, 218 .d_ioctl = comioctl, 219 .d_stop = comstop, 220 .d_tty = comtty, 221 .d_poll = compoll, 222 .d_mmap = nommap, 223 .d_kqfilter = ttykqfilter, 224 .d_discard = nodiscard, 225 .d_flag = D_TTY 226 }; 227 228 /* 229 * Make this an option variable one can patch. 230 * But be warned: this must be a power of 2! 231 */ 232 u_int com_rbuf_size = COM_RING_SIZE; 233 234 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 235 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 236 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 237 238 static int comconsattached; 239 static struct cnm_state com_cnm_state; 240 241 #ifdef KGDB 242 #include <sys/kgdb.h> 243 244 static struct com_regs comkgdbregs; 245 static int com_kgdb_attached; 246 247 int com_kgdb_getc(void *); 248 void com_kgdb_putc(void *, int); 249 #endif /* KGDB */ 250 251 #ifdef COM_REGMAP 252 /* initializer for typical 16550-ish hardware */ 253 #define COM_REG_STD { \ 254 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 255 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 256 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr, com_tfl, com_rfl, \ 257 0, 0, 0, 0, 0, 0, 0, com_halt } 258 259 const bus_size_t com_std_map[42] = COM_REG_STD; 260 #endif /* COM_REGMAP */ 261 262 #define COMDIALOUT_MASK TTDIALOUT_MASK 263 264 #define COMUNIT(x) TTUNIT(x) 265 #define COMDIALOUT(x) TTDIALOUT(x) 266 267 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 268 device_is_active((sc)->sc_dev)) 269 270 #define BR BUS_SPACE_BARRIER_READ 271 #define BW BUS_SPACE_BARRIER_WRITE 272 #define COM_BARRIER(r, f) \ 273 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 274 275 /*ARGSUSED*/ 276 int 277 comspeed(long speed, long frequency, int type) 278 { 279 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 280 281 int x, err; 282 int divisor = 16; 283 284 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 285 divisor = 13; 286 } 287 288 if (speed == 0) 289 return (0); 290 if (speed < 0) 291 return (-1); 292 x = divrnd(frequency / divisor, speed); 293 if (x <= 0) 294 return (-1); 295 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 296 if (err < 0) 297 err = -err; 298 if (err > COM_TOLERANCE) 299 return (-1); 300 return (x); 301 302 #undef divrnd 303 } 304 305 #ifdef COM_DEBUG 306 int com_debug = 0; 307 308 void comstatus(struct com_softc *, const char *); 309 void 310 comstatus(struct com_softc *sc, const char *str) 311 { 312 struct tty *tp = sc->sc_tty; 313 314 aprint_normal_dev(sc->sc_dev, 315 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 316 str, 317 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 318 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 319 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 320 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 321 sc->sc_tx_stopped ? '+' : '-'); 322 323 aprint_normal_dev(sc->sc_dev, 324 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 325 str, 326 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 327 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 328 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 329 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 330 sc->sc_rx_flags); 331 } 332 #endif 333 334 int 335 com_probe_subr(struct com_regs *regs) 336 { 337 338 /* force access to id reg */ 339 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 340 CSR_WRITE_1(regs, COM_REG_IIR, 0); 341 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 342 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 343 return (0); 344 345 return (1); 346 } 347 348 int 349 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 350 { 351 struct com_regs regs; 352 353 regs.cr_iot = iot; 354 regs.cr_ioh = ioh; 355 #ifdef COM_REGMAP 356 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 357 #endif 358 359 return com_probe_subr(®s); 360 } 361 362 /* 363 * No locking in this routine; it is only called during attach, 364 * or with the port already locked. 365 */ 366 static void 367 com_enable_debugport(struct com_softc *sc) 368 { 369 370 /* Turn on line break interrupt, set carrier. */ 371 sc->sc_ier = IER_ERLS; 372 if (sc->sc_type == COM_TYPE_PXA2x0) 373 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 374 if (sc->sc_type == COM_TYPE_INGENIC || 375 sc->sc_type == COM_TYPE_TEGRA) 376 sc->sc_ier |= IER_ERXTOUT; 377 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 378 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 379 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 380 } 381 382 void 383 com_attach_subr(struct com_softc *sc) 384 { 385 struct com_regs *regsp = &sc->sc_regs; 386 struct tty *tp; 387 u_int8_t lcr; 388 const char *fifo_msg = NULL; 389 prop_dictionary_t dict; 390 bool is_console = true; 391 392 aprint_naive("\n"); 393 394 dict = device_properties(sc->sc_dev); 395 prop_dictionary_get_bool(dict, "is_console", &is_console); 396 callout_init(&sc->sc_diag_callout, 0); 397 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 398 399 #if defined(COM_16650) 400 sc->sc_type = COM_TYPE_16650; 401 #elif defined(COM_16750) 402 sc->sc_type = COM_TYPE_16750; 403 #elif defined(COM_HAYESP) 404 sc->sc_type = COM_TYPE_HAYESP; 405 #elif defined(COM_PXA2X0) 406 sc->sc_type = COM_TYPE_PXA2x0; 407 #endif 408 409 /* Disable interrupts before configuring the device. */ 410 if (sc->sc_type == COM_TYPE_PXA2x0) 411 sc->sc_ier = IER_EUART; 412 else 413 sc->sc_ier = 0; 414 415 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 416 417 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 418 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 419 comconsattached = 1; 420 421 if (cn_tab == NULL && comcnreattach() != 0) { 422 printf("can't re-init serial console @%lx\n", 423 (u_long)comcons_info.regs.cr_iobase); 424 } 425 426 switch (sc->sc_type) { 427 case COM_TYPE_16750: 428 case COM_TYPE_DW_APB: 429 /* Use in comintr(). */ 430 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 431 break; 432 } 433 434 /* Make sure the console is always "hardwired". */ 435 delay(10000); /* wait for output to finish */ 436 if (is_console) { 437 SET(sc->sc_hwflags, COM_HW_CONSOLE); 438 } 439 440 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 441 } 442 443 /* Probe for FIFO */ 444 switch (sc->sc_type) { 445 case COM_TYPE_HAYESP: 446 goto fifodone; 447 448 case COM_TYPE_AU1x00: 449 sc->sc_fifolen = 16; 450 fifo_msg = "Au1X00 UART, working fifo"; 451 SET(sc->sc_hwflags, COM_HW_FIFO); 452 goto fifodelay; 453 454 case COM_TYPE_16550_NOERS: 455 sc->sc_fifolen = 16; 456 fifo_msg = "ns16650, no ERS, working fifo"; 457 SET(sc->sc_hwflags, COM_HW_FIFO); 458 goto fifodelay; 459 460 case COM_TYPE_OMAP: 461 sc->sc_fifolen = 64; 462 fifo_msg = "OMAP UART, working fifo"; 463 SET(sc->sc_hwflags, COM_HW_FIFO); 464 goto fifodelay; 465 466 case COM_TYPE_INGENIC: 467 sc->sc_fifolen = 16; 468 fifo_msg = "Ingenic UART, working fifo"; 469 SET(sc->sc_hwflags, COM_HW_FIFO); 470 SET(sc->sc_hwflags, COM_HW_NOIEN); 471 goto fifodelay; 472 473 case COM_TYPE_TEGRA: 474 sc->sc_fifolen = 8; 475 fifo_msg = "Tegra UART, working fifo"; 476 SET(sc->sc_hwflags, COM_HW_FIFO); 477 CSR_WRITE_1(regsp, COM_REG_FIFO, 478 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 479 goto fifodelay; 480 481 case COM_TYPE_BCMAUXUART: 482 sc->sc_fifolen = 1; 483 fifo_msg = "BCM AUX UART, working fifo"; 484 SET(sc->sc_hwflags, COM_HW_FIFO); 485 CSR_WRITE_1(regsp, COM_REG_FIFO, 486 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 487 goto fifodelay; 488 } 489 490 sc->sc_fifolen = 1; 491 /* look for a NS 16550AF UART with FIFOs */ 492 if (sc->sc_type == COM_TYPE_INGENIC) { 493 CSR_WRITE_1(regsp, COM_REG_FIFO, 494 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 495 FIFO_TRIGGER_14 | FIFO_UART_ON); 496 } else 497 CSR_WRITE_1(regsp, COM_REG_FIFO, 498 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 499 delay(100); 500 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 501 == IIR_FIFO_MASK) 502 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 503 == FIFO_TRIGGER_14) { 504 SET(sc->sc_hwflags, COM_HW_FIFO); 505 506 fifo_msg = "ns16550a, working fifo"; 507 508 /* 509 * IIR changes into the EFR if LCR is set to LCR_EERS 510 * on 16650s. We also know IIR != 0 at this point. 511 * Write 0 into the EFR, and read it. If the result 512 * is 0, we have a 16650. 513 * 514 * Older 16650s were broken; the test to detect them 515 * is taken from the Linux driver. Apparently 516 * setting DLAB enable gives access to the EFR on 517 * these chips. 518 */ 519 if (sc->sc_type == COM_TYPE_16650) { 520 lcr = CSR_READ_1(regsp, COM_REG_LCR); 521 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 522 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 523 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 524 CSR_WRITE_1(regsp, COM_REG_LCR, 525 lcr | LCR_DLAB); 526 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 527 CLR(sc->sc_hwflags, COM_HW_FIFO); 528 sc->sc_fifolen = 0; 529 } else { 530 SET(sc->sc_hwflags, COM_HW_FLOW); 531 sc->sc_fifolen = 32; 532 } 533 } else 534 sc->sc_fifolen = 16; 535 536 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 537 if (sc->sc_fifolen == 0) 538 fifo_msg = "st16650, broken fifo"; 539 else if (sc->sc_fifolen == 32) 540 fifo_msg = "st16650a, working fifo"; 541 else 542 fifo_msg = "ns16550a, working fifo"; 543 } 544 545 /* 546 * TL16C750 can enable 64byte FIFO, only when DLAB 547 * is 1. However, some 16750 may always enable. For 548 * example, restrictions according to DLAB in a data 549 * sheet for SC16C750 were not described. 550 * Please enable 'options COM_16650', supposing you 551 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 552 * should become effective. 553 */ 554 if (sc->sc_type == COM_TYPE_16750) { 555 uint8_t iir1, iir2; 556 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 557 558 lcr = CSR_READ_1(regsp, COM_REG_LCR); 559 CSR_WRITE_1(regsp, COM_REG_LCR, 560 lcr & ~LCR_DLAB); 561 CSR_WRITE_1(regsp, COM_REG_FIFO, 562 fcr | FIFO_64B_ENABLE); 563 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 564 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 565 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 566 CSR_WRITE_1(regsp, COM_REG_FIFO, 567 fcr | FIFO_64B_ENABLE); 568 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 569 570 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 571 572 if (!ISSET(iir1, IIR_64B_FIFO) && 573 ISSET(iir2, IIR_64B_FIFO)) { 574 /* It is TL16C750. */ 575 sc->sc_fifolen = 64; 576 SET(sc->sc_hwflags, COM_HW_AFE); 577 } else 578 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 579 580 if (sc->sc_fifolen == 64) 581 fifo_msg = "tl16c750, working fifo"; 582 else 583 fifo_msg = "ns16750, working fifo"; 584 } 585 } else 586 fifo_msg = "ns16550, broken fifo"; 587 else 588 fifo_msg = "ns8250 or ns16450, no fifo"; 589 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 590 591 fifodelay: 592 /* 593 * Some chips will clear down both Tx and Rx FIFOs when zero is 594 * written to com_fifo. If this chip is the console, writing zero 595 * results in some of the chip/FIFO description being lost, so delay 596 * printing it until now. 597 */ 598 delay(10); 599 aprint_normal(": %s\n", fifo_msg); 600 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 601 sc->sc_fifolen = 1; 602 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 603 } 604 605 fifodone: 606 607 tp = tty_alloc(); 608 tp->t_oproc = comstart; 609 tp->t_param = comparam; 610 tp->t_hwiflow = comhwiflow; 611 tp->t_softc = sc; 612 613 sc->sc_tty = tp; 614 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 615 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 616 sc->sc_rbavail = com_rbuf_size; 617 if (sc->sc_rbuf == NULL) { 618 aprint_error_dev(sc->sc_dev, 619 "unable to allocate ring buffer\n"); 620 return; 621 } 622 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 623 624 tty_attach(tp); 625 626 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 627 SET(sc->sc_mcr, MCR_IENABLE); 628 629 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 630 int maj; 631 632 /* locate the major number */ 633 maj = cdevsw_lookup_major(&com_cdevsw); 634 635 tp->t_dev = cn_tab->cn_dev = makedev(maj, 636 device_unit(sc->sc_dev)); 637 638 aprint_normal_dev(sc->sc_dev, "console\n"); 639 } 640 641 #ifdef KGDB 642 /* 643 * Allow kgdb to "take over" this port. If this is 644 * not the console and is the kgdb device, it has 645 * exclusive use. If it's the console _and_ the 646 * kgdb device, it doesn't. 647 */ 648 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 649 regsp->cr_iobase == comkgdbregs.cr_iobase) { 650 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 651 com_kgdb_attached = 1; 652 653 SET(sc->sc_hwflags, COM_HW_KGDB); 654 } 655 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 656 } 657 #endif 658 659 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 660 661 #ifdef RND_COM 662 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 663 RND_TYPE_TTY, RND_FLAG_DEFAULT); 664 #endif 665 666 /* if there are no enable/disable functions, assume the device 667 is always enabled */ 668 if (!sc->enable) 669 sc->enabled = 1; 670 671 com_config(sc); 672 673 SET(sc->sc_hwflags, COM_HW_DEV_OK); 674 } 675 676 void 677 com_config(struct com_softc *sc) 678 { 679 struct com_regs *regsp = &sc->sc_regs; 680 681 /* Disable interrupts before configuring the device. */ 682 if (sc->sc_type == COM_TYPE_PXA2x0) 683 sc->sc_ier = IER_EUART; 684 else 685 sc->sc_ier = 0; 686 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 687 (void) CSR_READ_1(regsp, COM_REG_IIR); 688 689 /* Look for a Hayes ESP board. */ 690 if (sc->sc_type == COM_TYPE_HAYESP) { 691 692 /* Set 16550 compatibility mode */ 693 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 694 HAYESP_SETMODE); 695 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 696 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 697 HAYESP_MODE_SCALE); 698 699 /* Set RTS/CTS flow control */ 700 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 701 HAYESP_SETFLOWTYPE); 702 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 703 HAYESP_FLOW_RTS); 704 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 705 HAYESP_FLOW_CTS); 706 707 /* Set flow control levels */ 708 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 709 HAYESP_SETRXFLOW); 710 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 711 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 712 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 713 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 714 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 715 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 716 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 717 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 718 } 719 720 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 721 com_enable_debugport(sc); 722 } 723 724 #if 0 725 static int 726 comcngetc_detached(dev_t dev) 727 { 728 return 0; 729 } 730 731 static void 732 comcnputc_detached(dev_t dev, int c) 733 { 734 } 735 #endif 736 737 int 738 com_detach(device_t self, int flags) 739 { 740 struct com_softc *sc = device_private(self); 741 int maj, mn; 742 743 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 744 return EBUSY; 745 746 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 747 (flags & DETACH_SHUTDOWN) != 0) 748 return EBUSY; 749 750 if (sc->disable != NULL && sc->enabled != 0) { 751 (*sc->disable)(sc); 752 sc->enabled = 0; 753 } 754 755 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 756 comconsattached = 0; 757 cn_tab = NULL; 758 } 759 760 /* locate the major number */ 761 maj = cdevsw_lookup_major(&com_cdevsw); 762 763 /* Nuke the vnodes for any open instances. */ 764 mn = device_unit(self); 765 vdevgone(maj, mn, mn, VCHR); 766 767 mn |= COMDIALOUT_MASK; 768 vdevgone(maj, mn, mn, VCHR); 769 770 if (sc->sc_rbuf == NULL) { 771 /* 772 * Ring buffer allocation failed in the com_attach_subr, 773 * only the tty is allocated, and nothing else. 774 */ 775 tty_free(sc->sc_tty); 776 return 0; 777 } 778 779 /* Free the receive buffer. */ 780 free(sc->sc_rbuf, M_DEVBUF); 781 782 /* Detach and free the tty. */ 783 tty_detach(sc->sc_tty); 784 tty_free(sc->sc_tty); 785 786 /* Unhook the soft interrupt handler. */ 787 softint_disestablish(sc->sc_si); 788 789 #ifdef RND_COM 790 /* Unhook the entropy source. */ 791 rnd_detach_source(&sc->rnd_source); 792 #endif 793 callout_destroy(&sc->sc_diag_callout); 794 795 /* Destroy the lock. */ 796 mutex_destroy(&sc->sc_lock); 797 798 return (0); 799 } 800 801 void 802 com_shutdown(struct com_softc *sc) 803 { 804 struct tty *tp = sc->sc_tty; 805 806 mutex_spin_enter(&sc->sc_lock); 807 808 /* If we were asserting flow control, then deassert it. */ 809 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 810 com_hwiflow(sc); 811 812 /* Clear any break condition set with TIOCSBRK. */ 813 com_break(sc, 0); 814 815 /* 816 * Hang up if necessary. Wait a bit, so the other side has time to 817 * notice even if we immediately open the port again. 818 * Avoid tsleeping above splhigh(). 819 */ 820 if (ISSET(tp->t_cflag, HUPCL)) { 821 com_modem(sc, 0); 822 mutex_spin_exit(&sc->sc_lock); 823 /* XXX will only timeout */ 824 (void) kpause(ttclos, false, hz, NULL); 825 mutex_spin_enter(&sc->sc_lock); 826 } 827 828 /* Turn off interrupts. */ 829 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 830 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 831 if ((sc->sc_type == COM_TYPE_PXA2x0) || 832 (sc->sc_type == COM_TYPE_INGENIC) || 833 (sc->sc_type == COM_TYPE_TEGRA)) 834 sc->sc_ier |= IER_ERXTOUT; 835 } else 836 sc->sc_ier = 0; 837 838 if (sc->sc_type == COM_TYPE_PXA2x0) 839 sc->sc_ier |= IER_EUART; 840 841 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 842 843 mutex_spin_exit(&sc->sc_lock); 844 845 if (sc->disable) { 846 #ifdef DIAGNOSTIC 847 if (!sc->enabled) 848 panic("com_shutdown: not enabled?"); 849 #endif 850 (*sc->disable)(sc); 851 sc->enabled = 0; 852 } 853 } 854 855 int 856 comopen(dev_t dev, int flag, int mode, struct lwp *l) 857 { 858 struct com_softc *sc; 859 struct tty *tp; 860 int s; 861 int error; 862 863 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 864 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 865 sc->sc_rbuf == NULL) 866 return (ENXIO); 867 868 if (!device_is_active(sc->sc_dev)) 869 return (ENXIO); 870 871 #ifdef KGDB 872 /* 873 * If this is the kgdb port, no other use is permitted. 874 */ 875 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 876 return (EBUSY); 877 #endif 878 879 tp = sc->sc_tty; 880 881 /* 882 * If the device is exclusively for kernel use, deny userland 883 * open. 884 */ 885 if (ISSET(tp->t_state, TS_KERN_ONLY)) 886 return (EBUSY); 887 888 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 889 return (EBUSY); 890 891 s = spltty(); 892 893 /* 894 * Do the following iff this is a first open. 895 */ 896 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 897 struct termios t; 898 899 tp->t_dev = dev; 900 901 if (sc->enable) { 902 if ((*sc->enable)(sc)) { 903 splx(s); 904 aprint_error_dev(sc->sc_dev, 905 "device enable failed\n"); 906 return (EIO); 907 } 908 mutex_spin_enter(&sc->sc_lock); 909 sc->enabled = 1; 910 com_config(sc); 911 } else { 912 mutex_spin_enter(&sc->sc_lock); 913 } 914 915 /* Turn on interrupts. */ 916 sc->sc_ier = IER_ERXRDY | IER_ERLS; 917 if (!ISSET(tp->t_cflag, CLOCAL)) 918 sc->sc_ier |= IER_EMSC; 919 920 if (sc->sc_type == COM_TYPE_PXA2x0) 921 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 922 else if (sc->sc_type == COM_TYPE_INGENIC || 923 sc->sc_type == COM_TYPE_TEGRA) 924 sc->sc_ier |= IER_ERXTOUT; 925 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 926 927 /* Fetch the current modem control status, needed later. */ 928 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 929 930 /* Clear PPS capture state on first open. */ 931 mutex_spin_enter(&timecounter_lock); 932 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 933 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 934 pps_init(&sc->sc_pps_state); 935 mutex_spin_exit(&timecounter_lock); 936 937 mutex_spin_exit(&sc->sc_lock); 938 939 /* 940 * Initialize the termios status to the defaults. Add in the 941 * sticky bits from TIOCSFLAGS. 942 */ 943 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 944 t.c_ospeed = comcons_info.rate; 945 t.c_cflag = comcons_info.cflag; 946 } else { 947 t.c_ospeed = TTYDEF_SPEED; 948 t.c_cflag = TTYDEF_CFLAG; 949 } 950 t.c_ispeed = t.c_ospeed; 951 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 952 SET(t.c_cflag, CLOCAL); 953 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 954 SET(t.c_cflag, CRTSCTS); 955 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 956 SET(t.c_cflag, MDMBUF); 957 /* Make sure comparam() will do something. */ 958 tp->t_ospeed = 0; 959 (void) comparam(tp, &t); 960 tp->t_iflag = TTYDEF_IFLAG; 961 tp->t_oflag = TTYDEF_OFLAG; 962 tp->t_lflag = TTYDEF_LFLAG; 963 ttychars(tp); 964 ttsetwater(tp); 965 966 mutex_spin_enter(&sc->sc_lock); 967 968 /* 969 * Turn on DTR. We must always do this, even if carrier is not 970 * present, because otherwise we'd have to use TIOCSDTR 971 * immediately after setting CLOCAL, which applications do not 972 * expect. We always assert DTR while the device is open 973 * unless explicitly requested to deassert it. 974 */ 975 com_modem(sc, 1); 976 977 /* Clear the input ring, and unblock. */ 978 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 979 sc->sc_rbavail = com_rbuf_size; 980 com_iflush(sc); 981 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 982 com_hwiflow(sc); 983 984 #ifdef COM_DEBUG 985 if (com_debug) 986 comstatus(sc, "comopen "); 987 #endif 988 989 mutex_spin_exit(&sc->sc_lock); 990 } 991 992 splx(s); 993 994 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 995 if (error) 996 goto bad; 997 998 error = (*tp->t_linesw->l_open)(dev, tp); 999 if (error) 1000 goto bad; 1001 1002 return (0); 1003 1004 bad: 1005 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1006 /* 1007 * We failed to open the device, and nobody else had it opened. 1008 * Clean up the state as appropriate. 1009 */ 1010 com_shutdown(sc); 1011 } 1012 1013 return (error); 1014 } 1015 1016 int 1017 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1018 { 1019 struct com_softc *sc = 1020 device_lookup_private(&com_cd, COMUNIT(dev)); 1021 struct tty *tp = sc->sc_tty; 1022 1023 /* XXX This is for cons.c. */ 1024 if (!ISSET(tp->t_state, TS_ISOPEN)) 1025 return (0); 1026 /* 1027 * If the device is exclusively for kernel use, deny userland 1028 * close. 1029 */ 1030 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1031 return (0); 1032 1033 (*tp->t_linesw->l_close)(tp, flag); 1034 ttyclose(tp); 1035 1036 if (COM_ISALIVE(sc) == 0) 1037 return (0); 1038 1039 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1040 /* 1041 * Although we got a last close, the device may still be in 1042 * use; e.g. if this was the dialout node, and there are still 1043 * processes waiting for carrier on the non-dialout node. 1044 */ 1045 com_shutdown(sc); 1046 } 1047 1048 return (0); 1049 } 1050 1051 int 1052 comread(dev_t dev, struct uio *uio, int flag) 1053 { 1054 struct com_softc *sc = 1055 device_lookup_private(&com_cd, COMUNIT(dev)); 1056 struct tty *tp = sc->sc_tty; 1057 1058 if (COM_ISALIVE(sc) == 0) 1059 return (EIO); 1060 1061 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1062 } 1063 1064 int 1065 comwrite(dev_t dev, struct uio *uio, int flag) 1066 { 1067 struct com_softc *sc = 1068 device_lookup_private(&com_cd, COMUNIT(dev)); 1069 struct tty *tp = sc->sc_tty; 1070 1071 if (COM_ISALIVE(sc) == 0) 1072 return (EIO); 1073 1074 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1075 } 1076 1077 int 1078 compoll(dev_t dev, int events, struct lwp *l) 1079 { 1080 struct com_softc *sc = 1081 device_lookup_private(&com_cd, COMUNIT(dev)); 1082 struct tty *tp = sc->sc_tty; 1083 1084 if (COM_ISALIVE(sc) == 0) 1085 return (POLLHUP); 1086 1087 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1088 } 1089 1090 struct tty * 1091 comtty(dev_t dev) 1092 { 1093 struct com_softc *sc = 1094 device_lookup_private(&com_cd, COMUNIT(dev)); 1095 struct tty *tp = sc->sc_tty; 1096 1097 return (tp); 1098 } 1099 1100 int 1101 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1102 { 1103 struct com_softc *sc; 1104 struct tty *tp; 1105 int error; 1106 1107 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1108 if (sc == NULL) 1109 return ENXIO; 1110 if (COM_ISALIVE(sc) == 0) 1111 return (EIO); 1112 1113 tp = sc->sc_tty; 1114 1115 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1116 if (error != EPASSTHROUGH) 1117 return (error); 1118 1119 error = ttioctl(tp, cmd, data, flag, l); 1120 if (error != EPASSTHROUGH) 1121 return (error); 1122 1123 error = 0; 1124 switch (cmd) { 1125 case TIOCSFLAGS: 1126 error = kauth_authorize_device_tty(l->l_cred, 1127 KAUTH_DEVICE_TTY_PRIVSET, tp); 1128 break; 1129 default: 1130 /* nothing */ 1131 break; 1132 } 1133 if (error) { 1134 return error; 1135 } 1136 1137 mutex_spin_enter(&sc->sc_lock); 1138 1139 switch (cmd) { 1140 case TIOCSBRK: 1141 com_break(sc, 1); 1142 break; 1143 1144 case TIOCCBRK: 1145 com_break(sc, 0); 1146 break; 1147 1148 case TIOCSDTR: 1149 com_modem(sc, 1); 1150 break; 1151 1152 case TIOCCDTR: 1153 com_modem(sc, 0); 1154 break; 1155 1156 case TIOCGFLAGS: 1157 *(int *)data = sc->sc_swflags; 1158 break; 1159 1160 case TIOCSFLAGS: 1161 sc->sc_swflags = *(int *)data; 1162 break; 1163 1164 case TIOCMSET: 1165 case TIOCMBIS: 1166 case TIOCMBIC: 1167 tiocm_to_com(sc, cmd, *(int *)data); 1168 break; 1169 1170 case TIOCMGET: 1171 *(int *)data = com_to_tiocm(sc); 1172 break; 1173 1174 case PPS_IOC_CREATE: 1175 case PPS_IOC_DESTROY: 1176 case PPS_IOC_GETPARAMS: 1177 case PPS_IOC_SETPARAMS: 1178 case PPS_IOC_GETCAP: 1179 case PPS_IOC_FETCH: 1180 #ifdef PPS_SYNC 1181 case PPS_IOC_KCBIND: 1182 #endif 1183 mutex_spin_enter(&timecounter_lock); 1184 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1185 mutex_spin_exit(&timecounter_lock); 1186 break; 1187 1188 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1189 mutex_spin_enter(&timecounter_lock); 1190 #ifndef PPS_TRAILING_EDGE 1191 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1192 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1193 #else 1194 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1195 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1196 #endif 1197 mutex_spin_exit(&timecounter_lock); 1198 break; 1199 1200 default: 1201 error = EPASSTHROUGH; 1202 break; 1203 } 1204 1205 mutex_spin_exit(&sc->sc_lock); 1206 1207 #ifdef COM_DEBUG 1208 if (com_debug) 1209 comstatus(sc, "comioctl "); 1210 #endif 1211 1212 return (error); 1213 } 1214 1215 integrate void 1216 com_schedrx(struct com_softc *sc) 1217 { 1218 1219 sc->sc_rx_ready = 1; 1220 1221 /* Wake up the poller. */ 1222 softint_schedule(sc->sc_si); 1223 } 1224 1225 void 1226 com_break(struct com_softc *sc, int onoff) 1227 { 1228 1229 if (onoff) 1230 SET(sc->sc_lcr, LCR_SBREAK); 1231 else 1232 CLR(sc->sc_lcr, LCR_SBREAK); 1233 1234 if (!sc->sc_heldchange) { 1235 if (sc->sc_tx_busy) { 1236 sc->sc_heldtbc = sc->sc_tbc; 1237 sc->sc_tbc = 0; 1238 sc->sc_heldchange = 1; 1239 } else 1240 com_loadchannelregs(sc); 1241 } 1242 } 1243 1244 void 1245 com_modem(struct com_softc *sc, int onoff) 1246 { 1247 1248 if (sc->sc_mcr_dtr == 0) 1249 return; 1250 1251 if (onoff) 1252 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1253 else 1254 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1255 1256 if (!sc->sc_heldchange) { 1257 if (sc->sc_tx_busy) { 1258 sc->sc_heldtbc = sc->sc_tbc; 1259 sc->sc_tbc = 0; 1260 sc->sc_heldchange = 1; 1261 } else 1262 com_loadchannelregs(sc); 1263 } 1264 } 1265 1266 void 1267 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1268 { 1269 u_char combits; 1270 1271 combits = 0; 1272 if (ISSET(ttybits, TIOCM_DTR)) 1273 SET(combits, MCR_DTR); 1274 if (ISSET(ttybits, TIOCM_RTS)) 1275 SET(combits, MCR_RTS); 1276 1277 switch (how) { 1278 case TIOCMBIC: 1279 CLR(sc->sc_mcr, combits); 1280 break; 1281 1282 case TIOCMBIS: 1283 SET(sc->sc_mcr, combits); 1284 break; 1285 1286 case TIOCMSET: 1287 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1288 SET(sc->sc_mcr, combits); 1289 break; 1290 } 1291 1292 if (!sc->sc_heldchange) { 1293 if (sc->sc_tx_busy) { 1294 sc->sc_heldtbc = sc->sc_tbc; 1295 sc->sc_tbc = 0; 1296 sc->sc_heldchange = 1; 1297 } else 1298 com_loadchannelregs(sc); 1299 } 1300 } 1301 1302 int 1303 com_to_tiocm(struct com_softc *sc) 1304 { 1305 u_char combits; 1306 int ttybits = 0; 1307 1308 combits = sc->sc_mcr; 1309 if (ISSET(combits, MCR_DTR)) 1310 SET(ttybits, TIOCM_DTR); 1311 if (ISSET(combits, MCR_RTS)) 1312 SET(ttybits, TIOCM_RTS); 1313 1314 combits = sc->sc_msr; 1315 if (sc->sc_type == COM_TYPE_INGENIC) { 1316 SET(ttybits, TIOCM_CD); 1317 } else { 1318 if (ISSET(combits, MSR_DCD)) 1319 SET(ttybits, TIOCM_CD); 1320 } 1321 if (ISSET(combits, MSR_CTS)) 1322 SET(ttybits, TIOCM_CTS); 1323 if (ISSET(combits, MSR_DSR)) 1324 SET(ttybits, TIOCM_DSR); 1325 if (ISSET(combits, MSR_RI | MSR_TERI)) 1326 SET(ttybits, TIOCM_RI); 1327 1328 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1329 SET(ttybits, TIOCM_LE); 1330 1331 return (ttybits); 1332 } 1333 1334 static u_char 1335 cflag2lcr(tcflag_t cflag) 1336 { 1337 u_char lcr = 0; 1338 1339 switch (ISSET(cflag, CSIZE)) { 1340 case CS5: 1341 SET(lcr, LCR_5BITS); 1342 break; 1343 case CS6: 1344 SET(lcr, LCR_6BITS); 1345 break; 1346 case CS7: 1347 SET(lcr, LCR_7BITS); 1348 break; 1349 case CS8: 1350 SET(lcr, LCR_8BITS); 1351 break; 1352 } 1353 if (ISSET(cflag, PARENB)) { 1354 SET(lcr, LCR_PENAB); 1355 if (!ISSET(cflag, PARODD)) 1356 SET(lcr, LCR_PEVEN); 1357 } 1358 if (ISSET(cflag, CSTOPB)) 1359 SET(lcr, LCR_STOPB); 1360 1361 return (lcr); 1362 } 1363 1364 int 1365 comparam(struct tty *tp, struct termios *t) 1366 { 1367 struct com_softc *sc = 1368 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1369 int ospeed; 1370 u_char lcr; 1371 1372 if (COM_ISALIVE(sc) == 0) 1373 return (EIO); 1374 1375 if (sc->sc_type == COM_TYPE_HAYESP) { 1376 int prescaler, speed; 1377 1378 /* 1379 * Calculate UART clock prescaler. It should be in 1380 * range of 0 .. 3. 1381 */ 1382 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1383 prescaler++, speed /= 2) 1384 if ((ospeed = comspeed(speed, sc->sc_frequency, 1385 sc->sc_type)) > 0) 1386 break; 1387 1388 if (prescaler == 4) 1389 return (EINVAL); 1390 sc->sc_prescaler = prescaler; 1391 } else 1392 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1393 1394 /* Check requested parameters. */ 1395 if (ospeed < 0) 1396 return (EINVAL); 1397 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1398 return (EINVAL); 1399 1400 /* 1401 * For the console, always force CLOCAL and !HUPCL, so that the port 1402 * is always active. 1403 */ 1404 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1405 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1406 SET(t->c_cflag, CLOCAL); 1407 CLR(t->c_cflag, HUPCL); 1408 } 1409 1410 /* 1411 * If there were no changes, don't do anything. This avoids dropping 1412 * input and improves performance when all we did was frob things like 1413 * VMIN and VTIME. 1414 */ 1415 if (tp->t_ospeed == t->c_ospeed && 1416 tp->t_cflag == t->c_cflag) 1417 return (0); 1418 1419 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1420 1421 mutex_spin_enter(&sc->sc_lock); 1422 1423 sc->sc_lcr = lcr; 1424 1425 /* 1426 * If we're not in a mode that assumes a connection is present, then 1427 * ignore carrier changes. 1428 */ 1429 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1430 sc->sc_msr_dcd = 0; 1431 else 1432 sc->sc_msr_dcd = MSR_DCD; 1433 /* 1434 * Set the flow control pins depending on the current flow control 1435 * mode. 1436 */ 1437 if (ISSET(t->c_cflag, CRTSCTS)) { 1438 sc->sc_mcr_dtr = MCR_DTR; 1439 sc->sc_mcr_rts = MCR_RTS; 1440 sc->sc_msr_cts = MSR_CTS; 1441 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1442 SET(sc->sc_mcr, MCR_AFE); 1443 } else { 1444 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1445 } 1446 } else if (ISSET(t->c_cflag, MDMBUF)) { 1447 /* 1448 * For DTR/DCD flow control, make sure we don't toggle DTR for 1449 * carrier detection. 1450 */ 1451 sc->sc_mcr_dtr = 0; 1452 sc->sc_mcr_rts = MCR_DTR; 1453 sc->sc_msr_cts = MSR_DCD; 1454 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1455 CLR(sc->sc_mcr, MCR_AFE); 1456 } else { 1457 sc->sc_efr = 0; 1458 } 1459 } else { 1460 /* 1461 * If no flow control, then always set RTS. This will make 1462 * the other side happy if it mistakenly thinks we're doing 1463 * RTS/CTS flow control. 1464 */ 1465 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1466 sc->sc_mcr_rts = 0; 1467 sc->sc_msr_cts = 0; 1468 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1469 CLR(sc->sc_mcr, MCR_AFE); 1470 } else { 1471 sc->sc_efr = 0; 1472 } 1473 if (ISSET(sc->sc_mcr, MCR_DTR)) 1474 SET(sc->sc_mcr, MCR_RTS); 1475 else 1476 CLR(sc->sc_mcr, MCR_RTS); 1477 } 1478 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1479 1480 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1481 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1482 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1483 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1484 1485 sc->sc_dlbl = ospeed; 1486 sc->sc_dlbh = ospeed >> 8; 1487 1488 /* 1489 * Set the FIFO threshold based on the receive speed. 1490 * 1491 * * If it's a low speed, it's probably a mouse or some other 1492 * interactive device, so set the threshold low. 1493 * * If it's a high speed, trim the trigger level down to prevent 1494 * overflows. 1495 * * Otherwise set it a bit higher. 1496 */ 1497 if (sc->sc_type == COM_TYPE_HAYESP) { 1498 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1499 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1500 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1501 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1502 if (t->c_ospeed <= 1200) 1503 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1504 else if (t->c_ospeed <= 38400) 1505 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1506 else 1507 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1508 } else { 1509 sc->sc_fifo = 0; 1510 } 1511 1512 if (sc->sc_type == COM_TYPE_INGENIC) 1513 sc->sc_fifo |= FIFO_UART_ON; 1514 1515 /* And copy to tty. */ 1516 tp->t_ispeed = t->c_ospeed; 1517 tp->t_ospeed = t->c_ospeed; 1518 tp->t_cflag = t->c_cflag; 1519 1520 if (!sc->sc_heldchange) { 1521 if (sc->sc_tx_busy) { 1522 sc->sc_heldtbc = sc->sc_tbc; 1523 sc->sc_tbc = 0; 1524 sc->sc_heldchange = 1; 1525 } else 1526 com_loadchannelregs(sc); 1527 } 1528 1529 if (!ISSET(t->c_cflag, CHWFLOW)) { 1530 /* Disable the high water mark. */ 1531 sc->sc_r_hiwat = 0; 1532 sc->sc_r_lowat = 0; 1533 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1534 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1535 com_schedrx(sc); 1536 } 1537 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1538 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1539 com_hwiflow(sc); 1540 } 1541 } else { 1542 sc->sc_r_hiwat = com_rbuf_hiwat; 1543 sc->sc_r_lowat = com_rbuf_lowat; 1544 } 1545 1546 mutex_spin_exit(&sc->sc_lock); 1547 1548 /* 1549 * Update the tty layer's idea of the carrier bit, in case we changed 1550 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1551 * explicit request. 1552 */ 1553 if (sc->sc_type == COM_TYPE_INGENIC) { 1554 /* no DCD here */ 1555 (void) (*tp->t_linesw->l_modem)(tp, 1); 1556 } else 1557 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1558 1559 #ifdef COM_DEBUG 1560 if (com_debug) 1561 comstatus(sc, "comparam "); 1562 #endif 1563 1564 if (!ISSET(t->c_cflag, CHWFLOW)) { 1565 if (sc->sc_tx_stopped) { 1566 sc->sc_tx_stopped = 0; 1567 comstart(tp); 1568 } 1569 } 1570 1571 return (0); 1572 } 1573 1574 void 1575 com_iflush(struct com_softc *sc) 1576 { 1577 struct com_regs *regsp = &sc->sc_regs; 1578 uint8_t fifo; 1579 #ifdef DIAGNOSTIC 1580 int reg; 1581 #endif 1582 int timo; 1583 1584 #ifdef DIAGNOSTIC 1585 reg = 0xffff; 1586 #endif 1587 timo = 50000; 1588 /* flush any pending I/O */ 1589 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1590 && --timo) 1591 #ifdef DIAGNOSTIC 1592 reg = 1593 #else 1594 (void) 1595 #endif 1596 CSR_READ_1(regsp, COM_REG_RXDATA); 1597 #ifdef DIAGNOSTIC 1598 if (!timo) 1599 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1600 #endif 1601 1602 switch (sc->sc_type) { 1603 case COM_TYPE_16750: 1604 case COM_TYPE_DW_APB: 1605 /* 1606 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1607 * This should prevent triggering busy interrupt while 1608 * manipulating divisors. 1609 */ 1610 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1611 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1612 CSR_WRITE_1(regsp, COM_REG_FIFO, 1613 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1614 delay(100); 1615 break; 1616 } 1617 } 1618 1619 void 1620 com_loadchannelregs(struct com_softc *sc) 1621 { 1622 struct com_regs *regsp = &sc->sc_regs; 1623 1624 /* XXXXX necessary? */ 1625 com_iflush(sc); 1626 1627 if (sc->sc_type == COM_TYPE_PXA2x0) 1628 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1629 else 1630 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1631 1632 if (sc->sc_type == COM_TYPE_OMAP) { 1633 /* disable before changing settings */ 1634 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1635 } 1636 1637 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1638 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1639 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1640 /* no EFR on alchemy */ 1641 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1642 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1643 } 1644 if (sc->sc_type == COM_TYPE_AU1x00) { 1645 /* alchemy has single separate 16-bit clock divisor register */ 1646 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1647 (sc->sc_dlbh << 8)); 1648 } else { 1649 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1650 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1651 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1652 } 1653 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1654 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1655 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1656 if (sc->sc_type == COM_TYPE_HAYESP) { 1657 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1658 HAYESP_SETPRESCALER); 1659 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1660 sc->sc_prescaler); 1661 } 1662 if (sc->sc_type == COM_TYPE_OMAP) { 1663 /* setup the fifos. the FCR value is not used as long 1664 as SCR[6] and SCR[7] are 0, which they are at reset 1665 and we never touch the SCR register */ 1666 uint8_t rx_fifo_trig = 40; 1667 uint8_t tx_fifo_trig = 60; 1668 uint8_t rx_start = 8; 1669 uint8_t rx_halt = 60; 1670 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1671 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1672 1673 /* enable access to TCR & TLR */ 1674 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1675 1676 /* write tcr and tlr values */ 1677 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1678 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1679 1680 /* disable access to TCR & TLR */ 1681 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1682 1683 /* enable again, but mode is based on speed */ 1684 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1685 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1686 } else { 1687 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1688 } 1689 } 1690 1691 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1692 } 1693 1694 int 1695 comhwiflow(struct tty *tp, int block) 1696 { 1697 struct com_softc *sc = 1698 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1699 1700 if (COM_ISALIVE(sc) == 0) 1701 return (0); 1702 1703 if (sc->sc_mcr_rts == 0) 1704 return (0); 1705 1706 mutex_spin_enter(&sc->sc_lock); 1707 1708 if (block) { 1709 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1710 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1711 com_hwiflow(sc); 1712 } 1713 } else { 1714 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1715 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1716 com_schedrx(sc); 1717 } 1718 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1719 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1720 com_hwiflow(sc); 1721 } 1722 } 1723 1724 mutex_spin_exit(&sc->sc_lock); 1725 return (1); 1726 } 1727 1728 /* 1729 * (un)block input via hw flowcontrol 1730 */ 1731 void 1732 com_hwiflow(struct com_softc *sc) 1733 { 1734 struct com_regs *regsp= &sc->sc_regs; 1735 1736 if (sc->sc_mcr_rts == 0) 1737 return; 1738 1739 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1740 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1741 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1742 } else { 1743 SET(sc->sc_mcr, sc->sc_mcr_rts); 1744 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1745 } 1746 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1747 } 1748 1749 1750 void 1751 comstart(struct tty *tp) 1752 { 1753 struct com_softc *sc = 1754 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1755 struct com_regs *regsp = &sc->sc_regs; 1756 int s; 1757 1758 if (COM_ISALIVE(sc) == 0) 1759 return; 1760 1761 s = spltty(); 1762 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1763 goto out; 1764 if (sc->sc_tx_stopped) 1765 goto out; 1766 if (!ttypull(tp)) 1767 goto out; 1768 1769 /* Grab the first contiguous region of buffer space. */ 1770 { 1771 u_char *tba; 1772 int tbc; 1773 1774 tba = tp->t_outq.c_cf; 1775 tbc = ndqb(&tp->t_outq, 0); 1776 1777 mutex_spin_enter(&sc->sc_lock); 1778 1779 sc->sc_tba = tba; 1780 sc->sc_tbc = tbc; 1781 } 1782 1783 SET(tp->t_state, TS_BUSY); 1784 sc->sc_tx_busy = 1; 1785 1786 /* Enable transmit completion interrupts if necessary. */ 1787 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1788 SET(sc->sc_ier, IER_ETXRDY); 1789 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1790 } 1791 1792 /* Output the first chunk of the contiguous buffer. */ 1793 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1794 u_int n; 1795 1796 n = sc->sc_tbc; 1797 if (n > sc->sc_fifolen) 1798 n = sc->sc_fifolen; 1799 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1800 sc->sc_tbc -= n; 1801 sc->sc_tba += n; 1802 } 1803 1804 mutex_spin_exit(&sc->sc_lock); 1805 out: 1806 splx(s); 1807 return; 1808 } 1809 1810 /* 1811 * Stop output on a line. 1812 */ 1813 void 1814 comstop(struct tty *tp, int flag) 1815 { 1816 struct com_softc *sc = 1817 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1818 1819 mutex_spin_enter(&sc->sc_lock); 1820 if (ISSET(tp->t_state, TS_BUSY)) { 1821 /* Stop transmitting at the next chunk. */ 1822 sc->sc_tbc = 0; 1823 sc->sc_heldtbc = 0; 1824 if (!ISSET(tp->t_state, TS_TTSTOP)) 1825 SET(tp->t_state, TS_FLUSH); 1826 } 1827 mutex_spin_exit(&sc->sc_lock); 1828 } 1829 1830 void 1831 comdiag(void *arg) 1832 { 1833 struct com_softc *sc = arg; 1834 int overflows, floods; 1835 1836 mutex_spin_enter(&sc->sc_lock); 1837 overflows = sc->sc_overflows; 1838 sc->sc_overflows = 0; 1839 floods = sc->sc_floods; 1840 sc->sc_floods = 0; 1841 sc->sc_errors = 0; 1842 mutex_spin_exit(&sc->sc_lock); 1843 1844 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1845 device_xname(sc->sc_dev), 1846 overflows, overflows == 1 ? "" : "s", 1847 floods, floods == 1 ? "" : "s"); 1848 } 1849 1850 integrate void 1851 com_rxsoft(struct com_softc *sc, struct tty *tp) 1852 { 1853 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1854 u_char *get, *end; 1855 u_int cc, scc; 1856 u_char lsr; 1857 int code; 1858 1859 end = sc->sc_ebuf; 1860 get = sc->sc_rbget; 1861 scc = cc = com_rbuf_size - sc->sc_rbavail; 1862 1863 if (cc == com_rbuf_size) { 1864 sc->sc_floods++; 1865 if (sc->sc_errors++ == 0) 1866 callout_reset(&sc->sc_diag_callout, 60 * hz, 1867 comdiag, sc); 1868 } 1869 1870 /* If not yet open, drop the entire buffer content here */ 1871 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1872 get += cc << 1; 1873 if (get >= end) 1874 get -= com_rbuf_size << 1; 1875 cc = 0; 1876 } 1877 while (cc) { 1878 code = get[0]; 1879 lsr = get[1]; 1880 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1881 if (ISSET(lsr, LSR_OE)) { 1882 sc->sc_overflows++; 1883 if (sc->sc_errors++ == 0) 1884 callout_reset(&sc->sc_diag_callout, 1885 60 * hz, comdiag, sc); 1886 } 1887 if (ISSET(lsr, LSR_BI | LSR_FE)) 1888 SET(code, TTY_FE); 1889 if (ISSET(lsr, LSR_PE)) 1890 SET(code, TTY_PE); 1891 } 1892 if ((*rint)(code, tp) == -1) { 1893 /* 1894 * The line discipline's buffer is out of space. 1895 */ 1896 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1897 /* 1898 * We're either not using flow control, or the 1899 * line discipline didn't tell us to block for 1900 * some reason. Either way, we have no way to 1901 * know when there's more space available, so 1902 * just drop the rest of the data. 1903 */ 1904 get += cc << 1; 1905 if (get >= end) 1906 get -= com_rbuf_size << 1; 1907 cc = 0; 1908 } else { 1909 /* 1910 * Don't schedule any more receive processing 1911 * until the line discipline tells us there's 1912 * space available (through comhwiflow()). 1913 * Leave the rest of the data in the input 1914 * buffer. 1915 */ 1916 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1917 } 1918 break; 1919 } 1920 get += 2; 1921 if (get >= end) 1922 get = sc->sc_rbuf; 1923 cc--; 1924 } 1925 1926 if (cc != scc) { 1927 sc->sc_rbget = get; 1928 mutex_spin_enter(&sc->sc_lock); 1929 1930 cc = sc->sc_rbavail += scc - cc; 1931 /* Buffers should be ok again, release possible block. */ 1932 if (cc >= sc->sc_r_lowat) { 1933 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1934 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1935 SET(sc->sc_ier, IER_ERXRDY); 1936 if (sc->sc_type == COM_TYPE_PXA2x0) 1937 SET(sc->sc_ier, IER_ERXTOUT); 1938 if (sc->sc_type == COM_TYPE_INGENIC || 1939 sc->sc_type == COM_TYPE_TEGRA) 1940 SET(sc->sc_ier, IER_ERXTOUT); 1941 1942 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 1943 sc->sc_ier); 1944 } 1945 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1946 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1947 com_hwiflow(sc); 1948 } 1949 } 1950 mutex_spin_exit(&sc->sc_lock); 1951 } 1952 } 1953 1954 integrate void 1955 com_txsoft(struct com_softc *sc, struct tty *tp) 1956 { 1957 1958 CLR(tp->t_state, TS_BUSY); 1959 if (ISSET(tp->t_state, TS_FLUSH)) 1960 CLR(tp->t_state, TS_FLUSH); 1961 else 1962 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1963 (*tp->t_linesw->l_start)(tp); 1964 } 1965 1966 integrate void 1967 com_stsoft(struct com_softc *sc, struct tty *tp) 1968 { 1969 u_char msr, delta; 1970 1971 mutex_spin_enter(&sc->sc_lock); 1972 msr = sc->sc_msr; 1973 delta = sc->sc_msr_delta; 1974 sc->sc_msr_delta = 0; 1975 mutex_spin_exit(&sc->sc_lock); 1976 1977 if (ISSET(delta, sc->sc_msr_dcd)) { 1978 /* 1979 * Inform the tty layer that carrier detect changed. 1980 */ 1981 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1982 } 1983 1984 if (ISSET(delta, sc->sc_msr_cts)) { 1985 /* Block or unblock output according to flow control. */ 1986 if (ISSET(msr, sc->sc_msr_cts)) { 1987 sc->sc_tx_stopped = 0; 1988 (*tp->t_linesw->l_start)(tp); 1989 } else { 1990 sc->sc_tx_stopped = 1; 1991 } 1992 } 1993 1994 #ifdef COM_DEBUG 1995 if (com_debug) 1996 comstatus(sc, "com_stsoft"); 1997 #endif 1998 } 1999 2000 void 2001 comsoft(void *arg) 2002 { 2003 struct com_softc *sc = arg; 2004 struct tty *tp; 2005 2006 if (COM_ISALIVE(sc) == 0) 2007 return; 2008 2009 tp = sc->sc_tty; 2010 2011 if (sc->sc_rx_ready) { 2012 sc->sc_rx_ready = 0; 2013 com_rxsoft(sc, tp); 2014 } 2015 2016 if (sc->sc_st_check) { 2017 sc->sc_st_check = 0; 2018 com_stsoft(sc, tp); 2019 } 2020 2021 if (sc->sc_tx_done) { 2022 sc->sc_tx_done = 0; 2023 com_txsoft(sc, tp); 2024 } 2025 } 2026 2027 int 2028 comintr(void *arg) 2029 { 2030 struct com_softc *sc = arg; 2031 struct com_regs *regsp = &sc->sc_regs; 2032 2033 u_char *put, *end; 2034 u_int cc; 2035 u_char lsr, iir; 2036 2037 if (COM_ISALIVE(sc) == 0) 2038 return (0); 2039 2040 KASSERT(regsp != NULL); 2041 2042 mutex_spin_enter(&sc->sc_lock); 2043 iir = CSR_READ_1(regsp, COM_REG_IIR); 2044 2045 /* Handle ns16750-specific busy interrupt. */ 2046 if (sc->sc_type == COM_TYPE_16750 && 2047 (iir & IIR_BUSY) == IIR_BUSY) { 2048 for (int timeout = 10000; 2049 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2050 if (timeout <= 0) { 2051 aprint_error_dev(sc->sc_dev, 2052 "timeout while waiting for BUSY interrupt " 2053 "acknowledge\n"); 2054 mutex_spin_exit(&sc->sc_lock); 2055 return (0); 2056 } 2057 2058 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2059 iir = CSR_READ_1(regsp, COM_REG_IIR); 2060 } 2061 2062 /* DesignWare APB UART BUSY interrupt */ 2063 if (sc->sc_type == COM_TYPE_DW_APB && 2064 (iir & IIR_BUSY) == IIR_BUSY) { 2065 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2066 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2067 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2068 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2069 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2070 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2071 CSR_WRITE_1(regsp, COM_REG_HALT, 2072 HALT_CHCFG_EN | HALT_CHCFG_UD); 2073 for (int timeout = 10000000; 2074 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2075 timeout--) { 2076 if (timeout <= 0) { 2077 aprint_error_dev(sc->sc_dev, 2078 "timeout while waiting for HALT " 2079 "update acknowledge 0x%x 0x%x\n", 2080 CSR_READ_1(regsp, COM_REG_HALT), 2081 CSR_READ_1(regsp, COM_REG_USR)); 2082 break; 2083 } 2084 } 2085 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2086 (void)CSR_READ_1(regsp, COM_REG_USR); 2087 } else { 2088 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2089 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2090 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2091 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2092 } 2093 } 2094 2095 if (ISSET(iir, IIR_NOPEND)) { 2096 mutex_spin_exit(&sc->sc_lock); 2097 return (0); 2098 } 2099 2100 end = sc->sc_ebuf; 2101 put = sc->sc_rbput; 2102 cc = sc->sc_rbavail; 2103 2104 again: do { 2105 u_char msr, delta; 2106 2107 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2108 if (ISSET(lsr, LSR_BI)) { 2109 int cn_trapped = 0; /* see above: cn_trap() */ 2110 2111 cn_check_magic(sc->sc_tty->t_dev, 2112 CNC_BREAK, com_cnm_state); 2113 if (cn_trapped) 2114 continue; 2115 #if defined(KGDB) && !defined(DDB) 2116 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2117 kgdb_connect(1); 2118 continue; 2119 } 2120 #endif 2121 } 2122 2123 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2124 lsr |= LSR_RXRDY; 2125 2126 if (ISSET(lsr, LSR_RCV_MASK) && 2127 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2128 while (cc > 0) { 2129 int cn_trapped = 0; 2130 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2131 put[1] = lsr; 2132 cn_check_magic(sc->sc_tty->t_dev, 2133 put[0], com_cnm_state); 2134 if (cn_trapped) 2135 goto next; 2136 put += 2; 2137 if (put >= end) 2138 put = sc->sc_rbuf; 2139 cc--; 2140 next: 2141 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2142 if (!ISSET(lsr, LSR_RCV_MASK)) 2143 break; 2144 } 2145 2146 /* 2147 * Current string of incoming characters ended because 2148 * no more data was available or we ran out of space. 2149 * Schedule a receive event if any data was received. 2150 * If we're out of space, turn off receive interrupts. 2151 */ 2152 sc->sc_rbput = put; 2153 sc->sc_rbavail = cc; 2154 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2155 sc->sc_rx_ready = 1; 2156 2157 /* 2158 * See if we are in danger of overflowing a buffer. If 2159 * so, use hardware flow control to ease the pressure. 2160 */ 2161 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2162 cc < sc->sc_r_hiwat) { 2163 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2164 com_hwiflow(sc); 2165 } 2166 2167 /* 2168 * If we're out of space, disable receive interrupts 2169 * until the queue has drained a bit. 2170 */ 2171 if (!cc) { 2172 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2173 switch (sc->sc_type) { 2174 case COM_TYPE_PXA2x0: 2175 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2176 break; 2177 case COM_TYPE_INGENIC: 2178 case COM_TYPE_TEGRA: 2179 CLR(sc->sc_ier, 2180 IER_ERXRDY | IER_ERXTOUT); 2181 break; 2182 default: 2183 CLR(sc->sc_ier, IER_ERXRDY); 2184 break; 2185 } 2186 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2187 } 2188 } else { 2189 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2190 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2191 continue; 2192 } 2193 } 2194 2195 msr = CSR_READ_1(regsp, COM_REG_MSR); 2196 delta = msr ^ sc->sc_msr; 2197 sc->sc_msr = msr; 2198 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2199 (delta & MSR_DCD)) { 2200 mutex_spin_enter(&timecounter_lock); 2201 pps_capture(&sc->sc_pps_state); 2202 pps_event(&sc->sc_pps_state, 2203 (msr & MSR_DCD) ? 2204 PPS_CAPTUREASSERT : 2205 PPS_CAPTURECLEAR); 2206 mutex_spin_exit(&timecounter_lock); 2207 } 2208 2209 /* 2210 * Process normal status changes 2211 */ 2212 if (ISSET(delta, sc->sc_msr_mask)) { 2213 SET(sc->sc_msr_delta, delta); 2214 2215 /* 2216 * Stop output immediately if we lose the output 2217 * flow control signal or carrier detect. 2218 */ 2219 if (ISSET(~msr, sc->sc_msr_mask)) { 2220 sc->sc_tbc = 0; 2221 sc->sc_heldtbc = 0; 2222 #ifdef COM_DEBUG 2223 if (com_debug) 2224 comstatus(sc, "comintr "); 2225 #endif 2226 } 2227 2228 sc->sc_st_check = 1; 2229 } 2230 } while (!ISSET((iir = 2231 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2232 /* 2233 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2234 * by IIR read, so we can't do this way: `process all interrupts, 2235 * then do TX if possible'. 2236 */ 2237 (iir & IIR_IMASK) != IIR_TXRDY); 2238 2239 /* 2240 * Read LSR again, since there may be an interrupt between 2241 * the last LSR read and IIR read above. 2242 */ 2243 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2244 2245 /* 2246 * See if data can be transmitted as well. 2247 * Schedule tx done event if no data left 2248 * and tty was marked busy. 2249 */ 2250 if (ISSET(lsr, LSR_TXRDY)) { 2251 /* 2252 * If we've delayed a parameter change, do it now, and restart 2253 * output. 2254 */ 2255 if (sc->sc_heldchange) { 2256 com_loadchannelregs(sc); 2257 sc->sc_heldchange = 0; 2258 sc->sc_tbc = sc->sc_heldtbc; 2259 sc->sc_heldtbc = 0; 2260 } 2261 2262 /* Output the next chunk of the contiguous buffer, if any. */ 2263 if (sc->sc_tbc > 0) { 2264 u_int n; 2265 2266 n = sc->sc_tbc; 2267 if (n > sc->sc_fifolen) 2268 n = sc->sc_fifolen; 2269 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2270 sc->sc_tbc -= n; 2271 sc->sc_tba += n; 2272 } else { 2273 /* Disable transmit completion interrupts if necessary. */ 2274 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2275 CLR(sc->sc_ier, IER_ETXRDY); 2276 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2277 } 2278 if (sc->sc_tx_busy) { 2279 sc->sc_tx_busy = 0; 2280 sc->sc_tx_done = 1; 2281 } 2282 } 2283 } 2284 2285 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2286 goto again; 2287 2288 mutex_spin_exit(&sc->sc_lock); 2289 2290 /* Wake up the poller. */ 2291 softint_schedule(sc->sc_si); 2292 2293 #ifdef RND_COM 2294 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2295 #endif 2296 2297 return (1); 2298 } 2299 2300 /* 2301 * The following functions are polled getc and putc routines, shared 2302 * by the console and kgdb glue. 2303 * 2304 * The read-ahead code is so that you can detect pending in-band 2305 * cn_magic in polled mode while doing output rather than having to 2306 * wait until the kernel decides it needs input. 2307 */ 2308 2309 #define MAX_READAHEAD 20 2310 static int com_readahead[MAX_READAHEAD]; 2311 static int com_readaheadcount = 0; 2312 2313 int 2314 com_common_getc(dev_t dev, struct com_regs *regsp) 2315 { 2316 int s = splserial(); 2317 u_char stat, c; 2318 2319 /* got a character from reading things earlier */ 2320 if (com_readaheadcount > 0) { 2321 int i; 2322 2323 c = com_readahead[0]; 2324 for (i = 1; i < com_readaheadcount; i++) { 2325 com_readahead[i-1] = com_readahead[i]; 2326 } 2327 com_readaheadcount--; 2328 splx(s); 2329 return (c); 2330 } 2331 2332 /* don't block until a character becomes available */ 2333 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2334 splx(s); 2335 return -1; 2336 } 2337 2338 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2339 stat = CSR_READ_1(regsp, COM_REG_IIR); 2340 { 2341 int cn_trapped = 0; /* required by cn_trap, see above */ 2342 #ifdef DDB 2343 extern int db_active; 2344 if (!db_active) 2345 #endif 2346 cn_check_magic(dev, c, com_cnm_state); 2347 } 2348 splx(s); 2349 return (c); 2350 } 2351 2352 static void 2353 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2354 { 2355 int s = splserial(); 2356 int cin, stat, timo; 2357 2358 if (com_readaheadcount < MAX_READAHEAD 2359 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2360 int cn_trapped = 0; 2361 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2362 stat = CSR_READ_1(regsp, COM_REG_IIR); 2363 cn_check_magic(dev, cin, com_cnm_state); 2364 com_readahead[com_readaheadcount++] = cin; 2365 } 2366 2367 /* wait for any pending transmission to finish */ 2368 timo = 150000; 2369 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2370 continue; 2371 2372 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2373 COM_BARRIER(regsp, BR | BW); 2374 2375 splx(s); 2376 } 2377 2378 /* 2379 * Initialize UART for use as console or KGDB line. 2380 */ 2381 int 2382 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2383 tcflag_t cflag) 2384 { 2385 2386 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2387 ®sp->cr_ioh)) 2388 return (ENOMEM); /* ??? */ 2389 2390 if (type == COM_TYPE_OMAP) { 2391 /* disable before changing settings */ 2392 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2393 } 2394 2395 rate = comspeed(rate, frequency, type); 2396 if (__predict_true(rate != -1)) { 2397 if (type == COM_TYPE_AU1x00) { 2398 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2399 } else { 2400 /* no EFR on alchemy */ 2401 if ((type != COM_TYPE_16550_NOERS) && 2402 (type != COM_TYPE_INGENIC)) { 2403 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2404 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2405 } 2406 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2407 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2408 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2409 } 2410 } 2411 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2412 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2413 2414 if (type == COM_TYPE_INGENIC) { 2415 CSR_WRITE_1(regsp, COM_REG_FIFO, 2416 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2417 FIFO_TRIGGER_1 | FIFO_UART_ON); 2418 } else { 2419 CSR_WRITE_1(regsp, COM_REG_FIFO, 2420 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2421 FIFO_TRIGGER_1); 2422 } 2423 2424 if (type == COM_TYPE_OMAP) { 2425 /* setup the fifos. the FCR value is not used as long 2426 as SCR[6] and SCR[7] are 0, which they are at reset 2427 and we never touch the SCR register */ 2428 uint8_t rx_fifo_trig = 40; 2429 uint8_t tx_fifo_trig = 60; 2430 uint8_t rx_start = 8; 2431 uint8_t rx_halt = 60; 2432 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2433 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2434 2435 /* enable access to TCR & TLR */ 2436 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2437 2438 /* write tcr and tlr values */ 2439 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2440 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2441 2442 /* disable access to TCR & TLR */ 2443 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2444 2445 /* enable again, but mode is based on speed */ 2446 if (rate > 230400) { 2447 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2448 } else { 2449 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2450 } 2451 } 2452 2453 if (type == COM_TYPE_PXA2x0) 2454 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2455 else 2456 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2457 2458 return (0); 2459 } 2460 2461 int 2462 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2463 tcflag_t cflag) 2464 { 2465 int res; 2466 2467 comcons_info.regs = *regsp; 2468 2469 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2470 if (res) 2471 return (res); 2472 2473 cn_tab = &comcons; 2474 cn_init_magic(&com_cnm_state); 2475 cn_set_magic("\047\001"); /* default magic is BREAK */ 2476 2477 comcons_info.frequency = frequency; 2478 comcons_info.type = type; 2479 comcons_info.rate = rate; 2480 comcons_info.cflag = cflag; 2481 2482 return (0); 2483 } 2484 2485 int 2486 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2487 int type, tcflag_t cflag) 2488 { 2489 struct com_regs regs; 2490 2491 memset(®s, 0, sizeof regs); 2492 regs.cr_iot = iot; 2493 regs.cr_iobase = iobase; 2494 regs.cr_nports = COM_NPORTS; 2495 #ifdef COM_REGMAP 2496 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2497 #endif 2498 2499 return comcnattach1(®s, rate, frequency, type, cflag); 2500 } 2501 2502 static int 2503 comcnreattach(void) 2504 { 2505 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2506 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2507 } 2508 2509 int 2510 comcngetc(dev_t dev) 2511 { 2512 2513 return (com_common_getc(dev, &comcons_info.regs)); 2514 } 2515 2516 /* 2517 * Console kernel output character routine. 2518 */ 2519 void 2520 comcnputc(dev_t dev, int c) 2521 { 2522 2523 com_common_putc(dev, &comcons_info.regs, c); 2524 } 2525 2526 void 2527 comcnpollc(dev_t dev, int on) 2528 { 2529 2530 com_readaheadcount = 0; 2531 } 2532 2533 #ifdef KGDB 2534 int 2535 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2536 tcflag_t cflag) 2537 { 2538 int res; 2539 2540 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2541 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2542 #if !defined(DDB) 2543 return (EBUSY); /* cannot share with console */ 2544 #else 2545 comkgdbregs = *regsp; 2546 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2547 #endif 2548 } else { 2549 comkgdbregs = *regsp; 2550 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2551 if (res) 2552 return (res); 2553 2554 /* 2555 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2556 * expects this to be initialized 2557 */ 2558 cn_init_magic(&com_cnm_state); 2559 cn_set_magic("\047\001"); 2560 } 2561 2562 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2563 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2564 2565 return (0); 2566 } 2567 2568 int 2569 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2570 int frequency, int type, tcflag_t cflag) 2571 { 2572 struct com_regs regs; 2573 2574 regs.cr_iot = iot; 2575 regs.cr_nports = COM_NPORTS; 2576 regs.cr_iobase = iobase; 2577 #ifdef COM_REGMAP 2578 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2579 #endif 2580 2581 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2582 } 2583 2584 /* ARGSUSED */ 2585 int 2586 com_kgdb_getc(void *arg) 2587 { 2588 2589 return (com_common_getc(NODEV, &comkgdbregs)); 2590 } 2591 2592 /* ARGSUSED */ 2593 void 2594 com_kgdb_putc(void *arg, int c) 2595 { 2596 2597 com_common_putc(NODEV, &comkgdbregs, c); 2598 } 2599 #endif /* KGDB */ 2600 2601 /* helper function to identify the com ports used by 2602 console or KGDB (and not yet autoconf attached) */ 2603 int 2604 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2605 { 2606 bus_space_handle_t help; 2607 2608 if (!comconsattached && 2609 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2610 iobase == comcons_info.regs.cr_iobase) 2611 help = comcons_info.regs.cr_ioh; 2612 #ifdef KGDB 2613 else if (!com_kgdb_attached && 2614 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2615 iobase == comkgdbregs.cr_iobase) 2616 help = comkgdbregs.cr_ioh; 2617 #endif 2618 else 2619 return (0); 2620 2621 if (ioh) 2622 *ioh = help; 2623 return (1); 2624 } 2625 2626 /* 2627 * this routine exists to serve as a shutdown hook for systems that 2628 * have firmware which doesn't interact properly with a com device in 2629 * FIFO mode. 2630 */ 2631 bool 2632 com_cleanup(device_t self, int how) 2633 { 2634 struct com_softc *sc = device_private(self); 2635 2636 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2637 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2638 2639 return true; 2640 } 2641 2642 bool 2643 com_suspend(device_t self, const pmf_qual_t *qual) 2644 { 2645 struct com_softc *sc = device_private(self); 2646 2647 #if 0 2648 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2649 cn_tab = &comcons_suspend; 2650 #endif 2651 2652 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2653 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2654 2655 return true; 2656 } 2657 2658 bool 2659 com_resume(device_t self, const pmf_qual_t *qual) 2660 { 2661 struct com_softc *sc = device_private(self); 2662 2663 mutex_spin_enter(&sc->sc_lock); 2664 com_loadchannelregs(sc); 2665 mutex_spin_exit(&sc->sc_lock); 2666 2667 return true; 2668 } 2669
Indexes created Thu Sep 25 16:09:42 GMT 2025