com.c revision 1.348.2.2
1 /* $NetBSD: com.c,v 1.348.2.2 2020/04/08 14:08:06 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.348.2.2 2020/04/08 14:08:06 martin Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #define CSR_WRITE_1(r, o, v) \ 132 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 133 #define CSR_READ_1(r, o) \ 134 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 135 #define CSR_WRITE_2(r, o, v) \ 136 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 137 #define CSR_READ_2(r, o) \ 138 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 139 #define CSR_WRITE_MULTI(r, o, p, n) \ 140 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 141 142 143 static void com_enable_debugport(struct com_softc *); 144 145 void com_config(struct com_softc *); 146 void com_shutdown(struct com_softc *); 147 int comspeed(long, long, int); 148 static u_char cflag2lcr(tcflag_t); 149 int comparam(struct tty *, struct termios *); 150 void comstart(struct tty *); 151 int comhwiflow(struct tty *, int); 152 153 void com_loadchannelregs(struct com_softc *); 154 void com_hwiflow(struct com_softc *); 155 void com_break(struct com_softc *, int); 156 void com_modem(struct com_softc *, int); 157 void tiocm_to_com(struct com_softc *, u_long, int); 158 int com_to_tiocm(struct com_softc *); 159 void com_iflush(struct com_softc *); 160 161 int com_common_getc(dev_t, struct com_regs *); 162 static void com_common_putc(dev_t, struct com_regs *, int); 163 164 int cominit(struct com_regs *, int, int, int, tcflag_t); 165 166 static int comcnreattach(void); 167 168 int comcngetc(dev_t); 169 void comcnputc(dev_t, int); 170 void comcnpollc(dev_t, int); 171 172 #define integrate static inline 173 void comsoft(void *); 174 integrate void com_rxsoft(struct com_softc *, struct tty *); 175 integrate void com_txsoft(struct com_softc *, struct tty *); 176 integrate void com_stsoft(struct com_softc *, struct tty *); 177 integrate void com_schedrx(struct com_softc *); 178 void comdiag(void *); 179 180 dev_type_open(comopen); 181 dev_type_close(comclose); 182 dev_type_read(comread); 183 dev_type_write(comwrite); 184 dev_type_ioctl(comioctl); 185 dev_type_stop(comstop); 186 dev_type_tty(comtty); 187 dev_type_poll(compoll); 188 189 static struct comcons_info comcons_info; 190 191 /* 192 * Following are all routines needed for COM to act as console 193 */ 194 static struct consdev comcons = { 195 .cn_getc = comcngetc, 196 .cn_putc = comcnputc, 197 .cn_pollc = comcnpollc, 198 .cn_dev = NODEV, 199 .cn_pri = CN_NORMAL 200 }; 201 202 203 const struct cdevsw com_cdevsw = { 204 .d_open = comopen, 205 .d_close = comclose, 206 .d_read = comread, 207 .d_write = comwrite, 208 .d_ioctl = comioctl, 209 .d_stop = comstop, 210 .d_tty = comtty, 211 .d_poll = compoll, 212 .d_mmap = nommap, 213 .d_kqfilter = ttykqfilter, 214 .d_discard = nodiscard, 215 .d_flag = D_TTY 216 }; 217 218 /* 219 * Make this an option variable one can patch. 220 * But be warned: this must be a power of 2! 221 */ 222 u_int com_rbuf_size = COM_RING_SIZE; 223 224 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 225 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 226 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 227 228 static int comconsattached; 229 static struct cnm_state com_cnm_state; 230 231 #ifdef KGDB 232 #include <sys/kgdb.h> 233 234 static struct com_regs comkgdbregs; 235 static int com_kgdb_attached; 236 237 int com_kgdb_getc(void *); 238 void com_kgdb_putc(void *, int); 239 #endif /* KGDB */ 240 241 /* initializer for typical 16550-ish hardware */ 242 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 243 [COM_REG_RXDATA] = com_data, 244 [COM_REG_TXDATA] = com_data, 245 [COM_REG_DLBL] = com_dlbl, 246 [COM_REG_DLBH] = com_dlbh, 247 [COM_REG_IER] = com_ier, 248 [COM_REG_IIR] = com_iir, 249 [COM_REG_FIFO] = com_fifo, 250 [COM_REG_TCR] = com_fifo, 251 [COM_REG_EFR] = com_efr, 252 [COM_REG_TLR] = com_efr, 253 [COM_REG_LCR] = com_lcr, 254 [COM_REG_MCR] = com_mcr, 255 [COM_REG_LSR] = com_lsr, 256 [COM_REG_MSR] = com_msr, 257 [COM_REG_USR] = com_usr, 258 [COM_REG_TFL] = com_tfl, 259 [COM_REG_RFL] = com_rfl, 260 [COM_REG_HALT] = com_halt, 261 [COM_REG_MDR1] = com_mdr1, 262 }; 263 264 #define COMDIALOUT_MASK TTDIALOUT_MASK 265 266 #define COMUNIT(x) TTUNIT(x) 267 #define COMDIALOUT(x) TTDIALOUT(x) 268 269 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 270 device_is_active((sc)->sc_dev)) 271 272 #define BR BUS_SPACE_BARRIER_READ 273 #define BW BUS_SPACE_BARRIER_WRITE 274 #define COM_BARRIER(r, f) \ 275 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 276 277 /* 278 * com_init_regs -- 279 * Driver front-ends use this to initialize our register map 280 * in the standard fashion. They may then tailor the map to 281 * their own particular requirements. 282 */ 283 void 284 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 285 bus_addr_t addr) 286 { 287 288 memset(regs, 0, sizeof(*regs)); 289 regs->cr_iot = st; 290 regs->cr_ioh = sh; 291 regs->cr_iobase = addr; 292 regs->cr_nports = COM_NPORTS; 293 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 294 } 295 296 /* 297 * com_init_regs_stride -- 298 * Convenience function for front-ends that have a stride between 299 * registers. 300 */ 301 void 302 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 303 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 304 { 305 306 com_init_regs(regs, st, sh, addr); 307 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 308 regs->cr_map[i] <<= regshift; 309 } 310 regs->cr_nports <<= regshift; 311 } 312 313 /*ARGSUSED*/ 314 int 315 comspeed(long speed, long frequency, int type) 316 { 317 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 318 319 int x, err; 320 int divisor = 16; 321 322 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 323 divisor = 13; 324 } 325 326 if (speed == 0) 327 return (0); 328 if (speed < 0) 329 return (-1); 330 x = divrnd(frequency / divisor, speed); 331 if (x <= 0) 332 return (-1); 333 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 334 if (err < 0) 335 err = -err; 336 if (err > COM_TOLERANCE) 337 return (-1); 338 return (x); 339 340 #undef divrnd 341 } 342 343 #ifdef COM_DEBUG 344 int com_debug = 0; 345 346 void comstatus(struct com_softc *, const char *); 347 void 348 comstatus(struct com_softc *sc, const char *str) 349 { 350 struct tty *tp = sc->sc_tty; 351 352 aprint_normal_dev(sc->sc_dev, 353 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 354 str, 355 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 356 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 357 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 358 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 359 sc->sc_tx_stopped ? '+' : '-'); 360 361 aprint_normal_dev(sc->sc_dev, 362 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 363 str, 364 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 365 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 366 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 367 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 368 sc->sc_rx_flags); 369 } 370 #endif 371 372 int 373 com_probe_subr(struct com_regs *regs) 374 { 375 376 /* force access to id reg */ 377 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 378 CSR_WRITE_1(regs, COM_REG_IIR, 0); 379 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 380 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 381 return (0); 382 383 return (1); 384 } 385 386 int 387 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 388 { 389 struct com_regs regs; 390 391 com_init_regs(®s, iot, ioh, 0/*XXX*/); 392 393 return com_probe_subr(®s); 394 } 395 396 /* 397 * No locking in this routine; it is only called during attach, 398 * or with the port already locked. 399 */ 400 static void 401 com_enable_debugport(struct com_softc *sc) 402 { 403 404 /* Turn on line break interrupt, set carrier. */ 405 sc->sc_ier = IER_ERLS; 406 if (sc->sc_type == COM_TYPE_PXA2x0) 407 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 408 if (sc->sc_type == COM_TYPE_INGENIC || 409 sc->sc_type == COM_TYPE_TEGRA) 410 sc->sc_ier |= IER_ERXTOUT; 411 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 412 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 413 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 414 } 415 416 static void 417 com_intr_poll(void *arg) 418 { 419 struct com_softc * const sc = arg; 420 421 comintr(sc); 422 423 callout_schedule(&sc->sc_poll_callout, 1); 424 } 425 426 void 427 com_attach_subr(struct com_softc *sc) 428 { 429 struct com_regs *regsp = &sc->sc_regs; 430 struct tty *tp; 431 u_int8_t lcr; 432 const char *fifo_msg = NULL; 433 prop_dictionary_t dict; 434 bool is_console = true; 435 bool force_console = false; 436 437 aprint_naive("\n"); 438 439 dict = device_properties(sc->sc_dev); 440 prop_dictionary_get_bool(dict, "is_console", &is_console); 441 prop_dictionary_get_bool(dict, "force_console", &force_console); 442 callout_init(&sc->sc_diag_callout, 0); 443 callout_init(&sc->sc_poll_callout, 0); 444 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 445 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 446 447 #if defined(COM_16650) 448 sc->sc_type = COM_TYPE_16650; 449 #elif defined(COM_16750) 450 sc->sc_type = COM_TYPE_16750; 451 #elif defined(COM_HAYESP) 452 sc->sc_type = COM_TYPE_HAYESP; 453 #elif defined(COM_PXA2X0) 454 sc->sc_type = COM_TYPE_PXA2x0; 455 #endif 456 457 /* Disable interrupts before configuring the device. */ 458 if (sc->sc_type == COM_TYPE_PXA2x0) 459 sc->sc_ier = IER_EUART; 460 else 461 sc->sc_ier = 0; 462 463 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 464 465 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 466 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 467 comconsattached = 1; 468 469 if (force_console) 470 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 471 472 if (cn_tab == NULL && comcnreattach() != 0) { 473 printf("can't re-init serial console @%lx\n", 474 (u_long)comcons_info.regs.cr_iobase); 475 } 476 477 switch (sc->sc_type) { 478 case COM_TYPE_16750: 479 case COM_TYPE_DW_APB: 480 /* Use in comintr(). */ 481 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 482 break; 483 } 484 485 /* Make sure the console is always "hardwired". */ 486 delay(10000); /* wait for output to finish */ 487 if (is_console) { 488 SET(sc->sc_hwflags, COM_HW_CONSOLE); 489 } 490 491 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 492 } 493 494 /* Probe for FIFO */ 495 switch (sc->sc_type) { 496 case COM_TYPE_HAYESP: 497 goto fifodone; 498 499 case COM_TYPE_AU1x00: 500 sc->sc_fifolen = 16; 501 fifo_msg = "Au1X00 UART, working fifo"; 502 SET(sc->sc_hwflags, COM_HW_FIFO); 503 goto fifodelay; 504 505 case COM_TYPE_16550_NOERS: 506 sc->sc_fifolen = 16; 507 fifo_msg = "ns16650, no ERS, working fifo"; 508 SET(sc->sc_hwflags, COM_HW_FIFO); 509 goto fifodelay; 510 511 case COM_TYPE_OMAP: 512 sc->sc_fifolen = 64; 513 fifo_msg = "OMAP UART, working fifo"; 514 SET(sc->sc_hwflags, COM_HW_FIFO); 515 goto fifodelay; 516 517 case COM_TYPE_INGENIC: 518 sc->sc_fifolen = 16; 519 fifo_msg = "Ingenic UART, working fifo"; 520 SET(sc->sc_hwflags, COM_HW_FIFO); 521 SET(sc->sc_hwflags, COM_HW_NOIEN); 522 goto fifodelay; 523 524 case COM_TYPE_TEGRA: 525 sc->sc_fifolen = 8; 526 fifo_msg = "Tegra UART, working fifo"; 527 SET(sc->sc_hwflags, COM_HW_FIFO); 528 CSR_WRITE_1(regsp, COM_REG_FIFO, 529 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 530 goto fifodelay; 531 532 case COM_TYPE_BCMAUXUART: 533 sc->sc_fifolen = 1; 534 fifo_msg = "BCM AUX UART, working fifo"; 535 SET(sc->sc_hwflags, COM_HW_FIFO); 536 CSR_WRITE_1(regsp, COM_REG_FIFO, 537 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 538 goto fifodelay; 539 } 540 541 sc->sc_fifolen = 1; 542 /* look for a NS 16550AF UART with FIFOs */ 543 if (sc->sc_type == COM_TYPE_INGENIC) { 544 CSR_WRITE_1(regsp, COM_REG_FIFO, 545 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 546 FIFO_TRIGGER_14 | FIFO_UART_ON); 547 } else 548 CSR_WRITE_1(regsp, COM_REG_FIFO, 549 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 550 delay(100); 551 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 552 == IIR_FIFO_MASK) 553 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 554 == FIFO_TRIGGER_14) { 555 SET(sc->sc_hwflags, COM_HW_FIFO); 556 557 fifo_msg = "ns16550a, working fifo"; 558 559 /* 560 * IIR changes into the EFR if LCR is set to LCR_EERS 561 * on 16650s. We also know IIR != 0 at this point. 562 * Write 0 into the EFR, and read it. If the result 563 * is 0, we have a 16650. 564 * 565 * Older 16650s were broken; the test to detect them 566 * is taken from the Linux driver. Apparently 567 * setting DLAB enable gives access to the EFR on 568 * these chips. 569 */ 570 if (sc->sc_type == COM_TYPE_16650) { 571 lcr = CSR_READ_1(regsp, COM_REG_LCR); 572 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 573 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 574 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 575 CSR_WRITE_1(regsp, COM_REG_LCR, 576 lcr | LCR_DLAB); 577 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 578 CLR(sc->sc_hwflags, COM_HW_FIFO); 579 sc->sc_fifolen = 0; 580 } else { 581 SET(sc->sc_hwflags, COM_HW_FLOW); 582 sc->sc_fifolen = 32; 583 } 584 } else 585 sc->sc_fifolen = 16; 586 587 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 588 if (sc->sc_fifolen == 0) 589 fifo_msg = "st16650, broken fifo"; 590 else if (sc->sc_fifolen == 32) 591 fifo_msg = "st16650a, working fifo"; 592 else 593 fifo_msg = "ns16550a, working fifo"; 594 } 595 596 /* 597 * TL16C750 can enable 64byte FIFO, only when DLAB 598 * is 1. However, some 16750 may always enable. For 599 * example, restrictions according to DLAB in a data 600 * sheet for SC16C750 were not described. 601 * Please enable 'options COM_16650', supposing you 602 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 603 * should become effective. 604 */ 605 if (sc->sc_type == COM_TYPE_16750) { 606 uint8_t iir1, iir2; 607 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 608 609 lcr = CSR_READ_1(regsp, COM_REG_LCR); 610 CSR_WRITE_1(regsp, COM_REG_LCR, 611 lcr & ~LCR_DLAB); 612 CSR_WRITE_1(regsp, COM_REG_FIFO, 613 fcr | FIFO_64B_ENABLE); 614 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 615 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 616 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 617 CSR_WRITE_1(regsp, COM_REG_FIFO, 618 fcr | FIFO_64B_ENABLE); 619 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 620 621 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 622 623 if (!ISSET(iir1, IIR_64B_FIFO) && 624 ISSET(iir2, IIR_64B_FIFO)) { 625 /* It is TL16C750. */ 626 sc->sc_fifolen = 64; 627 SET(sc->sc_hwflags, COM_HW_AFE); 628 } else 629 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 630 631 if (sc->sc_fifolen == 64) 632 fifo_msg = "tl16c750, working fifo"; 633 else 634 fifo_msg = "ns16750, working fifo"; 635 } 636 } else 637 fifo_msg = "ns16550, broken fifo"; 638 else 639 fifo_msg = "ns8250 or ns16450, no fifo"; 640 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 641 642 fifodelay: 643 /* 644 * Some chips will clear down both Tx and Rx FIFOs when zero is 645 * written to com_fifo. If this chip is the console, writing zero 646 * results in some of the chip/FIFO description being lost, so delay 647 * printing it until now. 648 */ 649 delay(10); 650 aprint_normal(": %s\n", fifo_msg); 651 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 652 sc->sc_fifolen = 1; 653 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 654 } 655 656 fifodone: 657 658 tp = tty_alloc(); 659 tp->t_oproc = comstart; 660 tp->t_param = comparam; 661 tp->t_hwiflow = comhwiflow; 662 tp->t_softc = sc; 663 664 sc->sc_tty = tp; 665 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 666 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 667 sc->sc_rbavail = com_rbuf_size; 668 if (sc->sc_rbuf == NULL) { 669 aprint_error_dev(sc->sc_dev, 670 "unable to allocate ring buffer\n"); 671 return; 672 } 673 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 674 675 tty_attach(tp); 676 677 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 678 SET(sc->sc_mcr, MCR_IENABLE); 679 680 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 681 int maj; 682 683 /* locate the major number */ 684 maj = cdevsw_lookup_major(&com_cdevsw); 685 686 tp->t_dev = cn_tab->cn_dev = makedev(maj, 687 device_unit(sc->sc_dev)); 688 689 aprint_normal_dev(sc->sc_dev, "console\n"); 690 } 691 692 #ifdef KGDB 693 /* 694 * Allow kgdb to "take over" this port. If this is 695 * not the console and is the kgdb device, it has 696 * exclusive use. If it's the console _and_ the 697 * kgdb device, it doesn't. 698 */ 699 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 700 regsp->cr_iobase == comkgdbregs.cr_iobase) { 701 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 702 com_kgdb_attached = 1; 703 704 SET(sc->sc_hwflags, COM_HW_KGDB); 705 } 706 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 707 } 708 #endif 709 710 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 711 712 #ifdef RND_COM 713 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 714 RND_TYPE_TTY, RND_FLAG_DEFAULT); 715 #endif 716 717 /* if there are no enable/disable functions, assume the device 718 is always enabled */ 719 if (!sc->enable) 720 sc->enabled = 1; 721 722 com_config(sc); 723 724 SET(sc->sc_hwflags, COM_HW_DEV_OK); 725 726 if (ISSET(sc->sc_hwflags, COM_HW_POLL)) 727 callout_schedule(&sc->sc_poll_callout, 1); 728 } 729 730 void 731 com_config(struct com_softc *sc) 732 { 733 struct com_regs *regsp = &sc->sc_regs; 734 735 /* Disable interrupts before configuring the device. */ 736 if (sc->sc_type == COM_TYPE_PXA2x0) 737 sc->sc_ier = IER_EUART; 738 else 739 sc->sc_ier = 0; 740 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 741 (void) CSR_READ_1(regsp, COM_REG_IIR); 742 743 /* Look for a Hayes ESP board. */ 744 if (sc->sc_type == COM_TYPE_HAYESP) { 745 746 /* Set 16550 compatibility mode */ 747 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 748 HAYESP_SETMODE); 749 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 750 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 751 HAYESP_MODE_SCALE); 752 753 /* Set RTS/CTS flow control */ 754 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 755 HAYESP_SETFLOWTYPE); 756 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 757 HAYESP_FLOW_RTS); 758 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 759 HAYESP_FLOW_CTS); 760 761 /* Set flow control levels */ 762 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 763 HAYESP_SETRXFLOW); 764 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 765 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 766 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 767 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 768 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 769 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 770 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 771 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 772 } 773 774 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 775 com_enable_debugport(sc); 776 } 777 778 #if 0 779 static int 780 comcngetc_detached(dev_t dev) 781 { 782 return 0; 783 } 784 785 static void 786 comcnputc_detached(dev_t dev, int c) 787 { 788 } 789 #endif 790 791 int 792 com_detach(device_t self, int flags) 793 { 794 struct com_softc *sc = device_private(self); 795 int maj, mn; 796 797 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 798 return EBUSY; 799 800 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 801 (flags & DETACH_SHUTDOWN) != 0) 802 return EBUSY; 803 804 if (sc->disable != NULL && sc->enabled != 0) { 805 (*sc->disable)(sc); 806 sc->enabled = 0; 807 } 808 809 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 810 comconsattached = 0; 811 cn_tab = NULL; 812 } 813 814 /* locate the major number */ 815 maj = cdevsw_lookup_major(&com_cdevsw); 816 817 /* Nuke the vnodes for any open instances. */ 818 mn = device_unit(self); 819 vdevgone(maj, mn, mn, VCHR); 820 821 mn |= COMDIALOUT_MASK; 822 vdevgone(maj, mn, mn, VCHR); 823 824 if (sc->sc_rbuf == NULL) { 825 /* 826 * Ring buffer allocation failed in the com_attach_subr, 827 * only the tty is allocated, and nothing else. 828 */ 829 tty_free(sc->sc_tty); 830 return 0; 831 } 832 833 /* Free the receive buffer. */ 834 free(sc->sc_rbuf, M_DEVBUF); 835 836 /* Detach and free the tty. */ 837 tty_detach(sc->sc_tty); 838 tty_free(sc->sc_tty); 839 840 /* Unhook the soft interrupt handler. */ 841 softint_disestablish(sc->sc_si); 842 843 #ifdef RND_COM 844 /* Unhook the entropy source. */ 845 rnd_detach_source(&sc->rnd_source); 846 #endif 847 callout_destroy(&sc->sc_diag_callout); 848 849 /* Destroy the lock. */ 850 mutex_destroy(&sc->sc_lock); 851 852 return (0); 853 } 854 855 void 856 com_shutdown(struct com_softc *sc) 857 { 858 struct tty *tp = sc->sc_tty; 859 860 mutex_spin_enter(&sc->sc_lock); 861 862 /* If we were asserting flow control, then deassert it. */ 863 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 864 com_hwiflow(sc); 865 866 /* Clear any break condition set with TIOCSBRK. */ 867 com_break(sc, 0); 868 869 /* 870 * Hang up if necessary. Wait a bit, so the other side has time to 871 * notice even if we immediately open the port again. 872 * Avoid tsleeping above splhigh(). 873 */ 874 if (ISSET(tp->t_cflag, HUPCL)) { 875 com_modem(sc, 0); 876 mutex_spin_exit(&sc->sc_lock); 877 /* XXX will only timeout */ 878 (void) kpause(ttclos, false, hz, NULL); 879 mutex_spin_enter(&sc->sc_lock); 880 } 881 882 /* Turn off interrupts. */ 883 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 884 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 885 if ((sc->sc_type == COM_TYPE_PXA2x0) || 886 (sc->sc_type == COM_TYPE_INGENIC) || 887 (sc->sc_type == COM_TYPE_TEGRA)) 888 sc->sc_ier |= IER_ERXTOUT; 889 } else 890 sc->sc_ier = 0; 891 892 if (sc->sc_type == COM_TYPE_PXA2x0) 893 sc->sc_ier |= IER_EUART; 894 895 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 896 897 mutex_spin_exit(&sc->sc_lock); 898 899 if (sc->disable) { 900 #ifdef DIAGNOSTIC 901 if (!sc->enabled) 902 panic("com_shutdown: not enabled?"); 903 #endif 904 (*sc->disable)(sc); 905 sc->enabled = 0; 906 } 907 } 908 909 int 910 comopen(dev_t dev, int flag, int mode, struct lwp *l) 911 { 912 struct com_softc *sc; 913 struct tty *tp; 914 int s; 915 int error; 916 917 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 918 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 919 sc->sc_rbuf == NULL) 920 return (ENXIO); 921 922 if (!device_is_active(sc->sc_dev)) 923 return (ENXIO); 924 925 #ifdef KGDB 926 /* 927 * If this is the kgdb port, no other use is permitted. 928 */ 929 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 930 return (EBUSY); 931 #endif 932 933 tp = sc->sc_tty; 934 935 /* 936 * If the device is exclusively for kernel use, deny userland 937 * open. 938 */ 939 if (ISSET(tp->t_state, TS_KERN_ONLY)) 940 return (EBUSY); 941 942 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 943 return (EBUSY); 944 945 s = spltty(); 946 947 /* 948 * Do the following iff this is a first open. 949 */ 950 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 951 struct termios t; 952 953 tp->t_dev = dev; 954 955 if (sc->enable) { 956 if ((*sc->enable)(sc)) { 957 splx(s); 958 aprint_error_dev(sc->sc_dev, 959 "device enable failed\n"); 960 return (EIO); 961 } 962 mutex_spin_enter(&sc->sc_lock); 963 sc->enabled = 1; 964 com_config(sc); 965 } else { 966 mutex_spin_enter(&sc->sc_lock); 967 } 968 969 /* Turn on interrupts. */ 970 sc->sc_ier = IER_ERXRDY | IER_ERLS; 971 if (!ISSET(tp->t_cflag, CLOCAL)) 972 sc->sc_ier |= IER_EMSC; 973 974 if (sc->sc_type == COM_TYPE_PXA2x0) 975 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 976 else if (sc->sc_type == COM_TYPE_INGENIC || 977 sc->sc_type == COM_TYPE_TEGRA) 978 sc->sc_ier |= IER_ERXTOUT; 979 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 980 981 /* Fetch the current modem control status, needed later. */ 982 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 983 984 /* Clear PPS capture state on first open. */ 985 mutex_spin_enter(&timecounter_lock); 986 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 987 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 988 pps_init(&sc->sc_pps_state); 989 mutex_spin_exit(&timecounter_lock); 990 991 mutex_spin_exit(&sc->sc_lock); 992 993 /* 994 * Initialize the termios status to the defaults. Add in the 995 * sticky bits from TIOCSFLAGS. 996 */ 997 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 998 t.c_ospeed = comcons_info.rate; 999 t.c_cflag = comcons_info.cflag; 1000 } else { 1001 t.c_ospeed = TTYDEF_SPEED; 1002 t.c_cflag = TTYDEF_CFLAG; 1003 } 1004 t.c_ispeed = t.c_ospeed; 1005 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1006 SET(t.c_cflag, CLOCAL); 1007 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1008 SET(t.c_cflag, CRTSCTS); 1009 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1010 SET(t.c_cflag, MDMBUF); 1011 /* Make sure comparam() will do something. */ 1012 tp->t_ospeed = 0; 1013 (void) comparam(tp, &t); 1014 tp->t_iflag = TTYDEF_IFLAG; 1015 tp->t_oflag = TTYDEF_OFLAG; 1016 tp->t_lflag = TTYDEF_LFLAG; 1017 ttychars(tp); 1018 ttsetwater(tp); 1019 1020 mutex_spin_enter(&sc->sc_lock); 1021 1022 /* 1023 * Turn on DTR. We must always do this, even if carrier is not 1024 * present, because otherwise we'd have to use TIOCSDTR 1025 * immediately after setting CLOCAL, which applications do not 1026 * expect. We always assert DTR while the device is open 1027 * unless explicitly requested to deassert it. 1028 */ 1029 com_modem(sc, 1); 1030 1031 /* Clear the input ring, and unblock. */ 1032 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1033 sc->sc_rbavail = com_rbuf_size; 1034 com_iflush(sc); 1035 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1036 com_hwiflow(sc); 1037 1038 #ifdef COM_DEBUG 1039 if (com_debug) 1040 comstatus(sc, "comopen "); 1041 #endif 1042 1043 mutex_spin_exit(&sc->sc_lock); 1044 } 1045 1046 splx(s); 1047 1048 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1049 if (error) 1050 goto bad; 1051 1052 error = (*tp->t_linesw->l_open)(dev, tp); 1053 if (error) 1054 goto bad; 1055 1056 return (0); 1057 1058 bad: 1059 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1060 /* 1061 * We failed to open the device, and nobody else had it opened. 1062 * Clean up the state as appropriate. 1063 */ 1064 com_shutdown(sc); 1065 } 1066 1067 return (error); 1068 } 1069 1070 int 1071 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1072 { 1073 struct com_softc *sc = 1074 device_lookup_private(&com_cd, COMUNIT(dev)); 1075 struct tty *tp = sc->sc_tty; 1076 1077 /* XXX This is for cons.c. */ 1078 if (!ISSET(tp->t_state, TS_ISOPEN)) 1079 return (0); 1080 /* 1081 * If the device is exclusively for kernel use, deny userland 1082 * close. 1083 */ 1084 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1085 return (0); 1086 1087 (*tp->t_linesw->l_close)(tp, flag); 1088 ttyclose(tp); 1089 1090 if (COM_ISALIVE(sc) == 0) 1091 return (0); 1092 1093 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1094 /* 1095 * Although we got a last close, the device may still be in 1096 * use; e.g. if this was the dialout node, and there are still 1097 * processes waiting for carrier on the non-dialout node. 1098 */ 1099 com_shutdown(sc); 1100 } 1101 1102 return (0); 1103 } 1104 1105 int 1106 comread(dev_t dev, struct uio *uio, int flag) 1107 { 1108 struct com_softc *sc = 1109 device_lookup_private(&com_cd, COMUNIT(dev)); 1110 struct tty *tp = sc->sc_tty; 1111 1112 if (COM_ISALIVE(sc) == 0) 1113 return (EIO); 1114 1115 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1116 } 1117 1118 int 1119 comwrite(dev_t dev, struct uio *uio, int flag) 1120 { 1121 struct com_softc *sc = 1122 device_lookup_private(&com_cd, COMUNIT(dev)); 1123 struct tty *tp = sc->sc_tty; 1124 1125 if (COM_ISALIVE(sc) == 0) 1126 return (EIO); 1127 1128 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1129 } 1130 1131 int 1132 compoll(dev_t dev, int events, struct lwp *l) 1133 { 1134 struct com_softc *sc = 1135 device_lookup_private(&com_cd, COMUNIT(dev)); 1136 struct tty *tp = sc->sc_tty; 1137 1138 if (COM_ISALIVE(sc) == 0) 1139 return (POLLHUP); 1140 1141 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1142 } 1143 1144 struct tty * 1145 comtty(dev_t dev) 1146 { 1147 struct com_softc *sc = 1148 device_lookup_private(&com_cd, COMUNIT(dev)); 1149 struct tty *tp = sc->sc_tty; 1150 1151 return (tp); 1152 } 1153 1154 int 1155 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1156 { 1157 struct com_softc *sc; 1158 struct tty *tp; 1159 int error; 1160 1161 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1162 if (sc == NULL) 1163 return ENXIO; 1164 if (COM_ISALIVE(sc) == 0) 1165 return (EIO); 1166 1167 tp = sc->sc_tty; 1168 1169 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1170 if (error != EPASSTHROUGH) 1171 return (error); 1172 1173 error = ttioctl(tp, cmd, data, flag, l); 1174 if (error != EPASSTHROUGH) 1175 return (error); 1176 1177 error = 0; 1178 switch (cmd) { 1179 case TIOCSFLAGS: 1180 error = kauth_authorize_device_tty(l->l_cred, 1181 KAUTH_DEVICE_TTY_PRIVSET, tp); 1182 break; 1183 default: 1184 /* nothing */ 1185 break; 1186 } 1187 if (error) { 1188 return error; 1189 } 1190 1191 mutex_spin_enter(&sc->sc_lock); 1192 1193 switch (cmd) { 1194 case TIOCSBRK: 1195 com_break(sc, 1); 1196 break; 1197 1198 case TIOCCBRK: 1199 com_break(sc, 0); 1200 break; 1201 1202 case TIOCSDTR: 1203 com_modem(sc, 1); 1204 break; 1205 1206 case TIOCCDTR: 1207 com_modem(sc, 0); 1208 break; 1209 1210 case TIOCGFLAGS: 1211 *(int *)data = sc->sc_swflags; 1212 break; 1213 1214 case TIOCSFLAGS: 1215 sc->sc_swflags = *(int *)data; 1216 break; 1217 1218 case TIOCMSET: 1219 case TIOCMBIS: 1220 case TIOCMBIC: 1221 tiocm_to_com(sc, cmd, *(int *)data); 1222 break; 1223 1224 case TIOCMGET: 1225 *(int *)data = com_to_tiocm(sc); 1226 break; 1227 1228 case PPS_IOC_CREATE: 1229 case PPS_IOC_DESTROY: 1230 case PPS_IOC_GETPARAMS: 1231 case PPS_IOC_SETPARAMS: 1232 case PPS_IOC_GETCAP: 1233 case PPS_IOC_FETCH: 1234 #ifdef PPS_SYNC 1235 case PPS_IOC_KCBIND: 1236 #endif 1237 mutex_spin_enter(&timecounter_lock); 1238 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1239 mutex_spin_exit(&timecounter_lock); 1240 break; 1241 1242 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1243 mutex_spin_enter(&timecounter_lock); 1244 #ifndef PPS_TRAILING_EDGE 1245 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1246 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1247 #else 1248 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1249 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1250 #endif 1251 mutex_spin_exit(&timecounter_lock); 1252 break; 1253 1254 default: 1255 error = EPASSTHROUGH; 1256 break; 1257 } 1258 1259 mutex_spin_exit(&sc->sc_lock); 1260 1261 #ifdef COM_DEBUG 1262 if (com_debug) 1263 comstatus(sc, "comioctl "); 1264 #endif 1265 1266 return (error); 1267 } 1268 1269 integrate void 1270 com_schedrx(struct com_softc *sc) 1271 { 1272 1273 sc->sc_rx_ready = 1; 1274 1275 /* Wake up the poller. */ 1276 softint_schedule(sc->sc_si); 1277 } 1278 1279 void 1280 com_break(struct com_softc *sc, int onoff) 1281 { 1282 1283 if (onoff) 1284 SET(sc->sc_lcr, LCR_SBREAK); 1285 else 1286 CLR(sc->sc_lcr, LCR_SBREAK); 1287 1288 if (!sc->sc_heldchange) { 1289 if (sc->sc_tx_busy) { 1290 sc->sc_heldtbc = sc->sc_tbc; 1291 sc->sc_tbc = 0; 1292 sc->sc_heldchange = 1; 1293 } else 1294 com_loadchannelregs(sc); 1295 } 1296 } 1297 1298 void 1299 com_modem(struct com_softc *sc, int onoff) 1300 { 1301 1302 if (sc->sc_mcr_dtr == 0) 1303 return; 1304 1305 if (onoff) 1306 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1307 else 1308 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1309 1310 if (!sc->sc_heldchange) { 1311 if (sc->sc_tx_busy) { 1312 sc->sc_heldtbc = sc->sc_tbc; 1313 sc->sc_tbc = 0; 1314 sc->sc_heldchange = 1; 1315 } else 1316 com_loadchannelregs(sc); 1317 } 1318 } 1319 1320 void 1321 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1322 { 1323 u_char combits; 1324 1325 combits = 0; 1326 if (ISSET(ttybits, TIOCM_DTR)) 1327 SET(combits, MCR_DTR); 1328 if (ISSET(ttybits, TIOCM_RTS)) 1329 SET(combits, MCR_RTS); 1330 1331 switch (how) { 1332 case TIOCMBIC: 1333 CLR(sc->sc_mcr, combits); 1334 break; 1335 1336 case TIOCMBIS: 1337 SET(sc->sc_mcr, combits); 1338 break; 1339 1340 case TIOCMSET: 1341 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1342 SET(sc->sc_mcr, combits); 1343 break; 1344 } 1345 1346 if (!sc->sc_heldchange) { 1347 if (sc->sc_tx_busy) { 1348 sc->sc_heldtbc = sc->sc_tbc; 1349 sc->sc_tbc = 0; 1350 sc->sc_heldchange = 1; 1351 } else 1352 com_loadchannelregs(sc); 1353 } 1354 } 1355 1356 int 1357 com_to_tiocm(struct com_softc *sc) 1358 { 1359 u_char combits; 1360 int ttybits = 0; 1361 1362 combits = sc->sc_mcr; 1363 if (ISSET(combits, MCR_DTR)) 1364 SET(ttybits, TIOCM_DTR); 1365 if (ISSET(combits, MCR_RTS)) 1366 SET(ttybits, TIOCM_RTS); 1367 1368 combits = sc->sc_msr; 1369 if (sc->sc_type == COM_TYPE_INGENIC) { 1370 SET(ttybits, TIOCM_CD); 1371 } else { 1372 if (ISSET(combits, MSR_DCD)) 1373 SET(ttybits, TIOCM_CD); 1374 } 1375 if (ISSET(combits, MSR_CTS)) 1376 SET(ttybits, TIOCM_CTS); 1377 if (ISSET(combits, MSR_DSR)) 1378 SET(ttybits, TIOCM_DSR); 1379 if (ISSET(combits, MSR_RI | MSR_TERI)) 1380 SET(ttybits, TIOCM_RI); 1381 1382 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1383 SET(ttybits, TIOCM_LE); 1384 1385 return (ttybits); 1386 } 1387 1388 static u_char 1389 cflag2lcr(tcflag_t cflag) 1390 { 1391 u_char lcr = 0; 1392 1393 switch (ISSET(cflag, CSIZE)) { 1394 case CS5: 1395 SET(lcr, LCR_5BITS); 1396 break; 1397 case CS6: 1398 SET(lcr, LCR_6BITS); 1399 break; 1400 case CS7: 1401 SET(lcr, LCR_7BITS); 1402 break; 1403 case CS8: 1404 SET(lcr, LCR_8BITS); 1405 break; 1406 } 1407 if (ISSET(cflag, PARENB)) { 1408 SET(lcr, LCR_PENAB); 1409 if (!ISSET(cflag, PARODD)) 1410 SET(lcr, LCR_PEVEN); 1411 } 1412 if (ISSET(cflag, CSTOPB)) 1413 SET(lcr, LCR_STOPB); 1414 1415 return (lcr); 1416 } 1417 1418 int 1419 comparam(struct tty *tp, struct termios *t) 1420 { 1421 struct com_softc *sc = 1422 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1423 int ospeed; 1424 u_char lcr; 1425 1426 if (COM_ISALIVE(sc) == 0) 1427 return (EIO); 1428 1429 if (sc->sc_type == COM_TYPE_HAYESP) { 1430 int prescaler, speed; 1431 1432 /* 1433 * Calculate UART clock prescaler. It should be in 1434 * range of 0 .. 3. 1435 */ 1436 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1437 prescaler++, speed /= 2) 1438 if ((ospeed = comspeed(speed, sc->sc_frequency, 1439 sc->sc_type)) > 0) 1440 break; 1441 1442 if (prescaler == 4) 1443 return (EINVAL); 1444 sc->sc_prescaler = prescaler; 1445 } else 1446 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1447 1448 /* Check requested parameters. */ 1449 if (ospeed < 0) 1450 return (EINVAL); 1451 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1452 return (EINVAL); 1453 1454 /* 1455 * For the console, always force CLOCAL and !HUPCL, so that the port 1456 * is always active. 1457 */ 1458 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1459 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1460 SET(t->c_cflag, CLOCAL); 1461 CLR(t->c_cflag, HUPCL); 1462 } 1463 1464 /* 1465 * If there were no changes, don't do anything. This avoids dropping 1466 * input and improves performance when all we did was frob things like 1467 * VMIN and VTIME. 1468 */ 1469 if (tp->t_ospeed == t->c_ospeed && 1470 tp->t_cflag == t->c_cflag) 1471 return (0); 1472 1473 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1474 1475 mutex_spin_enter(&sc->sc_lock); 1476 1477 sc->sc_lcr = lcr; 1478 1479 /* 1480 * If we're not in a mode that assumes a connection is present, then 1481 * ignore carrier changes. 1482 */ 1483 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1484 sc->sc_msr_dcd = 0; 1485 else 1486 sc->sc_msr_dcd = MSR_DCD; 1487 /* 1488 * Set the flow control pins depending on the current flow control 1489 * mode. 1490 */ 1491 if (ISSET(t->c_cflag, CRTSCTS)) { 1492 sc->sc_mcr_dtr = MCR_DTR; 1493 sc->sc_mcr_rts = MCR_RTS; 1494 sc->sc_msr_cts = MSR_CTS; 1495 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1496 SET(sc->sc_mcr, MCR_AFE); 1497 } else { 1498 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1499 } 1500 } else if (ISSET(t->c_cflag, MDMBUF)) { 1501 /* 1502 * For DTR/DCD flow control, make sure we don't toggle DTR for 1503 * carrier detection. 1504 */ 1505 sc->sc_mcr_dtr = 0; 1506 sc->sc_mcr_rts = MCR_DTR; 1507 sc->sc_msr_cts = MSR_DCD; 1508 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1509 CLR(sc->sc_mcr, MCR_AFE); 1510 } else { 1511 sc->sc_efr = 0; 1512 } 1513 } else { 1514 /* 1515 * If no flow control, then always set RTS. This will make 1516 * the other side happy if it mistakenly thinks we're doing 1517 * RTS/CTS flow control. 1518 */ 1519 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1520 sc->sc_mcr_rts = 0; 1521 sc->sc_msr_cts = 0; 1522 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1523 CLR(sc->sc_mcr, MCR_AFE); 1524 } else { 1525 sc->sc_efr = 0; 1526 } 1527 if (ISSET(sc->sc_mcr, MCR_DTR)) 1528 SET(sc->sc_mcr, MCR_RTS); 1529 else 1530 CLR(sc->sc_mcr, MCR_RTS); 1531 } 1532 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1533 1534 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1535 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1536 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1537 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1538 1539 sc->sc_dlbl = ospeed; 1540 sc->sc_dlbh = ospeed >> 8; 1541 1542 /* 1543 * Set the FIFO threshold based on the receive speed. 1544 * 1545 * * If it's a low speed, it's probably a mouse or some other 1546 * interactive device, so set the threshold low. 1547 * * If it's a high speed, trim the trigger level down to prevent 1548 * overflows. 1549 * * Otherwise set it a bit higher. 1550 */ 1551 if (sc->sc_type == COM_TYPE_HAYESP) { 1552 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1553 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1554 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1555 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1556 if (t->c_ospeed <= 1200) 1557 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1558 else if (t->c_ospeed <= 38400) 1559 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1560 else 1561 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1562 } else { 1563 sc->sc_fifo = 0; 1564 } 1565 1566 if (sc->sc_type == COM_TYPE_INGENIC) 1567 sc->sc_fifo |= FIFO_UART_ON; 1568 1569 /* And copy to tty. */ 1570 tp->t_ispeed = t->c_ospeed; 1571 tp->t_ospeed = t->c_ospeed; 1572 tp->t_cflag = t->c_cflag; 1573 1574 if (!sc->sc_heldchange) { 1575 if (sc->sc_tx_busy) { 1576 sc->sc_heldtbc = sc->sc_tbc; 1577 sc->sc_tbc = 0; 1578 sc->sc_heldchange = 1; 1579 } else 1580 com_loadchannelregs(sc); 1581 } 1582 1583 if (!ISSET(t->c_cflag, CHWFLOW)) { 1584 /* Disable the high water mark. */ 1585 sc->sc_r_hiwat = 0; 1586 sc->sc_r_lowat = 0; 1587 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1588 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1589 com_schedrx(sc); 1590 } 1591 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1592 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1593 com_hwiflow(sc); 1594 } 1595 } else { 1596 sc->sc_r_hiwat = com_rbuf_hiwat; 1597 sc->sc_r_lowat = com_rbuf_lowat; 1598 } 1599 1600 mutex_spin_exit(&sc->sc_lock); 1601 1602 /* 1603 * Update the tty layer's idea of the carrier bit, in case we changed 1604 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1605 * explicit request. 1606 */ 1607 if (sc->sc_type == COM_TYPE_INGENIC) { 1608 /* no DCD here */ 1609 (void) (*tp->t_linesw->l_modem)(tp, 1); 1610 } else 1611 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1612 1613 #ifdef COM_DEBUG 1614 if (com_debug) 1615 comstatus(sc, "comparam "); 1616 #endif 1617 1618 if (!ISSET(t->c_cflag, CHWFLOW)) { 1619 if (sc->sc_tx_stopped) { 1620 sc->sc_tx_stopped = 0; 1621 comstart(tp); 1622 } 1623 } 1624 1625 return (0); 1626 } 1627 1628 void 1629 com_iflush(struct com_softc *sc) 1630 { 1631 struct com_regs *regsp = &sc->sc_regs; 1632 uint8_t fifo; 1633 #ifdef DIAGNOSTIC 1634 int reg; 1635 #endif 1636 int timo; 1637 1638 #ifdef DIAGNOSTIC 1639 reg = 0xffff; 1640 #endif 1641 timo = 50000; 1642 /* flush any pending I/O */ 1643 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1644 && --timo) 1645 #ifdef DIAGNOSTIC 1646 reg = 1647 #else 1648 (void) 1649 #endif 1650 CSR_READ_1(regsp, COM_REG_RXDATA); 1651 #ifdef DIAGNOSTIC 1652 if (!timo) 1653 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1654 #endif 1655 1656 switch (sc->sc_type) { 1657 case COM_TYPE_16750: 1658 case COM_TYPE_DW_APB: 1659 /* 1660 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1661 * This should prevent triggering busy interrupt while 1662 * manipulating divisors. 1663 */ 1664 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1665 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1666 CSR_WRITE_1(regsp, COM_REG_FIFO, 1667 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1668 delay(100); 1669 break; 1670 } 1671 } 1672 1673 void 1674 com_loadchannelregs(struct com_softc *sc) 1675 { 1676 struct com_regs *regsp = &sc->sc_regs; 1677 1678 /* XXXXX necessary? */ 1679 com_iflush(sc); 1680 1681 if (sc->sc_type == COM_TYPE_PXA2x0) 1682 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1683 else 1684 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1685 1686 if (sc->sc_type == COM_TYPE_OMAP) { 1687 /* disable before changing settings */ 1688 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1689 } 1690 1691 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1692 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1693 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1694 /* no EFR on alchemy */ 1695 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1696 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1697 } 1698 if (sc->sc_type == COM_TYPE_AU1x00) { 1699 /* alchemy has single separate 16-bit clock divisor register */ 1700 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1701 (sc->sc_dlbh << 8)); 1702 } else { 1703 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1704 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1705 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1706 } 1707 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1708 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1709 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1710 if (sc->sc_type == COM_TYPE_HAYESP) { 1711 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1712 HAYESP_SETPRESCALER); 1713 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1714 sc->sc_prescaler); 1715 } 1716 if (sc->sc_type == COM_TYPE_OMAP) { 1717 /* setup the fifos. the FCR value is not used as long 1718 as SCR[6] and SCR[7] are 0, which they are at reset 1719 and we never touch the SCR register */ 1720 uint8_t rx_fifo_trig = 40; 1721 uint8_t tx_fifo_trig = 60; 1722 uint8_t rx_start = 8; 1723 uint8_t rx_halt = 60; 1724 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1725 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1726 1727 /* enable access to TCR & TLR */ 1728 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1729 1730 /* write tcr and tlr values */ 1731 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1732 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1733 1734 /* disable access to TCR & TLR */ 1735 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1736 1737 /* enable again, but mode is based on speed */ 1738 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1739 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1740 } else { 1741 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1742 } 1743 } 1744 1745 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1746 } 1747 1748 int 1749 comhwiflow(struct tty *tp, int block) 1750 { 1751 struct com_softc *sc = 1752 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1753 1754 if (COM_ISALIVE(sc) == 0) 1755 return (0); 1756 1757 if (sc->sc_mcr_rts == 0) 1758 return (0); 1759 1760 mutex_spin_enter(&sc->sc_lock); 1761 1762 if (block) { 1763 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1764 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1765 com_hwiflow(sc); 1766 } 1767 } else { 1768 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1769 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1770 com_schedrx(sc); 1771 } 1772 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1773 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1774 com_hwiflow(sc); 1775 } 1776 } 1777 1778 mutex_spin_exit(&sc->sc_lock); 1779 return (1); 1780 } 1781 1782 /* 1783 * (un)block input via hw flowcontrol 1784 */ 1785 void 1786 com_hwiflow(struct com_softc *sc) 1787 { 1788 struct com_regs *regsp= &sc->sc_regs; 1789 1790 if (sc->sc_mcr_rts == 0) 1791 return; 1792 1793 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1794 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1795 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1796 } else { 1797 SET(sc->sc_mcr, sc->sc_mcr_rts); 1798 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1799 } 1800 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1801 } 1802 1803 1804 void 1805 comstart(struct tty *tp) 1806 { 1807 struct com_softc *sc = 1808 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1809 struct com_regs *regsp = &sc->sc_regs; 1810 int s; 1811 1812 if (COM_ISALIVE(sc) == 0) 1813 return; 1814 1815 s = spltty(); 1816 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1817 goto out; 1818 if (sc->sc_tx_stopped) 1819 goto out; 1820 if (!ttypull(tp)) 1821 goto out; 1822 1823 /* Grab the first contiguous region of buffer space. */ 1824 { 1825 u_char *tba; 1826 int tbc; 1827 1828 tba = tp->t_outq.c_cf; 1829 tbc = ndqb(&tp->t_outq, 0); 1830 1831 mutex_spin_enter(&sc->sc_lock); 1832 1833 sc->sc_tba = tba; 1834 sc->sc_tbc = tbc; 1835 } 1836 1837 SET(tp->t_state, TS_BUSY); 1838 sc->sc_tx_busy = 1; 1839 1840 /* Enable transmit completion interrupts if necessary. */ 1841 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1842 SET(sc->sc_ier, IER_ETXRDY); 1843 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1844 } 1845 1846 /* Output the first chunk of the contiguous buffer. */ 1847 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1848 u_int n; 1849 1850 n = sc->sc_tbc; 1851 if (n > sc->sc_fifolen) 1852 n = sc->sc_fifolen; 1853 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1854 sc->sc_tbc -= n; 1855 sc->sc_tba += n; 1856 } 1857 1858 mutex_spin_exit(&sc->sc_lock); 1859 out: 1860 splx(s); 1861 return; 1862 } 1863 1864 /* 1865 * Stop output on a line. 1866 */ 1867 void 1868 comstop(struct tty *tp, int flag) 1869 { 1870 struct com_softc *sc = 1871 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1872 1873 mutex_spin_enter(&sc->sc_lock); 1874 if (ISSET(tp->t_state, TS_BUSY)) { 1875 /* Stop transmitting at the next chunk. */ 1876 sc->sc_tbc = 0; 1877 sc->sc_heldtbc = 0; 1878 if (!ISSET(tp->t_state, TS_TTSTOP)) 1879 SET(tp->t_state, TS_FLUSH); 1880 } 1881 mutex_spin_exit(&sc->sc_lock); 1882 } 1883 1884 void 1885 comdiag(void *arg) 1886 { 1887 struct com_softc *sc = arg; 1888 int overflows, floods; 1889 1890 mutex_spin_enter(&sc->sc_lock); 1891 overflows = sc->sc_overflows; 1892 sc->sc_overflows = 0; 1893 floods = sc->sc_floods; 1894 sc->sc_floods = 0; 1895 sc->sc_errors = 0; 1896 mutex_spin_exit(&sc->sc_lock); 1897 1898 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1899 device_xname(sc->sc_dev), 1900 overflows, overflows == 1 ? "" : "s", 1901 floods, floods == 1 ? "" : "s"); 1902 } 1903 1904 integrate void 1905 com_rxsoft(struct com_softc *sc, struct tty *tp) 1906 { 1907 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1908 u_char *get, *end; 1909 u_int cc, scc; 1910 u_char lsr; 1911 int code; 1912 1913 end = sc->sc_ebuf; 1914 get = sc->sc_rbget; 1915 scc = cc = com_rbuf_size - sc->sc_rbavail; 1916 1917 if (cc == com_rbuf_size) { 1918 sc->sc_floods++; 1919 if (sc->sc_errors++ == 0) 1920 callout_reset(&sc->sc_diag_callout, 60 * hz, 1921 comdiag, sc); 1922 } 1923 1924 /* If not yet open, drop the entire buffer content here */ 1925 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1926 get += cc << 1; 1927 if (get >= end) 1928 get -= com_rbuf_size << 1; 1929 cc = 0; 1930 } 1931 while (cc) { 1932 code = get[0]; 1933 lsr = get[1]; 1934 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1935 if (ISSET(lsr, LSR_OE)) { 1936 sc->sc_overflows++; 1937 if (sc->sc_errors++ == 0) 1938 callout_reset(&sc->sc_diag_callout, 1939 60 * hz, comdiag, sc); 1940 } 1941 if (ISSET(lsr, LSR_BI | LSR_FE)) 1942 SET(code, TTY_FE); 1943 if (ISSET(lsr, LSR_PE)) 1944 SET(code, TTY_PE); 1945 } 1946 if ((*rint)(code, tp) == -1) { 1947 /* 1948 * The line discipline's buffer is out of space. 1949 */ 1950 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1951 /* 1952 * We're either not using flow control, or the 1953 * line discipline didn't tell us to block for 1954 * some reason. Either way, we have no way to 1955 * know when there's more space available, so 1956 * just drop the rest of the data. 1957 */ 1958 get += cc << 1; 1959 if (get >= end) 1960 get -= com_rbuf_size << 1; 1961 cc = 0; 1962 } else { 1963 /* 1964 * Don't schedule any more receive processing 1965 * until the line discipline tells us there's 1966 * space available (through comhwiflow()). 1967 * Leave the rest of the data in the input 1968 * buffer. 1969 */ 1970 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1971 } 1972 break; 1973 } 1974 get += 2; 1975 if (get >= end) 1976 get = sc->sc_rbuf; 1977 cc--; 1978 } 1979 1980 if (cc != scc) { 1981 sc->sc_rbget = get; 1982 mutex_spin_enter(&sc->sc_lock); 1983 1984 cc = sc->sc_rbavail += scc - cc; 1985 /* Buffers should be ok again, release possible block. */ 1986 if (cc >= sc->sc_r_lowat) { 1987 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1988 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1989 SET(sc->sc_ier, IER_ERXRDY); 1990 if (sc->sc_type == COM_TYPE_PXA2x0) 1991 SET(sc->sc_ier, IER_ERXTOUT); 1992 if (sc->sc_type == COM_TYPE_INGENIC || 1993 sc->sc_type == COM_TYPE_TEGRA) 1994 SET(sc->sc_ier, IER_ERXTOUT); 1995 1996 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 1997 sc->sc_ier); 1998 } 1999 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 2000 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2001 com_hwiflow(sc); 2002 } 2003 } 2004 mutex_spin_exit(&sc->sc_lock); 2005 } 2006 } 2007 2008 integrate void 2009 com_txsoft(struct com_softc *sc, struct tty *tp) 2010 { 2011 2012 CLR(tp->t_state, TS_BUSY); 2013 if (ISSET(tp->t_state, TS_FLUSH)) 2014 CLR(tp->t_state, TS_FLUSH); 2015 else 2016 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2017 (*tp->t_linesw->l_start)(tp); 2018 } 2019 2020 integrate void 2021 com_stsoft(struct com_softc *sc, struct tty *tp) 2022 { 2023 u_char msr, delta; 2024 2025 mutex_spin_enter(&sc->sc_lock); 2026 msr = sc->sc_msr; 2027 delta = sc->sc_msr_delta; 2028 sc->sc_msr_delta = 0; 2029 mutex_spin_exit(&sc->sc_lock); 2030 2031 if (ISSET(delta, sc->sc_msr_dcd)) { 2032 /* 2033 * Inform the tty layer that carrier detect changed. 2034 */ 2035 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2036 } 2037 2038 if (ISSET(delta, sc->sc_msr_cts)) { 2039 /* Block or unblock output according to flow control. */ 2040 if (ISSET(msr, sc->sc_msr_cts)) { 2041 sc->sc_tx_stopped = 0; 2042 (*tp->t_linesw->l_start)(tp); 2043 } else { 2044 sc->sc_tx_stopped = 1; 2045 } 2046 } 2047 2048 #ifdef COM_DEBUG 2049 if (com_debug) 2050 comstatus(sc, "com_stsoft"); 2051 #endif 2052 } 2053 2054 void 2055 comsoft(void *arg) 2056 { 2057 struct com_softc *sc = arg; 2058 struct tty *tp; 2059 2060 if (COM_ISALIVE(sc) == 0) 2061 return; 2062 2063 tp = sc->sc_tty; 2064 2065 if (sc->sc_rx_ready) { 2066 sc->sc_rx_ready = 0; 2067 com_rxsoft(sc, tp); 2068 } 2069 2070 if (sc->sc_st_check) { 2071 sc->sc_st_check = 0; 2072 com_stsoft(sc, tp); 2073 } 2074 2075 if (sc->sc_tx_done) { 2076 sc->sc_tx_done = 0; 2077 com_txsoft(sc, tp); 2078 } 2079 } 2080 2081 int 2082 comintr(void *arg) 2083 { 2084 struct com_softc *sc = arg; 2085 struct com_regs *regsp = &sc->sc_regs; 2086 2087 u_char *put, *end; 2088 u_int cc; 2089 u_char lsr, iir; 2090 2091 if (COM_ISALIVE(sc) == 0) 2092 return (0); 2093 2094 KASSERT(regsp != NULL); 2095 2096 mutex_spin_enter(&sc->sc_lock); 2097 iir = CSR_READ_1(regsp, COM_REG_IIR); 2098 2099 /* Handle ns16750-specific busy interrupt. */ 2100 if (sc->sc_type == COM_TYPE_16750 && 2101 (iir & IIR_BUSY) == IIR_BUSY) { 2102 for (int timeout = 10000; 2103 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2104 if (timeout <= 0) { 2105 aprint_error_dev(sc->sc_dev, 2106 "timeout while waiting for BUSY interrupt " 2107 "acknowledge\n"); 2108 mutex_spin_exit(&sc->sc_lock); 2109 return (0); 2110 } 2111 2112 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2113 iir = CSR_READ_1(regsp, COM_REG_IIR); 2114 } 2115 2116 /* DesignWare APB UART BUSY interrupt */ 2117 if (sc->sc_type == COM_TYPE_DW_APB && 2118 (iir & IIR_BUSY) == IIR_BUSY) { 2119 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2120 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2121 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2122 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2123 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2124 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2125 CSR_WRITE_1(regsp, COM_REG_HALT, 2126 HALT_CHCFG_EN | HALT_CHCFG_UD); 2127 for (int timeout = 10000000; 2128 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2129 timeout--) { 2130 if (timeout <= 0) { 2131 aprint_error_dev(sc->sc_dev, 2132 "timeout while waiting for HALT " 2133 "update acknowledge 0x%x 0x%x\n", 2134 CSR_READ_1(regsp, COM_REG_HALT), 2135 CSR_READ_1(regsp, COM_REG_USR)); 2136 break; 2137 } 2138 } 2139 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2140 (void)CSR_READ_1(regsp, COM_REG_USR); 2141 } else { 2142 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2143 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2144 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2145 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2146 } 2147 } 2148 2149 if (ISSET(iir, IIR_NOPEND)) { 2150 mutex_spin_exit(&sc->sc_lock); 2151 return (0); 2152 } 2153 2154 end = sc->sc_ebuf; 2155 put = sc->sc_rbput; 2156 cc = sc->sc_rbavail; 2157 2158 again: do { 2159 u_char msr, delta; 2160 2161 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2162 if (ISSET(lsr, LSR_BI)) { 2163 int cn_trapped = 0; /* see above: cn_trap() */ 2164 2165 cn_check_magic(sc->sc_tty->t_dev, 2166 CNC_BREAK, com_cnm_state); 2167 if (cn_trapped) 2168 continue; 2169 #if defined(KGDB) && !defined(DDB) 2170 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2171 kgdb_connect(1); 2172 continue; 2173 } 2174 #endif 2175 } 2176 2177 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2178 lsr |= LSR_RXRDY; 2179 2180 if (ISSET(lsr, LSR_RCV_MASK) && 2181 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2182 while (cc > 0) { 2183 int cn_trapped = 0; 2184 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2185 put[1] = lsr; 2186 cn_check_magic(sc->sc_tty->t_dev, 2187 put[0], com_cnm_state); 2188 if (cn_trapped) 2189 goto next; 2190 put += 2; 2191 if (put >= end) 2192 put = sc->sc_rbuf; 2193 cc--; 2194 next: 2195 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2196 if (!ISSET(lsr, LSR_RCV_MASK)) 2197 break; 2198 } 2199 2200 /* 2201 * Current string of incoming characters ended because 2202 * no more data was available or we ran out of space. 2203 * Schedule a receive event if any data was received. 2204 * If we're out of space, turn off receive interrupts. 2205 */ 2206 sc->sc_rbput = put; 2207 sc->sc_rbavail = cc; 2208 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2209 sc->sc_rx_ready = 1; 2210 2211 /* 2212 * See if we are in danger of overflowing a buffer. If 2213 * so, use hardware flow control to ease the pressure. 2214 */ 2215 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2216 cc < sc->sc_r_hiwat) { 2217 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2218 com_hwiflow(sc); 2219 } 2220 2221 /* 2222 * If we're out of space, disable receive interrupts 2223 * until the queue has drained a bit. 2224 */ 2225 if (!cc) { 2226 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2227 switch (sc->sc_type) { 2228 case COM_TYPE_PXA2x0: 2229 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2230 break; 2231 case COM_TYPE_INGENIC: 2232 case COM_TYPE_TEGRA: 2233 CLR(sc->sc_ier, 2234 IER_ERXRDY | IER_ERXTOUT); 2235 break; 2236 default: 2237 CLR(sc->sc_ier, IER_ERXRDY); 2238 break; 2239 } 2240 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2241 } 2242 } else { 2243 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2244 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2245 continue; 2246 } 2247 } 2248 2249 msr = CSR_READ_1(regsp, COM_REG_MSR); 2250 delta = msr ^ sc->sc_msr; 2251 sc->sc_msr = msr; 2252 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2253 (delta & MSR_DCD)) { 2254 mutex_spin_enter(&timecounter_lock); 2255 pps_capture(&sc->sc_pps_state); 2256 pps_event(&sc->sc_pps_state, 2257 (msr & MSR_DCD) ? 2258 PPS_CAPTUREASSERT : 2259 PPS_CAPTURECLEAR); 2260 mutex_spin_exit(&timecounter_lock); 2261 } 2262 2263 /* 2264 * Process normal status changes 2265 */ 2266 if (ISSET(delta, sc->sc_msr_mask)) { 2267 SET(sc->sc_msr_delta, delta); 2268 2269 /* 2270 * Stop output immediately if we lose the output 2271 * flow control signal or carrier detect. 2272 */ 2273 if (ISSET(~msr, sc->sc_msr_mask)) { 2274 sc->sc_tbc = 0; 2275 sc->sc_heldtbc = 0; 2276 #ifdef COM_DEBUG 2277 if (com_debug) 2278 comstatus(sc, "comintr "); 2279 #endif 2280 } 2281 2282 sc->sc_st_check = 1; 2283 } 2284 } while (!ISSET((iir = 2285 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2286 /* 2287 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2288 * by IIR read, so we can't do this way: `process all interrupts, 2289 * then do TX if possible'. 2290 */ 2291 (iir & IIR_IMASK) != IIR_TXRDY); 2292 2293 /* 2294 * Read LSR again, since there may be an interrupt between 2295 * the last LSR read and IIR read above. 2296 */ 2297 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2298 2299 /* 2300 * See if data can be transmitted as well. 2301 * Schedule tx done event if no data left 2302 * and tty was marked busy. 2303 */ 2304 if (ISSET(lsr, LSR_TXRDY)) { 2305 /* 2306 * If we've delayed a parameter change, do it now, and restart 2307 * output. 2308 */ 2309 if (sc->sc_heldchange) { 2310 com_loadchannelregs(sc); 2311 sc->sc_heldchange = 0; 2312 sc->sc_tbc = sc->sc_heldtbc; 2313 sc->sc_heldtbc = 0; 2314 } 2315 2316 /* Output the next chunk of the contiguous buffer, if any. */ 2317 if (sc->sc_tbc > 0) { 2318 u_int n; 2319 2320 n = sc->sc_tbc; 2321 if (n > sc->sc_fifolen) 2322 n = sc->sc_fifolen; 2323 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2324 sc->sc_tbc -= n; 2325 sc->sc_tba += n; 2326 } else { 2327 /* Disable transmit completion interrupts if necessary. */ 2328 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2329 CLR(sc->sc_ier, IER_ETXRDY); 2330 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2331 } 2332 if (sc->sc_tx_busy) { 2333 sc->sc_tx_busy = 0; 2334 sc->sc_tx_done = 1; 2335 } 2336 } 2337 } 2338 2339 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2340 goto again; 2341 2342 mutex_spin_exit(&sc->sc_lock); 2343 2344 /* Wake up the poller. */ 2345 softint_schedule(sc->sc_si); 2346 2347 #ifdef RND_COM 2348 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2349 #endif 2350 2351 return (1); 2352 } 2353 2354 /* 2355 * The following functions are polled getc and putc routines, shared 2356 * by the console and kgdb glue. 2357 * 2358 * The read-ahead code is so that you can detect pending in-band 2359 * cn_magic in polled mode while doing output rather than having to 2360 * wait until the kernel decides it needs input. 2361 */ 2362 2363 #define MAX_READAHEAD 20 2364 static int com_readahead[MAX_READAHEAD]; 2365 static int com_readaheadcount = 0; 2366 2367 int 2368 com_common_getc(dev_t dev, struct com_regs *regsp) 2369 { 2370 int s = splserial(); 2371 u_char stat, c; 2372 2373 /* got a character from reading things earlier */ 2374 if (com_readaheadcount > 0) { 2375 int i; 2376 2377 c = com_readahead[0]; 2378 for (i = 1; i < com_readaheadcount; i++) { 2379 com_readahead[i-1] = com_readahead[i]; 2380 } 2381 com_readaheadcount--; 2382 splx(s); 2383 return (c); 2384 } 2385 2386 /* don't block until a character becomes available */ 2387 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2388 splx(s); 2389 return -1; 2390 } 2391 2392 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2393 stat = CSR_READ_1(regsp, COM_REG_IIR); 2394 { 2395 int cn_trapped = 0; /* required by cn_trap, see above */ 2396 #ifdef DDB 2397 extern int db_active; 2398 if (!db_active) 2399 #endif 2400 cn_check_magic(dev, c, com_cnm_state); 2401 } 2402 splx(s); 2403 return (c); 2404 } 2405 2406 static void 2407 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2408 { 2409 int s = splserial(); 2410 int cin, stat, timo; 2411 2412 if (com_readaheadcount < MAX_READAHEAD 2413 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2414 int cn_trapped = 0; 2415 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2416 stat = CSR_READ_1(regsp, COM_REG_IIR); 2417 cn_check_magic(dev, cin, com_cnm_state); 2418 com_readahead[com_readaheadcount++] = cin; 2419 } 2420 2421 /* wait for any pending transmission to finish */ 2422 timo = 150000; 2423 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2424 continue; 2425 2426 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2427 COM_BARRIER(regsp, BR | BW); 2428 2429 splx(s); 2430 } 2431 2432 /* 2433 * Initialize UART for use as console or KGDB line. 2434 */ 2435 int 2436 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2437 tcflag_t cflag) 2438 { 2439 2440 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2441 ®sp->cr_ioh)) 2442 return (ENOMEM); /* ??? */ 2443 2444 if (type == COM_TYPE_OMAP) { 2445 /* disable before changing settings */ 2446 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2447 } 2448 2449 rate = comspeed(rate, frequency, type); 2450 if (__predict_true(rate != -1)) { 2451 if (type == COM_TYPE_AU1x00) { 2452 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2453 } else { 2454 /* no EFR on alchemy */ 2455 if ((type != COM_TYPE_16550_NOERS) && 2456 (type != COM_TYPE_INGENIC)) { 2457 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2458 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2459 } 2460 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2461 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2462 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2463 } 2464 } 2465 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2466 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2467 2468 if (type == COM_TYPE_INGENIC) { 2469 CSR_WRITE_1(regsp, COM_REG_FIFO, 2470 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2471 FIFO_TRIGGER_1 | FIFO_UART_ON); 2472 } else { 2473 CSR_WRITE_1(regsp, COM_REG_FIFO, 2474 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2475 FIFO_TRIGGER_1); 2476 } 2477 2478 if (type == COM_TYPE_OMAP) { 2479 /* setup the fifos. the FCR value is not used as long 2480 as SCR[6] and SCR[7] are 0, which they are at reset 2481 and we never touch the SCR register */ 2482 uint8_t rx_fifo_trig = 40; 2483 uint8_t tx_fifo_trig = 60; 2484 uint8_t rx_start = 8; 2485 uint8_t rx_halt = 60; 2486 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2487 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2488 2489 /* enable access to TCR & TLR */ 2490 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2491 2492 /* write tcr and tlr values */ 2493 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2494 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2495 2496 /* disable access to TCR & TLR */ 2497 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2498 2499 /* enable again, but mode is based on speed */ 2500 if (rate > 230400) { 2501 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2502 } else { 2503 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2504 } 2505 } 2506 2507 if (type == COM_TYPE_PXA2x0) 2508 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2509 else 2510 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2511 2512 return (0); 2513 } 2514 2515 int 2516 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2517 tcflag_t cflag) 2518 { 2519 int res; 2520 2521 comcons_info.regs = *regsp; 2522 2523 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2524 if (res) 2525 return (res); 2526 2527 cn_tab = &comcons; 2528 cn_init_magic(&com_cnm_state); 2529 cn_set_magic("\047\001"); /* default magic is BREAK */ 2530 2531 comcons_info.frequency = frequency; 2532 comcons_info.type = type; 2533 comcons_info.rate = rate; 2534 comcons_info.cflag = cflag; 2535 2536 return (0); 2537 } 2538 2539 int 2540 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2541 int type, tcflag_t cflag) 2542 { 2543 struct com_regs regs; 2544 2545 /*XXX*/ 2546 bus_space_handle_t dummy_bsh; 2547 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2548 2549 /* 2550 * dummy_bsh required because com_init_regs() wants it. A 2551 * real bus_space_handle will be filled in by cominit() later. 2552 * XXXJRT Detangle this mess eventually, plz. 2553 */ 2554 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2555 2556 return comcnattach1(®s, rate, frequency, type, cflag); 2557 } 2558 2559 static int 2560 comcnreattach(void) 2561 { 2562 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2563 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2564 } 2565 2566 int 2567 comcngetc(dev_t dev) 2568 { 2569 2570 return (com_common_getc(dev, &comcons_info.regs)); 2571 } 2572 2573 /* 2574 * Console kernel output character routine. 2575 */ 2576 void 2577 comcnputc(dev_t dev, int c) 2578 { 2579 2580 com_common_putc(dev, &comcons_info.regs, c); 2581 } 2582 2583 void 2584 comcnpollc(dev_t dev, int on) 2585 { 2586 2587 com_readaheadcount = 0; 2588 } 2589 2590 #ifdef KGDB 2591 int 2592 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2593 tcflag_t cflag) 2594 { 2595 int res; 2596 2597 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2598 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2599 #if !defined(DDB) 2600 return (EBUSY); /* cannot share with console */ 2601 #else 2602 comkgdbregs = *regsp; 2603 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2604 #endif 2605 } else { 2606 comkgdbregs = *regsp; 2607 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2608 if (res) 2609 return (res); 2610 2611 /* 2612 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2613 * expects this to be initialized 2614 */ 2615 cn_init_magic(&com_cnm_state); 2616 cn_set_magic("\047\001"); 2617 } 2618 2619 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2620 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2621 2622 return (0); 2623 } 2624 2625 int 2626 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2627 int frequency, int type, tcflag_t cflag) 2628 { 2629 struct com_regs regs; 2630 2631 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2632 2633 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2634 } 2635 2636 /* ARGSUSED */ 2637 int 2638 com_kgdb_getc(void *arg) 2639 { 2640 2641 return (com_common_getc(NODEV, &comkgdbregs)); 2642 } 2643 2644 /* ARGSUSED */ 2645 void 2646 com_kgdb_putc(void *arg, int c) 2647 { 2648 2649 com_common_putc(NODEV, &comkgdbregs, c); 2650 } 2651 #endif /* KGDB */ 2652 2653 /* helper function to identify the com ports used by 2654 console or KGDB (and not yet autoconf attached) */ 2655 int 2656 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2657 { 2658 bus_space_handle_t help; 2659 2660 if (!comconsattached && 2661 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2662 iobase == comcons_info.regs.cr_iobase) 2663 help = comcons_info.regs.cr_ioh; 2664 #ifdef KGDB 2665 else if (!com_kgdb_attached && 2666 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2667 iobase == comkgdbregs.cr_iobase) 2668 help = comkgdbregs.cr_ioh; 2669 #endif 2670 else 2671 return (0); 2672 2673 if (ioh) 2674 *ioh = help; 2675 return (1); 2676 } 2677 2678 /* 2679 * this routine exists to serve as a shutdown hook for systems that 2680 * have firmware which doesn't interact properly with a com device in 2681 * FIFO mode. 2682 */ 2683 bool 2684 com_cleanup(device_t self, int how) 2685 { 2686 struct com_softc *sc = device_private(self); 2687 2688 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2689 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2690 2691 return true; 2692 } 2693 2694 bool 2695 com_suspend(device_t self, const pmf_qual_t *qual) 2696 { 2697 struct com_softc *sc = device_private(self); 2698 2699 #if 0 2700 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2701 cn_tab = &comcons_suspend; 2702 #endif 2703 2704 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2705 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2706 2707 return true; 2708 } 2709 2710 bool 2711 com_resume(device_t self, const pmf_qual_t *qual) 2712 { 2713 struct com_softc *sc = device_private(self); 2714 2715 mutex_spin_enter(&sc->sc_lock); 2716 com_loadchannelregs(sc); 2717 mutex_spin_exit(&sc->sc_lock); 2718 2719 return true; 2720 } 2721
Indexes created Mon Oct 20 20:10:13 GMT 2025