com.c revision 1.350
1 /* $NetBSD: com.c,v 1.350 2018/11/30 16:26:19 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.350 2018/11/30 16:26:19 jmcneill Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #ifdef COM_REGMAP 132 #define CSR_WRITE_1(r, o, v) \ 133 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 134 #define CSR_READ_1(r, o) \ 135 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 136 #define CSR_WRITE_2(r, o, v) \ 137 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 138 #define CSR_READ_2(r, o) \ 139 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 140 #define CSR_WRITE_MULTI(r, o, p, n) \ 141 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 142 #else 143 #define CSR_WRITE_1(r, o, v) \ 144 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v) 145 #define CSR_READ_1(r, o) \ 146 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o) 147 #define CSR_WRITE_2(r, o, v) \ 148 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v) 149 #define CSR_READ_2(r, o) \ 150 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o) 151 #define CSR_WRITE_MULTI(r, o, p, n) \ 152 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n) 153 #endif 154 155 156 static void com_enable_debugport(struct com_softc *); 157 158 void com_config(struct com_softc *); 159 void com_shutdown(struct com_softc *); 160 int comspeed(long, long, int); 161 static u_char cflag2lcr(tcflag_t); 162 int comparam(struct tty *, struct termios *); 163 void comstart(struct tty *); 164 int comhwiflow(struct tty *, int); 165 166 void com_loadchannelregs(struct com_softc *); 167 void com_hwiflow(struct com_softc *); 168 void com_break(struct com_softc *, int); 169 void com_modem(struct com_softc *, int); 170 void tiocm_to_com(struct com_softc *, u_long, int); 171 int com_to_tiocm(struct com_softc *); 172 void com_iflush(struct com_softc *); 173 174 int com_common_getc(dev_t, struct com_regs *); 175 static void com_common_putc(dev_t, struct com_regs *, int); 176 177 int cominit(struct com_regs *, int, int, int, tcflag_t); 178 179 static int comcnreattach(void); 180 181 int comcngetc(dev_t); 182 void comcnputc(dev_t, int); 183 void comcnpollc(dev_t, int); 184 185 #define integrate static inline 186 void comsoft(void *); 187 integrate void com_rxsoft(struct com_softc *, struct tty *); 188 integrate void com_txsoft(struct com_softc *, struct tty *); 189 integrate void com_stsoft(struct com_softc *, struct tty *); 190 integrate void com_schedrx(struct com_softc *); 191 void comdiag(void *); 192 193 dev_type_open(comopen); 194 dev_type_close(comclose); 195 dev_type_read(comread); 196 dev_type_write(comwrite); 197 dev_type_ioctl(comioctl); 198 dev_type_stop(comstop); 199 dev_type_tty(comtty); 200 dev_type_poll(compoll); 201 202 static struct comcons_info comcons_info; 203 204 /* 205 * Following are all routines needed for COM to act as console 206 */ 207 static struct consdev comcons = { 208 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 209 NODEV, CN_NORMAL 210 }; 211 212 213 const struct cdevsw com_cdevsw = { 214 .d_open = comopen, 215 .d_close = comclose, 216 .d_read = comread, 217 .d_write = comwrite, 218 .d_ioctl = comioctl, 219 .d_stop = comstop, 220 .d_tty = comtty, 221 .d_poll = compoll, 222 .d_mmap = nommap, 223 .d_kqfilter = ttykqfilter, 224 .d_discard = nodiscard, 225 .d_flag = D_TTY 226 }; 227 228 /* 229 * Make this an option variable one can patch. 230 * But be warned: this must be a power of 2! 231 */ 232 u_int com_rbuf_size = COM_RING_SIZE; 233 234 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 235 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 236 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 237 238 static int comconsattached; 239 static struct cnm_state com_cnm_state; 240 241 #ifdef KGDB 242 #include <sys/kgdb.h> 243 244 static struct com_regs comkgdbregs; 245 static int com_kgdb_attached; 246 247 int com_kgdb_getc(void *); 248 void com_kgdb_putc(void *, int); 249 #endif /* KGDB */ 250 251 #ifdef COM_REGMAP 252 /* initializer for typical 16550-ish hardware */ 253 #define COM_REG_STD { \ 254 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 255 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 256 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr, com_tfl, com_rfl, \ 257 0, 0, 0, 0, 0, 0, 0, com_halt } 258 259 const bus_size_t com_std_map[42] = COM_REG_STD; 260 #endif /* COM_REGMAP */ 261 262 #define COMDIALOUT_MASK TTDIALOUT_MASK 263 264 #define COMUNIT(x) TTUNIT(x) 265 #define COMDIALOUT(x) TTDIALOUT(x) 266 267 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 268 device_is_active((sc)->sc_dev)) 269 270 #define BR BUS_SPACE_BARRIER_READ 271 #define BW BUS_SPACE_BARRIER_WRITE 272 #define COM_BARRIER(r, f) \ 273 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 274 275 /*ARGSUSED*/ 276 int 277 comspeed(long speed, long frequency, int type) 278 { 279 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 280 281 int x, err; 282 int divisor = 16; 283 284 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 285 divisor = 13; 286 } 287 288 if (speed == 0) 289 return (0); 290 if (speed < 0) 291 return (-1); 292 x = divrnd(frequency / divisor, speed); 293 if (x <= 0) 294 return (-1); 295 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 296 if (err < 0) 297 err = -err; 298 if (err > COM_TOLERANCE) 299 return (-1); 300 return (x); 301 302 #undef divrnd 303 } 304 305 #ifdef COM_DEBUG 306 int com_debug = 0; 307 308 void comstatus(struct com_softc *, const char *); 309 void 310 comstatus(struct com_softc *sc, const char *str) 311 { 312 struct tty *tp = sc->sc_tty; 313 314 aprint_normal_dev(sc->sc_dev, 315 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 316 str, 317 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 318 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 319 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 320 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 321 sc->sc_tx_stopped ? '+' : '-'); 322 323 aprint_normal_dev(sc->sc_dev, 324 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 325 str, 326 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 327 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 328 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 329 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 330 sc->sc_rx_flags); 331 } 332 #endif 333 334 int 335 com_probe_subr(struct com_regs *regs) 336 { 337 338 /* force access to id reg */ 339 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 340 CSR_WRITE_1(regs, COM_REG_IIR, 0); 341 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 342 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 343 return (0); 344 345 return (1); 346 } 347 348 int 349 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 350 { 351 struct com_regs regs; 352 353 regs.cr_iot = iot; 354 regs.cr_ioh = ioh; 355 #ifdef COM_REGMAP 356 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 357 #endif 358 359 return com_probe_subr(®s); 360 } 361 362 /* 363 * No locking in this routine; it is only called during attach, 364 * or with the port already locked. 365 */ 366 static void 367 com_enable_debugport(struct com_softc *sc) 368 { 369 370 /* Turn on line break interrupt, set carrier. */ 371 sc->sc_ier = IER_ERLS; 372 if (sc->sc_type == COM_TYPE_PXA2x0) 373 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 374 if (sc->sc_type == COM_TYPE_INGENIC || 375 sc->sc_type == COM_TYPE_TEGRA) 376 sc->sc_ier |= IER_ERXTOUT; 377 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 378 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 379 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 380 } 381 382 static void 383 com_intr_poll(void *arg) 384 { 385 struct com_softc * const sc = arg; 386 387 comintr(sc); 388 389 callout_schedule(&sc->sc_poll_callout, 1); 390 } 391 392 void 393 com_attach_subr(struct com_softc *sc) 394 { 395 struct com_regs *regsp = &sc->sc_regs; 396 struct tty *tp; 397 u_int8_t lcr; 398 const char *fifo_msg = NULL; 399 prop_dictionary_t dict; 400 bool is_console = true; 401 bool force_console = false; 402 403 aprint_naive("\n"); 404 405 dict = device_properties(sc->sc_dev); 406 prop_dictionary_get_bool(dict, "is_console", &is_console); 407 prop_dictionary_get_bool(dict, "force_console", &force_console); 408 callout_init(&sc->sc_diag_callout, 0); 409 callout_init(&sc->sc_poll_callout, 0); 410 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 411 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 412 413 #if defined(COM_16650) 414 sc->sc_type = COM_TYPE_16650; 415 #elif defined(COM_16750) 416 sc->sc_type = COM_TYPE_16750; 417 #elif defined(COM_HAYESP) 418 sc->sc_type = COM_TYPE_HAYESP; 419 #elif defined(COM_PXA2X0) 420 sc->sc_type = COM_TYPE_PXA2x0; 421 #endif 422 423 /* Disable interrupts before configuring the device. */ 424 if (sc->sc_type == COM_TYPE_PXA2x0) 425 sc->sc_ier = IER_EUART; 426 else 427 sc->sc_ier = 0; 428 429 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 430 431 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 432 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 433 comconsattached = 1; 434 435 if (force_console) 436 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 437 438 if (cn_tab == NULL && comcnreattach() != 0) { 439 printf("can't re-init serial console @%lx\n", 440 (u_long)comcons_info.regs.cr_iobase); 441 } 442 443 switch (sc->sc_type) { 444 case COM_TYPE_16750: 445 case COM_TYPE_DW_APB: 446 /* Use in comintr(). */ 447 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 448 break; 449 } 450 451 /* Make sure the console is always "hardwired". */ 452 delay(10000); /* wait for output to finish */ 453 if (is_console) { 454 SET(sc->sc_hwflags, COM_HW_CONSOLE); 455 } 456 457 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 458 } 459 460 /* Probe for FIFO */ 461 switch (sc->sc_type) { 462 case COM_TYPE_HAYESP: 463 goto fifodone; 464 465 case COM_TYPE_AU1x00: 466 sc->sc_fifolen = 16; 467 fifo_msg = "Au1X00 UART, working fifo"; 468 SET(sc->sc_hwflags, COM_HW_FIFO); 469 goto fifodelay; 470 471 case COM_TYPE_16550_NOERS: 472 sc->sc_fifolen = 16; 473 fifo_msg = "ns16650, no ERS, working fifo"; 474 SET(sc->sc_hwflags, COM_HW_FIFO); 475 goto fifodelay; 476 477 case COM_TYPE_OMAP: 478 sc->sc_fifolen = 64; 479 fifo_msg = "OMAP UART, working fifo"; 480 SET(sc->sc_hwflags, COM_HW_FIFO); 481 goto fifodelay; 482 483 case COM_TYPE_INGENIC: 484 sc->sc_fifolen = 16; 485 fifo_msg = "Ingenic UART, working fifo"; 486 SET(sc->sc_hwflags, COM_HW_FIFO); 487 SET(sc->sc_hwflags, COM_HW_NOIEN); 488 goto fifodelay; 489 490 case COM_TYPE_TEGRA: 491 sc->sc_fifolen = 8; 492 fifo_msg = "Tegra UART, working fifo"; 493 SET(sc->sc_hwflags, COM_HW_FIFO); 494 CSR_WRITE_1(regsp, COM_REG_FIFO, 495 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 496 goto fifodelay; 497 498 case COM_TYPE_BCMAUXUART: 499 sc->sc_fifolen = 1; 500 fifo_msg = "BCM AUX UART, working fifo"; 501 SET(sc->sc_hwflags, COM_HW_FIFO); 502 CSR_WRITE_1(regsp, COM_REG_FIFO, 503 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 504 goto fifodelay; 505 } 506 507 sc->sc_fifolen = 1; 508 /* look for a NS 16550AF UART with FIFOs */ 509 if (sc->sc_type == COM_TYPE_INGENIC) { 510 CSR_WRITE_1(regsp, COM_REG_FIFO, 511 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 512 FIFO_TRIGGER_14 | FIFO_UART_ON); 513 } else 514 CSR_WRITE_1(regsp, COM_REG_FIFO, 515 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 516 delay(100); 517 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 518 == IIR_FIFO_MASK) 519 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 520 == FIFO_TRIGGER_14) { 521 SET(sc->sc_hwflags, COM_HW_FIFO); 522 523 fifo_msg = "ns16550a, working fifo"; 524 525 /* 526 * IIR changes into the EFR if LCR is set to LCR_EERS 527 * on 16650s. We also know IIR != 0 at this point. 528 * Write 0 into the EFR, and read it. If the result 529 * is 0, we have a 16650. 530 * 531 * Older 16650s were broken; the test to detect them 532 * is taken from the Linux driver. Apparently 533 * setting DLAB enable gives access to the EFR on 534 * these chips. 535 */ 536 if (sc->sc_type == COM_TYPE_16650) { 537 lcr = CSR_READ_1(regsp, COM_REG_LCR); 538 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 539 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 540 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 541 CSR_WRITE_1(regsp, COM_REG_LCR, 542 lcr | LCR_DLAB); 543 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 544 CLR(sc->sc_hwflags, COM_HW_FIFO); 545 sc->sc_fifolen = 0; 546 } else { 547 SET(sc->sc_hwflags, COM_HW_FLOW); 548 sc->sc_fifolen = 32; 549 } 550 } else 551 sc->sc_fifolen = 16; 552 553 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 554 if (sc->sc_fifolen == 0) 555 fifo_msg = "st16650, broken fifo"; 556 else if (sc->sc_fifolen == 32) 557 fifo_msg = "st16650a, working fifo"; 558 else 559 fifo_msg = "ns16550a, working fifo"; 560 } 561 562 /* 563 * TL16C750 can enable 64byte FIFO, only when DLAB 564 * is 1. However, some 16750 may always enable. For 565 * example, restrictions according to DLAB in a data 566 * sheet for SC16C750 were not described. 567 * Please enable 'options COM_16650', supposing you 568 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 569 * should become effective. 570 */ 571 if (sc->sc_type == COM_TYPE_16750) { 572 uint8_t iir1, iir2; 573 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 574 575 lcr = CSR_READ_1(regsp, COM_REG_LCR); 576 CSR_WRITE_1(regsp, COM_REG_LCR, 577 lcr & ~LCR_DLAB); 578 CSR_WRITE_1(regsp, COM_REG_FIFO, 579 fcr | FIFO_64B_ENABLE); 580 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 581 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 582 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 583 CSR_WRITE_1(regsp, COM_REG_FIFO, 584 fcr | FIFO_64B_ENABLE); 585 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 586 587 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 588 589 if (!ISSET(iir1, IIR_64B_FIFO) && 590 ISSET(iir2, IIR_64B_FIFO)) { 591 /* It is TL16C750. */ 592 sc->sc_fifolen = 64; 593 SET(sc->sc_hwflags, COM_HW_AFE); 594 } else 595 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 596 597 if (sc->sc_fifolen == 64) 598 fifo_msg = "tl16c750, working fifo"; 599 else 600 fifo_msg = "ns16750, working fifo"; 601 } 602 } else 603 fifo_msg = "ns16550, broken fifo"; 604 else 605 fifo_msg = "ns8250 or ns16450, no fifo"; 606 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 607 608 fifodelay: 609 /* 610 * Some chips will clear down both Tx and Rx FIFOs when zero is 611 * written to com_fifo. If this chip is the console, writing zero 612 * results in some of the chip/FIFO description being lost, so delay 613 * printing it until now. 614 */ 615 delay(10); 616 aprint_normal(": %s\n", fifo_msg); 617 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 618 sc->sc_fifolen = 1; 619 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 620 } 621 622 fifodone: 623 624 tp = tty_alloc(); 625 tp->t_oproc = comstart; 626 tp->t_param = comparam; 627 tp->t_hwiflow = comhwiflow; 628 tp->t_softc = sc; 629 630 sc->sc_tty = tp; 631 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 632 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 633 sc->sc_rbavail = com_rbuf_size; 634 if (sc->sc_rbuf == NULL) { 635 aprint_error_dev(sc->sc_dev, 636 "unable to allocate ring buffer\n"); 637 return; 638 } 639 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 640 641 tty_attach(tp); 642 643 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 644 SET(sc->sc_mcr, MCR_IENABLE); 645 646 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 647 int maj; 648 649 /* locate the major number */ 650 maj = cdevsw_lookup_major(&com_cdevsw); 651 652 tp->t_dev = cn_tab->cn_dev = makedev(maj, 653 device_unit(sc->sc_dev)); 654 655 aprint_normal_dev(sc->sc_dev, "console\n"); 656 } 657 658 #ifdef KGDB 659 /* 660 * Allow kgdb to "take over" this port. If this is 661 * not the console and is the kgdb device, it has 662 * exclusive use. If it's the console _and_ the 663 * kgdb device, it doesn't. 664 */ 665 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 666 regsp->cr_iobase == comkgdbregs.cr_iobase) { 667 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 668 com_kgdb_attached = 1; 669 670 SET(sc->sc_hwflags, COM_HW_KGDB); 671 } 672 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 673 } 674 #endif 675 676 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 677 678 #ifdef RND_COM 679 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 680 RND_TYPE_TTY, RND_FLAG_DEFAULT); 681 #endif 682 683 /* if there are no enable/disable functions, assume the device 684 is always enabled */ 685 if (!sc->enable) 686 sc->enabled = 1; 687 688 com_config(sc); 689 690 SET(sc->sc_hwflags, COM_HW_DEV_OK); 691 692 if (ISSET(sc->sc_hwflags, COM_HW_POLL)) 693 callout_schedule(&sc->sc_poll_callout, 1); 694 } 695 696 void 697 com_config(struct com_softc *sc) 698 { 699 struct com_regs *regsp = &sc->sc_regs; 700 701 /* Disable interrupts before configuring the device. */ 702 if (sc->sc_type == COM_TYPE_PXA2x0) 703 sc->sc_ier = IER_EUART; 704 else 705 sc->sc_ier = 0; 706 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 707 (void) CSR_READ_1(regsp, COM_REG_IIR); 708 709 /* Look for a Hayes ESP board. */ 710 if (sc->sc_type == COM_TYPE_HAYESP) { 711 712 /* Set 16550 compatibility mode */ 713 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 714 HAYESP_SETMODE); 715 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 716 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 717 HAYESP_MODE_SCALE); 718 719 /* Set RTS/CTS flow control */ 720 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 721 HAYESP_SETFLOWTYPE); 722 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 723 HAYESP_FLOW_RTS); 724 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 725 HAYESP_FLOW_CTS); 726 727 /* Set flow control levels */ 728 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 729 HAYESP_SETRXFLOW); 730 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 731 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 732 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 733 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 734 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 735 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 736 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 737 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 738 } 739 740 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 741 com_enable_debugport(sc); 742 } 743 744 #if 0 745 static int 746 comcngetc_detached(dev_t dev) 747 { 748 return 0; 749 } 750 751 static void 752 comcnputc_detached(dev_t dev, int c) 753 { 754 } 755 #endif 756 757 int 758 com_detach(device_t self, int flags) 759 { 760 struct com_softc *sc = device_private(self); 761 int maj, mn; 762 763 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 764 return EBUSY; 765 766 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 767 (flags & DETACH_SHUTDOWN) != 0) 768 return EBUSY; 769 770 if (sc->disable != NULL && sc->enabled != 0) { 771 (*sc->disable)(sc); 772 sc->enabled = 0; 773 } 774 775 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 776 comconsattached = 0; 777 cn_tab = NULL; 778 } 779 780 /* locate the major number */ 781 maj = cdevsw_lookup_major(&com_cdevsw); 782 783 /* Nuke the vnodes for any open instances. */ 784 mn = device_unit(self); 785 vdevgone(maj, mn, mn, VCHR); 786 787 mn |= COMDIALOUT_MASK; 788 vdevgone(maj, mn, mn, VCHR); 789 790 if (sc->sc_rbuf == NULL) { 791 /* 792 * Ring buffer allocation failed in the com_attach_subr, 793 * only the tty is allocated, and nothing else. 794 */ 795 tty_free(sc->sc_tty); 796 return 0; 797 } 798 799 /* Free the receive buffer. */ 800 free(sc->sc_rbuf, M_DEVBUF); 801 802 /* Detach and free the tty. */ 803 tty_detach(sc->sc_tty); 804 tty_free(sc->sc_tty); 805 806 /* Unhook the soft interrupt handler. */ 807 softint_disestablish(sc->sc_si); 808 809 #ifdef RND_COM 810 /* Unhook the entropy source. */ 811 rnd_detach_source(&sc->rnd_source); 812 #endif 813 callout_destroy(&sc->sc_diag_callout); 814 815 /* Destroy the lock. */ 816 mutex_destroy(&sc->sc_lock); 817 818 return (0); 819 } 820 821 void 822 com_shutdown(struct com_softc *sc) 823 { 824 struct tty *tp = sc->sc_tty; 825 826 mutex_spin_enter(&sc->sc_lock); 827 828 /* If we were asserting flow control, then deassert it. */ 829 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 830 com_hwiflow(sc); 831 832 /* Clear any break condition set with TIOCSBRK. */ 833 com_break(sc, 0); 834 835 /* 836 * Hang up if necessary. Wait a bit, so the other side has time to 837 * notice even if we immediately open the port again. 838 * Avoid tsleeping above splhigh(). 839 */ 840 if (ISSET(tp->t_cflag, HUPCL)) { 841 com_modem(sc, 0); 842 mutex_spin_exit(&sc->sc_lock); 843 /* XXX will only timeout */ 844 (void) kpause(ttclos, false, hz, NULL); 845 mutex_spin_enter(&sc->sc_lock); 846 } 847 848 /* Turn off interrupts. */ 849 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 850 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 851 if ((sc->sc_type == COM_TYPE_PXA2x0) || 852 (sc->sc_type == COM_TYPE_INGENIC) || 853 (sc->sc_type == COM_TYPE_TEGRA)) 854 sc->sc_ier |= IER_ERXTOUT; 855 } else 856 sc->sc_ier = 0; 857 858 if (sc->sc_type == COM_TYPE_PXA2x0) 859 sc->sc_ier |= IER_EUART; 860 861 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 862 863 mutex_spin_exit(&sc->sc_lock); 864 865 if (sc->disable) { 866 #ifdef DIAGNOSTIC 867 if (!sc->enabled) 868 panic("com_shutdown: not enabled?"); 869 #endif 870 (*sc->disable)(sc); 871 sc->enabled = 0; 872 } 873 } 874 875 int 876 comopen(dev_t dev, int flag, int mode, struct lwp *l) 877 { 878 struct com_softc *sc; 879 struct tty *tp; 880 int s; 881 int error; 882 883 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 884 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 885 sc->sc_rbuf == NULL) 886 return (ENXIO); 887 888 if (!device_is_active(sc->sc_dev)) 889 return (ENXIO); 890 891 #ifdef KGDB 892 /* 893 * If this is the kgdb port, no other use is permitted. 894 */ 895 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 896 return (EBUSY); 897 #endif 898 899 tp = sc->sc_tty; 900 901 /* 902 * If the device is exclusively for kernel use, deny userland 903 * open. 904 */ 905 if (ISSET(tp->t_state, TS_KERN_ONLY)) 906 return (EBUSY); 907 908 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 909 return (EBUSY); 910 911 s = spltty(); 912 913 /* 914 * Do the following iff this is a first open. 915 */ 916 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 917 struct termios t; 918 919 tp->t_dev = dev; 920 921 if (sc->enable) { 922 if ((*sc->enable)(sc)) { 923 splx(s); 924 aprint_error_dev(sc->sc_dev, 925 "device enable failed\n"); 926 return (EIO); 927 } 928 mutex_spin_enter(&sc->sc_lock); 929 sc->enabled = 1; 930 com_config(sc); 931 } else { 932 mutex_spin_enter(&sc->sc_lock); 933 } 934 935 /* Turn on interrupts. */ 936 sc->sc_ier = IER_ERXRDY | IER_ERLS; 937 if (!ISSET(tp->t_cflag, CLOCAL)) 938 sc->sc_ier |= IER_EMSC; 939 940 if (sc->sc_type == COM_TYPE_PXA2x0) 941 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 942 else if (sc->sc_type == COM_TYPE_INGENIC || 943 sc->sc_type == COM_TYPE_TEGRA) 944 sc->sc_ier |= IER_ERXTOUT; 945 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 946 947 /* Fetch the current modem control status, needed later. */ 948 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 949 950 /* Clear PPS capture state on first open. */ 951 mutex_spin_enter(&timecounter_lock); 952 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 953 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 954 pps_init(&sc->sc_pps_state); 955 mutex_spin_exit(&timecounter_lock); 956 957 mutex_spin_exit(&sc->sc_lock); 958 959 /* 960 * Initialize the termios status to the defaults. Add in the 961 * sticky bits from TIOCSFLAGS. 962 */ 963 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 964 t.c_ospeed = comcons_info.rate; 965 t.c_cflag = comcons_info.cflag; 966 } else { 967 t.c_ospeed = TTYDEF_SPEED; 968 t.c_cflag = TTYDEF_CFLAG; 969 } 970 t.c_ispeed = t.c_ospeed; 971 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 972 SET(t.c_cflag, CLOCAL); 973 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 974 SET(t.c_cflag, CRTSCTS); 975 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 976 SET(t.c_cflag, MDMBUF); 977 /* Make sure comparam() will do something. */ 978 tp->t_ospeed = 0; 979 (void) comparam(tp, &t); 980 tp->t_iflag = TTYDEF_IFLAG; 981 tp->t_oflag = TTYDEF_OFLAG; 982 tp->t_lflag = TTYDEF_LFLAG; 983 ttychars(tp); 984 ttsetwater(tp); 985 986 mutex_spin_enter(&sc->sc_lock); 987 988 /* 989 * Turn on DTR. We must always do this, even if carrier is not 990 * present, because otherwise we'd have to use TIOCSDTR 991 * immediately after setting CLOCAL, which applications do not 992 * expect. We always assert DTR while the device is open 993 * unless explicitly requested to deassert it. 994 */ 995 com_modem(sc, 1); 996 997 /* Clear the input ring, and unblock. */ 998 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 999 sc->sc_rbavail = com_rbuf_size; 1000 com_iflush(sc); 1001 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1002 com_hwiflow(sc); 1003 1004 #ifdef COM_DEBUG 1005 if (com_debug) 1006 comstatus(sc, "comopen "); 1007 #endif 1008 1009 mutex_spin_exit(&sc->sc_lock); 1010 } 1011 1012 splx(s); 1013 1014 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1015 if (error) 1016 goto bad; 1017 1018 error = (*tp->t_linesw->l_open)(dev, tp); 1019 if (error) 1020 goto bad; 1021 1022 return (0); 1023 1024 bad: 1025 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1026 /* 1027 * We failed to open the device, and nobody else had it opened. 1028 * Clean up the state as appropriate. 1029 */ 1030 com_shutdown(sc); 1031 } 1032 1033 return (error); 1034 } 1035 1036 int 1037 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1038 { 1039 struct com_softc *sc = 1040 device_lookup_private(&com_cd, COMUNIT(dev)); 1041 struct tty *tp = sc->sc_tty; 1042 1043 /* XXX This is for cons.c. */ 1044 if (!ISSET(tp->t_state, TS_ISOPEN)) 1045 return (0); 1046 /* 1047 * If the device is exclusively for kernel use, deny userland 1048 * close. 1049 */ 1050 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1051 return (0); 1052 1053 (*tp->t_linesw->l_close)(tp, flag); 1054 ttyclose(tp); 1055 1056 if (COM_ISALIVE(sc) == 0) 1057 return (0); 1058 1059 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1060 /* 1061 * Although we got a last close, the device may still be in 1062 * use; e.g. if this was the dialout node, and there are still 1063 * processes waiting for carrier on the non-dialout node. 1064 */ 1065 com_shutdown(sc); 1066 } 1067 1068 return (0); 1069 } 1070 1071 int 1072 comread(dev_t dev, struct uio *uio, int flag) 1073 { 1074 struct com_softc *sc = 1075 device_lookup_private(&com_cd, COMUNIT(dev)); 1076 struct tty *tp = sc->sc_tty; 1077 1078 if (COM_ISALIVE(sc) == 0) 1079 return (EIO); 1080 1081 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1082 } 1083 1084 int 1085 comwrite(dev_t dev, struct uio *uio, int flag) 1086 { 1087 struct com_softc *sc = 1088 device_lookup_private(&com_cd, COMUNIT(dev)); 1089 struct tty *tp = sc->sc_tty; 1090 1091 if (COM_ISALIVE(sc) == 0) 1092 return (EIO); 1093 1094 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1095 } 1096 1097 int 1098 compoll(dev_t dev, int events, struct lwp *l) 1099 { 1100 struct com_softc *sc = 1101 device_lookup_private(&com_cd, COMUNIT(dev)); 1102 struct tty *tp = sc->sc_tty; 1103 1104 if (COM_ISALIVE(sc) == 0) 1105 return (POLLHUP); 1106 1107 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1108 } 1109 1110 struct tty * 1111 comtty(dev_t dev) 1112 { 1113 struct com_softc *sc = 1114 device_lookup_private(&com_cd, COMUNIT(dev)); 1115 struct tty *tp = sc->sc_tty; 1116 1117 return (tp); 1118 } 1119 1120 int 1121 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1122 { 1123 struct com_softc *sc; 1124 struct tty *tp; 1125 int error; 1126 1127 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1128 if (sc == NULL) 1129 return ENXIO; 1130 if (COM_ISALIVE(sc) == 0) 1131 return (EIO); 1132 1133 tp = sc->sc_tty; 1134 1135 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1136 if (error != EPASSTHROUGH) 1137 return (error); 1138 1139 error = ttioctl(tp, cmd, data, flag, l); 1140 if (error != EPASSTHROUGH) 1141 return (error); 1142 1143 error = 0; 1144 switch (cmd) { 1145 case TIOCSFLAGS: 1146 error = kauth_authorize_device_tty(l->l_cred, 1147 KAUTH_DEVICE_TTY_PRIVSET, tp); 1148 break; 1149 default: 1150 /* nothing */ 1151 break; 1152 } 1153 if (error) { 1154 return error; 1155 } 1156 1157 mutex_spin_enter(&sc->sc_lock); 1158 1159 switch (cmd) { 1160 case TIOCSBRK: 1161 com_break(sc, 1); 1162 break; 1163 1164 case TIOCCBRK: 1165 com_break(sc, 0); 1166 break; 1167 1168 case TIOCSDTR: 1169 com_modem(sc, 1); 1170 break; 1171 1172 case TIOCCDTR: 1173 com_modem(sc, 0); 1174 break; 1175 1176 case TIOCGFLAGS: 1177 *(int *)data = sc->sc_swflags; 1178 break; 1179 1180 case TIOCSFLAGS: 1181 sc->sc_swflags = *(int *)data; 1182 break; 1183 1184 case TIOCMSET: 1185 case TIOCMBIS: 1186 case TIOCMBIC: 1187 tiocm_to_com(sc, cmd, *(int *)data); 1188 break; 1189 1190 case TIOCMGET: 1191 *(int *)data = com_to_tiocm(sc); 1192 break; 1193 1194 case PPS_IOC_CREATE: 1195 case PPS_IOC_DESTROY: 1196 case PPS_IOC_GETPARAMS: 1197 case PPS_IOC_SETPARAMS: 1198 case PPS_IOC_GETCAP: 1199 case PPS_IOC_FETCH: 1200 #ifdef PPS_SYNC 1201 case PPS_IOC_KCBIND: 1202 #endif 1203 mutex_spin_enter(&timecounter_lock); 1204 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1205 mutex_spin_exit(&timecounter_lock); 1206 break; 1207 1208 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1209 mutex_spin_enter(&timecounter_lock); 1210 #ifndef PPS_TRAILING_EDGE 1211 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1212 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1213 #else 1214 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1215 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1216 #endif 1217 mutex_spin_exit(&timecounter_lock); 1218 break; 1219 1220 default: 1221 error = EPASSTHROUGH; 1222 break; 1223 } 1224 1225 mutex_spin_exit(&sc->sc_lock); 1226 1227 #ifdef COM_DEBUG 1228 if (com_debug) 1229 comstatus(sc, "comioctl "); 1230 #endif 1231 1232 return (error); 1233 } 1234 1235 integrate void 1236 com_schedrx(struct com_softc *sc) 1237 { 1238 1239 sc->sc_rx_ready = 1; 1240 1241 /* Wake up the poller. */ 1242 softint_schedule(sc->sc_si); 1243 } 1244 1245 void 1246 com_break(struct com_softc *sc, int onoff) 1247 { 1248 1249 if (onoff) 1250 SET(sc->sc_lcr, LCR_SBREAK); 1251 else 1252 CLR(sc->sc_lcr, LCR_SBREAK); 1253 1254 if (!sc->sc_heldchange) { 1255 if (sc->sc_tx_busy) { 1256 sc->sc_heldtbc = sc->sc_tbc; 1257 sc->sc_tbc = 0; 1258 sc->sc_heldchange = 1; 1259 } else 1260 com_loadchannelregs(sc); 1261 } 1262 } 1263 1264 void 1265 com_modem(struct com_softc *sc, int onoff) 1266 { 1267 1268 if (sc->sc_mcr_dtr == 0) 1269 return; 1270 1271 if (onoff) 1272 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1273 else 1274 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1275 1276 if (!sc->sc_heldchange) { 1277 if (sc->sc_tx_busy) { 1278 sc->sc_heldtbc = sc->sc_tbc; 1279 sc->sc_tbc = 0; 1280 sc->sc_heldchange = 1; 1281 } else 1282 com_loadchannelregs(sc); 1283 } 1284 } 1285 1286 void 1287 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1288 { 1289 u_char combits; 1290 1291 combits = 0; 1292 if (ISSET(ttybits, TIOCM_DTR)) 1293 SET(combits, MCR_DTR); 1294 if (ISSET(ttybits, TIOCM_RTS)) 1295 SET(combits, MCR_RTS); 1296 1297 switch (how) { 1298 case TIOCMBIC: 1299 CLR(sc->sc_mcr, combits); 1300 break; 1301 1302 case TIOCMBIS: 1303 SET(sc->sc_mcr, combits); 1304 break; 1305 1306 case TIOCMSET: 1307 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1308 SET(sc->sc_mcr, combits); 1309 break; 1310 } 1311 1312 if (!sc->sc_heldchange) { 1313 if (sc->sc_tx_busy) { 1314 sc->sc_heldtbc = sc->sc_tbc; 1315 sc->sc_tbc = 0; 1316 sc->sc_heldchange = 1; 1317 } else 1318 com_loadchannelregs(sc); 1319 } 1320 } 1321 1322 int 1323 com_to_tiocm(struct com_softc *sc) 1324 { 1325 u_char combits; 1326 int ttybits = 0; 1327 1328 combits = sc->sc_mcr; 1329 if (ISSET(combits, MCR_DTR)) 1330 SET(ttybits, TIOCM_DTR); 1331 if (ISSET(combits, MCR_RTS)) 1332 SET(ttybits, TIOCM_RTS); 1333 1334 combits = sc->sc_msr; 1335 if (sc->sc_type == COM_TYPE_INGENIC) { 1336 SET(ttybits, TIOCM_CD); 1337 } else { 1338 if (ISSET(combits, MSR_DCD)) 1339 SET(ttybits, TIOCM_CD); 1340 } 1341 if (ISSET(combits, MSR_CTS)) 1342 SET(ttybits, TIOCM_CTS); 1343 if (ISSET(combits, MSR_DSR)) 1344 SET(ttybits, TIOCM_DSR); 1345 if (ISSET(combits, MSR_RI | MSR_TERI)) 1346 SET(ttybits, TIOCM_RI); 1347 1348 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1349 SET(ttybits, TIOCM_LE); 1350 1351 return (ttybits); 1352 } 1353 1354 static u_char 1355 cflag2lcr(tcflag_t cflag) 1356 { 1357 u_char lcr = 0; 1358 1359 switch (ISSET(cflag, CSIZE)) { 1360 case CS5: 1361 SET(lcr, LCR_5BITS); 1362 break; 1363 case CS6: 1364 SET(lcr, LCR_6BITS); 1365 break; 1366 case CS7: 1367 SET(lcr, LCR_7BITS); 1368 break; 1369 case CS8: 1370 SET(lcr, LCR_8BITS); 1371 break; 1372 } 1373 if (ISSET(cflag, PARENB)) { 1374 SET(lcr, LCR_PENAB); 1375 if (!ISSET(cflag, PARODD)) 1376 SET(lcr, LCR_PEVEN); 1377 } 1378 if (ISSET(cflag, CSTOPB)) 1379 SET(lcr, LCR_STOPB); 1380 1381 return (lcr); 1382 } 1383 1384 int 1385 comparam(struct tty *tp, struct termios *t) 1386 { 1387 struct com_softc *sc = 1388 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1389 int ospeed; 1390 u_char lcr; 1391 1392 if (COM_ISALIVE(sc) == 0) 1393 return (EIO); 1394 1395 if (sc->sc_type == COM_TYPE_HAYESP) { 1396 int prescaler, speed; 1397 1398 /* 1399 * Calculate UART clock prescaler. It should be in 1400 * range of 0 .. 3. 1401 */ 1402 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1403 prescaler++, speed /= 2) 1404 if ((ospeed = comspeed(speed, sc->sc_frequency, 1405 sc->sc_type)) > 0) 1406 break; 1407 1408 if (prescaler == 4) 1409 return (EINVAL); 1410 sc->sc_prescaler = prescaler; 1411 } else 1412 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1413 1414 /* Check requested parameters. */ 1415 if (ospeed < 0) 1416 return (EINVAL); 1417 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1418 return (EINVAL); 1419 1420 /* 1421 * For the console, always force CLOCAL and !HUPCL, so that the port 1422 * is always active. 1423 */ 1424 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1425 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1426 SET(t->c_cflag, CLOCAL); 1427 CLR(t->c_cflag, HUPCL); 1428 } 1429 1430 /* 1431 * If there were no changes, don't do anything. This avoids dropping 1432 * input and improves performance when all we did was frob things like 1433 * VMIN and VTIME. 1434 */ 1435 if (tp->t_ospeed == t->c_ospeed && 1436 tp->t_cflag == t->c_cflag) 1437 return (0); 1438 1439 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1440 1441 mutex_spin_enter(&sc->sc_lock); 1442 1443 sc->sc_lcr = lcr; 1444 1445 /* 1446 * If we're not in a mode that assumes a connection is present, then 1447 * ignore carrier changes. 1448 */ 1449 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1450 sc->sc_msr_dcd = 0; 1451 else 1452 sc->sc_msr_dcd = MSR_DCD; 1453 /* 1454 * Set the flow control pins depending on the current flow control 1455 * mode. 1456 */ 1457 if (ISSET(t->c_cflag, CRTSCTS)) { 1458 sc->sc_mcr_dtr = MCR_DTR; 1459 sc->sc_mcr_rts = MCR_RTS; 1460 sc->sc_msr_cts = MSR_CTS; 1461 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1462 SET(sc->sc_mcr, MCR_AFE); 1463 } else { 1464 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1465 } 1466 } else if (ISSET(t->c_cflag, MDMBUF)) { 1467 /* 1468 * For DTR/DCD flow control, make sure we don't toggle DTR for 1469 * carrier detection. 1470 */ 1471 sc->sc_mcr_dtr = 0; 1472 sc->sc_mcr_rts = MCR_DTR; 1473 sc->sc_msr_cts = MSR_DCD; 1474 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1475 CLR(sc->sc_mcr, MCR_AFE); 1476 } else { 1477 sc->sc_efr = 0; 1478 } 1479 } else { 1480 /* 1481 * If no flow control, then always set RTS. This will make 1482 * the other side happy if it mistakenly thinks we're doing 1483 * RTS/CTS flow control. 1484 */ 1485 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1486 sc->sc_mcr_rts = 0; 1487 sc->sc_msr_cts = 0; 1488 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1489 CLR(sc->sc_mcr, MCR_AFE); 1490 } else { 1491 sc->sc_efr = 0; 1492 } 1493 if (ISSET(sc->sc_mcr, MCR_DTR)) 1494 SET(sc->sc_mcr, MCR_RTS); 1495 else 1496 CLR(sc->sc_mcr, MCR_RTS); 1497 } 1498 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1499 1500 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1501 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1502 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1503 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1504 1505 sc->sc_dlbl = ospeed; 1506 sc->sc_dlbh = ospeed >> 8; 1507 1508 /* 1509 * Set the FIFO threshold based on the receive speed. 1510 * 1511 * * If it's a low speed, it's probably a mouse or some other 1512 * interactive device, so set the threshold low. 1513 * * If it's a high speed, trim the trigger level down to prevent 1514 * overflows. 1515 * * Otherwise set it a bit higher. 1516 */ 1517 if (sc->sc_type == COM_TYPE_HAYESP) { 1518 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1519 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1520 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1521 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1522 if (t->c_ospeed <= 1200) 1523 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1524 else if (t->c_ospeed <= 38400) 1525 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1526 else 1527 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1528 } else { 1529 sc->sc_fifo = 0; 1530 } 1531 1532 if (sc->sc_type == COM_TYPE_INGENIC) 1533 sc->sc_fifo |= FIFO_UART_ON; 1534 1535 /* And copy to tty. */ 1536 tp->t_ispeed = t->c_ospeed; 1537 tp->t_ospeed = t->c_ospeed; 1538 tp->t_cflag = t->c_cflag; 1539 1540 if (!sc->sc_heldchange) { 1541 if (sc->sc_tx_busy) { 1542 sc->sc_heldtbc = sc->sc_tbc; 1543 sc->sc_tbc = 0; 1544 sc->sc_heldchange = 1; 1545 } else 1546 com_loadchannelregs(sc); 1547 } 1548 1549 if (!ISSET(t->c_cflag, CHWFLOW)) { 1550 /* Disable the high water mark. */ 1551 sc->sc_r_hiwat = 0; 1552 sc->sc_r_lowat = 0; 1553 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1554 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1555 com_schedrx(sc); 1556 } 1557 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1558 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1559 com_hwiflow(sc); 1560 } 1561 } else { 1562 sc->sc_r_hiwat = com_rbuf_hiwat; 1563 sc->sc_r_lowat = com_rbuf_lowat; 1564 } 1565 1566 mutex_spin_exit(&sc->sc_lock); 1567 1568 /* 1569 * Update the tty layer's idea of the carrier bit, in case we changed 1570 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1571 * explicit request. 1572 */ 1573 if (sc->sc_type == COM_TYPE_INGENIC) { 1574 /* no DCD here */ 1575 (void) (*tp->t_linesw->l_modem)(tp, 1); 1576 } else 1577 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1578 1579 #ifdef COM_DEBUG 1580 if (com_debug) 1581 comstatus(sc, "comparam "); 1582 #endif 1583 1584 if (!ISSET(t->c_cflag, CHWFLOW)) { 1585 if (sc->sc_tx_stopped) { 1586 sc->sc_tx_stopped = 0; 1587 comstart(tp); 1588 } 1589 } 1590 1591 return (0); 1592 } 1593 1594 void 1595 com_iflush(struct com_softc *sc) 1596 { 1597 struct com_regs *regsp = &sc->sc_regs; 1598 uint8_t fifo; 1599 #ifdef DIAGNOSTIC 1600 int reg; 1601 #endif 1602 int timo; 1603 1604 #ifdef DIAGNOSTIC 1605 reg = 0xffff; 1606 #endif 1607 timo = 50000; 1608 /* flush any pending I/O */ 1609 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1610 && --timo) 1611 #ifdef DIAGNOSTIC 1612 reg = 1613 #else 1614 (void) 1615 #endif 1616 CSR_READ_1(regsp, COM_REG_RXDATA); 1617 #ifdef DIAGNOSTIC 1618 if (!timo) 1619 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1620 #endif 1621 1622 switch (sc->sc_type) { 1623 case COM_TYPE_16750: 1624 case COM_TYPE_DW_APB: 1625 /* 1626 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1627 * This should prevent triggering busy interrupt while 1628 * manipulating divisors. 1629 */ 1630 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1631 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1632 CSR_WRITE_1(regsp, COM_REG_FIFO, 1633 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1634 delay(100); 1635 break; 1636 } 1637 } 1638 1639 void 1640 com_loadchannelregs(struct com_softc *sc) 1641 { 1642 struct com_regs *regsp = &sc->sc_regs; 1643 1644 /* XXXXX necessary? */ 1645 com_iflush(sc); 1646 1647 if (sc->sc_type == COM_TYPE_PXA2x0) 1648 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1649 else 1650 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1651 1652 if (sc->sc_type == COM_TYPE_OMAP) { 1653 /* disable before changing settings */ 1654 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1655 } 1656 1657 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1658 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1659 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1660 /* no EFR on alchemy */ 1661 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1662 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1663 } 1664 if (sc->sc_type == COM_TYPE_AU1x00) { 1665 /* alchemy has single separate 16-bit clock divisor register */ 1666 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1667 (sc->sc_dlbh << 8)); 1668 } else { 1669 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1670 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1671 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1672 } 1673 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1674 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1675 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1676 if (sc->sc_type == COM_TYPE_HAYESP) { 1677 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1678 HAYESP_SETPRESCALER); 1679 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1680 sc->sc_prescaler); 1681 } 1682 if (sc->sc_type == COM_TYPE_OMAP) { 1683 /* setup the fifos. the FCR value is not used as long 1684 as SCR[6] and SCR[7] are 0, which they are at reset 1685 and we never touch the SCR register */ 1686 uint8_t rx_fifo_trig = 40; 1687 uint8_t tx_fifo_trig = 60; 1688 uint8_t rx_start = 8; 1689 uint8_t rx_halt = 60; 1690 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1691 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1692 1693 /* enable access to TCR & TLR */ 1694 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1695 1696 /* write tcr and tlr values */ 1697 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1698 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1699 1700 /* disable access to TCR & TLR */ 1701 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1702 1703 /* enable again, but mode is based on speed */ 1704 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1705 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1706 } else { 1707 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1708 } 1709 } 1710 1711 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1712 } 1713 1714 int 1715 comhwiflow(struct tty *tp, int block) 1716 { 1717 struct com_softc *sc = 1718 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1719 1720 if (COM_ISALIVE(sc) == 0) 1721 return (0); 1722 1723 if (sc->sc_mcr_rts == 0) 1724 return (0); 1725 1726 mutex_spin_enter(&sc->sc_lock); 1727 1728 if (block) { 1729 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1730 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1731 com_hwiflow(sc); 1732 } 1733 } else { 1734 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1735 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1736 com_schedrx(sc); 1737 } 1738 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1739 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1740 com_hwiflow(sc); 1741 } 1742 } 1743 1744 mutex_spin_exit(&sc->sc_lock); 1745 return (1); 1746 } 1747 1748 /* 1749 * (un)block input via hw flowcontrol 1750 */ 1751 void 1752 com_hwiflow(struct com_softc *sc) 1753 { 1754 struct com_regs *regsp= &sc->sc_regs; 1755 1756 if (sc->sc_mcr_rts == 0) 1757 return; 1758 1759 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1760 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1761 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1762 } else { 1763 SET(sc->sc_mcr, sc->sc_mcr_rts); 1764 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1765 } 1766 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1767 } 1768 1769 1770 void 1771 comstart(struct tty *tp) 1772 { 1773 struct com_softc *sc = 1774 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1775 struct com_regs *regsp = &sc->sc_regs; 1776 int s; 1777 1778 if (COM_ISALIVE(sc) == 0) 1779 return; 1780 1781 s = spltty(); 1782 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1783 goto out; 1784 if (sc->sc_tx_stopped) 1785 goto out; 1786 if (!ttypull(tp)) 1787 goto out; 1788 1789 /* Grab the first contiguous region of buffer space. */ 1790 { 1791 u_char *tba; 1792 int tbc; 1793 1794 tba = tp->t_outq.c_cf; 1795 tbc = ndqb(&tp->t_outq, 0); 1796 1797 mutex_spin_enter(&sc->sc_lock); 1798 1799 sc->sc_tba = tba; 1800 sc->sc_tbc = tbc; 1801 } 1802 1803 SET(tp->t_state, TS_BUSY); 1804 sc->sc_tx_busy = 1; 1805 1806 /* Enable transmit completion interrupts if necessary. */ 1807 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1808 SET(sc->sc_ier, IER_ETXRDY); 1809 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1810 } 1811 1812 /* Output the first chunk of the contiguous buffer. */ 1813 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1814 u_int n; 1815 1816 n = sc->sc_tbc; 1817 if (n > sc->sc_fifolen) 1818 n = sc->sc_fifolen; 1819 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1820 sc->sc_tbc -= n; 1821 sc->sc_tba += n; 1822 } 1823 1824 mutex_spin_exit(&sc->sc_lock); 1825 out: 1826 splx(s); 1827 return; 1828 } 1829 1830 /* 1831 * Stop output on a line. 1832 */ 1833 void 1834 comstop(struct tty *tp, int flag) 1835 { 1836 struct com_softc *sc = 1837 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1838 1839 mutex_spin_enter(&sc->sc_lock); 1840 if (ISSET(tp->t_state, TS_BUSY)) { 1841 /* Stop transmitting at the next chunk. */ 1842 sc->sc_tbc = 0; 1843 sc->sc_heldtbc = 0; 1844 if (!ISSET(tp->t_state, TS_TTSTOP)) 1845 SET(tp->t_state, TS_FLUSH); 1846 } 1847 mutex_spin_exit(&sc->sc_lock); 1848 } 1849 1850 void 1851 comdiag(void *arg) 1852 { 1853 struct com_softc *sc = arg; 1854 int overflows, floods; 1855 1856 mutex_spin_enter(&sc->sc_lock); 1857 overflows = sc->sc_overflows; 1858 sc->sc_overflows = 0; 1859 floods = sc->sc_floods; 1860 sc->sc_floods = 0; 1861 sc->sc_errors = 0; 1862 mutex_spin_exit(&sc->sc_lock); 1863 1864 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1865 device_xname(sc->sc_dev), 1866 overflows, overflows == 1 ? "" : "s", 1867 floods, floods == 1 ? "" : "s"); 1868 } 1869 1870 integrate void 1871 com_rxsoft(struct com_softc *sc, struct tty *tp) 1872 { 1873 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1874 u_char *get, *end; 1875 u_int cc, scc; 1876 u_char lsr; 1877 int code; 1878 1879 end = sc->sc_ebuf; 1880 get = sc->sc_rbget; 1881 scc = cc = com_rbuf_size - sc->sc_rbavail; 1882 1883 if (cc == com_rbuf_size) { 1884 sc->sc_floods++; 1885 if (sc->sc_errors++ == 0) 1886 callout_reset(&sc->sc_diag_callout, 60 * hz, 1887 comdiag, sc); 1888 } 1889 1890 /* If not yet open, drop the entire buffer content here */ 1891 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1892 get += cc << 1; 1893 if (get >= end) 1894 get -= com_rbuf_size << 1; 1895 cc = 0; 1896 } 1897 while (cc) { 1898 code = get[0]; 1899 lsr = get[1]; 1900 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1901 if (ISSET(lsr, LSR_OE)) { 1902 sc->sc_overflows++; 1903 if (sc->sc_errors++ == 0) 1904 callout_reset(&sc->sc_diag_callout, 1905 60 * hz, comdiag, sc); 1906 } 1907 if (ISSET(lsr, LSR_BI | LSR_FE)) 1908 SET(code, TTY_FE); 1909 if (ISSET(lsr, LSR_PE)) 1910 SET(code, TTY_PE); 1911 } 1912 if ((*rint)(code, tp) == -1) { 1913 /* 1914 * The line discipline's buffer is out of space. 1915 */ 1916 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1917 /* 1918 * We're either not using flow control, or the 1919 * line discipline didn't tell us to block for 1920 * some reason. Either way, we have no way to 1921 * know when there's more space available, so 1922 * just drop the rest of the data. 1923 */ 1924 get += cc << 1; 1925 if (get >= end) 1926 get -= com_rbuf_size << 1; 1927 cc = 0; 1928 } else { 1929 /* 1930 * Don't schedule any more receive processing 1931 * until the line discipline tells us there's 1932 * space available (through comhwiflow()). 1933 * Leave the rest of the data in the input 1934 * buffer. 1935 */ 1936 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1937 } 1938 break; 1939 } 1940 get += 2; 1941 if (get >= end) 1942 get = sc->sc_rbuf; 1943 cc--; 1944 } 1945 1946 if (cc != scc) { 1947 sc->sc_rbget = get; 1948 mutex_spin_enter(&sc->sc_lock); 1949 1950 cc = sc->sc_rbavail += scc - cc; 1951 /* Buffers should be ok again, release possible block. */ 1952 if (cc >= sc->sc_r_lowat) { 1953 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1954 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1955 SET(sc->sc_ier, IER_ERXRDY); 1956 if (sc->sc_type == COM_TYPE_PXA2x0) 1957 SET(sc->sc_ier, IER_ERXTOUT); 1958 if (sc->sc_type == COM_TYPE_INGENIC || 1959 sc->sc_type == COM_TYPE_TEGRA) 1960 SET(sc->sc_ier, IER_ERXTOUT); 1961 1962 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 1963 sc->sc_ier); 1964 } 1965 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1966 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1967 com_hwiflow(sc); 1968 } 1969 } 1970 mutex_spin_exit(&sc->sc_lock); 1971 } 1972 } 1973 1974 integrate void 1975 com_txsoft(struct com_softc *sc, struct tty *tp) 1976 { 1977 1978 CLR(tp->t_state, TS_BUSY); 1979 if (ISSET(tp->t_state, TS_FLUSH)) 1980 CLR(tp->t_state, TS_FLUSH); 1981 else 1982 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1983 (*tp->t_linesw->l_start)(tp); 1984 } 1985 1986 integrate void 1987 com_stsoft(struct com_softc *sc, struct tty *tp) 1988 { 1989 u_char msr, delta; 1990 1991 mutex_spin_enter(&sc->sc_lock); 1992 msr = sc->sc_msr; 1993 delta = sc->sc_msr_delta; 1994 sc->sc_msr_delta = 0; 1995 mutex_spin_exit(&sc->sc_lock); 1996 1997 if (ISSET(delta, sc->sc_msr_dcd)) { 1998 /* 1999 * Inform the tty layer that carrier detect changed. 2000 */ 2001 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2002 } 2003 2004 if (ISSET(delta, sc->sc_msr_cts)) { 2005 /* Block or unblock output according to flow control. */ 2006 if (ISSET(msr, sc->sc_msr_cts)) { 2007 sc->sc_tx_stopped = 0; 2008 (*tp->t_linesw->l_start)(tp); 2009 } else { 2010 sc->sc_tx_stopped = 1; 2011 } 2012 } 2013 2014 #ifdef COM_DEBUG 2015 if (com_debug) 2016 comstatus(sc, "com_stsoft"); 2017 #endif 2018 } 2019 2020 void 2021 comsoft(void *arg) 2022 { 2023 struct com_softc *sc = arg; 2024 struct tty *tp; 2025 2026 if (COM_ISALIVE(sc) == 0) 2027 return; 2028 2029 tp = sc->sc_tty; 2030 2031 if (sc->sc_rx_ready) { 2032 sc->sc_rx_ready = 0; 2033 com_rxsoft(sc, tp); 2034 } 2035 2036 if (sc->sc_st_check) { 2037 sc->sc_st_check = 0; 2038 com_stsoft(sc, tp); 2039 } 2040 2041 if (sc->sc_tx_done) { 2042 sc->sc_tx_done = 0; 2043 com_txsoft(sc, tp); 2044 } 2045 } 2046 2047 int 2048 comintr(void *arg) 2049 { 2050 struct com_softc *sc = arg; 2051 struct com_regs *regsp = &sc->sc_regs; 2052 2053 u_char *put, *end; 2054 u_int cc; 2055 u_char lsr, iir; 2056 2057 if (COM_ISALIVE(sc) == 0) 2058 return (0); 2059 2060 KASSERT(regsp != NULL); 2061 2062 mutex_spin_enter(&sc->sc_lock); 2063 iir = CSR_READ_1(regsp, COM_REG_IIR); 2064 2065 /* Handle ns16750-specific busy interrupt. */ 2066 if (sc->sc_type == COM_TYPE_16750 && 2067 (iir & IIR_BUSY) == IIR_BUSY) { 2068 for (int timeout = 10000; 2069 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2070 if (timeout <= 0) { 2071 aprint_error_dev(sc->sc_dev, 2072 "timeout while waiting for BUSY interrupt " 2073 "acknowledge\n"); 2074 mutex_spin_exit(&sc->sc_lock); 2075 return (0); 2076 } 2077 2078 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2079 iir = CSR_READ_1(regsp, COM_REG_IIR); 2080 } 2081 2082 /* DesignWare APB UART BUSY interrupt */ 2083 if (sc->sc_type == COM_TYPE_DW_APB && 2084 (iir & IIR_BUSY) == IIR_BUSY) { 2085 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2086 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2087 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2088 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2089 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2090 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2091 CSR_WRITE_1(regsp, COM_REG_HALT, 2092 HALT_CHCFG_EN | HALT_CHCFG_UD); 2093 for (int timeout = 10000000; 2094 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2095 timeout--) { 2096 if (timeout <= 0) { 2097 aprint_error_dev(sc->sc_dev, 2098 "timeout while waiting for HALT " 2099 "update acknowledge 0x%x 0x%x\n", 2100 CSR_READ_1(regsp, COM_REG_HALT), 2101 CSR_READ_1(regsp, COM_REG_USR)); 2102 break; 2103 } 2104 } 2105 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2106 (void)CSR_READ_1(regsp, COM_REG_USR); 2107 } else { 2108 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2109 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2110 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2111 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2112 } 2113 } 2114 2115 if (ISSET(iir, IIR_NOPEND)) { 2116 mutex_spin_exit(&sc->sc_lock); 2117 return (0); 2118 } 2119 2120 end = sc->sc_ebuf; 2121 put = sc->sc_rbput; 2122 cc = sc->sc_rbavail; 2123 2124 again: do { 2125 u_char msr, delta; 2126 2127 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2128 if (ISSET(lsr, LSR_BI)) { 2129 int cn_trapped = 0; /* see above: cn_trap() */ 2130 2131 cn_check_magic(sc->sc_tty->t_dev, 2132 CNC_BREAK, com_cnm_state); 2133 if (cn_trapped) 2134 continue; 2135 #if defined(KGDB) && !defined(DDB) 2136 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2137 kgdb_connect(1); 2138 continue; 2139 } 2140 #endif 2141 } 2142 2143 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2144 lsr |= LSR_RXRDY; 2145 2146 if (ISSET(lsr, LSR_RCV_MASK) && 2147 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2148 while (cc > 0) { 2149 int cn_trapped = 0; 2150 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2151 put[1] = lsr; 2152 cn_check_magic(sc->sc_tty->t_dev, 2153 put[0], com_cnm_state); 2154 if (cn_trapped) 2155 goto next; 2156 put += 2; 2157 if (put >= end) 2158 put = sc->sc_rbuf; 2159 cc--; 2160 next: 2161 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2162 if (!ISSET(lsr, LSR_RCV_MASK)) 2163 break; 2164 } 2165 2166 /* 2167 * Current string of incoming characters ended because 2168 * no more data was available or we ran out of space. 2169 * Schedule a receive event if any data was received. 2170 * If we're out of space, turn off receive interrupts. 2171 */ 2172 sc->sc_rbput = put; 2173 sc->sc_rbavail = cc; 2174 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2175 sc->sc_rx_ready = 1; 2176 2177 /* 2178 * See if we are in danger of overflowing a buffer. If 2179 * so, use hardware flow control to ease the pressure. 2180 */ 2181 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2182 cc < sc->sc_r_hiwat) { 2183 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2184 com_hwiflow(sc); 2185 } 2186 2187 /* 2188 * If we're out of space, disable receive interrupts 2189 * until the queue has drained a bit. 2190 */ 2191 if (!cc) { 2192 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2193 switch (sc->sc_type) { 2194 case COM_TYPE_PXA2x0: 2195 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2196 break; 2197 case COM_TYPE_INGENIC: 2198 case COM_TYPE_TEGRA: 2199 CLR(sc->sc_ier, 2200 IER_ERXRDY | IER_ERXTOUT); 2201 break; 2202 default: 2203 CLR(sc->sc_ier, IER_ERXRDY); 2204 break; 2205 } 2206 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2207 } 2208 } else { 2209 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2210 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2211 continue; 2212 } 2213 } 2214 2215 msr = CSR_READ_1(regsp, COM_REG_MSR); 2216 delta = msr ^ sc->sc_msr; 2217 sc->sc_msr = msr; 2218 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2219 (delta & MSR_DCD)) { 2220 mutex_spin_enter(&timecounter_lock); 2221 pps_capture(&sc->sc_pps_state); 2222 pps_event(&sc->sc_pps_state, 2223 (msr & MSR_DCD) ? 2224 PPS_CAPTUREASSERT : 2225 PPS_CAPTURECLEAR); 2226 mutex_spin_exit(&timecounter_lock); 2227 } 2228 2229 /* 2230 * Process normal status changes 2231 */ 2232 if (ISSET(delta, sc->sc_msr_mask)) { 2233 SET(sc->sc_msr_delta, delta); 2234 2235 /* 2236 * Stop output immediately if we lose the output 2237 * flow control signal or carrier detect. 2238 */ 2239 if (ISSET(~msr, sc->sc_msr_mask)) { 2240 sc->sc_tbc = 0; 2241 sc->sc_heldtbc = 0; 2242 #ifdef COM_DEBUG 2243 if (com_debug) 2244 comstatus(sc, "comintr "); 2245 #endif 2246 } 2247 2248 sc->sc_st_check = 1; 2249 } 2250 } while (!ISSET((iir = 2251 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2252 /* 2253 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2254 * by IIR read, so we can't do this way: `process all interrupts, 2255 * then do TX if possible'. 2256 */ 2257 (iir & IIR_IMASK) != IIR_TXRDY); 2258 2259 /* 2260 * Read LSR again, since there may be an interrupt between 2261 * the last LSR read and IIR read above. 2262 */ 2263 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2264 2265 /* 2266 * See if data can be transmitted as well. 2267 * Schedule tx done event if no data left 2268 * and tty was marked busy. 2269 */ 2270 if (ISSET(lsr, LSR_TXRDY)) { 2271 /* 2272 * If we've delayed a parameter change, do it now, and restart 2273 * output. 2274 */ 2275 if (sc->sc_heldchange) { 2276 com_loadchannelregs(sc); 2277 sc->sc_heldchange = 0; 2278 sc->sc_tbc = sc->sc_heldtbc; 2279 sc->sc_heldtbc = 0; 2280 } 2281 2282 /* Output the next chunk of the contiguous buffer, if any. */ 2283 if (sc->sc_tbc > 0) { 2284 u_int n; 2285 2286 n = sc->sc_tbc; 2287 if (n > sc->sc_fifolen) 2288 n = sc->sc_fifolen; 2289 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2290 sc->sc_tbc -= n; 2291 sc->sc_tba += n; 2292 } else { 2293 /* Disable transmit completion interrupts if necessary. */ 2294 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2295 CLR(sc->sc_ier, IER_ETXRDY); 2296 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2297 } 2298 if (sc->sc_tx_busy) { 2299 sc->sc_tx_busy = 0; 2300 sc->sc_tx_done = 1; 2301 } 2302 } 2303 } 2304 2305 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2306 goto again; 2307 2308 mutex_spin_exit(&sc->sc_lock); 2309 2310 /* Wake up the poller. */ 2311 softint_schedule(sc->sc_si); 2312 2313 #ifdef RND_COM 2314 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2315 #endif 2316 2317 return (1); 2318 } 2319 2320 /* 2321 * The following functions are polled getc and putc routines, shared 2322 * by the console and kgdb glue. 2323 * 2324 * The read-ahead code is so that you can detect pending in-band 2325 * cn_magic in polled mode while doing output rather than having to 2326 * wait until the kernel decides it needs input. 2327 */ 2328 2329 #define MAX_READAHEAD 20 2330 static int com_readahead[MAX_READAHEAD]; 2331 static int com_readaheadcount = 0; 2332 2333 int 2334 com_common_getc(dev_t dev, struct com_regs *regsp) 2335 { 2336 int s = splserial(); 2337 u_char stat, c; 2338 2339 /* got a character from reading things earlier */ 2340 if (com_readaheadcount > 0) { 2341 int i; 2342 2343 c = com_readahead[0]; 2344 for (i = 1; i < com_readaheadcount; i++) { 2345 com_readahead[i-1] = com_readahead[i]; 2346 } 2347 com_readaheadcount--; 2348 splx(s); 2349 return (c); 2350 } 2351 2352 /* don't block until a character becomes available */ 2353 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2354 splx(s); 2355 return -1; 2356 } 2357 2358 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2359 stat = CSR_READ_1(regsp, COM_REG_IIR); 2360 { 2361 int cn_trapped = 0; /* required by cn_trap, see above */ 2362 #ifdef DDB 2363 extern int db_active; 2364 if (!db_active) 2365 #endif 2366 cn_check_magic(dev, c, com_cnm_state); 2367 } 2368 splx(s); 2369 return (c); 2370 } 2371 2372 static void 2373 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2374 { 2375 int s = splserial(); 2376 int cin, stat, timo; 2377 2378 if (com_readaheadcount < MAX_READAHEAD 2379 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2380 int cn_trapped = 0; 2381 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2382 stat = CSR_READ_1(regsp, COM_REG_IIR); 2383 cn_check_magic(dev, cin, com_cnm_state); 2384 com_readahead[com_readaheadcount++] = cin; 2385 } 2386 2387 /* wait for any pending transmission to finish */ 2388 timo = 150000; 2389 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2390 continue; 2391 2392 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2393 COM_BARRIER(regsp, BR | BW); 2394 2395 splx(s); 2396 } 2397 2398 /* 2399 * Initialize UART for use as console or KGDB line. 2400 */ 2401 int 2402 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2403 tcflag_t cflag) 2404 { 2405 2406 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2407 ®sp->cr_ioh)) 2408 return (ENOMEM); /* ??? */ 2409 2410 if (type == COM_TYPE_OMAP) { 2411 /* disable before changing settings */ 2412 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2413 } 2414 2415 rate = comspeed(rate, frequency, type); 2416 if (__predict_true(rate != -1)) { 2417 if (type == COM_TYPE_AU1x00) { 2418 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2419 } else { 2420 /* no EFR on alchemy */ 2421 if ((type != COM_TYPE_16550_NOERS) && 2422 (type != COM_TYPE_INGENIC)) { 2423 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2424 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2425 } 2426 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2427 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2428 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2429 } 2430 } 2431 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2432 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2433 2434 if (type == COM_TYPE_INGENIC) { 2435 CSR_WRITE_1(regsp, COM_REG_FIFO, 2436 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2437 FIFO_TRIGGER_1 | FIFO_UART_ON); 2438 } else { 2439 CSR_WRITE_1(regsp, COM_REG_FIFO, 2440 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2441 FIFO_TRIGGER_1); 2442 } 2443 2444 if (type == COM_TYPE_OMAP) { 2445 /* setup the fifos. the FCR value is not used as long 2446 as SCR[6] and SCR[7] are 0, which they are at reset 2447 and we never touch the SCR register */ 2448 uint8_t rx_fifo_trig = 40; 2449 uint8_t tx_fifo_trig = 60; 2450 uint8_t rx_start = 8; 2451 uint8_t rx_halt = 60; 2452 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2453 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2454 2455 /* enable access to TCR & TLR */ 2456 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2457 2458 /* write tcr and tlr values */ 2459 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2460 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2461 2462 /* disable access to TCR & TLR */ 2463 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2464 2465 /* enable again, but mode is based on speed */ 2466 if (rate > 230400) { 2467 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2468 } else { 2469 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2470 } 2471 } 2472 2473 if (type == COM_TYPE_PXA2x0) 2474 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2475 else 2476 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2477 2478 return (0); 2479 } 2480 2481 int 2482 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2483 tcflag_t cflag) 2484 { 2485 int res; 2486 2487 comcons_info.regs = *regsp; 2488 2489 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2490 if (res) 2491 return (res); 2492 2493 cn_tab = &comcons; 2494 cn_init_magic(&com_cnm_state); 2495 cn_set_magic("\047\001"); /* default magic is BREAK */ 2496 2497 comcons_info.frequency = frequency; 2498 comcons_info.type = type; 2499 comcons_info.rate = rate; 2500 comcons_info.cflag = cflag; 2501 2502 return (0); 2503 } 2504 2505 int 2506 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2507 int type, tcflag_t cflag) 2508 { 2509 struct com_regs regs; 2510 2511 memset(®s, 0, sizeof regs); 2512 regs.cr_iot = iot; 2513 regs.cr_iobase = iobase; 2514 regs.cr_nports = COM_NPORTS; 2515 #ifdef COM_REGMAP 2516 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2517 #endif 2518 2519 return comcnattach1(®s, rate, frequency, type, cflag); 2520 } 2521 2522 static int 2523 comcnreattach(void) 2524 { 2525 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2526 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2527 } 2528 2529 int 2530 comcngetc(dev_t dev) 2531 { 2532 2533 return (com_common_getc(dev, &comcons_info.regs)); 2534 } 2535 2536 /* 2537 * Console kernel output character routine. 2538 */ 2539 void 2540 comcnputc(dev_t dev, int c) 2541 { 2542 2543 com_common_putc(dev, &comcons_info.regs, c); 2544 } 2545 2546 void 2547 comcnpollc(dev_t dev, int on) 2548 { 2549 2550 com_readaheadcount = 0; 2551 } 2552 2553 #ifdef KGDB 2554 int 2555 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2556 tcflag_t cflag) 2557 { 2558 int res; 2559 2560 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2561 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2562 #if !defined(DDB) 2563 return (EBUSY); /* cannot share with console */ 2564 #else 2565 comkgdbregs = *regsp; 2566 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2567 #endif 2568 } else { 2569 comkgdbregs = *regsp; 2570 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2571 if (res) 2572 return (res); 2573 2574 /* 2575 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2576 * expects this to be initialized 2577 */ 2578 cn_init_magic(&com_cnm_state); 2579 cn_set_magic("\047\001"); 2580 } 2581 2582 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2583 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2584 2585 return (0); 2586 } 2587 2588 int 2589 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2590 int frequency, int type, tcflag_t cflag) 2591 { 2592 struct com_regs regs; 2593 2594 regs.cr_iot = iot; 2595 regs.cr_nports = COM_NPORTS; 2596 regs.cr_iobase = iobase; 2597 #ifdef COM_REGMAP 2598 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map)); 2599 #endif 2600 2601 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2602 } 2603 2604 /* ARGSUSED */ 2605 int 2606 com_kgdb_getc(void *arg) 2607 { 2608 2609 return (com_common_getc(NODEV, &comkgdbregs)); 2610 } 2611 2612 /* ARGSUSED */ 2613 void 2614 com_kgdb_putc(void *arg, int c) 2615 { 2616 2617 com_common_putc(NODEV, &comkgdbregs, c); 2618 } 2619 #endif /* KGDB */ 2620 2621 /* helper function to identify the com ports used by 2622 console or KGDB (and not yet autoconf attached) */ 2623 int 2624 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2625 { 2626 bus_space_handle_t help; 2627 2628 if (!comconsattached && 2629 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2630 iobase == comcons_info.regs.cr_iobase) 2631 help = comcons_info.regs.cr_ioh; 2632 #ifdef KGDB 2633 else if (!com_kgdb_attached && 2634 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2635 iobase == comkgdbregs.cr_iobase) 2636 help = comkgdbregs.cr_ioh; 2637 #endif 2638 else 2639 return (0); 2640 2641 if (ioh) 2642 *ioh = help; 2643 return (1); 2644 } 2645 2646 /* 2647 * this routine exists to serve as a shutdown hook for systems that 2648 * have firmware which doesn't interact properly with a com device in 2649 * FIFO mode. 2650 */ 2651 bool 2652 com_cleanup(device_t self, int how) 2653 { 2654 struct com_softc *sc = device_private(self); 2655 2656 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2657 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2658 2659 return true; 2660 } 2661 2662 bool 2663 com_suspend(device_t self, const pmf_qual_t *qual) 2664 { 2665 struct com_softc *sc = device_private(self); 2666 2667 #if 0 2668 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2669 cn_tab = &comcons_suspend; 2670 #endif 2671 2672 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2673 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2674 2675 return true; 2676 } 2677 2678 bool 2679 com_resume(device_t self, const pmf_qual_t *qual) 2680 { 2681 struct com_softc *sc = device_private(self); 2682 2683 mutex_spin_enter(&sc->sc_lock); 2684 com_loadchannelregs(sc); 2685 mutex_spin_exit(&sc->sc_lock); 2686 2687 return true; 2688 } 2689
Indexes created Fri Sep 26 20:09:58 GMT 2025