com.c revision 1.354
1 /* $NetBSD: com.c,v 1.354 2018/12/11 06:34:00 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.354 2018/12/11 06:34:00 thorpej Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #define CSR_WRITE_1(r, o, v) \ 132 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 133 #define CSR_READ_1(r, o) \ 134 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 135 #define CSR_WRITE_2(r, o, v) \ 136 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 137 #define CSR_READ_2(r, o) \ 138 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 139 #define CSR_WRITE_MULTI(r, o, p, n) \ 140 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 141 142 143 static void com_enable_debugport(struct com_softc *); 144 145 void com_config(struct com_softc *); 146 void com_shutdown(struct com_softc *); 147 int comspeed(long, long, int); 148 static u_char cflag2lcr(tcflag_t); 149 int comparam(struct tty *, struct termios *); 150 void comstart(struct tty *); 151 int comhwiflow(struct tty *, int); 152 153 void com_loadchannelregs(struct com_softc *); 154 void com_hwiflow(struct com_softc *); 155 void com_break(struct com_softc *, int); 156 void com_modem(struct com_softc *, int); 157 void tiocm_to_com(struct com_softc *, u_long, int); 158 int com_to_tiocm(struct com_softc *); 159 void com_iflush(struct com_softc *); 160 161 int com_common_getc(dev_t, struct com_regs *); 162 static void com_common_putc(dev_t, struct com_regs *, int); 163 164 int cominit(struct com_regs *, int, int, int, tcflag_t); 165 166 static int comcnreattach(void); 167 168 int comcngetc(dev_t); 169 void comcnputc(dev_t, int); 170 void comcnpollc(dev_t, int); 171 172 #define integrate static inline 173 void comsoft(void *); 174 integrate void com_rxsoft(struct com_softc *, struct tty *); 175 integrate void com_txsoft(struct com_softc *, struct tty *); 176 integrate void com_stsoft(struct com_softc *, struct tty *); 177 integrate void com_schedrx(struct com_softc *); 178 void comdiag(void *); 179 180 dev_type_open(comopen); 181 dev_type_close(comclose); 182 dev_type_read(comread); 183 dev_type_write(comwrite); 184 dev_type_ioctl(comioctl); 185 dev_type_stop(comstop); 186 dev_type_tty(comtty); 187 dev_type_poll(compoll); 188 189 static struct comcons_info comcons_info; 190 191 /* 192 * Following are all routines needed for COM to act as console 193 */ 194 static struct consdev comcons = { 195 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 196 NODEV, CN_NORMAL 197 }; 198 199 200 const struct cdevsw com_cdevsw = { 201 .d_open = comopen, 202 .d_close = comclose, 203 .d_read = comread, 204 .d_write = comwrite, 205 .d_ioctl = comioctl, 206 .d_stop = comstop, 207 .d_tty = comtty, 208 .d_poll = compoll, 209 .d_mmap = nommap, 210 .d_kqfilter = ttykqfilter, 211 .d_discard = nodiscard, 212 .d_flag = D_TTY 213 }; 214 215 /* 216 * Make this an option variable one can patch. 217 * But be warned: this must be a power of 2! 218 */ 219 u_int com_rbuf_size = COM_RING_SIZE; 220 221 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 222 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 223 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 224 225 static int comconsattached; 226 static struct cnm_state com_cnm_state; 227 228 #ifdef KGDB 229 #include <sys/kgdb.h> 230 231 static struct com_regs comkgdbregs; 232 static int com_kgdb_attached; 233 234 int com_kgdb_getc(void *); 235 void com_kgdb_putc(void *, int); 236 #endif /* KGDB */ 237 238 /* initializer for typical 16550-ish hardware */ 239 #define COM_REG_STD { \ 240 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \ 241 com_efr, com_lcr, com_mcr, com_lsr, com_msr, 0, 0, 0, 0, 0, 0, 0, 0, \ 242 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, com_usr, com_tfl, com_rfl, \ 243 0, 0, 0, 0, 0, 0, 0, com_halt } 244 245 static const bus_size_t com_std_map[42] = COM_REG_STD; 246 247 #define COMDIALOUT_MASK TTDIALOUT_MASK 248 249 #define COMUNIT(x) TTUNIT(x) 250 #define COMDIALOUT(x) TTDIALOUT(x) 251 252 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 253 device_is_active((sc)->sc_dev)) 254 255 #define BR BUS_SPACE_BARRIER_READ 256 #define BW BUS_SPACE_BARRIER_WRITE 257 #define COM_BARRIER(r, f) \ 258 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 259 260 /* 261 * com_init_regs -- 262 * Driver front-ends use this to initialize our register map 263 * in the standard fashion. They may then tailor the map to 264 * their own particular requirements. 265 */ 266 void 267 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 268 bus_addr_t addr) 269 { 270 271 memset(regs, 0, sizeof(*regs)); 272 regs->cr_iot = st; 273 regs->cr_ioh = sh; 274 regs->cr_iobase = addr; 275 regs->cr_nports = COM_NPORTS; 276 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 277 } 278 279 /* 280 * com_init_regs_stride -- 281 * Convenience function for front-ends that have a stride between 282 * registers. 283 */ 284 void 285 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 286 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 287 { 288 289 com_init_regs(regs, st, sh, addr); 290 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 291 regs->cr_map[i] <<= regshift; 292 } 293 regs->cr_nports <<= regshift; 294 } 295 296 /*ARGSUSED*/ 297 int 298 comspeed(long speed, long frequency, int type) 299 { 300 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 301 302 int x, err; 303 int divisor = 16; 304 305 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 306 divisor = 13; 307 } 308 309 if (speed == 0) 310 return (0); 311 if (speed < 0) 312 return (-1); 313 x = divrnd(frequency / divisor, speed); 314 if (x <= 0) 315 return (-1); 316 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 317 if (err < 0) 318 err = -err; 319 if (err > COM_TOLERANCE) 320 return (-1); 321 return (x); 322 323 #undef divrnd 324 } 325 326 #ifdef COM_DEBUG 327 int com_debug = 0; 328 329 void comstatus(struct com_softc *, const char *); 330 void 331 comstatus(struct com_softc *sc, const char *str) 332 { 333 struct tty *tp = sc->sc_tty; 334 335 aprint_normal_dev(sc->sc_dev, 336 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 337 str, 338 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 339 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 340 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 341 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 342 sc->sc_tx_stopped ? '+' : '-'); 343 344 aprint_normal_dev(sc->sc_dev, 345 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 346 str, 347 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 348 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 349 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 350 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 351 sc->sc_rx_flags); 352 } 353 #endif 354 355 int 356 com_probe_subr(struct com_regs *regs) 357 { 358 359 /* force access to id reg */ 360 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 361 CSR_WRITE_1(regs, COM_REG_IIR, 0); 362 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 363 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 364 return (0); 365 366 return (1); 367 } 368 369 int 370 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 371 { 372 struct com_regs regs; 373 374 com_init_regs(®s, iot, ioh, 0/*XXX*/); 375 376 return com_probe_subr(®s); 377 } 378 379 /* 380 * No locking in this routine; it is only called during attach, 381 * or with the port already locked. 382 */ 383 static void 384 com_enable_debugport(struct com_softc *sc) 385 { 386 387 /* Turn on line break interrupt, set carrier. */ 388 sc->sc_ier = IER_ERLS; 389 if (sc->sc_type == COM_TYPE_PXA2x0) 390 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 391 if (sc->sc_type == COM_TYPE_INGENIC || 392 sc->sc_type == COM_TYPE_TEGRA) 393 sc->sc_ier |= IER_ERXTOUT; 394 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 395 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 396 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 397 } 398 399 static void 400 com_intr_poll(void *arg) 401 { 402 struct com_softc * const sc = arg; 403 404 comintr(sc); 405 406 callout_schedule(&sc->sc_poll_callout, 1); 407 } 408 409 void 410 com_attach_subr(struct com_softc *sc) 411 { 412 struct com_regs *regsp = &sc->sc_regs; 413 struct tty *tp; 414 u_int8_t lcr; 415 const char *fifo_msg = NULL; 416 prop_dictionary_t dict; 417 bool is_console = true; 418 bool force_console = false; 419 420 aprint_naive("\n"); 421 422 dict = device_properties(sc->sc_dev); 423 prop_dictionary_get_bool(dict, "is_console", &is_console); 424 prop_dictionary_get_bool(dict, "force_console", &force_console); 425 callout_init(&sc->sc_diag_callout, 0); 426 callout_init(&sc->sc_poll_callout, 0); 427 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 428 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 429 430 #if defined(COM_16650) 431 sc->sc_type = COM_TYPE_16650; 432 #elif defined(COM_16750) 433 sc->sc_type = COM_TYPE_16750; 434 #elif defined(COM_HAYESP) 435 sc->sc_type = COM_TYPE_HAYESP; 436 #elif defined(COM_PXA2X0) 437 sc->sc_type = COM_TYPE_PXA2x0; 438 #endif 439 440 /* Disable interrupts before configuring the device. */ 441 if (sc->sc_type == COM_TYPE_PXA2x0) 442 sc->sc_ier = IER_EUART; 443 else 444 sc->sc_ier = 0; 445 446 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 447 448 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 449 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 450 comconsattached = 1; 451 452 if (force_console) 453 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 454 455 if (cn_tab == NULL && comcnreattach() != 0) { 456 printf("can't re-init serial console @%lx\n", 457 (u_long)comcons_info.regs.cr_iobase); 458 } 459 460 switch (sc->sc_type) { 461 case COM_TYPE_16750: 462 case COM_TYPE_DW_APB: 463 /* Use in comintr(). */ 464 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 465 break; 466 } 467 468 /* Make sure the console is always "hardwired". */ 469 delay(10000); /* wait for output to finish */ 470 if (is_console) { 471 SET(sc->sc_hwflags, COM_HW_CONSOLE); 472 } 473 474 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 475 } 476 477 /* Probe for FIFO */ 478 switch (sc->sc_type) { 479 case COM_TYPE_HAYESP: 480 goto fifodone; 481 482 case COM_TYPE_AU1x00: 483 sc->sc_fifolen = 16; 484 fifo_msg = "Au1X00 UART, working fifo"; 485 SET(sc->sc_hwflags, COM_HW_FIFO); 486 goto fifodelay; 487 488 case COM_TYPE_16550_NOERS: 489 sc->sc_fifolen = 16; 490 fifo_msg = "ns16650, no ERS, working fifo"; 491 SET(sc->sc_hwflags, COM_HW_FIFO); 492 goto fifodelay; 493 494 case COM_TYPE_OMAP: 495 sc->sc_fifolen = 64; 496 fifo_msg = "OMAP UART, working fifo"; 497 SET(sc->sc_hwflags, COM_HW_FIFO); 498 goto fifodelay; 499 500 case COM_TYPE_INGENIC: 501 sc->sc_fifolen = 16; 502 fifo_msg = "Ingenic UART, working fifo"; 503 SET(sc->sc_hwflags, COM_HW_FIFO); 504 SET(sc->sc_hwflags, COM_HW_NOIEN); 505 goto fifodelay; 506 507 case COM_TYPE_TEGRA: 508 sc->sc_fifolen = 8; 509 fifo_msg = "Tegra UART, working fifo"; 510 SET(sc->sc_hwflags, COM_HW_FIFO); 511 CSR_WRITE_1(regsp, COM_REG_FIFO, 512 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 513 goto fifodelay; 514 515 case COM_TYPE_BCMAUXUART: 516 sc->sc_fifolen = 1; 517 fifo_msg = "BCM AUX UART, working fifo"; 518 SET(sc->sc_hwflags, COM_HW_FIFO); 519 CSR_WRITE_1(regsp, COM_REG_FIFO, 520 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 521 goto fifodelay; 522 } 523 524 sc->sc_fifolen = 1; 525 /* look for a NS 16550AF UART with FIFOs */ 526 if (sc->sc_type == COM_TYPE_INGENIC) { 527 CSR_WRITE_1(regsp, COM_REG_FIFO, 528 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 529 FIFO_TRIGGER_14 | FIFO_UART_ON); 530 } else 531 CSR_WRITE_1(regsp, COM_REG_FIFO, 532 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 533 delay(100); 534 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 535 == IIR_FIFO_MASK) 536 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 537 == FIFO_TRIGGER_14) { 538 SET(sc->sc_hwflags, COM_HW_FIFO); 539 540 fifo_msg = "ns16550a, working fifo"; 541 542 /* 543 * IIR changes into the EFR if LCR is set to LCR_EERS 544 * on 16650s. We also know IIR != 0 at this point. 545 * Write 0 into the EFR, and read it. If the result 546 * is 0, we have a 16650. 547 * 548 * Older 16650s were broken; the test to detect them 549 * is taken from the Linux driver. Apparently 550 * setting DLAB enable gives access to the EFR on 551 * these chips. 552 */ 553 if (sc->sc_type == COM_TYPE_16650) { 554 lcr = CSR_READ_1(regsp, COM_REG_LCR); 555 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 556 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 557 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 558 CSR_WRITE_1(regsp, COM_REG_LCR, 559 lcr | LCR_DLAB); 560 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 561 CLR(sc->sc_hwflags, COM_HW_FIFO); 562 sc->sc_fifolen = 0; 563 } else { 564 SET(sc->sc_hwflags, COM_HW_FLOW); 565 sc->sc_fifolen = 32; 566 } 567 } else 568 sc->sc_fifolen = 16; 569 570 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 571 if (sc->sc_fifolen == 0) 572 fifo_msg = "st16650, broken fifo"; 573 else if (sc->sc_fifolen == 32) 574 fifo_msg = "st16650a, working fifo"; 575 else 576 fifo_msg = "ns16550a, working fifo"; 577 } 578 579 /* 580 * TL16C750 can enable 64byte FIFO, only when DLAB 581 * is 1. However, some 16750 may always enable. For 582 * example, restrictions according to DLAB in a data 583 * sheet for SC16C750 were not described. 584 * Please enable 'options COM_16650', supposing you 585 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 586 * should become effective. 587 */ 588 if (sc->sc_type == COM_TYPE_16750) { 589 uint8_t iir1, iir2; 590 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 591 592 lcr = CSR_READ_1(regsp, COM_REG_LCR); 593 CSR_WRITE_1(regsp, COM_REG_LCR, 594 lcr & ~LCR_DLAB); 595 CSR_WRITE_1(regsp, COM_REG_FIFO, 596 fcr | FIFO_64B_ENABLE); 597 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 598 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 599 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 600 CSR_WRITE_1(regsp, COM_REG_FIFO, 601 fcr | FIFO_64B_ENABLE); 602 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 603 604 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 605 606 if (!ISSET(iir1, IIR_64B_FIFO) && 607 ISSET(iir2, IIR_64B_FIFO)) { 608 /* It is TL16C750. */ 609 sc->sc_fifolen = 64; 610 SET(sc->sc_hwflags, COM_HW_AFE); 611 } else 612 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 613 614 if (sc->sc_fifolen == 64) 615 fifo_msg = "tl16c750, working fifo"; 616 else 617 fifo_msg = "ns16750, working fifo"; 618 } 619 } else 620 fifo_msg = "ns16550, broken fifo"; 621 else 622 fifo_msg = "ns8250 or ns16450, no fifo"; 623 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 624 625 fifodelay: 626 /* 627 * Some chips will clear down both Tx and Rx FIFOs when zero is 628 * written to com_fifo. If this chip is the console, writing zero 629 * results in some of the chip/FIFO description being lost, so delay 630 * printing it until now. 631 */ 632 delay(10); 633 aprint_normal(": %s\n", fifo_msg); 634 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 635 sc->sc_fifolen = 1; 636 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 637 } 638 639 fifodone: 640 641 tp = tty_alloc(); 642 tp->t_oproc = comstart; 643 tp->t_param = comparam; 644 tp->t_hwiflow = comhwiflow; 645 tp->t_softc = sc; 646 647 sc->sc_tty = tp; 648 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 649 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 650 sc->sc_rbavail = com_rbuf_size; 651 if (sc->sc_rbuf == NULL) { 652 aprint_error_dev(sc->sc_dev, 653 "unable to allocate ring buffer\n"); 654 return; 655 } 656 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 657 658 tty_attach(tp); 659 660 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 661 SET(sc->sc_mcr, MCR_IENABLE); 662 663 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 664 int maj; 665 666 /* locate the major number */ 667 maj = cdevsw_lookup_major(&com_cdevsw); 668 669 tp->t_dev = cn_tab->cn_dev = makedev(maj, 670 device_unit(sc->sc_dev)); 671 672 aprint_normal_dev(sc->sc_dev, "console\n"); 673 } 674 675 #ifdef KGDB 676 /* 677 * Allow kgdb to "take over" this port. If this is 678 * not the console and is the kgdb device, it has 679 * exclusive use. If it's the console _and_ the 680 * kgdb device, it doesn't. 681 */ 682 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 683 regsp->cr_iobase == comkgdbregs.cr_iobase) { 684 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 685 com_kgdb_attached = 1; 686 687 SET(sc->sc_hwflags, COM_HW_KGDB); 688 } 689 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 690 } 691 #endif 692 693 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 694 695 #ifdef RND_COM 696 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 697 RND_TYPE_TTY, RND_FLAG_DEFAULT); 698 #endif 699 700 /* if there are no enable/disable functions, assume the device 701 is always enabled */ 702 if (!sc->enable) 703 sc->enabled = 1; 704 705 com_config(sc); 706 707 SET(sc->sc_hwflags, COM_HW_DEV_OK); 708 709 if (ISSET(sc->sc_hwflags, COM_HW_POLL)) 710 callout_schedule(&sc->sc_poll_callout, 1); 711 } 712 713 void 714 com_config(struct com_softc *sc) 715 { 716 struct com_regs *regsp = &sc->sc_regs; 717 718 /* Disable interrupts before configuring the device. */ 719 if (sc->sc_type == COM_TYPE_PXA2x0) 720 sc->sc_ier = IER_EUART; 721 else 722 sc->sc_ier = 0; 723 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 724 (void) CSR_READ_1(regsp, COM_REG_IIR); 725 726 /* Look for a Hayes ESP board. */ 727 if (sc->sc_type == COM_TYPE_HAYESP) { 728 729 /* Set 16550 compatibility mode */ 730 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 731 HAYESP_SETMODE); 732 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 733 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 734 HAYESP_MODE_SCALE); 735 736 /* Set RTS/CTS flow control */ 737 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 738 HAYESP_SETFLOWTYPE); 739 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 740 HAYESP_FLOW_RTS); 741 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 742 HAYESP_FLOW_CTS); 743 744 /* Set flow control levels */ 745 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 746 HAYESP_SETRXFLOW); 747 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 748 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 749 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 750 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 751 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 752 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 753 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 754 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 755 } 756 757 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 758 com_enable_debugport(sc); 759 } 760 761 #if 0 762 static int 763 comcngetc_detached(dev_t dev) 764 { 765 return 0; 766 } 767 768 static void 769 comcnputc_detached(dev_t dev, int c) 770 { 771 } 772 #endif 773 774 int 775 com_detach(device_t self, int flags) 776 { 777 struct com_softc *sc = device_private(self); 778 int maj, mn; 779 780 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 781 return EBUSY; 782 783 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 784 (flags & DETACH_SHUTDOWN) != 0) 785 return EBUSY; 786 787 if (sc->disable != NULL && sc->enabled != 0) { 788 (*sc->disable)(sc); 789 sc->enabled = 0; 790 } 791 792 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 793 comconsattached = 0; 794 cn_tab = NULL; 795 } 796 797 /* locate the major number */ 798 maj = cdevsw_lookup_major(&com_cdevsw); 799 800 /* Nuke the vnodes for any open instances. */ 801 mn = device_unit(self); 802 vdevgone(maj, mn, mn, VCHR); 803 804 mn |= COMDIALOUT_MASK; 805 vdevgone(maj, mn, mn, VCHR); 806 807 if (sc->sc_rbuf == NULL) { 808 /* 809 * Ring buffer allocation failed in the com_attach_subr, 810 * only the tty is allocated, and nothing else. 811 */ 812 tty_free(sc->sc_tty); 813 return 0; 814 } 815 816 /* Free the receive buffer. */ 817 free(sc->sc_rbuf, M_DEVBUF); 818 819 /* Detach and free the tty. */ 820 tty_detach(sc->sc_tty); 821 tty_free(sc->sc_tty); 822 823 /* Unhook the soft interrupt handler. */ 824 softint_disestablish(sc->sc_si); 825 826 #ifdef RND_COM 827 /* Unhook the entropy source. */ 828 rnd_detach_source(&sc->rnd_source); 829 #endif 830 callout_destroy(&sc->sc_diag_callout); 831 832 /* Destroy the lock. */ 833 mutex_destroy(&sc->sc_lock); 834 835 return (0); 836 } 837 838 void 839 com_shutdown(struct com_softc *sc) 840 { 841 struct tty *tp = sc->sc_tty; 842 843 mutex_spin_enter(&sc->sc_lock); 844 845 /* If we were asserting flow control, then deassert it. */ 846 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 847 com_hwiflow(sc); 848 849 /* Clear any break condition set with TIOCSBRK. */ 850 com_break(sc, 0); 851 852 /* 853 * Hang up if necessary. Wait a bit, so the other side has time to 854 * notice even if we immediately open the port again. 855 * Avoid tsleeping above splhigh(). 856 */ 857 if (ISSET(tp->t_cflag, HUPCL)) { 858 com_modem(sc, 0); 859 mutex_spin_exit(&sc->sc_lock); 860 /* XXX will only timeout */ 861 (void) kpause(ttclos, false, hz, NULL); 862 mutex_spin_enter(&sc->sc_lock); 863 } 864 865 /* Turn off interrupts. */ 866 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 867 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 868 if ((sc->sc_type == COM_TYPE_PXA2x0) || 869 (sc->sc_type == COM_TYPE_INGENIC) || 870 (sc->sc_type == COM_TYPE_TEGRA)) 871 sc->sc_ier |= IER_ERXTOUT; 872 } else 873 sc->sc_ier = 0; 874 875 if (sc->sc_type == COM_TYPE_PXA2x0) 876 sc->sc_ier |= IER_EUART; 877 878 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 879 880 mutex_spin_exit(&sc->sc_lock); 881 882 if (sc->disable) { 883 #ifdef DIAGNOSTIC 884 if (!sc->enabled) 885 panic("com_shutdown: not enabled?"); 886 #endif 887 (*sc->disable)(sc); 888 sc->enabled = 0; 889 } 890 } 891 892 int 893 comopen(dev_t dev, int flag, int mode, struct lwp *l) 894 { 895 struct com_softc *sc; 896 struct tty *tp; 897 int s; 898 int error; 899 900 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 901 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 902 sc->sc_rbuf == NULL) 903 return (ENXIO); 904 905 if (!device_is_active(sc->sc_dev)) 906 return (ENXIO); 907 908 #ifdef KGDB 909 /* 910 * If this is the kgdb port, no other use is permitted. 911 */ 912 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 913 return (EBUSY); 914 #endif 915 916 tp = sc->sc_tty; 917 918 /* 919 * If the device is exclusively for kernel use, deny userland 920 * open. 921 */ 922 if (ISSET(tp->t_state, TS_KERN_ONLY)) 923 return (EBUSY); 924 925 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 926 return (EBUSY); 927 928 s = spltty(); 929 930 /* 931 * Do the following iff this is a first open. 932 */ 933 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 934 struct termios t; 935 936 tp->t_dev = dev; 937 938 if (sc->enable) { 939 if ((*sc->enable)(sc)) { 940 splx(s); 941 aprint_error_dev(sc->sc_dev, 942 "device enable failed\n"); 943 return (EIO); 944 } 945 mutex_spin_enter(&sc->sc_lock); 946 sc->enabled = 1; 947 com_config(sc); 948 } else { 949 mutex_spin_enter(&sc->sc_lock); 950 } 951 952 /* Turn on interrupts. */ 953 sc->sc_ier = IER_ERXRDY | IER_ERLS; 954 if (!ISSET(tp->t_cflag, CLOCAL)) 955 sc->sc_ier |= IER_EMSC; 956 957 if (sc->sc_type == COM_TYPE_PXA2x0) 958 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 959 else if (sc->sc_type == COM_TYPE_INGENIC || 960 sc->sc_type == COM_TYPE_TEGRA) 961 sc->sc_ier |= IER_ERXTOUT; 962 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 963 964 /* Fetch the current modem control status, needed later. */ 965 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 966 967 /* Clear PPS capture state on first open. */ 968 mutex_spin_enter(&timecounter_lock); 969 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 970 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 971 pps_init(&sc->sc_pps_state); 972 mutex_spin_exit(&timecounter_lock); 973 974 mutex_spin_exit(&sc->sc_lock); 975 976 /* 977 * Initialize the termios status to the defaults. Add in the 978 * sticky bits from TIOCSFLAGS. 979 */ 980 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 981 t.c_ospeed = comcons_info.rate; 982 t.c_cflag = comcons_info.cflag; 983 } else { 984 t.c_ospeed = TTYDEF_SPEED; 985 t.c_cflag = TTYDEF_CFLAG; 986 } 987 t.c_ispeed = t.c_ospeed; 988 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 989 SET(t.c_cflag, CLOCAL); 990 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 991 SET(t.c_cflag, CRTSCTS); 992 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 993 SET(t.c_cflag, MDMBUF); 994 /* Make sure comparam() will do something. */ 995 tp->t_ospeed = 0; 996 (void) comparam(tp, &t); 997 tp->t_iflag = TTYDEF_IFLAG; 998 tp->t_oflag = TTYDEF_OFLAG; 999 tp->t_lflag = TTYDEF_LFLAG; 1000 ttychars(tp); 1001 ttsetwater(tp); 1002 1003 mutex_spin_enter(&sc->sc_lock); 1004 1005 /* 1006 * Turn on DTR. We must always do this, even if carrier is not 1007 * present, because otherwise we'd have to use TIOCSDTR 1008 * immediately after setting CLOCAL, which applications do not 1009 * expect. We always assert DTR while the device is open 1010 * unless explicitly requested to deassert it. 1011 */ 1012 com_modem(sc, 1); 1013 1014 /* Clear the input ring, and unblock. */ 1015 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1016 sc->sc_rbavail = com_rbuf_size; 1017 com_iflush(sc); 1018 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1019 com_hwiflow(sc); 1020 1021 #ifdef COM_DEBUG 1022 if (com_debug) 1023 comstatus(sc, "comopen "); 1024 #endif 1025 1026 mutex_spin_exit(&sc->sc_lock); 1027 } 1028 1029 splx(s); 1030 1031 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1032 if (error) 1033 goto bad; 1034 1035 error = (*tp->t_linesw->l_open)(dev, tp); 1036 if (error) 1037 goto bad; 1038 1039 return (0); 1040 1041 bad: 1042 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1043 /* 1044 * We failed to open the device, and nobody else had it opened. 1045 * Clean up the state as appropriate. 1046 */ 1047 com_shutdown(sc); 1048 } 1049 1050 return (error); 1051 } 1052 1053 int 1054 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1055 { 1056 struct com_softc *sc = 1057 device_lookup_private(&com_cd, COMUNIT(dev)); 1058 struct tty *tp = sc->sc_tty; 1059 1060 /* XXX This is for cons.c. */ 1061 if (!ISSET(tp->t_state, TS_ISOPEN)) 1062 return (0); 1063 /* 1064 * If the device is exclusively for kernel use, deny userland 1065 * close. 1066 */ 1067 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1068 return (0); 1069 1070 (*tp->t_linesw->l_close)(tp, flag); 1071 ttyclose(tp); 1072 1073 if (COM_ISALIVE(sc) == 0) 1074 return (0); 1075 1076 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1077 /* 1078 * Although we got a last close, the device may still be in 1079 * use; e.g. if this was the dialout node, and there are still 1080 * processes waiting for carrier on the non-dialout node. 1081 */ 1082 com_shutdown(sc); 1083 } 1084 1085 return (0); 1086 } 1087 1088 int 1089 comread(dev_t dev, struct uio *uio, int flag) 1090 { 1091 struct com_softc *sc = 1092 device_lookup_private(&com_cd, COMUNIT(dev)); 1093 struct tty *tp = sc->sc_tty; 1094 1095 if (COM_ISALIVE(sc) == 0) 1096 return (EIO); 1097 1098 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1099 } 1100 1101 int 1102 comwrite(dev_t dev, struct uio *uio, int flag) 1103 { 1104 struct com_softc *sc = 1105 device_lookup_private(&com_cd, COMUNIT(dev)); 1106 struct tty *tp = sc->sc_tty; 1107 1108 if (COM_ISALIVE(sc) == 0) 1109 return (EIO); 1110 1111 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1112 } 1113 1114 int 1115 compoll(dev_t dev, int events, struct lwp *l) 1116 { 1117 struct com_softc *sc = 1118 device_lookup_private(&com_cd, COMUNIT(dev)); 1119 struct tty *tp = sc->sc_tty; 1120 1121 if (COM_ISALIVE(sc) == 0) 1122 return (POLLHUP); 1123 1124 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1125 } 1126 1127 struct tty * 1128 comtty(dev_t dev) 1129 { 1130 struct com_softc *sc = 1131 device_lookup_private(&com_cd, COMUNIT(dev)); 1132 struct tty *tp = sc->sc_tty; 1133 1134 return (tp); 1135 } 1136 1137 int 1138 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1139 { 1140 struct com_softc *sc; 1141 struct tty *tp; 1142 int error; 1143 1144 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1145 if (sc == NULL) 1146 return ENXIO; 1147 if (COM_ISALIVE(sc) == 0) 1148 return (EIO); 1149 1150 tp = sc->sc_tty; 1151 1152 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1153 if (error != EPASSTHROUGH) 1154 return (error); 1155 1156 error = ttioctl(tp, cmd, data, flag, l); 1157 if (error != EPASSTHROUGH) 1158 return (error); 1159 1160 error = 0; 1161 switch (cmd) { 1162 case TIOCSFLAGS: 1163 error = kauth_authorize_device_tty(l->l_cred, 1164 KAUTH_DEVICE_TTY_PRIVSET, tp); 1165 break; 1166 default: 1167 /* nothing */ 1168 break; 1169 } 1170 if (error) { 1171 return error; 1172 } 1173 1174 mutex_spin_enter(&sc->sc_lock); 1175 1176 switch (cmd) { 1177 case TIOCSBRK: 1178 com_break(sc, 1); 1179 break; 1180 1181 case TIOCCBRK: 1182 com_break(sc, 0); 1183 break; 1184 1185 case TIOCSDTR: 1186 com_modem(sc, 1); 1187 break; 1188 1189 case TIOCCDTR: 1190 com_modem(sc, 0); 1191 break; 1192 1193 case TIOCGFLAGS: 1194 *(int *)data = sc->sc_swflags; 1195 break; 1196 1197 case TIOCSFLAGS: 1198 sc->sc_swflags = *(int *)data; 1199 break; 1200 1201 case TIOCMSET: 1202 case TIOCMBIS: 1203 case TIOCMBIC: 1204 tiocm_to_com(sc, cmd, *(int *)data); 1205 break; 1206 1207 case TIOCMGET: 1208 *(int *)data = com_to_tiocm(sc); 1209 break; 1210 1211 case PPS_IOC_CREATE: 1212 case PPS_IOC_DESTROY: 1213 case PPS_IOC_GETPARAMS: 1214 case PPS_IOC_SETPARAMS: 1215 case PPS_IOC_GETCAP: 1216 case PPS_IOC_FETCH: 1217 #ifdef PPS_SYNC 1218 case PPS_IOC_KCBIND: 1219 #endif 1220 mutex_spin_enter(&timecounter_lock); 1221 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1222 mutex_spin_exit(&timecounter_lock); 1223 break; 1224 1225 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1226 mutex_spin_enter(&timecounter_lock); 1227 #ifndef PPS_TRAILING_EDGE 1228 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1229 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1230 #else 1231 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1232 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1233 #endif 1234 mutex_spin_exit(&timecounter_lock); 1235 break; 1236 1237 default: 1238 error = EPASSTHROUGH; 1239 break; 1240 } 1241 1242 mutex_spin_exit(&sc->sc_lock); 1243 1244 #ifdef COM_DEBUG 1245 if (com_debug) 1246 comstatus(sc, "comioctl "); 1247 #endif 1248 1249 return (error); 1250 } 1251 1252 integrate void 1253 com_schedrx(struct com_softc *sc) 1254 { 1255 1256 sc->sc_rx_ready = 1; 1257 1258 /* Wake up the poller. */ 1259 softint_schedule(sc->sc_si); 1260 } 1261 1262 void 1263 com_break(struct com_softc *sc, int onoff) 1264 { 1265 1266 if (onoff) 1267 SET(sc->sc_lcr, LCR_SBREAK); 1268 else 1269 CLR(sc->sc_lcr, LCR_SBREAK); 1270 1271 if (!sc->sc_heldchange) { 1272 if (sc->sc_tx_busy) { 1273 sc->sc_heldtbc = sc->sc_tbc; 1274 sc->sc_tbc = 0; 1275 sc->sc_heldchange = 1; 1276 } else 1277 com_loadchannelregs(sc); 1278 } 1279 } 1280 1281 void 1282 com_modem(struct com_softc *sc, int onoff) 1283 { 1284 1285 if (sc->sc_mcr_dtr == 0) 1286 return; 1287 1288 if (onoff) 1289 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1290 else 1291 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1292 1293 if (!sc->sc_heldchange) { 1294 if (sc->sc_tx_busy) { 1295 sc->sc_heldtbc = sc->sc_tbc; 1296 sc->sc_tbc = 0; 1297 sc->sc_heldchange = 1; 1298 } else 1299 com_loadchannelregs(sc); 1300 } 1301 } 1302 1303 void 1304 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1305 { 1306 u_char combits; 1307 1308 combits = 0; 1309 if (ISSET(ttybits, TIOCM_DTR)) 1310 SET(combits, MCR_DTR); 1311 if (ISSET(ttybits, TIOCM_RTS)) 1312 SET(combits, MCR_RTS); 1313 1314 switch (how) { 1315 case TIOCMBIC: 1316 CLR(sc->sc_mcr, combits); 1317 break; 1318 1319 case TIOCMBIS: 1320 SET(sc->sc_mcr, combits); 1321 break; 1322 1323 case TIOCMSET: 1324 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1325 SET(sc->sc_mcr, combits); 1326 break; 1327 } 1328 1329 if (!sc->sc_heldchange) { 1330 if (sc->sc_tx_busy) { 1331 sc->sc_heldtbc = sc->sc_tbc; 1332 sc->sc_tbc = 0; 1333 sc->sc_heldchange = 1; 1334 } else 1335 com_loadchannelregs(sc); 1336 } 1337 } 1338 1339 int 1340 com_to_tiocm(struct com_softc *sc) 1341 { 1342 u_char combits; 1343 int ttybits = 0; 1344 1345 combits = sc->sc_mcr; 1346 if (ISSET(combits, MCR_DTR)) 1347 SET(ttybits, TIOCM_DTR); 1348 if (ISSET(combits, MCR_RTS)) 1349 SET(ttybits, TIOCM_RTS); 1350 1351 combits = sc->sc_msr; 1352 if (sc->sc_type == COM_TYPE_INGENIC) { 1353 SET(ttybits, TIOCM_CD); 1354 } else { 1355 if (ISSET(combits, MSR_DCD)) 1356 SET(ttybits, TIOCM_CD); 1357 } 1358 if (ISSET(combits, MSR_CTS)) 1359 SET(ttybits, TIOCM_CTS); 1360 if (ISSET(combits, MSR_DSR)) 1361 SET(ttybits, TIOCM_DSR); 1362 if (ISSET(combits, MSR_RI | MSR_TERI)) 1363 SET(ttybits, TIOCM_RI); 1364 1365 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1366 SET(ttybits, TIOCM_LE); 1367 1368 return (ttybits); 1369 } 1370 1371 static u_char 1372 cflag2lcr(tcflag_t cflag) 1373 { 1374 u_char lcr = 0; 1375 1376 switch (ISSET(cflag, CSIZE)) { 1377 case CS5: 1378 SET(lcr, LCR_5BITS); 1379 break; 1380 case CS6: 1381 SET(lcr, LCR_6BITS); 1382 break; 1383 case CS7: 1384 SET(lcr, LCR_7BITS); 1385 break; 1386 case CS8: 1387 SET(lcr, LCR_8BITS); 1388 break; 1389 } 1390 if (ISSET(cflag, PARENB)) { 1391 SET(lcr, LCR_PENAB); 1392 if (!ISSET(cflag, PARODD)) 1393 SET(lcr, LCR_PEVEN); 1394 } 1395 if (ISSET(cflag, CSTOPB)) 1396 SET(lcr, LCR_STOPB); 1397 1398 return (lcr); 1399 } 1400 1401 int 1402 comparam(struct tty *tp, struct termios *t) 1403 { 1404 struct com_softc *sc = 1405 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1406 int ospeed; 1407 u_char lcr; 1408 1409 if (COM_ISALIVE(sc) == 0) 1410 return (EIO); 1411 1412 if (sc->sc_type == COM_TYPE_HAYESP) { 1413 int prescaler, speed; 1414 1415 /* 1416 * Calculate UART clock prescaler. It should be in 1417 * range of 0 .. 3. 1418 */ 1419 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1420 prescaler++, speed /= 2) 1421 if ((ospeed = comspeed(speed, sc->sc_frequency, 1422 sc->sc_type)) > 0) 1423 break; 1424 1425 if (prescaler == 4) 1426 return (EINVAL); 1427 sc->sc_prescaler = prescaler; 1428 } else 1429 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1430 1431 /* Check requested parameters. */ 1432 if (ospeed < 0) 1433 return (EINVAL); 1434 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1435 return (EINVAL); 1436 1437 /* 1438 * For the console, always force CLOCAL and !HUPCL, so that the port 1439 * is always active. 1440 */ 1441 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1442 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1443 SET(t->c_cflag, CLOCAL); 1444 CLR(t->c_cflag, HUPCL); 1445 } 1446 1447 /* 1448 * If there were no changes, don't do anything. This avoids dropping 1449 * input and improves performance when all we did was frob things like 1450 * VMIN and VTIME. 1451 */ 1452 if (tp->t_ospeed == t->c_ospeed && 1453 tp->t_cflag == t->c_cflag) 1454 return (0); 1455 1456 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1457 1458 mutex_spin_enter(&sc->sc_lock); 1459 1460 sc->sc_lcr = lcr; 1461 1462 /* 1463 * If we're not in a mode that assumes a connection is present, then 1464 * ignore carrier changes. 1465 */ 1466 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1467 sc->sc_msr_dcd = 0; 1468 else 1469 sc->sc_msr_dcd = MSR_DCD; 1470 /* 1471 * Set the flow control pins depending on the current flow control 1472 * mode. 1473 */ 1474 if (ISSET(t->c_cflag, CRTSCTS)) { 1475 sc->sc_mcr_dtr = MCR_DTR; 1476 sc->sc_mcr_rts = MCR_RTS; 1477 sc->sc_msr_cts = MSR_CTS; 1478 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1479 SET(sc->sc_mcr, MCR_AFE); 1480 } else { 1481 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1482 } 1483 } else if (ISSET(t->c_cflag, MDMBUF)) { 1484 /* 1485 * For DTR/DCD flow control, make sure we don't toggle DTR for 1486 * carrier detection. 1487 */ 1488 sc->sc_mcr_dtr = 0; 1489 sc->sc_mcr_rts = MCR_DTR; 1490 sc->sc_msr_cts = MSR_DCD; 1491 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1492 CLR(sc->sc_mcr, MCR_AFE); 1493 } else { 1494 sc->sc_efr = 0; 1495 } 1496 } else { 1497 /* 1498 * If no flow control, then always set RTS. This will make 1499 * the other side happy if it mistakenly thinks we're doing 1500 * RTS/CTS flow control. 1501 */ 1502 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1503 sc->sc_mcr_rts = 0; 1504 sc->sc_msr_cts = 0; 1505 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1506 CLR(sc->sc_mcr, MCR_AFE); 1507 } else { 1508 sc->sc_efr = 0; 1509 } 1510 if (ISSET(sc->sc_mcr, MCR_DTR)) 1511 SET(sc->sc_mcr, MCR_RTS); 1512 else 1513 CLR(sc->sc_mcr, MCR_RTS); 1514 } 1515 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1516 1517 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1518 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1519 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1520 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1521 1522 sc->sc_dlbl = ospeed; 1523 sc->sc_dlbh = ospeed >> 8; 1524 1525 /* 1526 * Set the FIFO threshold based on the receive speed. 1527 * 1528 * * If it's a low speed, it's probably a mouse or some other 1529 * interactive device, so set the threshold low. 1530 * * If it's a high speed, trim the trigger level down to prevent 1531 * overflows. 1532 * * Otherwise set it a bit higher. 1533 */ 1534 if (sc->sc_type == COM_TYPE_HAYESP) { 1535 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1536 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1537 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1538 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1539 if (t->c_ospeed <= 1200) 1540 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1541 else if (t->c_ospeed <= 38400) 1542 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1543 else 1544 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1545 } else { 1546 sc->sc_fifo = 0; 1547 } 1548 1549 if (sc->sc_type == COM_TYPE_INGENIC) 1550 sc->sc_fifo |= FIFO_UART_ON; 1551 1552 /* And copy to tty. */ 1553 tp->t_ispeed = t->c_ospeed; 1554 tp->t_ospeed = t->c_ospeed; 1555 tp->t_cflag = t->c_cflag; 1556 1557 if (!sc->sc_heldchange) { 1558 if (sc->sc_tx_busy) { 1559 sc->sc_heldtbc = sc->sc_tbc; 1560 sc->sc_tbc = 0; 1561 sc->sc_heldchange = 1; 1562 } else 1563 com_loadchannelregs(sc); 1564 } 1565 1566 if (!ISSET(t->c_cflag, CHWFLOW)) { 1567 /* Disable the high water mark. */ 1568 sc->sc_r_hiwat = 0; 1569 sc->sc_r_lowat = 0; 1570 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1571 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1572 com_schedrx(sc); 1573 } 1574 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1575 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1576 com_hwiflow(sc); 1577 } 1578 } else { 1579 sc->sc_r_hiwat = com_rbuf_hiwat; 1580 sc->sc_r_lowat = com_rbuf_lowat; 1581 } 1582 1583 mutex_spin_exit(&sc->sc_lock); 1584 1585 /* 1586 * Update the tty layer's idea of the carrier bit, in case we changed 1587 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1588 * explicit request. 1589 */ 1590 if (sc->sc_type == COM_TYPE_INGENIC) { 1591 /* no DCD here */ 1592 (void) (*tp->t_linesw->l_modem)(tp, 1); 1593 } else 1594 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1595 1596 #ifdef COM_DEBUG 1597 if (com_debug) 1598 comstatus(sc, "comparam "); 1599 #endif 1600 1601 if (!ISSET(t->c_cflag, CHWFLOW)) { 1602 if (sc->sc_tx_stopped) { 1603 sc->sc_tx_stopped = 0; 1604 comstart(tp); 1605 } 1606 } 1607 1608 return (0); 1609 } 1610 1611 void 1612 com_iflush(struct com_softc *sc) 1613 { 1614 struct com_regs *regsp = &sc->sc_regs; 1615 uint8_t fifo; 1616 #ifdef DIAGNOSTIC 1617 int reg; 1618 #endif 1619 int timo; 1620 1621 #ifdef DIAGNOSTIC 1622 reg = 0xffff; 1623 #endif 1624 timo = 50000; 1625 /* flush any pending I/O */ 1626 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1627 && --timo) 1628 #ifdef DIAGNOSTIC 1629 reg = 1630 #else 1631 (void) 1632 #endif 1633 CSR_READ_1(regsp, COM_REG_RXDATA); 1634 #ifdef DIAGNOSTIC 1635 if (!timo) 1636 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1637 #endif 1638 1639 switch (sc->sc_type) { 1640 case COM_TYPE_16750: 1641 case COM_TYPE_DW_APB: 1642 /* 1643 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1644 * This should prevent triggering busy interrupt while 1645 * manipulating divisors. 1646 */ 1647 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1648 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1649 CSR_WRITE_1(regsp, COM_REG_FIFO, 1650 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1651 delay(100); 1652 break; 1653 } 1654 } 1655 1656 void 1657 com_loadchannelregs(struct com_softc *sc) 1658 { 1659 struct com_regs *regsp = &sc->sc_regs; 1660 1661 /* XXXXX necessary? */ 1662 com_iflush(sc); 1663 1664 if (sc->sc_type == COM_TYPE_PXA2x0) 1665 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1666 else 1667 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1668 1669 if (sc->sc_type == COM_TYPE_OMAP) { 1670 /* disable before changing settings */ 1671 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1672 } 1673 1674 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1675 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1676 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1677 /* no EFR on alchemy */ 1678 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1679 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1680 } 1681 if (sc->sc_type == COM_TYPE_AU1x00) { 1682 /* alchemy has single separate 16-bit clock divisor register */ 1683 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1684 (sc->sc_dlbh << 8)); 1685 } else { 1686 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1687 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1688 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1689 } 1690 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1691 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1692 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1693 if (sc->sc_type == COM_TYPE_HAYESP) { 1694 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1695 HAYESP_SETPRESCALER); 1696 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1697 sc->sc_prescaler); 1698 } 1699 if (sc->sc_type == COM_TYPE_OMAP) { 1700 /* setup the fifos. the FCR value is not used as long 1701 as SCR[6] and SCR[7] are 0, which they are at reset 1702 and we never touch the SCR register */ 1703 uint8_t rx_fifo_trig = 40; 1704 uint8_t tx_fifo_trig = 60; 1705 uint8_t rx_start = 8; 1706 uint8_t rx_halt = 60; 1707 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1708 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1709 1710 /* enable access to TCR & TLR */ 1711 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1712 1713 /* write tcr and tlr values */ 1714 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1715 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1716 1717 /* disable access to TCR & TLR */ 1718 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1719 1720 /* enable again, but mode is based on speed */ 1721 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1722 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1723 } else { 1724 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1725 } 1726 } 1727 1728 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1729 } 1730 1731 int 1732 comhwiflow(struct tty *tp, int block) 1733 { 1734 struct com_softc *sc = 1735 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1736 1737 if (COM_ISALIVE(sc) == 0) 1738 return (0); 1739 1740 if (sc->sc_mcr_rts == 0) 1741 return (0); 1742 1743 mutex_spin_enter(&sc->sc_lock); 1744 1745 if (block) { 1746 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1747 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1748 com_hwiflow(sc); 1749 } 1750 } else { 1751 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1752 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1753 com_schedrx(sc); 1754 } 1755 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1756 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1757 com_hwiflow(sc); 1758 } 1759 } 1760 1761 mutex_spin_exit(&sc->sc_lock); 1762 return (1); 1763 } 1764 1765 /* 1766 * (un)block input via hw flowcontrol 1767 */ 1768 void 1769 com_hwiflow(struct com_softc *sc) 1770 { 1771 struct com_regs *regsp= &sc->sc_regs; 1772 1773 if (sc->sc_mcr_rts == 0) 1774 return; 1775 1776 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1777 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1778 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1779 } else { 1780 SET(sc->sc_mcr, sc->sc_mcr_rts); 1781 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1782 } 1783 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1784 } 1785 1786 1787 void 1788 comstart(struct tty *tp) 1789 { 1790 struct com_softc *sc = 1791 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1792 struct com_regs *regsp = &sc->sc_regs; 1793 int s; 1794 1795 if (COM_ISALIVE(sc) == 0) 1796 return; 1797 1798 s = spltty(); 1799 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1800 goto out; 1801 if (sc->sc_tx_stopped) 1802 goto out; 1803 if (!ttypull(tp)) 1804 goto out; 1805 1806 /* Grab the first contiguous region of buffer space. */ 1807 { 1808 u_char *tba; 1809 int tbc; 1810 1811 tba = tp->t_outq.c_cf; 1812 tbc = ndqb(&tp->t_outq, 0); 1813 1814 mutex_spin_enter(&sc->sc_lock); 1815 1816 sc->sc_tba = tba; 1817 sc->sc_tbc = tbc; 1818 } 1819 1820 SET(tp->t_state, TS_BUSY); 1821 sc->sc_tx_busy = 1; 1822 1823 /* Enable transmit completion interrupts if necessary. */ 1824 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1825 SET(sc->sc_ier, IER_ETXRDY); 1826 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1827 } 1828 1829 /* Output the first chunk of the contiguous buffer. */ 1830 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1831 u_int n; 1832 1833 n = sc->sc_tbc; 1834 if (n > sc->sc_fifolen) 1835 n = sc->sc_fifolen; 1836 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1837 sc->sc_tbc -= n; 1838 sc->sc_tba += n; 1839 } 1840 1841 mutex_spin_exit(&sc->sc_lock); 1842 out: 1843 splx(s); 1844 return; 1845 } 1846 1847 /* 1848 * Stop output on a line. 1849 */ 1850 void 1851 comstop(struct tty *tp, int flag) 1852 { 1853 struct com_softc *sc = 1854 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1855 1856 mutex_spin_enter(&sc->sc_lock); 1857 if (ISSET(tp->t_state, TS_BUSY)) { 1858 /* Stop transmitting at the next chunk. */ 1859 sc->sc_tbc = 0; 1860 sc->sc_heldtbc = 0; 1861 if (!ISSET(tp->t_state, TS_TTSTOP)) 1862 SET(tp->t_state, TS_FLUSH); 1863 } 1864 mutex_spin_exit(&sc->sc_lock); 1865 } 1866 1867 void 1868 comdiag(void *arg) 1869 { 1870 struct com_softc *sc = arg; 1871 int overflows, floods; 1872 1873 mutex_spin_enter(&sc->sc_lock); 1874 overflows = sc->sc_overflows; 1875 sc->sc_overflows = 0; 1876 floods = sc->sc_floods; 1877 sc->sc_floods = 0; 1878 sc->sc_errors = 0; 1879 mutex_spin_exit(&sc->sc_lock); 1880 1881 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1882 device_xname(sc->sc_dev), 1883 overflows, overflows == 1 ? "" : "s", 1884 floods, floods == 1 ? "" : "s"); 1885 } 1886 1887 integrate void 1888 com_rxsoft(struct com_softc *sc, struct tty *tp) 1889 { 1890 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1891 u_char *get, *end; 1892 u_int cc, scc; 1893 u_char lsr; 1894 int code; 1895 1896 end = sc->sc_ebuf; 1897 get = sc->sc_rbget; 1898 scc = cc = com_rbuf_size - sc->sc_rbavail; 1899 1900 if (cc == com_rbuf_size) { 1901 sc->sc_floods++; 1902 if (sc->sc_errors++ == 0) 1903 callout_reset(&sc->sc_diag_callout, 60 * hz, 1904 comdiag, sc); 1905 } 1906 1907 /* If not yet open, drop the entire buffer content here */ 1908 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1909 get += cc << 1; 1910 if (get >= end) 1911 get -= com_rbuf_size << 1; 1912 cc = 0; 1913 } 1914 while (cc) { 1915 code = get[0]; 1916 lsr = get[1]; 1917 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1918 if (ISSET(lsr, LSR_OE)) { 1919 sc->sc_overflows++; 1920 if (sc->sc_errors++ == 0) 1921 callout_reset(&sc->sc_diag_callout, 1922 60 * hz, comdiag, sc); 1923 } 1924 if (ISSET(lsr, LSR_BI | LSR_FE)) 1925 SET(code, TTY_FE); 1926 if (ISSET(lsr, LSR_PE)) 1927 SET(code, TTY_PE); 1928 } 1929 if ((*rint)(code, tp) == -1) { 1930 /* 1931 * The line discipline's buffer is out of space. 1932 */ 1933 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1934 /* 1935 * We're either not using flow control, or the 1936 * line discipline didn't tell us to block for 1937 * some reason. Either way, we have no way to 1938 * know when there's more space available, so 1939 * just drop the rest of the data. 1940 */ 1941 get += cc << 1; 1942 if (get >= end) 1943 get -= com_rbuf_size << 1; 1944 cc = 0; 1945 } else { 1946 /* 1947 * Don't schedule any more receive processing 1948 * until the line discipline tells us there's 1949 * space available (through comhwiflow()). 1950 * Leave the rest of the data in the input 1951 * buffer. 1952 */ 1953 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1954 } 1955 break; 1956 } 1957 get += 2; 1958 if (get >= end) 1959 get = sc->sc_rbuf; 1960 cc--; 1961 } 1962 1963 if (cc != scc) { 1964 sc->sc_rbget = get; 1965 mutex_spin_enter(&sc->sc_lock); 1966 1967 cc = sc->sc_rbavail += scc - cc; 1968 /* Buffers should be ok again, release possible block. */ 1969 if (cc >= sc->sc_r_lowat) { 1970 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1971 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1972 SET(sc->sc_ier, IER_ERXRDY); 1973 if (sc->sc_type == COM_TYPE_PXA2x0) 1974 SET(sc->sc_ier, IER_ERXTOUT); 1975 if (sc->sc_type == COM_TYPE_INGENIC || 1976 sc->sc_type == COM_TYPE_TEGRA) 1977 SET(sc->sc_ier, IER_ERXTOUT); 1978 1979 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 1980 sc->sc_ier); 1981 } 1982 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1983 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1984 com_hwiflow(sc); 1985 } 1986 } 1987 mutex_spin_exit(&sc->sc_lock); 1988 } 1989 } 1990 1991 integrate void 1992 com_txsoft(struct com_softc *sc, struct tty *tp) 1993 { 1994 1995 CLR(tp->t_state, TS_BUSY); 1996 if (ISSET(tp->t_state, TS_FLUSH)) 1997 CLR(tp->t_state, TS_FLUSH); 1998 else 1999 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2000 (*tp->t_linesw->l_start)(tp); 2001 } 2002 2003 integrate void 2004 com_stsoft(struct com_softc *sc, struct tty *tp) 2005 { 2006 u_char msr, delta; 2007 2008 mutex_spin_enter(&sc->sc_lock); 2009 msr = sc->sc_msr; 2010 delta = sc->sc_msr_delta; 2011 sc->sc_msr_delta = 0; 2012 mutex_spin_exit(&sc->sc_lock); 2013 2014 if (ISSET(delta, sc->sc_msr_dcd)) { 2015 /* 2016 * Inform the tty layer that carrier detect changed. 2017 */ 2018 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2019 } 2020 2021 if (ISSET(delta, sc->sc_msr_cts)) { 2022 /* Block or unblock output according to flow control. */ 2023 if (ISSET(msr, sc->sc_msr_cts)) { 2024 sc->sc_tx_stopped = 0; 2025 (*tp->t_linesw->l_start)(tp); 2026 } else { 2027 sc->sc_tx_stopped = 1; 2028 } 2029 } 2030 2031 #ifdef COM_DEBUG 2032 if (com_debug) 2033 comstatus(sc, "com_stsoft"); 2034 #endif 2035 } 2036 2037 void 2038 comsoft(void *arg) 2039 { 2040 struct com_softc *sc = arg; 2041 struct tty *tp; 2042 2043 if (COM_ISALIVE(sc) == 0) 2044 return; 2045 2046 tp = sc->sc_tty; 2047 2048 if (sc->sc_rx_ready) { 2049 sc->sc_rx_ready = 0; 2050 com_rxsoft(sc, tp); 2051 } 2052 2053 if (sc->sc_st_check) { 2054 sc->sc_st_check = 0; 2055 com_stsoft(sc, tp); 2056 } 2057 2058 if (sc->sc_tx_done) { 2059 sc->sc_tx_done = 0; 2060 com_txsoft(sc, tp); 2061 } 2062 } 2063 2064 int 2065 comintr(void *arg) 2066 { 2067 struct com_softc *sc = arg; 2068 struct com_regs *regsp = &sc->sc_regs; 2069 2070 u_char *put, *end; 2071 u_int cc; 2072 u_char lsr, iir; 2073 2074 if (COM_ISALIVE(sc) == 0) 2075 return (0); 2076 2077 KASSERT(regsp != NULL); 2078 2079 mutex_spin_enter(&sc->sc_lock); 2080 iir = CSR_READ_1(regsp, COM_REG_IIR); 2081 2082 /* Handle ns16750-specific busy interrupt. */ 2083 if (sc->sc_type == COM_TYPE_16750 && 2084 (iir & IIR_BUSY) == IIR_BUSY) { 2085 for (int timeout = 10000; 2086 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2087 if (timeout <= 0) { 2088 aprint_error_dev(sc->sc_dev, 2089 "timeout while waiting for BUSY interrupt " 2090 "acknowledge\n"); 2091 mutex_spin_exit(&sc->sc_lock); 2092 return (0); 2093 } 2094 2095 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2096 iir = CSR_READ_1(regsp, COM_REG_IIR); 2097 } 2098 2099 /* DesignWare APB UART BUSY interrupt */ 2100 if (sc->sc_type == COM_TYPE_DW_APB && 2101 (iir & IIR_BUSY) == IIR_BUSY) { 2102 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2103 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2104 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2105 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2106 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2107 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2108 CSR_WRITE_1(regsp, COM_REG_HALT, 2109 HALT_CHCFG_EN | HALT_CHCFG_UD); 2110 for (int timeout = 10000000; 2111 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2112 timeout--) { 2113 if (timeout <= 0) { 2114 aprint_error_dev(sc->sc_dev, 2115 "timeout while waiting for HALT " 2116 "update acknowledge 0x%x 0x%x\n", 2117 CSR_READ_1(regsp, COM_REG_HALT), 2118 CSR_READ_1(regsp, COM_REG_USR)); 2119 break; 2120 } 2121 } 2122 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2123 (void)CSR_READ_1(regsp, COM_REG_USR); 2124 } else { 2125 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2126 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2127 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2128 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2129 } 2130 } 2131 2132 if (ISSET(iir, IIR_NOPEND)) { 2133 mutex_spin_exit(&sc->sc_lock); 2134 return (0); 2135 } 2136 2137 end = sc->sc_ebuf; 2138 put = sc->sc_rbput; 2139 cc = sc->sc_rbavail; 2140 2141 again: do { 2142 u_char msr, delta; 2143 2144 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2145 if (ISSET(lsr, LSR_BI)) { 2146 int cn_trapped = 0; /* see above: cn_trap() */ 2147 2148 cn_check_magic(sc->sc_tty->t_dev, 2149 CNC_BREAK, com_cnm_state); 2150 if (cn_trapped) 2151 continue; 2152 #if defined(KGDB) && !defined(DDB) 2153 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2154 kgdb_connect(1); 2155 continue; 2156 } 2157 #endif 2158 } 2159 2160 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2161 lsr |= LSR_RXRDY; 2162 2163 if (ISSET(lsr, LSR_RCV_MASK) && 2164 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2165 while (cc > 0) { 2166 int cn_trapped = 0; 2167 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2168 put[1] = lsr; 2169 cn_check_magic(sc->sc_tty->t_dev, 2170 put[0], com_cnm_state); 2171 if (cn_trapped) 2172 goto next; 2173 put += 2; 2174 if (put >= end) 2175 put = sc->sc_rbuf; 2176 cc--; 2177 next: 2178 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2179 if (!ISSET(lsr, LSR_RCV_MASK)) 2180 break; 2181 } 2182 2183 /* 2184 * Current string of incoming characters ended because 2185 * no more data was available or we ran out of space. 2186 * Schedule a receive event if any data was received. 2187 * If we're out of space, turn off receive interrupts. 2188 */ 2189 sc->sc_rbput = put; 2190 sc->sc_rbavail = cc; 2191 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2192 sc->sc_rx_ready = 1; 2193 2194 /* 2195 * See if we are in danger of overflowing a buffer. If 2196 * so, use hardware flow control to ease the pressure. 2197 */ 2198 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2199 cc < sc->sc_r_hiwat) { 2200 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2201 com_hwiflow(sc); 2202 } 2203 2204 /* 2205 * If we're out of space, disable receive interrupts 2206 * until the queue has drained a bit. 2207 */ 2208 if (!cc) { 2209 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2210 switch (sc->sc_type) { 2211 case COM_TYPE_PXA2x0: 2212 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2213 break; 2214 case COM_TYPE_INGENIC: 2215 case COM_TYPE_TEGRA: 2216 CLR(sc->sc_ier, 2217 IER_ERXRDY | IER_ERXTOUT); 2218 break; 2219 default: 2220 CLR(sc->sc_ier, IER_ERXRDY); 2221 break; 2222 } 2223 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2224 } 2225 } else { 2226 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2227 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2228 continue; 2229 } 2230 } 2231 2232 msr = CSR_READ_1(regsp, COM_REG_MSR); 2233 delta = msr ^ sc->sc_msr; 2234 sc->sc_msr = msr; 2235 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2236 (delta & MSR_DCD)) { 2237 mutex_spin_enter(&timecounter_lock); 2238 pps_capture(&sc->sc_pps_state); 2239 pps_event(&sc->sc_pps_state, 2240 (msr & MSR_DCD) ? 2241 PPS_CAPTUREASSERT : 2242 PPS_CAPTURECLEAR); 2243 mutex_spin_exit(&timecounter_lock); 2244 } 2245 2246 /* 2247 * Process normal status changes 2248 */ 2249 if (ISSET(delta, sc->sc_msr_mask)) { 2250 SET(sc->sc_msr_delta, delta); 2251 2252 /* 2253 * Stop output immediately if we lose the output 2254 * flow control signal or carrier detect. 2255 */ 2256 if (ISSET(~msr, sc->sc_msr_mask)) { 2257 sc->sc_tbc = 0; 2258 sc->sc_heldtbc = 0; 2259 #ifdef COM_DEBUG 2260 if (com_debug) 2261 comstatus(sc, "comintr "); 2262 #endif 2263 } 2264 2265 sc->sc_st_check = 1; 2266 } 2267 } while (!ISSET((iir = 2268 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2269 /* 2270 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2271 * by IIR read, so we can't do this way: `process all interrupts, 2272 * then do TX if possible'. 2273 */ 2274 (iir & IIR_IMASK) != IIR_TXRDY); 2275 2276 /* 2277 * Read LSR again, since there may be an interrupt between 2278 * the last LSR read and IIR read above. 2279 */ 2280 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2281 2282 /* 2283 * See if data can be transmitted as well. 2284 * Schedule tx done event if no data left 2285 * and tty was marked busy. 2286 */ 2287 if (ISSET(lsr, LSR_TXRDY)) { 2288 /* 2289 * If we've delayed a parameter change, do it now, and restart 2290 * output. 2291 */ 2292 if (sc->sc_heldchange) { 2293 com_loadchannelregs(sc); 2294 sc->sc_heldchange = 0; 2295 sc->sc_tbc = sc->sc_heldtbc; 2296 sc->sc_heldtbc = 0; 2297 } 2298 2299 /* Output the next chunk of the contiguous buffer, if any. */ 2300 if (sc->sc_tbc > 0) { 2301 u_int n; 2302 2303 n = sc->sc_tbc; 2304 if (n > sc->sc_fifolen) 2305 n = sc->sc_fifolen; 2306 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2307 sc->sc_tbc -= n; 2308 sc->sc_tba += n; 2309 } else { 2310 /* Disable transmit completion interrupts if necessary. */ 2311 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2312 CLR(sc->sc_ier, IER_ETXRDY); 2313 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2314 } 2315 if (sc->sc_tx_busy) { 2316 sc->sc_tx_busy = 0; 2317 sc->sc_tx_done = 1; 2318 } 2319 } 2320 } 2321 2322 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2323 goto again; 2324 2325 mutex_spin_exit(&sc->sc_lock); 2326 2327 /* Wake up the poller. */ 2328 softint_schedule(sc->sc_si); 2329 2330 #ifdef RND_COM 2331 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2332 #endif 2333 2334 return (1); 2335 } 2336 2337 /* 2338 * The following functions are polled getc and putc routines, shared 2339 * by the console and kgdb glue. 2340 * 2341 * The read-ahead code is so that you can detect pending in-band 2342 * cn_magic in polled mode while doing output rather than having to 2343 * wait until the kernel decides it needs input. 2344 */ 2345 2346 #define MAX_READAHEAD 20 2347 static int com_readahead[MAX_READAHEAD]; 2348 static int com_readaheadcount = 0; 2349 2350 int 2351 com_common_getc(dev_t dev, struct com_regs *regsp) 2352 { 2353 int s = splserial(); 2354 u_char stat, c; 2355 2356 /* got a character from reading things earlier */ 2357 if (com_readaheadcount > 0) { 2358 int i; 2359 2360 c = com_readahead[0]; 2361 for (i = 1; i < com_readaheadcount; i++) { 2362 com_readahead[i-1] = com_readahead[i]; 2363 } 2364 com_readaheadcount--; 2365 splx(s); 2366 return (c); 2367 } 2368 2369 /* don't block until a character becomes available */ 2370 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2371 splx(s); 2372 return -1; 2373 } 2374 2375 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2376 stat = CSR_READ_1(regsp, COM_REG_IIR); 2377 { 2378 int cn_trapped = 0; /* required by cn_trap, see above */ 2379 #ifdef DDB 2380 extern int db_active; 2381 if (!db_active) 2382 #endif 2383 cn_check_magic(dev, c, com_cnm_state); 2384 } 2385 splx(s); 2386 return (c); 2387 } 2388 2389 static void 2390 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2391 { 2392 int s = splserial(); 2393 int cin, stat, timo; 2394 2395 if (com_readaheadcount < MAX_READAHEAD 2396 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2397 int cn_trapped = 0; 2398 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2399 stat = CSR_READ_1(regsp, COM_REG_IIR); 2400 cn_check_magic(dev, cin, com_cnm_state); 2401 com_readahead[com_readaheadcount++] = cin; 2402 } 2403 2404 /* wait for any pending transmission to finish */ 2405 timo = 150000; 2406 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2407 continue; 2408 2409 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2410 COM_BARRIER(regsp, BR | BW); 2411 2412 splx(s); 2413 } 2414 2415 /* 2416 * Initialize UART for use as console or KGDB line. 2417 */ 2418 int 2419 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2420 tcflag_t cflag) 2421 { 2422 2423 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2424 ®sp->cr_ioh)) 2425 return (ENOMEM); /* ??? */ 2426 2427 if (type == COM_TYPE_OMAP) { 2428 /* disable before changing settings */ 2429 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2430 } 2431 2432 rate = comspeed(rate, frequency, type); 2433 if (__predict_true(rate != -1)) { 2434 if (type == COM_TYPE_AU1x00) { 2435 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2436 } else { 2437 /* no EFR on alchemy */ 2438 if ((type != COM_TYPE_16550_NOERS) && 2439 (type != COM_TYPE_INGENIC)) { 2440 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2441 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2442 } 2443 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2444 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2445 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2446 } 2447 } 2448 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2449 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2450 2451 if (type == COM_TYPE_INGENIC) { 2452 CSR_WRITE_1(regsp, COM_REG_FIFO, 2453 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2454 FIFO_TRIGGER_1 | FIFO_UART_ON); 2455 } else { 2456 CSR_WRITE_1(regsp, COM_REG_FIFO, 2457 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2458 FIFO_TRIGGER_1); 2459 } 2460 2461 if (type == COM_TYPE_OMAP) { 2462 /* setup the fifos. the FCR value is not used as long 2463 as SCR[6] and SCR[7] are 0, which they are at reset 2464 and we never touch the SCR register */ 2465 uint8_t rx_fifo_trig = 40; 2466 uint8_t tx_fifo_trig = 60; 2467 uint8_t rx_start = 8; 2468 uint8_t rx_halt = 60; 2469 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2470 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2471 2472 /* enable access to TCR & TLR */ 2473 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2474 2475 /* write tcr and tlr values */ 2476 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2477 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2478 2479 /* disable access to TCR & TLR */ 2480 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2481 2482 /* enable again, but mode is based on speed */ 2483 if (rate > 230400) { 2484 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2485 } else { 2486 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2487 } 2488 } 2489 2490 if (type == COM_TYPE_PXA2x0) 2491 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2492 else 2493 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2494 2495 return (0); 2496 } 2497 2498 int 2499 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2500 tcflag_t cflag) 2501 { 2502 int res; 2503 2504 comcons_info.regs = *regsp; 2505 2506 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2507 if (res) 2508 return (res); 2509 2510 cn_tab = &comcons; 2511 cn_init_magic(&com_cnm_state); 2512 cn_set_magic("\047\001"); /* default magic is BREAK */ 2513 2514 comcons_info.frequency = frequency; 2515 comcons_info.type = type; 2516 comcons_info.rate = rate; 2517 comcons_info.cflag = cflag; 2518 2519 return (0); 2520 } 2521 2522 int 2523 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2524 int type, tcflag_t cflag) 2525 { 2526 struct com_regs regs; 2527 2528 /*XXX*/ 2529 bus_space_handle_t dummy_bsh; 2530 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2531 2532 /* 2533 * dummy_bsh required because com_init_regs() wants it. A 2534 * real bus_space_handle will be filled in by cominit() later. 2535 * XXXJRT Detangle this mess eventually, plz. 2536 */ 2537 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2538 2539 return comcnattach1(®s, rate, frequency, type, cflag); 2540 } 2541 2542 static int 2543 comcnreattach(void) 2544 { 2545 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2546 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2547 } 2548 2549 int 2550 comcngetc(dev_t dev) 2551 { 2552 2553 return (com_common_getc(dev, &comcons_info.regs)); 2554 } 2555 2556 /* 2557 * Console kernel output character routine. 2558 */ 2559 void 2560 comcnputc(dev_t dev, int c) 2561 { 2562 2563 com_common_putc(dev, &comcons_info.regs, c); 2564 } 2565 2566 void 2567 comcnpollc(dev_t dev, int on) 2568 { 2569 2570 com_readaheadcount = 0; 2571 } 2572 2573 #ifdef KGDB 2574 int 2575 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2576 tcflag_t cflag) 2577 { 2578 int res; 2579 2580 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2581 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2582 #if !defined(DDB) 2583 return (EBUSY); /* cannot share with console */ 2584 #else 2585 comkgdbregs = *regsp; 2586 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2587 #endif 2588 } else { 2589 comkgdbregs = *regsp; 2590 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2591 if (res) 2592 return (res); 2593 2594 /* 2595 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2596 * expects this to be initialized 2597 */ 2598 cn_init_magic(&com_cnm_state); 2599 cn_set_magic("\047\001"); 2600 } 2601 2602 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2603 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2604 2605 return (0); 2606 } 2607 2608 int 2609 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2610 int frequency, int type, tcflag_t cflag) 2611 { 2612 struct com_regs regs; 2613 2614 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2615 2616 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2617 } 2618 2619 /* ARGSUSED */ 2620 int 2621 com_kgdb_getc(void *arg) 2622 { 2623 2624 return (com_common_getc(NODEV, &comkgdbregs)); 2625 } 2626 2627 /* ARGSUSED */ 2628 void 2629 com_kgdb_putc(void *arg, int c) 2630 { 2631 2632 com_common_putc(NODEV, &comkgdbregs, c); 2633 } 2634 #endif /* KGDB */ 2635 2636 /* helper function to identify the com ports used by 2637 console or KGDB (and not yet autoconf attached) */ 2638 int 2639 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2640 { 2641 bus_space_handle_t help; 2642 2643 if (!comconsattached && 2644 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2645 iobase == comcons_info.regs.cr_iobase) 2646 help = comcons_info.regs.cr_ioh; 2647 #ifdef KGDB 2648 else if (!com_kgdb_attached && 2649 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2650 iobase == comkgdbregs.cr_iobase) 2651 help = comkgdbregs.cr_ioh; 2652 #endif 2653 else 2654 return (0); 2655 2656 if (ioh) 2657 *ioh = help; 2658 return (1); 2659 } 2660 2661 /* 2662 * this routine exists to serve as a shutdown hook for systems that 2663 * have firmware which doesn't interact properly with a com device in 2664 * FIFO mode. 2665 */ 2666 bool 2667 com_cleanup(device_t self, int how) 2668 { 2669 struct com_softc *sc = device_private(self); 2670 2671 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2672 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2673 2674 return true; 2675 } 2676 2677 bool 2678 com_suspend(device_t self, const pmf_qual_t *qual) 2679 { 2680 struct com_softc *sc = device_private(self); 2681 2682 #if 0 2683 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2684 cn_tab = &comcons_suspend; 2685 #endif 2686 2687 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2688 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2689 2690 return true; 2691 } 2692 2693 bool 2694 com_resume(device_t self, const pmf_qual_t *qual) 2695 { 2696 struct com_softc *sc = device_private(self); 2697 2698 mutex_spin_enter(&sc->sc_lock); 2699 com_loadchannelregs(sc); 2700 mutex_spin_exit(&sc->sc_lock); 2701 2702 return true; 2703 } 2704
Indexes created Sat Sep 27 14:09:57 GMT 2025