com.c revision 1.356
1 /* $NetBSD: com.c,v 1.356 2019/11/10 21:16:35 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.356 2019/11/10 21:16:35 chs Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #define CSR_WRITE_1(r, o, v) \ 132 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 133 #define CSR_READ_1(r, o) \ 134 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 135 #define CSR_WRITE_2(r, o, v) \ 136 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 137 #define CSR_READ_2(r, o) \ 138 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 139 #define CSR_WRITE_MULTI(r, o, p, n) \ 140 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 141 142 143 static void com_enable_debugport(struct com_softc *); 144 145 void com_config(struct com_softc *); 146 void com_shutdown(struct com_softc *); 147 int comspeed(long, long, int); 148 static u_char cflag2lcr(tcflag_t); 149 int comparam(struct tty *, struct termios *); 150 void comstart(struct tty *); 151 int comhwiflow(struct tty *, int); 152 153 void com_loadchannelregs(struct com_softc *); 154 void com_hwiflow(struct com_softc *); 155 void com_break(struct com_softc *, int); 156 void com_modem(struct com_softc *, int); 157 void tiocm_to_com(struct com_softc *, u_long, int); 158 int com_to_tiocm(struct com_softc *); 159 void com_iflush(struct com_softc *); 160 161 int com_common_getc(dev_t, struct com_regs *); 162 static void com_common_putc(dev_t, struct com_regs *, int); 163 164 int cominit(struct com_regs *, int, int, int, tcflag_t); 165 166 static int comcnreattach(void); 167 168 int comcngetc(dev_t); 169 void comcnputc(dev_t, int); 170 void comcnpollc(dev_t, int); 171 172 #define integrate static inline 173 void comsoft(void *); 174 integrate void com_rxsoft(struct com_softc *, struct tty *); 175 integrate void com_txsoft(struct com_softc *, struct tty *); 176 integrate void com_stsoft(struct com_softc *, struct tty *); 177 integrate void com_schedrx(struct com_softc *); 178 void comdiag(void *); 179 180 dev_type_open(comopen); 181 dev_type_close(comclose); 182 dev_type_read(comread); 183 dev_type_write(comwrite); 184 dev_type_ioctl(comioctl); 185 dev_type_stop(comstop); 186 dev_type_tty(comtty); 187 dev_type_poll(compoll); 188 189 static struct comcons_info comcons_info; 190 191 /* 192 * Following are all routines needed for COM to act as console 193 */ 194 static struct consdev comcons = { 195 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL, 196 NODEV, CN_NORMAL 197 }; 198 199 200 const struct cdevsw com_cdevsw = { 201 .d_open = comopen, 202 .d_close = comclose, 203 .d_read = comread, 204 .d_write = comwrite, 205 .d_ioctl = comioctl, 206 .d_stop = comstop, 207 .d_tty = comtty, 208 .d_poll = compoll, 209 .d_mmap = nommap, 210 .d_kqfilter = ttykqfilter, 211 .d_discard = nodiscard, 212 .d_flag = D_TTY 213 }; 214 215 /* 216 * Make this an option variable one can patch. 217 * But be warned: this must be a power of 2! 218 */ 219 u_int com_rbuf_size = COM_RING_SIZE; 220 221 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 222 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 223 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 224 225 static int comconsattached; 226 static struct cnm_state com_cnm_state; 227 228 #ifdef KGDB 229 #include <sys/kgdb.h> 230 231 static struct com_regs comkgdbregs; 232 static int com_kgdb_attached; 233 234 int com_kgdb_getc(void *); 235 void com_kgdb_putc(void *, int); 236 #endif /* KGDB */ 237 238 /* initializer for typical 16550-ish hardware */ 239 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 240 [COM_REG_RXDATA] = com_data, 241 [COM_REG_TXDATA] = com_data, 242 [COM_REG_DLBL] = com_dlbl, 243 [COM_REG_DLBH] = com_dlbh, 244 [COM_REG_IER] = com_ier, 245 [COM_REG_IIR] = com_iir, 246 [COM_REG_FIFO] = com_fifo, 247 [COM_REG_TCR] = com_fifo, 248 [COM_REG_EFR] = com_efr, 249 [COM_REG_TLR] = com_efr, 250 [COM_REG_LCR] = com_lcr, 251 [COM_REG_MCR] = com_mcr, 252 [COM_REG_LSR] = com_lsr, 253 [COM_REG_MSR] = com_msr, 254 [COM_REG_USR] = com_usr, 255 [COM_REG_TFL] = com_tfl, 256 [COM_REG_RFL] = com_rfl, 257 [COM_REG_HALT] = com_halt, 258 [COM_REG_MDR1] = com_mdr1, 259 }; 260 261 #define COMDIALOUT_MASK TTDIALOUT_MASK 262 263 #define COMUNIT(x) TTUNIT(x) 264 #define COMDIALOUT(x) TTDIALOUT(x) 265 266 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 267 device_is_active((sc)->sc_dev)) 268 269 #define BR BUS_SPACE_BARRIER_READ 270 #define BW BUS_SPACE_BARRIER_WRITE 271 #define COM_BARRIER(r, f) \ 272 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 273 274 /* 275 * com_init_regs -- 276 * Driver front-ends use this to initialize our register map 277 * in the standard fashion. They may then tailor the map to 278 * their own particular requirements. 279 */ 280 void 281 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 282 bus_addr_t addr) 283 { 284 285 memset(regs, 0, sizeof(*regs)); 286 regs->cr_iot = st; 287 regs->cr_ioh = sh; 288 regs->cr_iobase = addr; 289 regs->cr_nports = COM_NPORTS; 290 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 291 } 292 293 /* 294 * com_init_regs_stride -- 295 * Convenience function for front-ends that have a stride between 296 * registers. 297 */ 298 void 299 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 300 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 301 { 302 303 com_init_regs(regs, st, sh, addr); 304 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 305 regs->cr_map[i] <<= regshift; 306 } 307 regs->cr_nports <<= regshift; 308 } 309 310 /*ARGSUSED*/ 311 int 312 comspeed(long speed, long frequency, int type) 313 { 314 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 315 316 int x, err; 317 int divisor = 16; 318 319 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 320 divisor = 13; 321 } 322 323 if (speed == 0) 324 return (0); 325 if (speed < 0) 326 return (-1); 327 x = divrnd(frequency / divisor, speed); 328 if (x <= 0) 329 return (-1); 330 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 331 if (err < 0) 332 err = -err; 333 if (err > COM_TOLERANCE) 334 return (-1); 335 return (x); 336 337 #undef divrnd 338 } 339 340 #ifdef COM_DEBUG 341 int com_debug = 0; 342 343 void comstatus(struct com_softc *, const char *); 344 void 345 comstatus(struct com_softc *sc, const char *str) 346 { 347 struct tty *tp = sc->sc_tty; 348 349 aprint_normal_dev(sc->sc_dev, 350 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 351 str, 352 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 353 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 354 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 355 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 356 sc->sc_tx_stopped ? '+' : '-'); 357 358 aprint_normal_dev(sc->sc_dev, 359 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 360 str, 361 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 362 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 363 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 364 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 365 sc->sc_rx_flags); 366 } 367 #endif 368 369 int 370 com_probe_subr(struct com_regs *regs) 371 { 372 373 /* force access to id reg */ 374 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 375 CSR_WRITE_1(regs, COM_REG_IIR, 0); 376 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 377 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 378 return (0); 379 380 return (1); 381 } 382 383 int 384 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 385 { 386 struct com_regs regs; 387 388 com_init_regs(®s, iot, ioh, 0/*XXX*/); 389 390 return com_probe_subr(®s); 391 } 392 393 /* 394 * No locking in this routine; it is only called during attach, 395 * or with the port already locked. 396 */ 397 static void 398 com_enable_debugport(struct com_softc *sc) 399 { 400 401 /* Turn on line break interrupt, set carrier. */ 402 sc->sc_ier = IER_ERLS; 403 if (sc->sc_type == COM_TYPE_PXA2x0) 404 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 405 if (sc->sc_type == COM_TYPE_INGENIC || 406 sc->sc_type == COM_TYPE_TEGRA) 407 sc->sc_ier |= IER_ERXTOUT; 408 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 409 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 410 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 411 } 412 413 static void 414 com_intr_poll(void *arg) 415 { 416 struct com_softc * const sc = arg; 417 418 comintr(sc); 419 420 callout_schedule(&sc->sc_poll_callout, 1); 421 } 422 423 void 424 com_attach_subr(struct com_softc *sc) 425 { 426 struct com_regs *regsp = &sc->sc_regs; 427 struct tty *tp; 428 u_int8_t lcr; 429 const char *fifo_msg = NULL; 430 prop_dictionary_t dict; 431 bool is_console = true; 432 bool force_console = false; 433 434 aprint_naive("\n"); 435 436 dict = device_properties(sc->sc_dev); 437 prop_dictionary_get_bool(dict, "is_console", &is_console); 438 prop_dictionary_get_bool(dict, "force_console", &force_console); 439 callout_init(&sc->sc_diag_callout, 0); 440 callout_init(&sc->sc_poll_callout, 0); 441 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 442 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 443 444 #if defined(COM_16650) 445 sc->sc_type = COM_TYPE_16650; 446 #elif defined(COM_16750) 447 sc->sc_type = COM_TYPE_16750; 448 #elif defined(COM_HAYESP) 449 sc->sc_type = COM_TYPE_HAYESP; 450 #elif defined(COM_PXA2X0) 451 sc->sc_type = COM_TYPE_PXA2x0; 452 #endif 453 454 /* Disable interrupts before configuring the device. */ 455 if (sc->sc_type == COM_TYPE_PXA2x0) 456 sc->sc_ier = IER_EUART; 457 else 458 sc->sc_ier = 0; 459 460 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 461 462 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 463 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 464 comconsattached = 1; 465 466 if (force_console) 467 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 468 469 if (cn_tab == NULL && comcnreattach() != 0) { 470 printf("can't re-init serial console @%lx\n", 471 (u_long)comcons_info.regs.cr_iobase); 472 } 473 474 switch (sc->sc_type) { 475 case COM_TYPE_16750: 476 case COM_TYPE_DW_APB: 477 /* Use in comintr(). */ 478 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 479 break; 480 } 481 482 /* Make sure the console is always "hardwired". */ 483 delay(10000); /* wait for output to finish */ 484 if (is_console) { 485 SET(sc->sc_hwflags, COM_HW_CONSOLE); 486 } 487 488 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 489 } 490 491 /* Probe for FIFO */ 492 switch (sc->sc_type) { 493 case COM_TYPE_HAYESP: 494 goto fifodone; 495 496 case COM_TYPE_AU1x00: 497 sc->sc_fifolen = 16; 498 fifo_msg = "Au1X00 UART, working fifo"; 499 SET(sc->sc_hwflags, COM_HW_FIFO); 500 goto fifodelay; 501 502 case COM_TYPE_16550_NOERS: 503 sc->sc_fifolen = 16; 504 fifo_msg = "ns16650, no ERS, working fifo"; 505 SET(sc->sc_hwflags, COM_HW_FIFO); 506 goto fifodelay; 507 508 case COM_TYPE_OMAP: 509 sc->sc_fifolen = 64; 510 fifo_msg = "OMAP UART, working fifo"; 511 SET(sc->sc_hwflags, COM_HW_FIFO); 512 goto fifodelay; 513 514 case COM_TYPE_INGENIC: 515 sc->sc_fifolen = 16; 516 fifo_msg = "Ingenic UART, working fifo"; 517 SET(sc->sc_hwflags, COM_HW_FIFO); 518 SET(sc->sc_hwflags, COM_HW_NOIEN); 519 goto fifodelay; 520 521 case COM_TYPE_TEGRA: 522 sc->sc_fifolen = 8; 523 fifo_msg = "Tegra UART, working fifo"; 524 SET(sc->sc_hwflags, COM_HW_FIFO); 525 CSR_WRITE_1(regsp, COM_REG_FIFO, 526 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 527 goto fifodelay; 528 529 case COM_TYPE_BCMAUXUART: 530 sc->sc_fifolen = 1; 531 fifo_msg = "BCM AUX UART, working fifo"; 532 SET(sc->sc_hwflags, COM_HW_FIFO); 533 CSR_WRITE_1(regsp, COM_REG_FIFO, 534 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 535 goto fifodelay; 536 } 537 538 sc->sc_fifolen = 1; 539 /* look for a NS 16550AF UART with FIFOs */ 540 if (sc->sc_type == COM_TYPE_INGENIC) { 541 CSR_WRITE_1(regsp, COM_REG_FIFO, 542 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 543 FIFO_TRIGGER_14 | FIFO_UART_ON); 544 } else 545 CSR_WRITE_1(regsp, COM_REG_FIFO, 546 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 547 delay(100); 548 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 549 == IIR_FIFO_MASK) 550 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 551 == FIFO_TRIGGER_14) { 552 SET(sc->sc_hwflags, COM_HW_FIFO); 553 554 fifo_msg = "ns16550a, working fifo"; 555 556 /* 557 * IIR changes into the EFR if LCR is set to LCR_EERS 558 * on 16650s. We also know IIR != 0 at this point. 559 * Write 0 into the EFR, and read it. If the result 560 * is 0, we have a 16650. 561 * 562 * Older 16650s were broken; the test to detect them 563 * is taken from the Linux driver. Apparently 564 * setting DLAB enable gives access to the EFR on 565 * these chips. 566 */ 567 if (sc->sc_type == COM_TYPE_16650) { 568 lcr = CSR_READ_1(regsp, COM_REG_LCR); 569 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 570 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 571 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 572 CSR_WRITE_1(regsp, COM_REG_LCR, 573 lcr | LCR_DLAB); 574 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 575 CLR(sc->sc_hwflags, COM_HW_FIFO); 576 sc->sc_fifolen = 0; 577 } else { 578 SET(sc->sc_hwflags, COM_HW_FLOW); 579 sc->sc_fifolen = 32; 580 } 581 } else 582 sc->sc_fifolen = 16; 583 584 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 585 if (sc->sc_fifolen == 0) 586 fifo_msg = "st16650, broken fifo"; 587 else if (sc->sc_fifolen == 32) 588 fifo_msg = "st16650a, working fifo"; 589 else 590 fifo_msg = "ns16550a, working fifo"; 591 } 592 593 /* 594 * TL16C750 can enable 64byte FIFO, only when DLAB 595 * is 1. However, some 16750 may always enable. For 596 * example, restrictions according to DLAB in a data 597 * sheet for SC16C750 were not described. 598 * Please enable 'options COM_16650', supposing you 599 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 600 * should become effective. 601 */ 602 if (sc->sc_type == COM_TYPE_16750) { 603 uint8_t iir1, iir2; 604 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 605 606 lcr = CSR_READ_1(regsp, COM_REG_LCR); 607 CSR_WRITE_1(regsp, COM_REG_LCR, 608 lcr & ~LCR_DLAB); 609 CSR_WRITE_1(regsp, COM_REG_FIFO, 610 fcr | FIFO_64B_ENABLE); 611 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 612 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 613 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 614 CSR_WRITE_1(regsp, COM_REG_FIFO, 615 fcr | FIFO_64B_ENABLE); 616 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 617 618 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 619 620 if (!ISSET(iir1, IIR_64B_FIFO) && 621 ISSET(iir2, IIR_64B_FIFO)) { 622 /* It is TL16C750. */ 623 sc->sc_fifolen = 64; 624 SET(sc->sc_hwflags, COM_HW_AFE); 625 } else 626 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 627 628 if (sc->sc_fifolen == 64) 629 fifo_msg = "tl16c750, working fifo"; 630 else 631 fifo_msg = "ns16750, working fifo"; 632 } 633 } else 634 fifo_msg = "ns16550, broken fifo"; 635 else 636 fifo_msg = "ns8250 or ns16450, no fifo"; 637 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 638 639 fifodelay: 640 /* 641 * Some chips will clear down both Tx and Rx FIFOs when zero is 642 * written to com_fifo. If this chip is the console, writing zero 643 * results in some of the chip/FIFO description being lost, so delay 644 * printing it until now. 645 */ 646 delay(10); 647 aprint_normal(": %s\n", fifo_msg); 648 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 649 sc->sc_fifolen = 1; 650 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 651 } 652 653 fifodone: 654 655 tp = tty_alloc(); 656 tp->t_oproc = comstart; 657 tp->t_param = comparam; 658 tp->t_hwiflow = comhwiflow; 659 tp->t_softc = sc; 660 661 sc->sc_tty = tp; 662 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK); 663 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 664 sc->sc_rbavail = com_rbuf_size; 665 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 666 667 tty_attach(tp); 668 669 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 670 SET(sc->sc_mcr, MCR_IENABLE); 671 672 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 673 int maj; 674 675 /* locate the major number */ 676 maj = cdevsw_lookup_major(&com_cdevsw); 677 678 tp->t_dev = cn_tab->cn_dev = makedev(maj, 679 device_unit(sc->sc_dev)); 680 681 aprint_normal_dev(sc->sc_dev, "console\n"); 682 } 683 684 #ifdef KGDB 685 /* 686 * Allow kgdb to "take over" this port. If this is 687 * not the console and is the kgdb device, it has 688 * exclusive use. If it's the console _and_ the 689 * kgdb device, it doesn't. 690 */ 691 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 692 regsp->cr_iobase == comkgdbregs.cr_iobase) { 693 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 694 com_kgdb_attached = 1; 695 696 SET(sc->sc_hwflags, COM_HW_KGDB); 697 } 698 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 699 } 700 #endif 701 702 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 703 704 #ifdef RND_COM 705 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 706 RND_TYPE_TTY, RND_FLAG_DEFAULT); 707 #endif 708 709 /* if there are no enable/disable functions, assume the device 710 is always enabled */ 711 if (!sc->enable) 712 sc->enabled = 1; 713 714 com_config(sc); 715 716 SET(sc->sc_hwflags, COM_HW_DEV_OK); 717 718 if (ISSET(sc->sc_hwflags, COM_HW_POLL)) 719 callout_schedule(&sc->sc_poll_callout, 1); 720 } 721 722 void 723 com_config(struct com_softc *sc) 724 { 725 struct com_regs *regsp = &sc->sc_regs; 726 727 /* Disable interrupts before configuring the device. */ 728 if (sc->sc_type == COM_TYPE_PXA2x0) 729 sc->sc_ier = IER_EUART; 730 else 731 sc->sc_ier = 0; 732 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 733 (void) CSR_READ_1(regsp, COM_REG_IIR); 734 735 /* Look for a Hayes ESP board. */ 736 if (sc->sc_type == COM_TYPE_HAYESP) { 737 738 /* Set 16550 compatibility mode */ 739 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 740 HAYESP_SETMODE); 741 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 742 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 743 HAYESP_MODE_SCALE); 744 745 /* Set RTS/CTS flow control */ 746 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 747 HAYESP_SETFLOWTYPE); 748 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 749 HAYESP_FLOW_RTS); 750 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 751 HAYESP_FLOW_CTS); 752 753 /* Set flow control levels */ 754 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 755 HAYESP_SETRXFLOW); 756 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 757 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 758 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 759 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 760 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 761 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 762 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 763 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 764 } 765 766 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 767 com_enable_debugport(sc); 768 } 769 770 #if 0 771 static int 772 comcngetc_detached(dev_t dev) 773 { 774 return 0; 775 } 776 777 static void 778 comcnputc_detached(dev_t dev, int c) 779 { 780 } 781 #endif 782 783 int 784 com_detach(device_t self, int flags) 785 { 786 struct com_softc *sc = device_private(self); 787 int maj, mn; 788 789 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 790 return EBUSY; 791 792 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 793 (flags & DETACH_SHUTDOWN) != 0) 794 return EBUSY; 795 796 if (sc->disable != NULL && sc->enabled != 0) { 797 (*sc->disable)(sc); 798 sc->enabled = 0; 799 } 800 801 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 802 comconsattached = 0; 803 cn_tab = NULL; 804 } 805 806 /* locate the major number */ 807 maj = cdevsw_lookup_major(&com_cdevsw); 808 809 /* Nuke the vnodes for any open instances. */ 810 mn = device_unit(self); 811 vdevgone(maj, mn, mn, VCHR); 812 813 mn |= COMDIALOUT_MASK; 814 vdevgone(maj, mn, mn, VCHR); 815 816 if (sc->sc_rbuf == NULL) { 817 /* 818 * Ring buffer allocation failed in the com_attach_subr, 819 * only the tty is allocated, and nothing else. 820 */ 821 tty_free(sc->sc_tty); 822 return 0; 823 } 824 825 /* Free the receive buffer. */ 826 free(sc->sc_rbuf, M_DEVBUF); 827 828 /* Detach and free the tty. */ 829 tty_detach(sc->sc_tty); 830 tty_free(sc->sc_tty); 831 832 /* Unhook the soft interrupt handler. */ 833 softint_disestablish(sc->sc_si); 834 835 #ifdef RND_COM 836 /* Unhook the entropy source. */ 837 rnd_detach_source(&sc->rnd_source); 838 #endif 839 callout_destroy(&sc->sc_diag_callout); 840 841 /* Destroy the lock. */ 842 mutex_destroy(&sc->sc_lock); 843 844 return (0); 845 } 846 847 void 848 com_shutdown(struct com_softc *sc) 849 { 850 struct tty *tp = sc->sc_tty; 851 852 mutex_spin_enter(&sc->sc_lock); 853 854 /* If we were asserting flow control, then deassert it. */ 855 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 856 com_hwiflow(sc); 857 858 /* Clear any break condition set with TIOCSBRK. */ 859 com_break(sc, 0); 860 861 /* 862 * Hang up if necessary. Wait a bit, so the other side has time to 863 * notice even if we immediately open the port again. 864 * Avoid tsleeping above splhigh(). 865 */ 866 if (ISSET(tp->t_cflag, HUPCL)) { 867 com_modem(sc, 0); 868 mutex_spin_exit(&sc->sc_lock); 869 /* XXX will only timeout */ 870 (void) kpause(ttclos, false, hz, NULL); 871 mutex_spin_enter(&sc->sc_lock); 872 } 873 874 /* Turn off interrupts. */ 875 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 876 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 877 if ((sc->sc_type == COM_TYPE_PXA2x0) || 878 (sc->sc_type == COM_TYPE_INGENIC) || 879 (sc->sc_type == COM_TYPE_TEGRA)) 880 sc->sc_ier |= IER_ERXTOUT; 881 } else 882 sc->sc_ier = 0; 883 884 if (sc->sc_type == COM_TYPE_PXA2x0) 885 sc->sc_ier |= IER_EUART; 886 887 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 888 889 mutex_spin_exit(&sc->sc_lock); 890 891 if (sc->disable) { 892 #ifdef DIAGNOSTIC 893 if (!sc->enabled) 894 panic("com_shutdown: not enabled?"); 895 #endif 896 (*sc->disable)(sc); 897 sc->enabled = 0; 898 } 899 } 900 901 int 902 comopen(dev_t dev, int flag, int mode, struct lwp *l) 903 { 904 struct com_softc *sc; 905 struct tty *tp; 906 int s; 907 int error; 908 909 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 910 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 911 sc->sc_rbuf == NULL) 912 return (ENXIO); 913 914 if (!device_is_active(sc->sc_dev)) 915 return (ENXIO); 916 917 #ifdef KGDB 918 /* 919 * If this is the kgdb port, no other use is permitted. 920 */ 921 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 922 return (EBUSY); 923 #endif 924 925 tp = sc->sc_tty; 926 927 /* 928 * If the device is exclusively for kernel use, deny userland 929 * open. 930 */ 931 if (ISSET(tp->t_state, TS_KERN_ONLY)) 932 return (EBUSY); 933 934 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 935 return (EBUSY); 936 937 s = spltty(); 938 939 /* 940 * Do the following iff this is a first open. 941 */ 942 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 943 struct termios t; 944 945 tp->t_dev = dev; 946 947 if (sc->enable) { 948 if ((*sc->enable)(sc)) { 949 splx(s); 950 aprint_error_dev(sc->sc_dev, 951 "device enable failed\n"); 952 return (EIO); 953 } 954 mutex_spin_enter(&sc->sc_lock); 955 sc->enabled = 1; 956 com_config(sc); 957 } else { 958 mutex_spin_enter(&sc->sc_lock); 959 } 960 961 /* Turn on interrupts. */ 962 sc->sc_ier = IER_ERXRDY | IER_ERLS; 963 if (!ISSET(tp->t_cflag, CLOCAL)) 964 sc->sc_ier |= IER_EMSC; 965 966 if (sc->sc_type == COM_TYPE_PXA2x0) 967 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 968 else if (sc->sc_type == COM_TYPE_INGENIC || 969 sc->sc_type == COM_TYPE_TEGRA) 970 sc->sc_ier |= IER_ERXTOUT; 971 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 972 973 /* Fetch the current modem control status, needed later. */ 974 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 975 976 /* Clear PPS capture state on first open. */ 977 mutex_spin_enter(&timecounter_lock); 978 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 979 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 980 pps_init(&sc->sc_pps_state); 981 mutex_spin_exit(&timecounter_lock); 982 983 mutex_spin_exit(&sc->sc_lock); 984 985 /* 986 * Initialize the termios status to the defaults. Add in the 987 * sticky bits from TIOCSFLAGS. 988 */ 989 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 990 t.c_ospeed = comcons_info.rate; 991 t.c_cflag = comcons_info.cflag; 992 } else { 993 t.c_ospeed = TTYDEF_SPEED; 994 t.c_cflag = TTYDEF_CFLAG; 995 } 996 t.c_ispeed = t.c_ospeed; 997 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 998 SET(t.c_cflag, CLOCAL); 999 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1000 SET(t.c_cflag, CRTSCTS); 1001 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1002 SET(t.c_cflag, MDMBUF); 1003 /* Make sure comparam() will do something. */ 1004 tp->t_ospeed = 0; 1005 (void) comparam(tp, &t); 1006 tp->t_iflag = TTYDEF_IFLAG; 1007 tp->t_oflag = TTYDEF_OFLAG; 1008 tp->t_lflag = TTYDEF_LFLAG; 1009 ttychars(tp); 1010 ttsetwater(tp); 1011 1012 mutex_spin_enter(&sc->sc_lock); 1013 1014 /* 1015 * Turn on DTR. We must always do this, even if carrier is not 1016 * present, because otherwise we'd have to use TIOCSDTR 1017 * immediately after setting CLOCAL, which applications do not 1018 * expect. We always assert DTR while the device is open 1019 * unless explicitly requested to deassert it. 1020 */ 1021 com_modem(sc, 1); 1022 1023 /* Clear the input ring, and unblock. */ 1024 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1025 sc->sc_rbavail = com_rbuf_size; 1026 com_iflush(sc); 1027 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1028 com_hwiflow(sc); 1029 1030 #ifdef COM_DEBUG 1031 if (com_debug) 1032 comstatus(sc, "comopen "); 1033 #endif 1034 1035 mutex_spin_exit(&sc->sc_lock); 1036 } 1037 1038 splx(s); 1039 1040 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1041 if (error) 1042 goto bad; 1043 1044 error = (*tp->t_linesw->l_open)(dev, tp); 1045 if (error) 1046 goto bad; 1047 1048 return (0); 1049 1050 bad: 1051 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1052 /* 1053 * We failed to open the device, and nobody else had it opened. 1054 * Clean up the state as appropriate. 1055 */ 1056 com_shutdown(sc); 1057 } 1058 1059 return (error); 1060 } 1061 1062 int 1063 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1064 { 1065 struct com_softc *sc = 1066 device_lookup_private(&com_cd, COMUNIT(dev)); 1067 struct tty *tp = sc->sc_tty; 1068 1069 /* XXX This is for cons.c. */ 1070 if (!ISSET(tp->t_state, TS_ISOPEN)) 1071 return (0); 1072 /* 1073 * If the device is exclusively for kernel use, deny userland 1074 * close. 1075 */ 1076 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1077 return (0); 1078 1079 (*tp->t_linesw->l_close)(tp, flag); 1080 ttyclose(tp); 1081 1082 if (COM_ISALIVE(sc) == 0) 1083 return (0); 1084 1085 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1086 /* 1087 * Although we got a last close, the device may still be in 1088 * use; e.g. if this was the dialout node, and there are still 1089 * processes waiting for carrier on the non-dialout node. 1090 */ 1091 com_shutdown(sc); 1092 } 1093 1094 return (0); 1095 } 1096 1097 int 1098 comread(dev_t dev, struct uio *uio, int flag) 1099 { 1100 struct com_softc *sc = 1101 device_lookup_private(&com_cd, COMUNIT(dev)); 1102 struct tty *tp = sc->sc_tty; 1103 1104 if (COM_ISALIVE(sc) == 0) 1105 return (EIO); 1106 1107 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1108 } 1109 1110 int 1111 comwrite(dev_t dev, struct uio *uio, int flag) 1112 { 1113 struct com_softc *sc = 1114 device_lookup_private(&com_cd, COMUNIT(dev)); 1115 struct tty *tp = sc->sc_tty; 1116 1117 if (COM_ISALIVE(sc) == 0) 1118 return (EIO); 1119 1120 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1121 } 1122 1123 int 1124 compoll(dev_t dev, int events, struct lwp *l) 1125 { 1126 struct com_softc *sc = 1127 device_lookup_private(&com_cd, COMUNIT(dev)); 1128 struct tty *tp = sc->sc_tty; 1129 1130 if (COM_ISALIVE(sc) == 0) 1131 return (POLLHUP); 1132 1133 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1134 } 1135 1136 struct tty * 1137 comtty(dev_t dev) 1138 { 1139 struct com_softc *sc = 1140 device_lookup_private(&com_cd, COMUNIT(dev)); 1141 struct tty *tp = sc->sc_tty; 1142 1143 return (tp); 1144 } 1145 1146 int 1147 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1148 { 1149 struct com_softc *sc; 1150 struct tty *tp; 1151 int error; 1152 1153 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1154 if (sc == NULL) 1155 return ENXIO; 1156 if (COM_ISALIVE(sc) == 0) 1157 return (EIO); 1158 1159 tp = sc->sc_tty; 1160 1161 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1162 if (error != EPASSTHROUGH) 1163 return (error); 1164 1165 error = ttioctl(tp, cmd, data, flag, l); 1166 if (error != EPASSTHROUGH) 1167 return (error); 1168 1169 error = 0; 1170 switch (cmd) { 1171 case TIOCSFLAGS: 1172 error = kauth_authorize_device_tty(l->l_cred, 1173 KAUTH_DEVICE_TTY_PRIVSET, tp); 1174 break; 1175 default: 1176 /* nothing */ 1177 break; 1178 } 1179 if (error) { 1180 return error; 1181 } 1182 1183 mutex_spin_enter(&sc->sc_lock); 1184 1185 switch (cmd) { 1186 case TIOCSBRK: 1187 com_break(sc, 1); 1188 break; 1189 1190 case TIOCCBRK: 1191 com_break(sc, 0); 1192 break; 1193 1194 case TIOCSDTR: 1195 com_modem(sc, 1); 1196 break; 1197 1198 case TIOCCDTR: 1199 com_modem(sc, 0); 1200 break; 1201 1202 case TIOCGFLAGS: 1203 *(int *)data = sc->sc_swflags; 1204 break; 1205 1206 case TIOCSFLAGS: 1207 sc->sc_swflags = *(int *)data; 1208 break; 1209 1210 case TIOCMSET: 1211 case TIOCMBIS: 1212 case TIOCMBIC: 1213 tiocm_to_com(sc, cmd, *(int *)data); 1214 break; 1215 1216 case TIOCMGET: 1217 *(int *)data = com_to_tiocm(sc); 1218 break; 1219 1220 case PPS_IOC_CREATE: 1221 case PPS_IOC_DESTROY: 1222 case PPS_IOC_GETPARAMS: 1223 case PPS_IOC_SETPARAMS: 1224 case PPS_IOC_GETCAP: 1225 case PPS_IOC_FETCH: 1226 #ifdef PPS_SYNC 1227 case PPS_IOC_KCBIND: 1228 #endif 1229 mutex_spin_enter(&timecounter_lock); 1230 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1231 mutex_spin_exit(&timecounter_lock); 1232 break; 1233 1234 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1235 mutex_spin_enter(&timecounter_lock); 1236 #ifndef PPS_TRAILING_EDGE 1237 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1238 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1239 #else 1240 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1241 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1242 #endif 1243 mutex_spin_exit(&timecounter_lock); 1244 break; 1245 1246 default: 1247 error = EPASSTHROUGH; 1248 break; 1249 } 1250 1251 mutex_spin_exit(&sc->sc_lock); 1252 1253 #ifdef COM_DEBUG 1254 if (com_debug) 1255 comstatus(sc, "comioctl "); 1256 #endif 1257 1258 return (error); 1259 } 1260 1261 integrate void 1262 com_schedrx(struct com_softc *sc) 1263 { 1264 1265 sc->sc_rx_ready = 1; 1266 1267 /* Wake up the poller. */ 1268 softint_schedule(sc->sc_si); 1269 } 1270 1271 void 1272 com_break(struct com_softc *sc, int onoff) 1273 { 1274 1275 if (onoff) 1276 SET(sc->sc_lcr, LCR_SBREAK); 1277 else 1278 CLR(sc->sc_lcr, LCR_SBREAK); 1279 1280 if (!sc->sc_heldchange) { 1281 if (sc->sc_tx_busy) { 1282 sc->sc_heldtbc = sc->sc_tbc; 1283 sc->sc_tbc = 0; 1284 sc->sc_heldchange = 1; 1285 } else 1286 com_loadchannelregs(sc); 1287 } 1288 } 1289 1290 void 1291 com_modem(struct com_softc *sc, int onoff) 1292 { 1293 1294 if (sc->sc_mcr_dtr == 0) 1295 return; 1296 1297 if (onoff) 1298 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1299 else 1300 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1301 1302 if (!sc->sc_heldchange) { 1303 if (sc->sc_tx_busy) { 1304 sc->sc_heldtbc = sc->sc_tbc; 1305 sc->sc_tbc = 0; 1306 sc->sc_heldchange = 1; 1307 } else 1308 com_loadchannelregs(sc); 1309 } 1310 } 1311 1312 void 1313 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1314 { 1315 u_char combits; 1316 1317 combits = 0; 1318 if (ISSET(ttybits, TIOCM_DTR)) 1319 SET(combits, MCR_DTR); 1320 if (ISSET(ttybits, TIOCM_RTS)) 1321 SET(combits, MCR_RTS); 1322 1323 switch (how) { 1324 case TIOCMBIC: 1325 CLR(sc->sc_mcr, combits); 1326 break; 1327 1328 case TIOCMBIS: 1329 SET(sc->sc_mcr, combits); 1330 break; 1331 1332 case TIOCMSET: 1333 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1334 SET(sc->sc_mcr, combits); 1335 break; 1336 } 1337 1338 if (!sc->sc_heldchange) { 1339 if (sc->sc_tx_busy) { 1340 sc->sc_heldtbc = sc->sc_tbc; 1341 sc->sc_tbc = 0; 1342 sc->sc_heldchange = 1; 1343 } else 1344 com_loadchannelregs(sc); 1345 } 1346 } 1347 1348 int 1349 com_to_tiocm(struct com_softc *sc) 1350 { 1351 u_char combits; 1352 int ttybits = 0; 1353 1354 combits = sc->sc_mcr; 1355 if (ISSET(combits, MCR_DTR)) 1356 SET(ttybits, TIOCM_DTR); 1357 if (ISSET(combits, MCR_RTS)) 1358 SET(ttybits, TIOCM_RTS); 1359 1360 combits = sc->sc_msr; 1361 if (sc->sc_type == COM_TYPE_INGENIC) { 1362 SET(ttybits, TIOCM_CD); 1363 } else { 1364 if (ISSET(combits, MSR_DCD)) 1365 SET(ttybits, TIOCM_CD); 1366 } 1367 if (ISSET(combits, MSR_CTS)) 1368 SET(ttybits, TIOCM_CTS); 1369 if (ISSET(combits, MSR_DSR)) 1370 SET(ttybits, TIOCM_DSR); 1371 if (ISSET(combits, MSR_RI | MSR_TERI)) 1372 SET(ttybits, TIOCM_RI); 1373 1374 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1375 SET(ttybits, TIOCM_LE); 1376 1377 return (ttybits); 1378 } 1379 1380 static u_char 1381 cflag2lcr(tcflag_t cflag) 1382 { 1383 u_char lcr = 0; 1384 1385 switch (ISSET(cflag, CSIZE)) { 1386 case CS5: 1387 SET(lcr, LCR_5BITS); 1388 break; 1389 case CS6: 1390 SET(lcr, LCR_6BITS); 1391 break; 1392 case CS7: 1393 SET(lcr, LCR_7BITS); 1394 break; 1395 case CS8: 1396 SET(lcr, LCR_8BITS); 1397 break; 1398 } 1399 if (ISSET(cflag, PARENB)) { 1400 SET(lcr, LCR_PENAB); 1401 if (!ISSET(cflag, PARODD)) 1402 SET(lcr, LCR_PEVEN); 1403 } 1404 if (ISSET(cflag, CSTOPB)) 1405 SET(lcr, LCR_STOPB); 1406 1407 return (lcr); 1408 } 1409 1410 int 1411 comparam(struct tty *tp, struct termios *t) 1412 { 1413 struct com_softc *sc = 1414 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1415 int ospeed; 1416 u_char lcr; 1417 1418 if (COM_ISALIVE(sc) == 0) 1419 return (EIO); 1420 1421 if (sc->sc_type == COM_TYPE_HAYESP) { 1422 int prescaler, speed; 1423 1424 /* 1425 * Calculate UART clock prescaler. It should be in 1426 * range of 0 .. 3. 1427 */ 1428 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1429 prescaler++, speed /= 2) 1430 if ((ospeed = comspeed(speed, sc->sc_frequency, 1431 sc->sc_type)) > 0) 1432 break; 1433 1434 if (prescaler == 4) 1435 return (EINVAL); 1436 sc->sc_prescaler = prescaler; 1437 } else 1438 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1439 1440 /* Check requested parameters. */ 1441 if (ospeed < 0) 1442 return (EINVAL); 1443 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1444 return (EINVAL); 1445 1446 /* 1447 * For the console, always force CLOCAL and !HUPCL, so that the port 1448 * is always active. 1449 */ 1450 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1451 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1452 SET(t->c_cflag, CLOCAL); 1453 CLR(t->c_cflag, HUPCL); 1454 } 1455 1456 /* 1457 * If there were no changes, don't do anything. This avoids dropping 1458 * input and improves performance when all we did was frob things like 1459 * VMIN and VTIME. 1460 */ 1461 if (tp->t_ospeed == t->c_ospeed && 1462 tp->t_cflag == t->c_cflag) 1463 return (0); 1464 1465 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1466 1467 mutex_spin_enter(&sc->sc_lock); 1468 1469 sc->sc_lcr = lcr; 1470 1471 /* 1472 * If we're not in a mode that assumes a connection is present, then 1473 * ignore carrier changes. 1474 */ 1475 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1476 sc->sc_msr_dcd = 0; 1477 else 1478 sc->sc_msr_dcd = MSR_DCD; 1479 /* 1480 * Set the flow control pins depending on the current flow control 1481 * mode. 1482 */ 1483 if (ISSET(t->c_cflag, CRTSCTS)) { 1484 sc->sc_mcr_dtr = MCR_DTR; 1485 sc->sc_mcr_rts = MCR_RTS; 1486 sc->sc_msr_cts = MSR_CTS; 1487 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1488 SET(sc->sc_mcr, MCR_AFE); 1489 } else { 1490 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1491 } 1492 } else if (ISSET(t->c_cflag, MDMBUF)) { 1493 /* 1494 * For DTR/DCD flow control, make sure we don't toggle DTR for 1495 * carrier detection. 1496 */ 1497 sc->sc_mcr_dtr = 0; 1498 sc->sc_mcr_rts = MCR_DTR; 1499 sc->sc_msr_cts = MSR_DCD; 1500 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1501 CLR(sc->sc_mcr, MCR_AFE); 1502 } else { 1503 sc->sc_efr = 0; 1504 } 1505 } else { 1506 /* 1507 * If no flow control, then always set RTS. This will make 1508 * the other side happy if it mistakenly thinks we're doing 1509 * RTS/CTS flow control. 1510 */ 1511 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1512 sc->sc_mcr_rts = 0; 1513 sc->sc_msr_cts = 0; 1514 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1515 CLR(sc->sc_mcr, MCR_AFE); 1516 } else { 1517 sc->sc_efr = 0; 1518 } 1519 if (ISSET(sc->sc_mcr, MCR_DTR)) 1520 SET(sc->sc_mcr, MCR_RTS); 1521 else 1522 CLR(sc->sc_mcr, MCR_RTS); 1523 } 1524 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1525 1526 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1527 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1528 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1529 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1530 1531 sc->sc_dlbl = ospeed; 1532 sc->sc_dlbh = ospeed >> 8; 1533 1534 /* 1535 * Set the FIFO threshold based on the receive speed. 1536 * 1537 * * If it's a low speed, it's probably a mouse or some other 1538 * interactive device, so set the threshold low. 1539 * * If it's a high speed, trim the trigger level down to prevent 1540 * overflows. 1541 * * Otherwise set it a bit higher. 1542 */ 1543 if (sc->sc_type == COM_TYPE_HAYESP) { 1544 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1545 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1546 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1547 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1548 if (t->c_ospeed <= 1200) 1549 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1550 else if (t->c_ospeed <= 38400) 1551 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1552 else 1553 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1554 } else { 1555 sc->sc_fifo = 0; 1556 } 1557 1558 if (sc->sc_type == COM_TYPE_INGENIC) 1559 sc->sc_fifo |= FIFO_UART_ON; 1560 1561 /* And copy to tty. */ 1562 tp->t_ispeed = t->c_ospeed; 1563 tp->t_ospeed = t->c_ospeed; 1564 tp->t_cflag = t->c_cflag; 1565 1566 if (!sc->sc_heldchange) { 1567 if (sc->sc_tx_busy) { 1568 sc->sc_heldtbc = sc->sc_tbc; 1569 sc->sc_tbc = 0; 1570 sc->sc_heldchange = 1; 1571 } else 1572 com_loadchannelregs(sc); 1573 } 1574 1575 if (!ISSET(t->c_cflag, CHWFLOW)) { 1576 /* Disable the high water mark. */ 1577 sc->sc_r_hiwat = 0; 1578 sc->sc_r_lowat = 0; 1579 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1580 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1581 com_schedrx(sc); 1582 } 1583 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1584 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1585 com_hwiflow(sc); 1586 } 1587 } else { 1588 sc->sc_r_hiwat = com_rbuf_hiwat; 1589 sc->sc_r_lowat = com_rbuf_lowat; 1590 } 1591 1592 mutex_spin_exit(&sc->sc_lock); 1593 1594 /* 1595 * Update the tty layer's idea of the carrier bit, in case we changed 1596 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1597 * explicit request. 1598 */ 1599 if (sc->sc_type == COM_TYPE_INGENIC) { 1600 /* no DCD here */ 1601 (void) (*tp->t_linesw->l_modem)(tp, 1); 1602 } else 1603 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1604 1605 #ifdef COM_DEBUG 1606 if (com_debug) 1607 comstatus(sc, "comparam "); 1608 #endif 1609 1610 if (!ISSET(t->c_cflag, CHWFLOW)) { 1611 if (sc->sc_tx_stopped) { 1612 sc->sc_tx_stopped = 0; 1613 comstart(tp); 1614 } 1615 } 1616 1617 return (0); 1618 } 1619 1620 void 1621 com_iflush(struct com_softc *sc) 1622 { 1623 struct com_regs *regsp = &sc->sc_regs; 1624 uint8_t fifo; 1625 #ifdef DIAGNOSTIC 1626 int reg; 1627 #endif 1628 int timo; 1629 1630 #ifdef DIAGNOSTIC 1631 reg = 0xffff; 1632 #endif 1633 timo = 50000; 1634 /* flush any pending I/O */ 1635 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1636 && --timo) 1637 #ifdef DIAGNOSTIC 1638 reg = 1639 #else 1640 (void) 1641 #endif 1642 CSR_READ_1(regsp, COM_REG_RXDATA); 1643 #ifdef DIAGNOSTIC 1644 if (!timo) 1645 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1646 #endif 1647 1648 switch (sc->sc_type) { 1649 case COM_TYPE_16750: 1650 case COM_TYPE_DW_APB: 1651 /* 1652 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1653 * This should prevent triggering busy interrupt while 1654 * manipulating divisors. 1655 */ 1656 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1657 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1658 CSR_WRITE_1(regsp, COM_REG_FIFO, 1659 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1660 delay(100); 1661 break; 1662 } 1663 } 1664 1665 void 1666 com_loadchannelregs(struct com_softc *sc) 1667 { 1668 struct com_regs *regsp = &sc->sc_regs; 1669 1670 /* XXXXX necessary? */ 1671 com_iflush(sc); 1672 1673 if (sc->sc_type == COM_TYPE_PXA2x0) 1674 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1675 else 1676 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1677 1678 if (sc->sc_type == COM_TYPE_OMAP) { 1679 /* disable before changing settings */ 1680 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1681 } 1682 1683 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1684 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1685 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1686 /* no EFR on alchemy */ 1687 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1688 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1689 } 1690 if (sc->sc_type == COM_TYPE_AU1x00) { 1691 /* alchemy has single separate 16-bit clock divisor register */ 1692 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1693 (sc->sc_dlbh << 8)); 1694 } else { 1695 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1696 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1697 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1698 } 1699 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1700 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1701 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1702 if (sc->sc_type == COM_TYPE_HAYESP) { 1703 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1704 HAYESP_SETPRESCALER); 1705 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1706 sc->sc_prescaler); 1707 } 1708 if (sc->sc_type == COM_TYPE_OMAP) { 1709 /* setup the fifos. the FCR value is not used as long 1710 as SCR[6] and SCR[7] are 0, which they are at reset 1711 and we never touch the SCR register */ 1712 uint8_t rx_fifo_trig = 40; 1713 uint8_t tx_fifo_trig = 60; 1714 uint8_t rx_start = 8; 1715 uint8_t rx_halt = 60; 1716 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1717 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1718 1719 /* enable access to TCR & TLR */ 1720 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1721 1722 /* write tcr and tlr values */ 1723 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1724 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1725 1726 /* disable access to TCR & TLR */ 1727 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1728 1729 /* enable again, but mode is based on speed */ 1730 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1731 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1732 } else { 1733 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1734 } 1735 } 1736 1737 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1738 } 1739 1740 int 1741 comhwiflow(struct tty *tp, int block) 1742 { 1743 struct com_softc *sc = 1744 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1745 1746 if (COM_ISALIVE(sc) == 0) 1747 return (0); 1748 1749 if (sc->sc_mcr_rts == 0) 1750 return (0); 1751 1752 mutex_spin_enter(&sc->sc_lock); 1753 1754 if (block) { 1755 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1756 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1757 com_hwiflow(sc); 1758 } 1759 } else { 1760 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1761 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1762 com_schedrx(sc); 1763 } 1764 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1765 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1766 com_hwiflow(sc); 1767 } 1768 } 1769 1770 mutex_spin_exit(&sc->sc_lock); 1771 return (1); 1772 } 1773 1774 /* 1775 * (un)block input via hw flowcontrol 1776 */ 1777 void 1778 com_hwiflow(struct com_softc *sc) 1779 { 1780 struct com_regs *regsp= &sc->sc_regs; 1781 1782 if (sc->sc_mcr_rts == 0) 1783 return; 1784 1785 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1786 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1787 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1788 } else { 1789 SET(sc->sc_mcr, sc->sc_mcr_rts); 1790 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1791 } 1792 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1793 } 1794 1795 1796 void 1797 comstart(struct tty *tp) 1798 { 1799 struct com_softc *sc = 1800 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1801 struct com_regs *regsp = &sc->sc_regs; 1802 int s; 1803 1804 if (COM_ISALIVE(sc) == 0) 1805 return; 1806 1807 s = spltty(); 1808 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1809 goto out; 1810 if (sc->sc_tx_stopped) 1811 goto out; 1812 if (!ttypull(tp)) 1813 goto out; 1814 1815 /* Grab the first contiguous region of buffer space. */ 1816 { 1817 u_char *tba; 1818 int tbc; 1819 1820 tba = tp->t_outq.c_cf; 1821 tbc = ndqb(&tp->t_outq, 0); 1822 1823 mutex_spin_enter(&sc->sc_lock); 1824 1825 sc->sc_tba = tba; 1826 sc->sc_tbc = tbc; 1827 } 1828 1829 SET(tp->t_state, TS_BUSY); 1830 sc->sc_tx_busy = 1; 1831 1832 /* Enable transmit completion interrupts if necessary. */ 1833 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1834 SET(sc->sc_ier, IER_ETXRDY); 1835 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1836 } 1837 1838 /* Output the first chunk of the contiguous buffer. */ 1839 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1840 u_int n; 1841 1842 n = sc->sc_tbc; 1843 if (n > sc->sc_fifolen) 1844 n = sc->sc_fifolen; 1845 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1846 sc->sc_tbc -= n; 1847 sc->sc_tba += n; 1848 } 1849 1850 mutex_spin_exit(&sc->sc_lock); 1851 out: 1852 splx(s); 1853 return; 1854 } 1855 1856 /* 1857 * Stop output on a line. 1858 */ 1859 void 1860 comstop(struct tty *tp, int flag) 1861 { 1862 struct com_softc *sc = 1863 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1864 1865 mutex_spin_enter(&sc->sc_lock); 1866 if (ISSET(tp->t_state, TS_BUSY)) { 1867 /* Stop transmitting at the next chunk. */ 1868 sc->sc_tbc = 0; 1869 sc->sc_heldtbc = 0; 1870 if (!ISSET(tp->t_state, TS_TTSTOP)) 1871 SET(tp->t_state, TS_FLUSH); 1872 } 1873 mutex_spin_exit(&sc->sc_lock); 1874 } 1875 1876 void 1877 comdiag(void *arg) 1878 { 1879 struct com_softc *sc = arg; 1880 int overflows, floods; 1881 1882 mutex_spin_enter(&sc->sc_lock); 1883 overflows = sc->sc_overflows; 1884 sc->sc_overflows = 0; 1885 floods = sc->sc_floods; 1886 sc->sc_floods = 0; 1887 sc->sc_errors = 0; 1888 mutex_spin_exit(&sc->sc_lock); 1889 1890 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1891 device_xname(sc->sc_dev), 1892 overflows, overflows == 1 ? "" : "s", 1893 floods, floods == 1 ? "" : "s"); 1894 } 1895 1896 integrate void 1897 com_rxsoft(struct com_softc *sc, struct tty *tp) 1898 { 1899 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1900 u_char *get, *end; 1901 u_int cc, scc; 1902 u_char lsr; 1903 int code; 1904 1905 end = sc->sc_ebuf; 1906 get = sc->sc_rbget; 1907 scc = cc = com_rbuf_size - sc->sc_rbavail; 1908 1909 if (cc == com_rbuf_size) { 1910 sc->sc_floods++; 1911 if (sc->sc_errors++ == 0) 1912 callout_reset(&sc->sc_diag_callout, 60 * hz, 1913 comdiag, sc); 1914 } 1915 1916 /* If not yet open, drop the entire buffer content here */ 1917 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1918 get += cc << 1; 1919 if (get >= end) 1920 get -= com_rbuf_size << 1; 1921 cc = 0; 1922 } 1923 while (cc) { 1924 code = get[0]; 1925 lsr = get[1]; 1926 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1927 if (ISSET(lsr, LSR_OE)) { 1928 sc->sc_overflows++; 1929 if (sc->sc_errors++ == 0) 1930 callout_reset(&sc->sc_diag_callout, 1931 60 * hz, comdiag, sc); 1932 } 1933 if (ISSET(lsr, LSR_BI | LSR_FE)) 1934 SET(code, TTY_FE); 1935 if (ISSET(lsr, LSR_PE)) 1936 SET(code, TTY_PE); 1937 } 1938 if ((*rint)(code, tp) == -1) { 1939 /* 1940 * The line discipline's buffer is out of space. 1941 */ 1942 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1943 /* 1944 * We're either not using flow control, or the 1945 * line discipline didn't tell us to block for 1946 * some reason. Either way, we have no way to 1947 * know when there's more space available, so 1948 * just drop the rest of the data. 1949 */ 1950 get += cc << 1; 1951 if (get >= end) 1952 get -= com_rbuf_size << 1; 1953 cc = 0; 1954 } else { 1955 /* 1956 * Don't schedule any more receive processing 1957 * until the line discipline tells us there's 1958 * space available (through comhwiflow()). 1959 * Leave the rest of the data in the input 1960 * buffer. 1961 */ 1962 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1963 } 1964 break; 1965 } 1966 get += 2; 1967 if (get >= end) 1968 get = sc->sc_rbuf; 1969 cc--; 1970 } 1971 1972 if (cc != scc) { 1973 sc->sc_rbget = get; 1974 mutex_spin_enter(&sc->sc_lock); 1975 1976 cc = sc->sc_rbavail += scc - cc; 1977 /* Buffers should be ok again, release possible block. */ 1978 if (cc >= sc->sc_r_lowat) { 1979 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1980 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1981 SET(sc->sc_ier, IER_ERXRDY); 1982 if (sc->sc_type == COM_TYPE_PXA2x0) 1983 SET(sc->sc_ier, IER_ERXTOUT); 1984 if (sc->sc_type == COM_TYPE_INGENIC || 1985 sc->sc_type == COM_TYPE_TEGRA) 1986 SET(sc->sc_ier, IER_ERXTOUT); 1987 1988 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 1989 sc->sc_ier); 1990 } 1991 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1992 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1993 com_hwiflow(sc); 1994 } 1995 } 1996 mutex_spin_exit(&sc->sc_lock); 1997 } 1998 } 1999 2000 integrate void 2001 com_txsoft(struct com_softc *sc, struct tty *tp) 2002 { 2003 2004 CLR(tp->t_state, TS_BUSY); 2005 if (ISSET(tp->t_state, TS_FLUSH)) 2006 CLR(tp->t_state, TS_FLUSH); 2007 else 2008 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2009 (*tp->t_linesw->l_start)(tp); 2010 } 2011 2012 integrate void 2013 com_stsoft(struct com_softc *sc, struct tty *tp) 2014 { 2015 u_char msr, delta; 2016 2017 mutex_spin_enter(&sc->sc_lock); 2018 msr = sc->sc_msr; 2019 delta = sc->sc_msr_delta; 2020 sc->sc_msr_delta = 0; 2021 mutex_spin_exit(&sc->sc_lock); 2022 2023 if (ISSET(delta, sc->sc_msr_dcd)) { 2024 /* 2025 * Inform the tty layer that carrier detect changed. 2026 */ 2027 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2028 } 2029 2030 if (ISSET(delta, sc->sc_msr_cts)) { 2031 /* Block or unblock output according to flow control. */ 2032 if (ISSET(msr, sc->sc_msr_cts)) { 2033 sc->sc_tx_stopped = 0; 2034 (*tp->t_linesw->l_start)(tp); 2035 } else { 2036 sc->sc_tx_stopped = 1; 2037 } 2038 } 2039 2040 #ifdef COM_DEBUG 2041 if (com_debug) 2042 comstatus(sc, "com_stsoft"); 2043 #endif 2044 } 2045 2046 void 2047 comsoft(void *arg) 2048 { 2049 struct com_softc *sc = arg; 2050 struct tty *tp; 2051 2052 if (COM_ISALIVE(sc) == 0) 2053 return; 2054 2055 tp = sc->sc_tty; 2056 2057 if (sc->sc_rx_ready) { 2058 sc->sc_rx_ready = 0; 2059 com_rxsoft(sc, tp); 2060 } 2061 2062 if (sc->sc_st_check) { 2063 sc->sc_st_check = 0; 2064 com_stsoft(sc, tp); 2065 } 2066 2067 if (sc->sc_tx_done) { 2068 sc->sc_tx_done = 0; 2069 com_txsoft(sc, tp); 2070 } 2071 } 2072 2073 int 2074 comintr(void *arg) 2075 { 2076 struct com_softc *sc = arg; 2077 struct com_regs *regsp = &sc->sc_regs; 2078 2079 u_char *put, *end; 2080 u_int cc; 2081 u_char lsr, iir; 2082 2083 if (COM_ISALIVE(sc) == 0) 2084 return (0); 2085 2086 KASSERT(regsp != NULL); 2087 2088 mutex_spin_enter(&sc->sc_lock); 2089 iir = CSR_READ_1(regsp, COM_REG_IIR); 2090 2091 /* Handle ns16750-specific busy interrupt. */ 2092 if (sc->sc_type == COM_TYPE_16750 && 2093 (iir & IIR_BUSY) == IIR_BUSY) { 2094 for (int timeout = 10000; 2095 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2096 if (timeout <= 0) { 2097 aprint_error_dev(sc->sc_dev, 2098 "timeout while waiting for BUSY interrupt " 2099 "acknowledge\n"); 2100 mutex_spin_exit(&sc->sc_lock); 2101 return (0); 2102 } 2103 2104 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2105 iir = CSR_READ_1(regsp, COM_REG_IIR); 2106 } 2107 2108 /* DesignWare APB UART BUSY interrupt */ 2109 if (sc->sc_type == COM_TYPE_DW_APB && 2110 (iir & IIR_BUSY) == IIR_BUSY) { 2111 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2112 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2113 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2114 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2115 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2116 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2117 CSR_WRITE_1(regsp, COM_REG_HALT, 2118 HALT_CHCFG_EN | HALT_CHCFG_UD); 2119 for (int timeout = 10000000; 2120 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2121 timeout--) { 2122 if (timeout <= 0) { 2123 aprint_error_dev(sc->sc_dev, 2124 "timeout while waiting for HALT " 2125 "update acknowledge 0x%x 0x%x\n", 2126 CSR_READ_1(regsp, COM_REG_HALT), 2127 CSR_READ_1(regsp, COM_REG_USR)); 2128 break; 2129 } 2130 } 2131 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2132 (void)CSR_READ_1(regsp, COM_REG_USR); 2133 } else { 2134 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2135 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2136 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2137 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2138 } 2139 } 2140 2141 if (ISSET(iir, IIR_NOPEND)) { 2142 mutex_spin_exit(&sc->sc_lock); 2143 return (0); 2144 } 2145 2146 end = sc->sc_ebuf; 2147 put = sc->sc_rbput; 2148 cc = sc->sc_rbavail; 2149 2150 again: do { 2151 u_char msr, delta; 2152 2153 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2154 if (ISSET(lsr, LSR_BI)) { 2155 int cn_trapped = 0; /* see above: cn_trap() */ 2156 2157 cn_check_magic(sc->sc_tty->t_dev, 2158 CNC_BREAK, com_cnm_state); 2159 if (cn_trapped) 2160 continue; 2161 #if defined(KGDB) && !defined(DDB) 2162 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2163 kgdb_connect(1); 2164 continue; 2165 } 2166 #endif 2167 } 2168 2169 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2170 lsr |= LSR_RXRDY; 2171 2172 if (ISSET(lsr, LSR_RCV_MASK) && 2173 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2174 while (cc > 0) { 2175 int cn_trapped = 0; 2176 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2177 put[1] = lsr; 2178 cn_check_magic(sc->sc_tty->t_dev, 2179 put[0], com_cnm_state); 2180 if (cn_trapped) 2181 goto next; 2182 put += 2; 2183 if (put >= end) 2184 put = sc->sc_rbuf; 2185 cc--; 2186 next: 2187 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2188 if (!ISSET(lsr, LSR_RCV_MASK)) 2189 break; 2190 } 2191 2192 /* 2193 * Current string of incoming characters ended because 2194 * no more data was available or we ran out of space. 2195 * Schedule a receive event if any data was received. 2196 * If we're out of space, turn off receive interrupts. 2197 */ 2198 sc->sc_rbput = put; 2199 sc->sc_rbavail = cc; 2200 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2201 sc->sc_rx_ready = 1; 2202 2203 /* 2204 * See if we are in danger of overflowing a buffer. If 2205 * so, use hardware flow control to ease the pressure. 2206 */ 2207 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2208 cc < sc->sc_r_hiwat) { 2209 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2210 com_hwiflow(sc); 2211 } 2212 2213 /* 2214 * If we're out of space, disable receive interrupts 2215 * until the queue has drained a bit. 2216 */ 2217 if (!cc) { 2218 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2219 switch (sc->sc_type) { 2220 case COM_TYPE_PXA2x0: 2221 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2222 break; 2223 case COM_TYPE_INGENIC: 2224 case COM_TYPE_TEGRA: 2225 CLR(sc->sc_ier, 2226 IER_ERXRDY | IER_ERXTOUT); 2227 break; 2228 default: 2229 CLR(sc->sc_ier, IER_ERXRDY); 2230 break; 2231 } 2232 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2233 } 2234 } else { 2235 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2236 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2237 continue; 2238 } 2239 } 2240 2241 msr = CSR_READ_1(regsp, COM_REG_MSR); 2242 delta = msr ^ sc->sc_msr; 2243 sc->sc_msr = msr; 2244 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2245 (delta & MSR_DCD)) { 2246 mutex_spin_enter(&timecounter_lock); 2247 pps_capture(&sc->sc_pps_state); 2248 pps_event(&sc->sc_pps_state, 2249 (msr & MSR_DCD) ? 2250 PPS_CAPTUREASSERT : 2251 PPS_CAPTURECLEAR); 2252 mutex_spin_exit(&timecounter_lock); 2253 } 2254 2255 /* 2256 * Process normal status changes 2257 */ 2258 if (ISSET(delta, sc->sc_msr_mask)) { 2259 SET(sc->sc_msr_delta, delta); 2260 2261 /* 2262 * Stop output immediately if we lose the output 2263 * flow control signal or carrier detect. 2264 */ 2265 if (ISSET(~msr, sc->sc_msr_mask)) { 2266 sc->sc_tbc = 0; 2267 sc->sc_heldtbc = 0; 2268 #ifdef COM_DEBUG 2269 if (com_debug) 2270 comstatus(sc, "comintr "); 2271 #endif 2272 } 2273 2274 sc->sc_st_check = 1; 2275 } 2276 } while (!ISSET((iir = 2277 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2278 /* 2279 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2280 * by IIR read, so we can't do this way: `process all interrupts, 2281 * then do TX if possible'. 2282 */ 2283 (iir & IIR_IMASK) != IIR_TXRDY); 2284 2285 /* 2286 * Read LSR again, since there may be an interrupt between 2287 * the last LSR read and IIR read above. 2288 */ 2289 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2290 2291 /* 2292 * See if data can be transmitted as well. 2293 * Schedule tx done event if no data left 2294 * and tty was marked busy. 2295 */ 2296 if (ISSET(lsr, LSR_TXRDY)) { 2297 /* 2298 * If we've delayed a parameter change, do it now, and restart 2299 * output. 2300 */ 2301 if (sc->sc_heldchange) { 2302 com_loadchannelregs(sc); 2303 sc->sc_heldchange = 0; 2304 sc->sc_tbc = sc->sc_heldtbc; 2305 sc->sc_heldtbc = 0; 2306 } 2307 2308 /* Output the next chunk of the contiguous buffer, if any. */ 2309 if (sc->sc_tbc > 0) { 2310 u_int n; 2311 2312 n = sc->sc_tbc; 2313 if (n > sc->sc_fifolen) 2314 n = sc->sc_fifolen; 2315 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2316 sc->sc_tbc -= n; 2317 sc->sc_tba += n; 2318 } else { 2319 /* Disable transmit completion interrupts if necessary. */ 2320 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2321 CLR(sc->sc_ier, IER_ETXRDY); 2322 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2323 } 2324 if (sc->sc_tx_busy) { 2325 sc->sc_tx_busy = 0; 2326 sc->sc_tx_done = 1; 2327 } 2328 } 2329 } 2330 2331 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2332 goto again; 2333 2334 mutex_spin_exit(&sc->sc_lock); 2335 2336 /* Wake up the poller. */ 2337 softint_schedule(sc->sc_si); 2338 2339 #ifdef RND_COM 2340 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2341 #endif 2342 2343 return (1); 2344 } 2345 2346 /* 2347 * The following functions are polled getc and putc routines, shared 2348 * by the console and kgdb glue. 2349 * 2350 * The read-ahead code is so that you can detect pending in-band 2351 * cn_magic in polled mode while doing output rather than having to 2352 * wait until the kernel decides it needs input. 2353 */ 2354 2355 #define MAX_READAHEAD 20 2356 static int com_readahead[MAX_READAHEAD]; 2357 static int com_readaheadcount = 0; 2358 2359 int 2360 com_common_getc(dev_t dev, struct com_regs *regsp) 2361 { 2362 int s = splserial(); 2363 u_char stat, c; 2364 2365 /* got a character from reading things earlier */ 2366 if (com_readaheadcount > 0) { 2367 int i; 2368 2369 c = com_readahead[0]; 2370 for (i = 1; i < com_readaheadcount; i++) { 2371 com_readahead[i-1] = com_readahead[i]; 2372 } 2373 com_readaheadcount--; 2374 splx(s); 2375 return (c); 2376 } 2377 2378 /* don't block until a character becomes available */ 2379 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2380 splx(s); 2381 return -1; 2382 } 2383 2384 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2385 stat = CSR_READ_1(regsp, COM_REG_IIR); 2386 { 2387 int cn_trapped = 0; /* required by cn_trap, see above */ 2388 #ifdef DDB 2389 extern int db_active; 2390 if (!db_active) 2391 #endif 2392 cn_check_magic(dev, c, com_cnm_state); 2393 } 2394 splx(s); 2395 return (c); 2396 } 2397 2398 static void 2399 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2400 { 2401 int s = splserial(); 2402 int cin, stat, timo; 2403 2404 if (com_readaheadcount < MAX_READAHEAD 2405 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2406 int cn_trapped = 0; 2407 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2408 stat = CSR_READ_1(regsp, COM_REG_IIR); 2409 cn_check_magic(dev, cin, com_cnm_state); 2410 com_readahead[com_readaheadcount++] = cin; 2411 } 2412 2413 /* wait for any pending transmission to finish */ 2414 timo = 150000; 2415 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2416 continue; 2417 2418 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2419 COM_BARRIER(regsp, BR | BW); 2420 2421 splx(s); 2422 } 2423 2424 /* 2425 * Initialize UART for use as console or KGDB line. 2426 */ 2427 int 2428 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2429 tcflag_t cflag) 2430 { 2431 2432 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2433 ®sp->cr_ioh)) 2434 return (ENOMEM); /* ??? */ 2435 2436 if (type == COM_TYPE_OMAP) { 2437 /* disable before changing settings */ 2438 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2439 } 2440 2441 rate = comspeed(rate, frequency, type); 2442 if (__predict_true(rate != -1)) { 2443 if (type == COM_TYPE_AU1x00) { 2444 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2445 } else { 2446 /* no EFR on alchemy */ 2447 if ((type != COM_TYPE_16550_NOERS) && 2448 (type != COM_TYPE_INGENIC)) { 2449 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2450 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2451 } 2452 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2453 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2454 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2455 } 2456 } 2457 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2458 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2459 2460 if (type == COM_TYPE_INGENIC) { 2461 CSR_WRITE_1(regsp, COM_REG_FIFO, 2462 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2463 FIFO_TRIGGER_1 | FIFO_UART_ON); 2464 } else { 2465 CSR_WRITE_1(regsp, COM_REG_FIFO, 2466 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2467 FIFO_TRIGGER_1); 2468 } 2469 2470 if (type == COM_TYPE_OMAP) { 2471 /* setup the fifos. the FCR value is not used as long 2472 as SCR[6] and SCR[7] are 0, which they are at reset 2473 and we never touch the SCR register */ 2474 uint8_t rx_fifo_trig = 40; 2475 uint8_t tx_fifo_trig = 60; 2476 uint8_t rx_start = 8; 2477 uint8_t rx_halt = 60; 2478 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2479 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2480 2481 /* enable access to TCR & TLR */ 2482 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2483 2484 /* write tcr and tlr values */ 2485 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2486 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2487 2488 /* disable access to TCR & TLR */ 2489 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2490 2491 /* enable again, but mode is based on speed */ 2492 if (rate > 230400) { 2493 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2494 } else { 2495 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2496 } 2497 } 2498 2499 if (type == COM_TYPE_PXA2x0) 2500 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2501 else 2502 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2503 2504 return (0); 2505 } 2506 2507 int 2508 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2509 tcflag_t cflag) 2510 { 2511 int res; 2512 2513 comcons_info.regs = *regsp; 2514 2515 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2516 if (res) 2517 return (res); 2518 2519 cn_tab = &comcons; 2520 cn_init_magic(&com_cnm_state); 2521 cn_set_magic("\047\001"); /* default magic is BREAK */ 2522 2523 comcons_info.frequency = frequency; 2524 comcons_info.type = type; 2525 comcons_info.rate = rate; 2526 comcons_info.cflag = cflag; 2527 2528 return (0); 2529 } 2530 2531 int 2532 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2533 int type, tcflag_t cflag) 2534 { 2535 struct com_regs regs; 2536 2537 /*XXX*/ 2538 bus_space_handle_t dummy_bsh; 2539 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2540 2541 /* 2542 * dummy_bsh required because com_init_regs() wants it. A 2543 * real bus_space_handle will be filled in by cominit() later. 2544 * XXXJRT Detangle this mess eventually, plz. 2545 */ 2546 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2547 2548 return comcnattach1(®s, rate, frequency, type, cflag); 2549 } 2550 2551 static int 2552 comcnreattach(void) 2553 { 2554 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2555 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2556 } 2557 2558 int 2559 comcngetc(dev_t dev) 2560 { 2561 2562 return (com_common_getc(dev, &comcons_info.regs)); 2563 } 2564 2565 /* 2566 * Console kernel output character routine. 2567 */ 2568 void 2569 comcnputc(dev_t dev, int c) 2570 { 2571 2572 com_common_putc(dev, &comcons_info.regs, c); 2573 } 2574 2575 void 2576 comcnpollc(dev_t dev, int on) 2577 { 2578 2579 com_readaheadcount = 0; 2580 } 2581 2582 #ifdef KGDB 2583 int 2584 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2585 tcflag_t cflag) 2586 { 2587 int res; 2588 2589 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2590 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2591 #if !defined(DDB) 2592 return (EBUSY); /* cannot share with console */ 2593 #else 2594 comkgdbregs = *regsp; 2595 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2596 #endif 2597 } else { 2598 comkgdbregs = *regsp; 2599 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2600 if (res) 2601 return (res); 2602 2603 /* 2604 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2605 * expects this to be initialized 2606 */ 2607 cn_init_magic(&com_cnm_state); 2608 cn_set_magic("\047\001"); 2609 } 2610 2611 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2612 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2613 2614 return (0); 2615 } 2616 2617 int 2618 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2619 int frequency, int type, tcflag_t cflag) 2620 { 2621 struct com_regs regs; 2622 2623 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2624 2625 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2626 } 2627 2628 /* ARGSUSED */ 2629 int 2630 com_kgdb_getc(void *arg) 2631 { 2632 2633 return (com_common_getc(NODEV, &comkgdbregs)); 2634 } 2635 2636 /* ARGSUSED */ 2637 void 2638 com_kgdb_putc(void *arg, int c) 2639 { 2640 2641 com_common_putc(NODEV, &comkgdbregs, c); 2642 } 2643 #endif /* KGDB */ 2644 2645 /* helper function to identify the com ports used by 2646 console or KGDB (and not yet autoconf attached) */ 2647 int 2648 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2649 { 2650 bus_space_handle_t help; 2651 2652 if (!comconsattached && 2653 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2654 iobase == comcons_info.regs.cr_iobase) 2655 help = comcons_info.regs.cr_ioh; 2656 #ifdef KGDB 2657 else if (!com_kgdb_attached && 2658 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2659 iobase == comkgdbregs.cr_iobase) 2660 help = comkgdbregs.cr_ioh; 2661 #endif 2662 else 2663 return (0); 2664 2665 if (ioh) 2666 *ioh = help; 2667 return (1); 2668 } 2669 2670 /* 2671 * this routine exists to serve as a shutdown hook for systems that 2672 * have firmware which doesn't interact properly with a com device in 2673 * FIFO mode. 2674 */ 2675 bool 2676 com_cleanup(device_t self, int how) 2677 { 2678 struct com_softc *sc = device_private(self); 2679 2680 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2681 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2682 2683 return true; 2684 } 2685 2686 bool 2687 com_suspend(device_t self, const pmf_qual_t *qual) 2688 { 2689 struct com_softc *sc = device_private(self); 2690 2691 #if 0 2692 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2693 cn_tab = &comcons_suspend; 2694 #endif 2695 2696 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2697 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2698 2699 return true; 2700 } 2701 2702 bool 2703 com_resume(device_t self, const pmf_qual_t *qual) 2704 { 2705 struct com_softc *sc = device_private(self); 2706 2707 mutex_spin_enter(&sc->sc_lock); 2708 com_loadchannelregs(sc); 2709 mutex_spin_exit(&sc->sc_lock); 2710 2711 return true; 2712 } 2713
Indexes created Wed Sep 24 15:09:51 GMT 2025