com.c revision 1.358
1 /* $NetBSD: com.c,v 1.358 2020/05/01 07:27:51 simonb Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.358 2020/05/01 07:27:51 simonb Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #define CSR_WRITE_1(r, o, v) \ 132 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 133 #define CSR_READ_1(r, o) \ 134 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 135 #define CSR_WRITE_2(r, o, v) \ 136 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 137 #define CSR_READ_2(r, o) \ 138 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 139 #define CSR_WRITE_MULTI(r, o, p, n) \ 140 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 141 142 143 static void com_enable_debugport(struct com_softc *); 144 145 void com_config(struct com_softc *); 146 void com_shutdown(struct com_softc *); 147 int comspeed(long, long, int); 148 static u_char cflag2lcr(tcflag_t); 149 int comparam(struct tty *, struct termios *); 150 void comstart(struct tty *); 151 int comhwiflow(struct tty *, int); 152 153 void com_loadchannelregs(struct com_softc *); 154 void com_hwiflow(struct com_softc *); 155 void com_break(struct com_softc *, int); 156 void com_modem(struct com_softc *, int); 157 void tiocm_to_com(struct com_softc *, u_long, int); 158 int com_to_tiocm(struct com_softc *); 159 void com_iflush(struct com_softc *); 160 161 int com_common_getc(dev_t, struct com_regs *); 162 static void com_common_putc(dev_t, struct com_regs *, int); 163 164 int cominit(struct com_regs *, int, int, int, tcflag_t); 165 166 static int comcnreattach(void); 167 168 int comcngetc(dev_t); 169 void comcnputc(dev_t, int); 170 void comcnpollc(dev_t, int); 171 172 #define integrate static inline 173 void comsoft(void *); 174 integrate void com_rxsoft(struct com_softc *, struct tty *); 175 integrate void com_txsoft(struct com_softc *, struct tty *); 176 integrate void com_stsoft(struct com_softc *, struct tty *); 177 integrate void com_schedrx(struct com_softc *); 178 void comdiag(void *); 179 180 dev_type_open(comopen); 181 dev_type_close(comclose); 182 dev_type_read(comread); 183 dev_type_write(comwrite); 184 dev_type_ioctl(comioctl); 185 dev_type_stop(comstop); 186 dev_type_tty(comtty); 187 dev_type_poll(compoll); 188 189 static struct comcons_info comcons_info; 190 191 /* 192 * Following are all routines needed for COM to act as console 193 */ 194 static struct consdev comcons = { 195 .cn_getc = comcngetc, 196 .cn_putc = comcnputc, 197 .cn_pollc = comcnpollc, 198 .cn_dev = NODEV, 199 .cn_pri = CN_NORMAL 200 }; 201 202 203 const struct cdevsw com_cdevsw = { 204 .d_open = comopen, 205 .d_close = comclose, 206 .d_read = comread, 207 .d_write = comwrite, 208 .d_ioctl = comioctl, 209 .d_stop = comstop, 210 .d_tty = comtty, 211 .d_poll = compoll, 212 .d_mmap = nommap, 213 .d_kqfilter = ttykqfilter, 214 .d_discard = nodiscard, 215 .d_flag = D_TTY 216 }; 217 218 /* 219 * Make this an option variable one can patch. 220 * But be warned: this must be a power of 2! 221 */ 222 u_int com_rbuf_size = COM_RING_SIZE; 223 224 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 225 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 226 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 227 228 static int comconsattached; 229 static struct cnm_state com_cnm_state; 230 231 #ifdef KGDB 232 #include <sys/kgdb.h> 233 234 static struct com_regs comkgdbregs; 235 static int com_kgdb_attached; 236 237 int com_kgdb_getc(void *); 238 void com_kgdb_putc(void *, int); 239 #endif /* KGDB */ 240 241 /* initializer for typical 16550-ish hardware */ 242 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 243 [COM_REG_RXDATA] = com_data, 244 [COM_REG_TXDATA] = com_data, 245 [COM_REG_DLBL] = com_dlbl, 246 [COM_REG_DLBH] = com_dlbh, 247 [COM_REG_IER] = com_ier, 248 [COM_REG_IIR] = com_iir, 249 [COM_REG_FIFO] = com_fifo, 250 [COM_REG_TCR] = com_fifo, 251 [COM_REG_EFR] = com_efr, 252 [COM_REG_TLR] = com_efr, 253 [COM_REG_LCR] = com_lcr, 254 [COM_REG_MCR] = com_mcr, 255 [COM_REG_LSR] = com_lsr, 256 [COM_REG_MSR] = com_msr, 257 [COM_REG_USR] = com_usr, 258 [COM_REG_TFL] = com_tfl, 259 [COM_REG_RFL] = com_rfl, 260 [COM_REG_HALT] = com_halt, 261 [COM_REG_MDR1] = com_mdr1, 262 }; 263 264 #define COMDIALOUT_MASK TTDIALOUT_MASK 265 266 #define COMUNIT(x) TTUNIT(x) 267 #define COMDIALOUT(x) TTDIALOUT(x) 268 269 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 270 device_is_active((sc)->sc_dev)) 271 272 #define BR BUS_SPACE_BARRIER_READ 273 #define BW BUS_SPACE_BARRIER_WRITE 274 #define COM_BARRIER(r, f) \ 275 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 276 277 /* 278 * com_init_regs -- 279 * Driver front-ends use this to initialize our register map 280 * in the standard fashion. They may then tailor the map to 281 * their own particular requirements. 282 */ 283 void 284 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 285 bus_addr_t addr) 286 { 287 288 memset(regs, 0, sizeof(*regs)); 289 regs->cr_iot = st; 290 regs->cr_ioh = sh; 291 regs->cr_iobase = addr; 292 regs->cr_nports = COM_NPORTS; 293 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 294 } 295 296 /* 297 * com_init_regs_stride -- 298 * Convenience function for front-ends that have a stride between 299 * registers. 300 */ 301 void 302 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 303 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 304 { 305 306 com_init_regs(regs, st, sh, addr); 307 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 308 regs->cr_map[i] <<= regshift; 309 } 310 regs->cr_nports <<= regshift; 311 } 312 313 /*ARGSUSED*/ 314 int 315 comspeed(long speed, long frequency, int type) 316 { 317 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 318 319 int x, err; 320 int divisor = 16; 321 322 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 323 divisor = 13; 324 } 325 326 if (speed == 0) 327 return (0); 328 if (speed < 0) 329 return (-1); 330 x = divrnd(frequency / divisor, speed); 331 if (x <= 0) 332 return (-1); 333 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 334 if (err < 0) 335 err = -err; 336 if (err > COM_TOLERANCE) 337 return (-1); 338 return (x); 339 340 #undef divrnd 341 } 342 343 #ifdef COM_DEBUG 344 int com_debug = 0; 345 346 void comstatus(struct com_softc *, const char *); 347 void 348 comstatus(struct com_softc *sc, const char *str) 349 { 350 struct tty *tp = sc->sc_tty; 351 352 aprint_normal_dev(sc->sc_dev, 353 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 354 str, 355 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 356 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 357 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 358 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 359 sc->sc_tx_stopped ? '+' : '-'); 360 361 aprint_normal_dev(sc->sc_dev, 362 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 363 str, 364 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 365 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 366 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 367 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 368 sc->sc_rx_flags); 369 } 370 #endif 371 372 int 373 com_probe_subr(struct com_regs *regs) 374 { 375 376 /* force access to id reg */ 377 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 378 CSR_WRITE_1(regs, COM_REG_IIR, 0); 379 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 380 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 381 return (0); 382 383 return (1); 384 } 385 386 int 387 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 388 { 389 struct com_regs regs; 390 391 com_init_regs(®s, iot, ioh, 0/*XXX*/); 392 393 return com_probe_subr(®s); 394 } 395 396 /* 397 * No locking in this routine; it is only called during attach, 398 * or with the port already locked. 399 */ 400 static void 401 com_enable_debugport(struct com_softc *sc) 402 { 403 404 /* Turn on line break interrupt, set carrier. */ 405 sc->sc_ier = IER_ERLS; 406 if (sc->sc_type == COM_TYPE_PXA2x0) 407 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 408 if (sc->sc_type == COM_TYPE_INGENIC || 409 sc->sc_type == COM_TYPE_TEGRA) 410 sc->sc_ier |= IER_ERXTOUT; 411 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 412 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 413 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 414 } 415 416 static void 417 com_intr_poll(void *arg) 418 { 419 struct com_softc * const sc = arg; 420 421 comintr(sc); 422 423 callout_schedule(&sc->sc_poll_callout, 1); 424 } 425 426 void 427 com_attach_subr(struct com_softc *sc) 428 { 429 struct com_regs *regsp = &sc->sc_regs; 430 struct tty *tp; 431 u_int8_t lcr; 432 const char *fifo_msg = NULL; 433 prop_dictionary_t dict; 434 bool is_console = true; 435 bool force_console = false; 436 437 aprint_naive("\n"); 438 439 dict = device_properties(sc->sc_dev); 440 prop_dictionary_get_bool(dict, "is_console", &is_console); 441 prop_dictionary_get_bool(dict, "force_console", &force_console); 442 callout_init(&sc->sc_diag_callout, 0); 443 callout_init(&sc->sc_poll_callout, 0); 444 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 445 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 446 447 #if defined(COM_16650) 448 sc->sc_type = COM_TYPE_16650; 449 #elif defined(COM_16750) 450 sc->sc_type = COM_TYPE_16750; 451 #elif defined(COM_HAYESP) 452 sc->sc_type = COM_TYPE_HAYESP; 453 #elif defined(COM_PXA2X0) 454 sc->sc_type = COM_TYPE_PXA2x0; 455 #endif 456 457 /* Disable interrupts before configuring the device. */ 458 if (sc->sc_type == COM_TYPE_PXA2x0) 459 sc->sc_ier = IER_EUART; 460 else 461 sc->sc_ier = 0; 462 463 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 464 465 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 466 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 467 comconsattached = 1; 468 469 if (force_console) 470 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 471 472 if (cn_tab == NULL && comcnreattach() != 0) { 473 printf("can't re-init serial console @%lx\n", 474 (u_long)comcons_info.regs.cr_iobase); 475 } 476 477 switch (sc->sc_type) { 478 case COM_TYPE_16750: 479 case COM_TYPE_DW_APB: 480 /* Use in comintr(). */ 481 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 482 break; 483 } 484 485 /* Make sure the console is always "hardwired". */ 486 delay(10000); /* wait for output to finish */ 487 if (is_console) { 488 SET(sc->sc_hwflags, COM_HW_CONSOLE); 489 } 490 491 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 492 } 493 494 /* Probe for FIFO */ 495 switch (sc->sc_type) { 496 case COM_TYPE_HAYESP: 497 goto fifodone; 498 499 case COM_TYPE_AU1x00: 500 sc->sc_fifolen = 16; 501 fifo_msg = "Au1X00 UART, working fifo"; 502 SET(sc->sc_hwflags, COM_HW_FIFO); 503 goto fifodelay; 504 505 case COM_TYPE_16550_NOERS: 506 sc->sc_fifolen = 16; 507 fifo_msg = "ns16650, no ERS, working fifo"; 508 SET(sc->sc_hwflags, COM_HW_FIFO); 509 goto fifodelay; 510 511 case COM_TYPE_OMAP: 512 sc->sc_fifolen = 64; 513 fifo_msg = "OMAP UART, working fifo"; 514 SET(sc->sc_hwflags, COM_HW_FIFO); 515 goto fifodelay; 516 517 case COM_TYPE_INGENIC: 518 sc->sc_fifolen = 16; 519 fifo_msg = "Ingenic UART, working fifo"; 520 SET(sc->sc_hwflags, COM_HW_FIFO); 521 SET(sc->sc_hwflags, COM_HW_NOIEN); 522 goto fifodelay; 523 524 case COM_TYPE_TEGRA: 525 sc->sc_fifolen = 8; 526 fifo_msg = "Tegra UART, working fifo"; 527 SET(sc->sc_hwflags, COM_HW_FIFO); 528 CSR_WRITE_1(regsp, COM_REG_FIFO, 529 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 530 goto fifodelay; 531 532 case COM_TYPE_BCMAUXUART: 533 sc->sc_fifolen = 1; 534 fifo_msg = "BCM AUX UART, working fifo"; 535 SET(sc->sc_hwflags, COM_HW_FIFO); 536 CSR_WRITE_1(regsp, COM_REG_FIFO, 537 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 538 goto fifodelay; 539 } 540 541 sc->sc_fifolen = 1; 542 /* look for a NS 16550AF UART with FIFOs */ 543 if (sc->sc_type == COM_TYPE_INGENIC) { 544 CSR_WRITE_1(regsp, COM_REG_FIFO, 545 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 546 FIFO_TRIGGER_14 | FIFO_UART_ON); 547 } else 548 CSR_WRITE_1(regsp, COM_REG_FIFO, 549 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 550 delay(100); 551 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 552 == IIR_FIFO_MASK) 553 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 554 == FIFO_TRIGGER_14) { 555 SET(sc->sc_hwflags, COM_HW_FIFO); 556 557 fifo_msg = "ns16550a, working fifo"; 558 559 /* 560 * IIR changes into the EFR if LCR is set to LCR_EERS 561 * on 16650s. We also know IIR != 0 at this point. 562 * Write 0 into the EFR, and read it. If the result 563 * is 0, we have a 16650. 564 * 565 * Older 16650s were broken; the test to detect them 566 * is taken from the Linux driver. Apparently 567 * setting DLAB enable gives access to the EFR on 568 * these chips. 569 */ 570 if (sc->sc_type == COM_TYPE_16650) { 571 lcr = CSR_READ_1(regsp, COM_REG_LCR); 572 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 573 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 574 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 575 CSR_WRITE_1(regsp, COM_REG_LCR, 576 lcr | LCR_DLAB); 577 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 578 CLR(sc->sc_hwflags, COM_HW_FIFO); 579 sc->sc_fifolen = 0; 580 } else { 581 SET(sc->sc_hwflags, COM_HW_FLOW); 582 sc->sc_fifolen = 32; 583 } 584 } else 585 sc->sc_fifolen = 16; 586 587 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 588 if (sc->sc_fifolen == 0) 589 fifo_msg = "st16650, broken fifo"; 590 else if (sc->sc_fifolen == 32) 591 fifo_msg = "st16650a, working fifo"; 592 else 593 fifo_msg = "ns16550a, working fifo"; 594 } 595 596 /* 597 * TL16C750 can enable 64byte FIFO, only when DLAB 598 * is 1. However, some 16750 may always enable. For 599 * example, restrictions according to DLAB in a data 600 * sheet for SC16C750 were not described. 601 * Please enable 'options COM_16650', supposing you 602 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 603 * should become effective. 604 */ 605 if (sc->sc_type == COM_TYPE_16750) { 606 uint8_t iir1, iir2; 607 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 608 609 lcr = CSR_READ_1(regsp, COM_REG_LCR); 610 CSR_WRITE_1(regsp, COM_REG_LCR, 611 lcr & ~LCR_DLAB); 612 CSR_WRITE_1(regsp, COM_REG_FIFO, 613 fcr | FIFO_64B_ENABLE); 614 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 615 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 616 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 617 CSR_WRITE_1(regsp, COM_REG_FIFO, 618 fcr | FIFO_64B_ENABLE); 619 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 620 621 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 622 623 if (!ISSET(iir1, IIR_64B_FIFO) && 624 ISSET(iir2, IIR_64B_FIFO)) { 625 /* It is TL16C750. */ 626 sc->sc_fifolen = 64; 627 SET(sc->sc_hwflags, COM_HW_AFE); 628 } else 629 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 630 631 if (sc->sc_fifolen == 64) 632 fifo_msg = "tl16c750, working fifo"; 633 else 634 fifo_msg = "ns16750, working fifo"; 635 } 636 } else 637 fifo_msg = "ns16550, broken fifo"; 638 else 639 fifo_msg = "ns8250 or ns16450, no fifo"; 640 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 641 642 fifodelay: 643 /* 644 * Some chips will clear down both Tx and Rx FIFOs when zero is 645 * written to com_fifo. If this chip is the console, writing zero 646 * results in some of the chip/FIFO description being lost, so delay 647 * printing it until now. 648 */ 649 delay(10); 650 aprint_normal(": %s\n", fifo_msg); 651 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 652 sc->sc_fifolen = 1; 653 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 654 } 655 656 fifodone: 657 658 tp = tty_alloc(); 659 tp->t_oproc = comstart; 660 tp->t_param = comparam; 661 tp->t_hwiflow = comhwiflow; 662 tp->t_softc = sc; 663 664 sc->sc_tty = tp; 665 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK); 666 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 667 sc->sc_rbavail = com_rbuf_size; 668 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 669 670 tty_attach(tp); 671 672 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 673 SET(sc->sc_mcr, MCR_IENABLE); 674 675 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 676 int maj; 677 678 /* locate the major number */ 679 maj = cdevsw_lookup_major(&com_cdevsw); 680 681 tp->t_dev = cn_tab->cn_dev = makedev(maj, 682 device_unit(sc->sc_dev)); 683 684 aprint_normal_dev(sc->sc_dev, "console\n"); 685 } 686 687 #ifdef KGDB 688 /* 689 * Allow kgdb to "take over" this port. If this is 690 * not the console and is the kgdb device, it has 691 * exclusive use. If it's the console _and_ the 692 * kgdb device, it doesn't. 693 */ 694 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 695 regsp->cr_iobase == comkgdbregs.cr_iobase) { 696 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 697 com_kgdb_attached = 1; 698 699 SET(sc->sc_hwflags, COM_HW_KGDB); 700 } 701 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 702 } 703 #endif 704 705 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 706 707 #ifdef RND_COM 708 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 709 RND_TYPE_TTY, RND_FLAG_DEFAULT); 710 #endif 711 712 /* if there are no enable/disable functions, assume the device 713 is always enabled */ 714 if (!sc->enable) 715 sc->enabled = 1; 716 717 com_config(sc); 718 719 SET(sc->sc_hwflags, COM_HW_DEV_OK); 720 721 if (ISSET(sc->sc_hwflags, COM_HW_POLL)) 722 callout_schedule(&sc->sc_poll_callout, 1); 723 } 724 725 void 726 com_config(struct com_softc *sc) 727 { 728 struct com_regs *regsp = &sc->sc_regs; 729 730 /* Disable interrupts before configuring the device. */ 731 if (sc->sc_type == COM_TYPE_PXA2x0) 732 sc->sc_ier = IER_EUART; 733 else 734 sc->sc_ier = 0; 735 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 736 (void) CSR_READ_1(regsp, COM_REG_IIR); 737 738 /* Look for a Hayes ESP board. */ 739 if (sc->sc_type == COM_TYPE_HAYESP) { 740 741 /* Set 16550 compatibility mode */ 742 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 743 HAYESP_SETMODE); 744 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 745 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 746 HAYESP_MODE_SCALE); 747 748 /* Set RTS/CTS flow control */ 749 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 750 HAYESP_SETFLOWTYPE); 751 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 752 HAYESP_FLOW_RTS); 753 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 754 HAYESP_FLOW_CTS); 755 756 /* Set flow control levels */ 757 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 758 HAYESP_SETRXFLOW); 759 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 760 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 761 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 762 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 763 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 764 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 765 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 766 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 767 } 768 769 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 770 com_enable_debugport(sc); 771 } 772 773 #if 0 774 static int 775 comcngetc_detached(dev_t dev) 776 { 777 return 0; 778 } 779 780 static void 781 comcnputc_detached(dev_t dev, int c) 782 { 783 } 784 #endif 785 786 int 787 com_detach(device_t self, int flags) 788 { 789 struct com_softc *sc = device_private(self); 790 int maj, mn; 791 792 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 793 return EBUSY; 794 795 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 796 (flags & DETACH_SHUTDOWN) != 0) 797 return EBUSY; 798 799 if (sc->disable != NULL && sc->enabled != 0) { 800 (*sc->disable)(sc); 801 sc->enabled = 0; 802 } 803 804 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 805 comconsattached = 0; 806 cn_tab = NULL; 807 } 808 809 /* locate the major number */ 810 maj = cdevsw_lookup_major(&com_cdevsw); 811 812 /* Nuke the vnodes for any open instances. */ 813 mn = device_unit(self); 814 vdevgone(maj, mn, mn, VCHR); 815 816 mn |= COMDIALOUT_MASK; 817 vdevgone(maj, mn, mn, VCHR); 818 819 if (sc->sc_rbuf == NULL) { 820 /* 821 * Ring buffer allocation failed in the com_attach_subr, 822 * only the tty is allocated, and nothing else. 823 */ 824 tty_free(sc->sc_tty); 825 return 0; 826 } 827 828 /* Free the receive buffer. */ 829 free(sc->sc_rbuf, M_DEVBUF); 830 831 /* Detach and free the tty. */ 832 tty_detach(sc->sc_tty); 833 tty_free(sc->sc_tty); 834 835 /* Unhook the soft interrupt handler. */ 836 softint_disestablish(sc->sc_si); 837 838 #ifdef RND_COM 839 /* Unhook the entropy source. */ 840 rnd_detach_source(&sc->rnd_source); 841 #endif 842 callout_destroy(&sc->sc_diag_callout); 843 844 /* Destroy the lock. */ 845 mutex_destroy(&sc->sc_lock); 846 847 return (0); 848 } 849 850 void 851 com_shutdown(struct com_softc *sc) 852 { 853 struct tty *tp = sc->sc_tty; 854 855 mutex_spin_enter(&sc->sc_lock); 856 857 /* If we were asserting flow control, then deassert it. */ 858 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 859 com_hwiflow(sc); 860 861 /* Clear any break condition set with TIOCSBRK. */ 862 com_break(sc, 0); 863 864 /* 865 * Hang up if necessary. Wait a bit, so the other side has time to 866 * notice even if we immediately open the port again. 867 * Avoid tsleeping above splhigh(). 868 */ 869 if (ISSET(tp->t_cflag, HUPCL)) { 870 com_modem(sc, 0); 871 mutex_spin_exit(&sc->sc_lock); 872 /* XXX will only timeout */ 873 (void) kpause(ttclos, false, hz, NULL); 874 mutex_spin_enter(&sc->sc_lock); 875 } 876 877 /* Turn off interrupts. */ 878 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 879 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 880 if ((sc->sc_type == COM_TYPE_PXA2x0) || 881 (sc->sc_type == COM_TYPE_INGENIC) || 882 (sc->sc_type == COM_TYPE_TEGRA)) 883 sc->sc_ier |= IER_ERXTOUT; 884 } else 885 sc->sc_ier = 0; 886 887 if (sc->sc_type == COM_TYPE_PXA2x0) 888 sc->sc_ier |= IER_EUART; 889 890 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 891 892 mutex_spin_exit(&sc->sc_lock); 893 894 if (sc->disable) { 895 #ifdef DIAGNOSTIC 896 if (!sc->enabled) 897 panic("com_shutdown: not enabled?"); 898 #endif 899 (*sc->disable)(sc); 900 sc->enabled = 0; 901 } 902 } 903 904 int 905 comopen(dev_t dev, int flag, int mode, struct lwp *l) 906 { 907 struct com_softc *sc; 908 struct tty *tp; 909 int s; 910 int error; 911 912 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 913 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 914 sc->sc_rbuf == NULL) 915 return (ENXIO); 916 917 if (!device_is_active(sc->sc_dev)) 918 return (ENXIO); 919 920 #ifdef KGDB 921 /* 922 * If this is the kgdb port, no other use is permitted. 923 */ 924 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 925 return (EBUSY); 926 #endif 927 928 tp = sc->sc_tty; 929 930 /* 931 * If the device is exclusively for kernel use, deny userland 932 * open. 933 */ 934 if (ISSET(tp->t_state, TS_KERN_ONLY)) 935 return (EBUSY); 936 937 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 938 return (EBUSY); 939 940 s = spltty(); 941 942 /* 943 * Do the following iff this is a first open. 944 */ 945 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 946 struct termios t; 947 948 tp->t_dev = dev; 949 950 if (sc->enable) { 951 if ((*sc->enable)(sc)) { 952 splx(s); 953 aprint_error_dev(sc->sc_dev, 954 "device enable failed\n"); 955 return (EIO); 956 } 957 mutex_spin_enter(&sc->sc_lock); 958 sc->enabled = 1; 959 com_config(sc); 960 } else { 961 mutex_spin_enter(&sc->sc_lock); 962 } 963 964 /* Turn on interrupts. */ 965 sc->sc_ier = IER_ERXRDY | IER_ERLS; 966 if (!ISSET(tp->t_cflag, CLOCAL)) 967 sc->sc_ier |= IER_EMSC; 968 969 if (sc->sc_type == COM_TYPE_PXA2x0) 970 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 971 else if (sc->sc_type == COM_TYPE_INGENIC || 972 sc->sc_type == COM_TYPE_TEGRA) 973 sc->sc_ier |= IER_ERXTOUT; 974 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 975 976 /* Fetch the current modem control status, needed later. */ 977 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 978 979 /* Clear PPS capture state on first open. */ 980 mutex_spin_enter(&timecounter_lock); 981 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 982 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 983 pps_init(&sc->sc_pps_state); 984 mutex_spin_exit(&timecounter_lock); 985 986 mutex_spin_exit(&sc->sc_lock); 987 988 /* 989 * Initialize the termios status to the defaults. Add in the 990 * sticky bits from TIOCSFLAGS. 991 */ 992 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 993 t.c_ospeed = comcons_info.rate; 994 t.c_cflag = comcons_info.cflag; 995 } else { 996 t.c_ospeed = TTYDEF_SPEED; 997 t.c_cflag = TTYDEF_CFLAG; 998 } 999 t.c_ispeed = t.c_ospeed; 1000 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1001 SET(t.c_cflag, CLOCAL); 1002 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1003 SET(t.c_cflag, CRTSCTS); 1004 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1005 SET(t.c_cflag, MDMBUF); 1006 /* Make sure comparam() will do something. */ 1007 tp->t_ospeed = 0; 1008 (void) comparam(tp, &t); 1009 tp->t_iflag = TTYDEF_IFLAG; 1010 tp->t_oflag = TTYDEF_OFLAG; 1011 tp->t_lflag = TTYDEF_LFLAG; 1012 ttychars(tp); 1013 ttsetwater(tp); 1014 1015 mutex_spin_enter(&sc->sc_lock); 1016 1017 /* 1018 * Turn on DTR. We must always do this, even if carrier is not 1019 * present, because otherwise we'd have to use TIOCSDTR 1020 * immediately after setting CLOCAL, which applications do not 1021 * expect. We always assert DTR while the device is open 1022 * unless explicitly requested to deassert it. 1023 */ 1024 com_modem(sc, 1); 1025 1026 /* Clear the input ring, and unblock. */ 1027 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1028 sc->sc_rbavail = com_rbuf_size; 1029 com_iflush(sc); 1030 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1031 com_hwiflow(sc); 1032 1033 #ifdef COM_DEBUG 1034 if (com_debug) 1035 comstatus(sc, "comopen "); 1036 #endif 1037 1038 mutex_spin_exit(&sc->sc_lock); 1039 } 1040 1041 splx(s); 1042 1043 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1044 if (error) 1045 goto bad; 1046 1047 error = (*tp->t_linesw->l_open)(dev, tp); 1048 if (error) 1049 goto bad; 1050 1051 return (0); 1052 1053 bad: 1054 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1055 /* 1056 * We failed to open the device, and nobody else had it opened. 1057 * Clean up the state as appropriate. 1058 */ 1059 com_shutdown(sc); 1060 } 1061 1062 return (error); 1063 } 1064 1065 int 1066 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1067 { 1068 struct com_softc *sc = 1069 device_lookup_private(&com_cd, COMUNIT(dev)); 1070 struct tty *tp = sc->sc_tty; 1071 1072 /* XXX This is for cons.c. */ 1073 if (!ISSET(tp->t_state, TS_ISOPEN)) 1074 return (0); 1075 /* 1076 * If the device is exclusively for kernel use, deny userland 1077 * close. 1078 */ 1079 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1080 return (0); 1081 1082 (*tp->t_linesw->l_close)(tp, flag); 1083 ttyclose(tp); 1084 1085 if (COM_ISALIVE(sc) == 0) 1086 return (0); 1087 1088 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1089 /* 1090 * Although we got a last close, the device may still be in 1091 * use; e.g. if this was the dialout node, and there are still 1092 * processes waiting for carrier on the non-dialout node. 1093 */ 1094 com_shutdown(sc); 1095 } 1096 1097 return (0); 1098 } 1099 1100 int 1101 comread(dev_t dev, struct uio *uio, int flag) 1102 { 1103 struct com_softc *sc = 1104 device_lookup_private(&com_cd, COMUNIT(dev)); 1105 struct tty *tp = sc->sc_tty; 1106 1107 if (COM_ISALIVE(sc) == 0) 1108 return (EIO); 1109 1110 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1111 } 1112 1113 int 1114 comwrite(dev_t dev, struct uio *uio, int flag) 1115 { 1116 struct com_softc *sc = 1117 device_lookup_private(&com_cd, COMUNIT(dev)); 1118 struct tty *tp = sc->sc_tty; 1119 1120 if (COM_ISALIVE(sc) == 0) 1121 return (EIO); 1122 1123 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1124 } 1125 1126 int 1127 compoll(dev_t dev, int events, struct lwp *l) 1128 { 1129 struct com_softc *sc = 1130 device_lookup_private(&com_cd, COMUNIT(dev)); 1131 struct tty *tp = sc->sc_tty; 1132 1133 if (COM_ISALIVE(sc) == 0) 1134 return (POLLHUP); 1135 1136 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1137 } 1138 1139 struct tty * 1140 comtty(dev_t dev) 1141 { 1142 struct com_softc *sc = 1143 device_lookup_private(&com_cd, COMUNIT(dev)); 1144 struct tty *tp = sc->sc_tty; 1145 1146 return (tp); 1147 } 1148 1149 int 1150 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1151 { 1152 struct com_softc *sc; 1153 struct tty *tp; 1154 int error; 1155 1156 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1157 if (sc == NULL) 1158 return ENXIO; 1159 if (COM_ISALIVE(sc) == 0) 1160 return (EIO); 1161 1162 tp = sc->sc_tty; 1163 1164 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1165 if (error != EPASSTHROUGH) 1166 return (error); 1167 1168 error = ttioctl(tp, cmd, data, flag, l); 1169 if (error != EPASSTHROUGH) 1170 return (error); 1171 1172 error = 0; 1173 switch (cmd) { 1174 case TIOCSFLAGS: 1175 error = kauth_authorize_device_tty(l->l_cred, 1176 KAUTH_DEVICE_TTY_PRIVSET, tp); 1177 break; 1178 default: 1179 /* nothing */ 1180 break; 1181 } 1182 if (error) { 1183 return error; 1184 } 1185 1186 mutex_spin_enter(&sc->sc_lock); 1187 1188 switch (cmd) { 1189 case TIOCSBRK: 1190 com_break(sc, 1); 1191 break; 1192 1193 case TIOCCBRK: 1194 com_break(sc, 0); 1195 break; 1196 1197 case TIOCSDTR: 1198 com_modem(sc, 1); 1199 break; 1200 1201 case TIOCCDTR: 1202 com_modem(sc, 0); 1203 break; 1204 1205 case TIOCGFLAGS: 1206 *(int *)data = sc->sc_swflags; 1207 break; 1208 1209 case TIOCSFLAGS: 1210 sc->sc_swflags = *(int *)data; 1211 break; 1212 1213 case TIOCMSET: 1214 case TIOCMBIS: 1215 case TIOCMBIC: 1216 tiocm_to_com(sc, cmd, *(int *)data); 1217 break; 1218 1219 case TIOCMGET: 1220 *(int *)data = com_to_tiocm(sc); 1221 break; 1222 1223 case PPS_IOC_CREATE: 1224 case PPS_IOC_DESTROY: 1225 case PPS_IOC_GETPARAMS: 1226 case PPS_IOC_SETPARAMS: 1227 case PPS_IOC_GETCAP: 1228 case PPS_IOC_FETCH: 1229 #ifdef PPS_SYNC 1230 case PPS_IOC_KCBIND: 1231 #endif 1232 mutex_spin_enter(&timecounter_lock); 1233 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1234 mutex_spin_exit(&timecounter_lock); 1235 break; 1236 1237 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1238 mutex_spin_enter(&timecounter_lock); 1239 #ifndef PPS_TRAILING_EDGE 1240 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1241 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1242 #else 1243 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1244 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1245 #endif 1246 mutex_spin_exit(&timecounter_lock); 1247 break; 1248 1249 default: 1250 error = EPASSTHROUGH; 1251 break; 1252 } 1253 1254 mutex_spin_exit(&sc->sc_lock); 1255 1256 #ifdef COM_DEBUG 1257 if (com_debug) 1258 comstatus(sc, "comioctl "); 1259 #endif 1260 1261 return (error); 1262 } 1263 1264 integrate void 1265 com_schedrx(struct com_softc *sc) 1266 { 1267 1268 sc->sc_rx_ready = 1; 1269 1270 /* Wake up the poller. */ 1271 softint_schedule(sc->sc_si); 1272 } 1273 1274 void 1275 com_break(struct com_softc *sc, int onoff) 1276 { 1277 1278 if (onoff) 1279 SET(sc->sc_lcr, LCR_SBREAK); 1280 else 1281 CLR(sc->sc_lcr, LCR_SBREAK); 1282 1283 if (!sc->sc_heldchange) { 1284 if (sc->sc_tx_busy) { 1285 sc->sc_heldtbc = sc->sc_tbc; 1286 sc->sc_tbc = 0; 1287 sc->sc_heldchange = 1; 1288 } else 1289 com_loadchannelregs(sc); 1290 } 1291 } 1292 1293 void 1294 com_modem(struct com_softc *sc, int onoff) 1295 { 1296 1297 if (sc->sc_mcr_dtr == 0) 1298 return; 1299 1300 if (onoff) 1301 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1302 else 1303 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1304 1305 if (!sc->sc_heldchange) { 1306 if (sc->sc_tx_busy) { 1307 sc->sc_heldtbc = sc->sc_tbc; 1308 sc->sc_tbc = 0; 1309 sc->sc_heldchange = 1; 1310 } else 1311 com_loadchannelregs(sc); 1312 } 1313 } 1314 1315 void 1316 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1317 { 1318 u_char combits; 1319 1320 combits = 0; 1321 if (ISSET(ttybits, TIOCM_DTR)) 1322 SET(combits, MCR_DTR); 1323 if (ISSET(ttybits, TIOCM_RTS)) 1324 SET(combits, MCR_RTS); 1325 1326 switch (how) { 1327 case TIOCMBIC: 1328 CLR(sc->sc_mcr, combits); 1329 break; 1330 1331 case TIOCMBIS: 1332 SET(sc->sc_mcr, combits); 1333 break; 1334 1335 case TIOCMSET: 1336 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1337 SET(sc->sc_mcr, combits); 1338 break; 1339 } 1340 1341 if (!sc->sc_heldchange) { 1342 if (sc->sc_tx_busy) { 1343 sc->sc_heldtbc = sc->sc_tbc; 1344 sc->sc_tbc = 0; 1345 sc->sc_heldchange = 1; 1346 } else 1347 com_loadchannelregs(sc); 1348 } 1349 } 1350 1351 int 1352 com_to_tiocm(struct com_softc *sc) 1353 { 1354 u_char combits; 1355 int ttybits = 0; 1356 1357 combits = sc->sc_mcr; 1358 if (ISSET(combits, MCR_DTR)) 1359 SET(ttybits, TIOCM_DTR); 1360 if (ISSET(combits, MCR_RTS)) 1361 SET(ttybits, TIOCM_RTS); 1362 1363 combits = sc->sc_msr; 1364 if (sc->sc_type == COM_TYPE_INGENIC) { 1365 SET(ttybits, TIOCM_CD); 1366 } else { 1367 if (ISSET(combits, MSR_DCD)) 1368 SET(ttybits, TIOCM_CD); 1369 } 1370 if (ISSET(combits, MSR_CTS)) 1371 SET(ttybits, TIOCM_CTS); 1372 if (ISSET(combits, MSR_DSR)) 1373 SET(ttybits, TIOCM_DSR); 1374 if (ISSET(combits, MSR_RI | MSR_TERI)) 1375 SET(ttybits, TIOCM_RI); 1376 1377 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1378 SET(ttybits, TIOCM_LE); 1379 1380 return (ttybits); 1381 } 1382 1383 static u_char 1384 cflag2lcr(tcflag_t cflag) 1385 { 1386 u_char lcr = 0; 1387 1388 switch (ISSET(cflag, CSIZE)) { 1389 case CS5: 1390 SET(lcr, LCR_5BITS); 1391 break; 1392 case CS6: 1393 SET(lcr, LCR_6BITS); 1394 break; 1395 case CS7: 1396 SET(lcr, LCR_7BITS); 1397 break; 1398 case CS8: 1399 SET(lcr, LCR_8BITS); 1400 break; 1401 } 1402 if (ISSET(cflag, PARENB)) { 1403 SET(lcr, LCR_PENAB); 1404 if (!ISSET(cflag, PARODD)) 1405 SET(lcr, LCR_PEVEN); 1406 } 1407 if (ISSET(cflag, CSTOPB)) 1408 SET(lcr, LCR_STOPB); 1409 1410 return (lcr); 1411 } 1412 1413 int 1414 comparam(struct tty *tp, struct termios *t) 1415 { 1416 struct com_softc *sc = 1417 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1418 int ospeed; 1419 u_char lcr; 1420 1421 if (COM_ISALIVE(sc) == 0) 1422 return (EIO); 1423 1424 if (sc->sc_type == COM_TYPE_HAYESP) { 1425 int prescaler, speed; 1426 1427 /* 1428 * Calculate UART clock prescaler. It should be in 1429 * range of 0 .. 3. 1430 */ 1431 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1432 prescaler++, speed /= 2) 1433 if ((ospeed = comspeed(speed, sc->sc_frequency, 1434 sc->sc_type)) > 0) 1435 break; 1436 1437 if (prescaler == 4) 1438 return (EINVAL); 1439 sc->sc_prescaler = prescaler; 1440 } else 1441 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1442 1443 /* Check requested parameters. */ 1444 if (ospeed < 0) 1445 return (EINVAL); 1446 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1447 return (EINVAL); 1448 1449 /* 1450 * For the console, always force CLOCAL and !HUPCL, so that the port 1451 * is always active. 1452 */ 1453 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1454 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1455 SET(t->c_cflag, CLOCAL); 1456 CLR(t->c_cflag, HUPCL); 1457 } 1458 1459 /* 1460 * If there were no changes, don't do anything. This avoids dropping 1461 * input and improves performance when all we did was frob things like 1462 * VMIN and VTIME. 1463 */ 1464 if (tp->t_ospeed == t->c_ospeed && 1465 tp->t_cflag == t->c_cflag) 1466 return (0); 1467 1468 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1469 1470 mutex_spin_enter(&sc->sc_lock); 1471 1472 sc->sc_lcr = lcr; 1473 1474 /* 1475 * If we're not in a mode that assumes a connection is present, then 1476 * ignore carrier changes. 1477 */ 1478 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1479 sc->sc_msr_dcd = 0; 1480 else 1481 sc->sc_msr_dcd = MSR_DCD; 1482 /* 1483 * Set the flow control pins depending on the current flow control 1484 * mode. 1485 */ 1486 if (ISSET(t->c_cflag, CRTSCTS)) { 1487 sc->sc_mcr_dtr = MCR_DTR; 1488 sc->sc_mcr_rts = MCR_RTS; 1489 sc->sc_msr_cts = MSR_CTS; 1490 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1491 SET(sc->sc_mcr, MCR_AFE); 1492 } else { 1493 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1494 } 1495 } else if (ISSET(t->c_cflag, MDMBUF)) { 1496 /* 1497 * For DTR/DCD flow control, make sure we don't toggle DTR for 1498 * carrier detection. 1499 */ 1500 sc->sc_mcr_dtr = 0; 1501 sc->sc_mcr_rts = MCR_DTR; 1502 sc->sc_msr_cts = MSR_DCD; 1503 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1504 CLR(sc->sc_mcr, MCR_AFE); 1505 } else { 1506 sc->sc_efr = 0; 1507 } 1508 } else { 1509 /* 1510 * If no flow control, then always set RTS. This will make 1511 * the other side happy if it mistakenly thinks we're doing 1512 * RTS/CTS flow control. 1513 */ 1514 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1515 sc->sc_mcr_rts = 0; 1516 sc->sc_msr_cts = 0; 1517 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1518 CLR(sc->sc_mcr, MCR_AFE); 1519 } else { 1520 sc->sc_efr = 0; 1521 } 1522 if (ISSET(sc->sc_mcr, MCR_DTR)) 1523 SET(sc->sc_mcr, MCR_RTS); 1524 else 1525 CLR(sc->sc_mcr, MCR_RTS); 1526 } 1527 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1528 1529 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1530 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1531 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1532 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1533 1534 sc->sc_dlbl = ospeed; 1535 sc->sc_dlbh = ospeed >> 8; 1536 1537 /* 1538 * Set the FIFO threshold based on the receive speed. 1539 * 1540 * * If it's a low speed, it's probably a mouse or some other 1541 * interactive device, so set the threshold low. 1542 * * If it's a high speed, trim the trigger level down to prevent 1543 * overflows. 1544 * * Otherwise set it a bit higher. 1545 */ 1546 if (sc->sc_type == COM_TYPE_HAYESP) { 1547 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1548 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1549 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1550 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1551 if (t->c_ospeed <= 1200) 1552 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1553 else if (t->c_ospeed <= 38400) 1554 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1555 else 1556 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1557 } else { 1558 sc->sc_fifo = 0; 1559 } 1560 1561 if (sc->sc_type == COM_TYPE_INGENIC) 1562 sc->sc_fifo |= FIFO_UART_ON; 1563 1564 /* And copy to tty. */ 1565 tp->t_ispeed = t->c_ospeed; 1566 tp->t_ospeed = t->c_ospeed; 1567 tp->t_cflag = t->c_cflag; 1568 1569 if (!sc->sc_heldchange) { 1570 if (sc->sc_tx_busy) { 1571 sc->sc_heldtbc = sc->sc_tbc; 1572 sc->sc_tbc = 0; 1573 sc->sc_heldchange = 1; 1574 } else 1575 com_loadchannelregs(sc); 1576 } 1577 1578 if (!ISSET(t->c_cflag, CHWFLOW)) { 1579 /* Disable the high water mark. */ 1580 sc->sc_r_hiwat = 0; 1581 sc->sc_r_lowat = 0; 1582 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1583 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1584 com_schedrx(sc); 1585 } 1586 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1587 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1588 com_hwiflow(sc); 1589 } 1590 } else { 1591 sc->sc_r_hiwat = com_rbuf_hiwat; 1592 sc->sc_r_lowat = com_rbuf_lowat; 1593 } 1594 1595 mutex_spin_exit(&sc->sc_lock); 1596 1597 /* 1598 * Update the tty layer's idea of the carrier bit, in case we changed 1599 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1600 * explicit request. 1601 */ 1602 if (sc->sc_type == COM_TYPE_INGENIC) { 1603 /* no DCD here */ 1604 (void) (*tp->t_linesw->l_modem)(tp, 1); 1605 } else 1606 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1607 1608 #ifdef COM_DEBUG 1609 if (com_debug) 1610 comstatus(sc, "comparam "); 1611 #endif 1612 1613 if (!ISSET(t->c_cflag, CHWFLOW)) { 1614 if (sc->sc_tx_stopped) { 1615 sc->sc_tx_stopped = 0; 1616 comstart(tp); 1617 } 1618 } 1619 1620 return (0); 1621 } 1622 1623 void 1624 com_iflush(struct com_softc *sc) 1625 { 1626 struct com_regs *regsp = &sc->sc_regs; 1627 uint8_t fifo; 1628 #ifdef DIAGNOSTIC 1629 int reg; 1630 #endif 1631 int timo; 1632 1633 #ifdef DIAGNOSTIC 1634 reg = 0xffff; 1635 #endif 1636 timo = 50000; 1637 /* flush any pending I/O */ 1638 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1639 && --timo) 1640 #ifdef DIAGNOSTIC 1641 reg = 1642 #else 1643 (void) 1644 #endif 1645 CSR_READ_1(regsp, COM_REG_RXDATA); 1646 #ifdef DIAGNOSTIC 1647 if (!timo) 1648 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1649 #endif 1650 1651 switch (sc->sc_type) { 1652 case COM_TYPE_16750: 1653 case COM_TYPE_DW_APB: 1654 /* 1655 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1656 * This should prevent triggering busy interrupt while 1657 * manipulating divisors. 1658 */ 1659 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1660 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1661 CSR_WRITE_1(regsp, COM_REG_FIFO, 1662 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1663 delay(100); 1664 break; 1665 } 1666 } 1667 1668 void 1669 com_loadchannelregs(struct com_softc *sc) 1670 { 1671 struct com_regs *regsp = &sc->sc_regs; 1672 1673 /* XXXXX necessary? */ 1674 com_iflush(sc); 1675 1676 if (sc->sc_type == COM_TYPE_PXA2x0) 1677 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1678 else 1679 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1680 1681 if (sc->sc_type == COM_TYPE_OMAP) { 1682 /* disable before changing settings */ 1683 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1684 } 1685 1686 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1687 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1688 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1689 /* no EFR on alchemy */ 1690 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1691 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1692 } 1693 if (sc->sc_type == COM_TYPE_AU1x00) { 1694 /* alchemy has single separate 16-bit clock divisor register */ 1695 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1696 (sc->sc_dlbh << 8)); 1697 } else { 1698 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1699 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1700 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1701 } 1702 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1703 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1704 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1705 if (sc->sc_type == COM_TYPE_HAYESP) { 1706 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1707 HAYESP_SETPRESCALER); 1708 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1709 sc->sc_prescaler); 1710 } 1711 if (sc->sc_type == COM_TYPE_OMAP) { 1712 /* setup the fifos. the FCR value is not used as long 1713 as SCR[6] and SCR[7] are 0, which they are at reset 1714 and we never touch the SCR register */ 1715 uint8_t rx_fifo_trig = 40; 1716 uint8_t tx_fifo_trig = 60; 1717 uint8_t rx_start = 8; 1718 uint8_t rx_halt = 60; 1719 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1720 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1721 1722 /* enable access to TCR & TLR */ 1723 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1724 1725 /* write tcr and tlr values */ 1726 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1727 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1728 1729 /* disable access to TCR & TLR */ 1730 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1731 1732 /* enable again, but mode is based on speed */ 1733 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1734 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1735 } else { 1736 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1737 } 1738 } 1739 1740 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1741 } 1742 1743 int 1744 comhwiflow(struct tty *tp, int block) 1745 { 1746 struct com_softc *sc = 1747 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1748 1749 if (COM_ISALIVE(sc) == 0) 1750 return (0); 1751 1752 if (sc->sc_mcr_rts == 0) 1753 return (0); 1754 1755 mutex_spin_enter(&sc->sc_lock); 1756 1757 if (block) { 1758 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1759 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1760 com_hwiflow(sc); 1761 } 1762 } else { 1763 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1764 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1765 com_schedrx(sc); 1766 } 1767 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1768 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1769 com_hwiflow(sc); 1770 } 1771 } 1772 1773 mutex_spin_exit(&sc->sc_lock); 1774 return (1); 1775 } 1776 1777 /* 1778 * (un)block input via hw flowcontrol 1779 */ 1780 void 1781 com_hwiflow(struct com_softc *sc) 1782 { 1783 struct com_regs *regsp= &sc->sc_regs; 1784 1785 if (sc->sc_mcr_rts == 0) 1786 return; 1787 1788 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1789 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1790 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1791 } else { 1792 SET(sc->sc_mcr, sc->sc_mcr_rts); 1793 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1794 } 1795 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1796 } 1797 1798 1799 void 1800 comstart(struct tty *tp) 1801 { 1802 struct com_softc *sc = 1803 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1804 struct com_regs *regsp = &sc->sc_regs; 1805 int s; 1806 1807 if (COM_ISALIVE(sc) == 0) 1808 return; 1809 1810 s = spltty(); 1811 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1812 goto out; 1813 if (sc->sc_tx_stopped) 1814 goto out; 1815 if (!ttypull(tp)) 1816 goto out; 1817 1818 /* Grab the first contiguous region of buffer space. */ 1819 { 1820 u_char *tba; 1821 int tbc; 1822 1823 tba = tp->t_outq.c_cf; 1824 tbc = ndqb(&tp->t_outq, 0); 1825 1826 mutex_spin_enter(&sc->sc_lock); 1827 1828 sc->sc_tba = tba; 1829 sc->sc_tbc = tbc; 1830 } 1831 1832 SET(tp->t_state, TS_BUSY); 1833 sc->sc_tx_busy = 1; 1834 1835 /* Enable transmit completion interrupts if necessary. */ 1836 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1837 SET(sc->sc_ier, IER_ETXRDY); 1838 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1839 } 1840 1841 /* Output the first chunk of the contiguous buffer. */ 1842 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1843 u_int n; 1844 1845 n = sc->sc_tbc; 1846 if (n > sc->sc_fifolen) 1847 n = sc->sc_fifolen; 1848 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1849 sc->sc_tbc -= n; 1850 sc->sc_tba += n; 1851 } 1852 1853 mutex_spin_exit(&sc->sc_lock); 1854 out: 1855 splx(s); 1856 return; 1857 } 1858 1859 /* 1860 * Stop output on a line. 1861 */ 1862 void 1863 comstop(struct tty *tp, int flag) 1864 { 1865 struct com_softc *sc = 1866 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1867 1868 mutex_spin_enter(&sc->sc_lock); 1869 if (ISSET(tp->t_state, TS_BUSY)) { 1870 /* Stop transmitting at the next chunk. */ 1871 sc->sc_tbc = 0; 1872 sc->sc_heldtbc = 0; 1873 if (!ISSET(tp->t_state, TS_TTSTOP)) 1874 SET(tp->t_state, TS_FLUSH); 1875 } 1876 mutex_spin_exit(&sc->sc_lock); 1877 } 1878 1879 void 1880 comdiag(void *arg) 1881 { 1882 struct com_softc *sc = arg; 1883 int overflows, floods; 1884 1885 mutex_spin_enter(&sc->sc_lock); 1886 overflows = sc->sc_overflows; 1887 sc->sc_overflows = 0; 1888 floods = sc->sc_floods; 1889 sc->sc_floods = 0; 1890 sc->sc_errors = 0; 1891 mutex_spin_exit(&sc->sc_lock); 1892 1893 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1894 device_xname(sc->sc_dev), 1895 overflows, overflows == 1 ? "" : "s", 1896 floods, floods == 1 ? "" : "s"); 1897 } 1898 1899 integrate void 1900 com_rxsoft(struct com_softc *sc, struct tty *tp) 1901 { 1902 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1903 u_char *get, *end; 1904 u_int cc, scc; 1905 u_char lsr; 1906 int code; 1907 1908 end = sc->sc_ebuf; 1909 get = sc->sc_rbget; 1910 scc = cc = com_rbuf_size - sc->sc_rbavail; 1911 1912 if (cc == com_rbuf_size) { 1913 sc->sc_floods++; 1914 if (sc->sc_errors++ == 0) 1915 callout_reset(&sc->sc_diag_callout, 60 * hz, 1916 comdiag, sc); 1917 } 1918 1919 /* If not yet open, drop the entire buffer content here */ 1920 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1921 get += cc << 1; 1922 if (get >= end) 1923 get -= com_rbuf_size << 1; 1924 cc = 0; 1925 } 1926 while (cc) { 1927 code = get[0]; 1928 lsr = get[1]; 1929 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1930 if (ISSET(lsr, LSR_OE)) { 1931 sc->sc_overflows++; 1932 if (sc->sc_errors++ == 0) 1933 callout_reset(&sc->sc_diag_callout, 1934 60 * hz, comdiag, sc); 1935 } 1936 if (ISSET(lsr, LSR_BI | LSR_FE)) 1937 SET(code, TTY_FE); 1938 if (ISSET(lsr, LSR_PE)) 1939 SET(code, TTY_PE); 1940 } 1941 if ((*rint)(code, tp) == -1) { 1942 /* 1943 * The line discipline's buffer is out of space. 1944 */ 1945 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1946 /* 1947 * We're either not using flow control, or the 1948 * line discipline didn't tell us to block for 1949 * some reason. Either way, we have no way to 1950 * know when there's more space available, so 1951 * just drop the rest of the data. 1952 */ 1953 get += cc << 1; 1954 if (get >= end) 1955 get -= com_rbuf_size << 1; 1956 cc = 0; 1957 } else { 1958 /* 1959 * Don't schedule any more receive processing 1960 * until the line discipline tells us there's 1961 * space available (through comhwiflow()). 1962 * Leave the rest of the data in the input 1963 * buffer. 1964 */ 1965 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1966 } 1967 break; 1968 } 1969 get += 2; 1970 if (get >= end) 1971 get = sc->sc_rbuf; 1972 cc--; 1973 } 1974 1975 if (cc != scc) { 1976 sc->sc_rbget = get; 1977 mutex_spin_enter(&sc->sc_lock); 1978 1979 cc = sc->sc_rbavail += scc - cc; 1980 /* Buffers should be ok again, release possible block. */ 1981 if (cc >= sc->sc_r_lowat) { 1982 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1983 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1984 SET(sc->sc_ier, IER_ERXRDY); 1985 if (sc->sc_type == COM_TYPE_PXA2x0) 1986 SET(sc->sc_ier, IER_ERXTOUT); 1987 if (sc->sc_type == COM_TYPE_INGENIC || 1988 sc->sc_type == COM_TYPE_TEGRA) 1989 SET(sc->sc_ier, IER_ERXTOUT); 1990 1991 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 1992 sc->sc_ier); 1993 } 1994 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1995 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1996 com_hwiflow(sc); 1997 } 1998 } 1999 mutex_spin_exit(&sc->sc_lock); 2000 } 2001 } 2002 2003 integrate void 2004 com_txsoft(struct com_softc *sc, struct tty *tp) 2005 { 2006 2007 CLR(tp->t_state, TS_BUSY); 2008 if (ISSET(tp->t_state, TS_FLUSH)) 2009 CLR(tp->t_state, TS_FLUSH); 2010 else 2011 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2012 (*tp->t_linesw->l_start)(tp); 2013 } 2014 2015 integrate void 2016 com_stsoft(struct com_softc *sc, struct tty *tp) 2017 { 2018 u_char msr, delta; 2019 2020 mutex_spin_enter(&sc->sc_lock); 2021 msr = sc->sc_msr; 2022 delta = sc->sc_msr_delta; 2023 sc->sc_msr_delta = 0; 2024 mutex_spin_exit(&sc->sc_lock); 2025 2026 if (ISSET(delta, sc->sc_msr_dcd)) { 2027 /* 2028 * Inform the tty layer that carrier detect changed. 2029 */ 2030 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2031 } 2032 2033 if (ISSET(delta, sc->sc_msr_cts)) { 2034 /* Block or unblock output according to flow control. */ 2035 if (ISSET(msr, sc->sc_msr_cts)) { 2036 sc->sc_tx_stopped = 0; 2037 (*tp->t_linesw->l_start)(tp); 2038 } else { 2039 sc->sc_tx_stopped = 1; 2040 } 2041 } 2042 2043 #ifdef COM_DEBUG 2044 if (com_debug) 2045 comstatus(sc, "com_stsoft"); 2046 #endif 2047 } 2048 2049 void 2050 comsoft(void *arg) 2051 { 2052 struct com_softc *sc = arg; 2053 struct tty *tp; 2054 2055 if (COM_ISALIVE(sc) == 0) 2056 return; 2057 2058 tp = sc->sc_tty; 2059 2060 if (sc->sc_rx_ready) { 2061 sc->sc_rx_ready = 0; 2062 com_rxsoft(sc, tp); 2063 } 2064 2065 if (sc->sc_st_check) { 2066 sc->sc_st_check = 0; 2067 com_stsoft(sc, tp); 2068 } 2069 2070 if (sc->sc_tx_done) { 2071 sc->sc_tx_done = 0; 2072 com_txsoft(sc, tp); 2073 } 2074 } 2075 2076 int 2077 comintr(void *arg) 2078 { 2079 struct com_softc *sc = arg; 2080 struct com_regs *regsp = &sc->sc_regs; 2081 2082 u_char *put, *end; 2083 u_int cc; 2084 u_char lsr, iir; 2085 2086 if (COM_ISALIVE(sc) == 0) 2087 return (0); 2088 2089 KASSERT(regsp != NULL); 2090 2091 mutex_spin_enter(&sc->sc_lock); 2092 iir = CSR_READ_1(regsp, COM_REG_IIR); 2093 2094 /* Handle ns16750-specific busy interrupt. */ 2095 if (sc->sc_type == COM_TYPE_16750 && 2096 (iir & IIR_BUSY) == IIR_BUSY) { 2097 for (int timeout = 10000; 2098 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2099 if (timeout <= 0) { 2100 aprint_error_dev(sc->sc_dev, 2101 "timeout while waiting for BUSY interrupt " 2102 "acknowledge\n"); 2103 mutex_spin_exit(&sc->sc_lock); 2104 return (0); 2105 } 2106 2107 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2108 iir = CSR_READ_1(regsp, COM_REG_IIR); 2109 } 2110 2111 /* DesignWare APB UART BUSY interrupt */ 2112 if (sc->sc_type == COM_TYPE_DW_APB && 2113 (iir & IIR_BUSY) == IIR_BUSY) { 2114 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2115 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2116 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2117 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2118 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2119 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2120 CSR_WRITE_1(regsp, COM_REG_HALT, 2121 HALT_CHCFG_EN | HALT_CHCFG_UD); 2122 for (int timeout = 10000000; 2123 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2124 timeout--) { 2125 if (timeout <= 0) { 2126 aprint_error_dev(sc->sc_dev, 2127 "timeout while waiting for HALT " 2128 "update acknowledge 0x%x 0x%x\n", 2129 CSR_READ_1(regsp, COM_REG_HALT), 2130 CSR_READ_1(regsp, COM_REG_USR)); 2131 break; 2132 } 2133 } 2134 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2135 (void)CSR_READ_1(regsp, COM_REG_USR); 2136 } else { 2137 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2138 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2139 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2140 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2141 } 2142 } 2143 2144 if (ISSET(iir, IIR_NOPEND)) { 2145 mutex_spin_exit(&sc->sc_lock); 2146 return (0); 2147 } 2148 2149 end = sc->sc_ebuf; 2150 put = sc->sc_rbput; 2151 cc = sc->sc_rbavail; 2152 2153 again: do { 2154 u_char msr, delta; 2155 2156 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2157 if (ISSET(lsr, LSR_BI)) { 2158 int cn_trapped = 0; /* see above: cn_trap() */ 2159 2160 cn_check_magic(sc->sc_tty->t_dev, 2161 CNC_BREAK, com_cnm_state); 2162 if (cn_trapped) 2163 continue; 2164 #if defined(KGDB) && !defined(DDB) 2165 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2166 kgdb_connect(1); 2167 continue; 2168 } 2169 #endif 2170 } 2171 2172 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2173 lsr |= LSR_RXRDY; 2174 2175 if (ISSET(lsr, LSR_RCV_MASK) && 2176 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2177 while (cc > 0) { 2178 int cn_trapped = 0; 2179 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2180 put[1] = lsr; 2181 cn_check_magic(sc->sc_tty->t_dev, 2182 put[0], com_cnm_state); 2183 if (cn_trapped) 2184 goto next; 2185 put += 2; 2186 if (put >= end) 2187 put = sc->sc_rbuf; 2188 cc--; 2189 next: 2190 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2191 if (!ISSET(lsr, LSR_RCV_MASK)) 2192 break; 2193 } 2194 2195 /* 2196 * Current string of incoming characters ended because 2197 * no more data was available or we ran out of space. 2198 * Schedule a receive event if any data was received. 2199 * If we're out of space, turn off receive interrupts. 2200 */ 2201 sc->sc_rbput = put; 2202 sc->sc_rbavail = cc; 2203 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2204 sc->sc_rx_ready = 1; 2205 2206 /* 2207 * See if we are in danger of overflowing a buffer. If 2208 * so, use hardware flow control to ease the pressure. 2209 */ 2210 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2211 cc < sc->sc_r_hiwat) { 2212 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2213 com_hwiflow(sc); 2214 } 2215 2216 /* 2217 * If we're out of space, disable receive interrupts 2218 * until the queue has drained a bit. 2219 */ 2220 if (!cc) { 2221 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2222 switch (sc->sc_type) { 2223 case COM_TYPE_PXA2x0: 2224 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2225 break; 2226 case COM_TYPE_INGENIC: 2227 case COM_TYPE_TEGRA: 2228 CLR(sc->sc_ier, 2229 IER_ERXRDY | IER_ERXTOUT); 2230 break; 2231 default: 2232 CLR(sc->sc_ier, IER_ERXRDY); 2233 break; 2234 } 2235 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2236 } 2237 } else { 2238 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2239 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2240 continue; 2241 } 2242 } 2243 2244 msr = CSR_READ_1(regsp, COM_REG_MSR); 2245 delta = msr ^ sc->sc_msr; 2246 sc->sc_msr = msr; 2247 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2248 (delta & MSR_DCD)) { 2249 mutex_spin_enter(&timecounter_lock); 2250 pps_capture(&sc->sc_pps_state); 2251 pps_event(&sc->sc_pps_state, 2252 (msr & MSR_DCD) ? 2253 PPS_CAPTUREASSERT : 2254 PPS_CAPTURECLEAR); 2255 mutex_spin_exit(&timecounter_lock); 2256 } 2257 2258 /* 2259 * Process normal status changes 2260 */ 2261 if (ISSET(delta, sc->sc_msr_mask)) { 2262 SET(sc->sc_msr_delta, delta); 2263 2264 /* 2265 * Stop output immediately if we lose the output 2266 * flow control signal or carrier detect. 2267 */ 2268 if (ISSET(~msr, sc->sc_msr_mask)) { 2269 sc->sc_tbc = 0; 2270 sc->sc_heldtbc = 0; 2271 #ifdef COM_DEBUG 2272 if (com_debug) 2273 comstatus(sc, "comintr "); 2274 #endif 2275 } 2276 2277 sc->sc_st_check = 1; 2278 } 2279 } while (!ISSET((iir = 2280 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2281 /* 2282 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2283 * by IIR read, so we can't do this way: `process all interrupts, 2284 * then do TX if possible'. 2285 */ 2286 (iir & IIR_IMASK) != IIR_TXRDY); 2287 2288 /* 2289 * Read LSR again, since there may be an interrupt between 2290 * the last LSR read and IIR read above. 2291 */ 2292 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2293 2294 /* 2295 * See if data can be transmitted as well. 2296 * Schedule tx done event if no data left 2297 * and tty was marked busy. 2298 */ 2299 if (ISSET(lsr, LSR_TXRDY)) { 2300 /* 2301 * If we've delayed a parameter change, do it now, and restart 2302 * output. 2303 */ 2304 if (sc->sc_heldchange) { 2305 com_loadchannelregs(sc); 2306 sc->sc_heldchange = 0; 2307 sc->sc_tbc = sc->sc_heldtbc; 2308 sc->sc_heldtbc = 0; 2309 } 2310 2311 /* Output the next chunk of the contiguous buffer, if any. */ 2312 if (sc->sc_tbc > 0) { 2313 u_int n; 2314 2315 n = sc->sc_tbc; 2316 if (n > sc->sc_fifolen) 2317 n = sc->sc_fifolen; 2318 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2319 sc->sc_tbc -= n; 2320 sc->sc_tba += n; 2321 } else { 2322 /* Disable transmit completion interrupts if necessary. */ 2323 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2324 CLR(sc->sc_ier, IER_ETXRDY); 2325 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2326 } 2327 if (sc->sc_tx_busy) { 2328 sc->sc_tx_busy = 0; 2329 sc->sc_tx_done = 1; 2330 } 2331 } 2332 } 2333 2334 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2335 goto again; 2336 2337 mutex_spin_exit(&sc->sc_lock); 2338 2339 /* Wake up the poller. */ 2340 softint_schedule(sc->sc_si); 2341 2342 #ifdef RND_COM 2343 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2344 #endif 2345 2346 return (1); 2347 } 2348 2349 /* 2350 * The following functions are polled getc and putc routines, shared 2351 * by the console and kgdb glue. 2352 * 2353 * The read-ahead code is so that you can detect pending in-band 2354 * cn_magic in polled mode while doing output rather than having to 2355 * wait until the kernel decides it needs input. 2356 */ 2357 2358 #define MAX_READAHEAD 20 2359 static int com_readahead[MAX_READAHEAD]; 2360 static int com_readaheadcount = 0; 2361 2362 int 2363 com_common_getc(dev_t dev, struct com_regs *regsp) 2364 { 2365 int s = splserial(); 2366 u_char stat, c; 2367 2368 /* got a character from reading things earlier */ 2369 if (com_readaheadcount > 0) { 2370 int i; 2371 2372 c = com_readahead[0]; 2373 for (i = 1; i < com_readaheadcount; i++) { 2374 com_readahead[i-1] = com_readahead[i]; 2375 } 2376 com_readaheadcount--; 2377 splx(s); 2378 return (c); 2379 } 2380 2381 /* don't block until a character becomes available */ 2382 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2383 splx(s); 2384 return -1; 2385 } 2386 2387 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2388 stat = CSR_READ_1(regsp, COM_REG_IIR); 2389 { 2390 int cn_trapped = 0; /* required by cn_trap, see above */ 2391 #ifdef DDB 2392 extern int db_active; 2393 if (!db_active) 2394 #endif 2395 cn_check_magic(dev, c, com_cnm_state); 2396 } 2397 splx(s); 2398 return (c); 2399 } 2400 2401 static void 2402 com_common_putc(dev_t dev, struct com_regs *regsp, int c) 2403 { 2404 int s = splserial(); 2405 int cin, stat, timo; 2406 2407 if (com_readaheadcount < MAX_READAHEAD 2408 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2409 int cn_trapped = 0; 2410 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2411 stat = CSR_READ_1(regsp, COM_REG_IIR); 2412 cn_check_magic(dev, cin, com_cnm_state); 2413 com_readahead[com_readaheadcount++] = cin; 2414 } 2415 2416 /* wait for any pending transmission to finish */ 2417 timo = 150000; 2418 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2419 continue; 2420 2421 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2422 COM_BARRIER(regsp, BR | BW); 2423 2424 splx(s); 2425 } 2426 2427 /* 2428 * Initialize UART for use as console or KGDB line. 2429 */ 2430 int 2431 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2432 tcflag_t cflag) 2433 { 2434 2435 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2436 ®sp->cr_ioh)) 2437 return (ENOMEM); /* ??? */ 2438 2439 if (type == COM_TYPE_OMAP) { 2440 /* disable before changing settings */ 2441 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2442 } 2443 2444 rate = comspeed(rate, frequency, type); 2445 if (rate != -1) { 2446 if (type == COM_TYPE_AU1x00) { 2447 /* no EFR on alchemy */ 2448 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2449 } else { 2450 if ((type != COM_TYPE_16550_NOERS) && 2451 (type != COM_TYPE_INGENIC)) { 2452 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2453 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2454 } 2455 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2456 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2457 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2458 } 2459 } 2460 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2461 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2462 2463 if (type == COM_TYPE_INGENIC) { 2464 CSR_WRITE_1(regsp, COM_REG_FIFO, 2465 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2466 FIFO_TRIGGER_1 | FIFO_UART_ON); 2467 } else { 2468 CSR_WRITE_1(regsp, COM_REG_FIFO, 2469 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2470 FIFO_TRIGGER_1); 2471 } 2472 2473 if (type == COM_TYPE_OMAP) { 2474 /* setup the fifos. the FCR value is not used as long 2475 as SCR[6] and SCR[7] are 0, which they are at reset 2476 and we never touch the SCR register */ 2477 uint8_t rx_fifo_trig = 40; 2478 uint8_t tx_fifo_trig = 60; 2479 uint8_t rx_start = 8; 2480 uint8_t rx_halt = 60; 2481 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2482 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2483 2484 /* enable access to TCR & TLR */ 2485 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2486 2487 /* write tcr and tlr values */ 2488 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2489 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2490 2491 /* disable access to TCR & TLR */ 2492 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2493 2494 /* enable again, but mode is based on speed */ 2495 if (rate > 230400) { 2496 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2497 } else { 2498 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2499 } 2500 } 2501 2502 if (type == COM_TYPE_PXA2x0) 2503 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2504 else 2505 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2506 2507 return (0); 2508 } 2509 2510 int 2511 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2512 tcflag_t cflag) 2513 { 2514 int res; 2515 2516 comcons_info.regs = *regsp; 2517 2518 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2519 if (res) 2520 return (res); 2521 2522 cn_tab = &comcons; 2523 cn_init_magic(&com_cnm_state); 2524 cn_set_magic("\047\001"); /* default magic is BREAK */ 2525 2526 comcons_info.frequency = frequency; 2527 comcons_info.type = type; 2528 comcons_info.rate = rate; 2529 comcons_info.cflag = cflag; 2530 2531 return (0); 2532 } 2533 2534 int 2535 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2536 int type, tcflag_t cflag) 2537 { 2538 struct com_regs regs; 2539 2540 /*XXX*/ 2541 bus_space_handle_t dummy_bsh; 2542 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2543 2544 /* 2545 * dummy_bsh required because com_init_regs() wants it. A 2546 * real bus_space_handle will be filled in by cominit() later. 2547 * XXXJRT Detangle this mess eventually, plz. 2548 */ 2549 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2550 2551 return comcnattach1(®s, rate, frequency, type, cflag); 2552 } 2553 2554 static int 2555 comcnreattach(void) 2556 { 2557 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2558 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2559 } 2560 2561 int 2562 comcngetc(dev_t dev) 2563 { 2564 2565 return (com_common_getc(dev, &comcons_info.regs)); 2566 } 2567 2568 /* 2569 * Console kernel output character routine. 2570 */ 2571 void 2572 comcnputc(dev_t dev, int c) 2573 { 2574 2575 com_common_putc(dev, &comcons_info.regs, c); 2576 } 2577 2578 void 2579 comcnpollc(dev_t dev, int on) 2580 { 2581 2582 com_readaheadcount = 0; 2583 } 2584 2585 #ifdef KGDB 2586 int 2587 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2588 tcflag_t cflag) 2589 { 2590 int res; 2591 2592 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2593 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2594 #if !defined(DDB) 2595 return (EBUSY); /* cannot share with console */ 2596 #else 2597 comkgdbregs = *regsp; 2598 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2599 #endif 2600 } else { 2601 comkgdbregs = *regsp; 2602 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2603 if (res) 2604 return (res); 2605 2606 /* 2607 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2608 * expects this to be initialized 2609 */ 2610 cn_init_magic(&com_cnm_state); 2611 cn_set_magic("\047\001"); 2612 } 2613 2614 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2615 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2616 2617 return (0); 2618 } 2619 2620 int 2621 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2622 int frequency, int type, tcflag_t cflag) 2623 { 2624 struct com_regs regs; 2625 2626 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2627 2628 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2629 } 2630 2631 /* ARGSUSED */ 2632 int 2633 com_kgdb_getc(void *arg) 2634 { 2635 2636 return (com_common_getc(NODEV, &comkgdbregs)); 2637 } 2638 2639 /* ARGSUSED */ 2640 void 2641 com_kgdb_putc(void *arg, int c) 2642 { 2643 2644 com_common_putc(NODEV, &comkgdbregs, c); 2645 } 2646 #endif /* KGDB */ 2647 2648 /* helper function to identify the com ports used by 2649 console or KGDB (and not yet autoconf attached) */ 2650 int 2651 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2652 { 2653 bus_space_handle_t help; 2654 2655 if (!comconsattached && 2656 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2657 iobase == comcons_info.regs.cr_iobase) 2658 help = comcons_info.regs.cr_ioh; 2659 #ifdef KGDB 2660 else if (!com_kgdb_attached && 2661 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2662 iobase == comkgdbregs.cr_iobase) 2663 help = comkgdbregs.cr_ioh; 2664 #endif 2665 else 2666 return (0); 2667 2668 if (ioh) 2669 *ioh = help; 2670 return (1); 2671 } 2672 2673 /* 2674 * this routine exists to serve as a shutdown hook for systems that 2675 * have firmware which doesn't interact properly with a com device in 2676 * FIFO mode. 2677 */ 2678 bool 2679 com_cleanup(device_t self, int how) 2680 { 2681 struct com_softc *sc = device_private(self); 2682 2683 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2684 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2685 2686 return true; 2687 } 2688 2689 bool 2690 com_suspend(device_t self, const pmf_qual_t *qual) 2691 { 2692 struct com_softc *sc = device_private(self); 2693 2694 #if 0 2695 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2696 cn_tab = &comcons_suspend; 2697 #endif 2698 2699 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2700 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2701 2702 return true; 2703 } 2704 2705 bool 2706 com_resume(device_t self, const pmf_qual_t *qual) 2707 { 2708 struct com_softc *sc = device_private(self); 2709 2710 mutex_spin_enter(&sc->sc_lock); 2711 com_loadchannelregs(sc); 2712 mutex_spin_exit(&sc->sc_lock); 2713 2714 return true; 2715 } 2716
Indexes created Thu Sep 25 16:09:42 GMT 2025