com.c revision 1.362
1 /* $NetBSD: com.c,v 1.362 2021/03/25 05:33:59 rin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.362 2021/03/25 05:33:59 rin Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #define CSR_WRITE_1(r, o, v) \ 132 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 133 #define CSR_READ_1(r, o) \ 134 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 135 #define CSR_WRITE_2(r, o, v) \ 136 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 137 #define CSR_READ_2(r, o) \ 138 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 139 #define CSR_WRITE_MULTI(r, o, p, n) \ 140 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 141 142 143 static void com_enable_debugport(struct com_softc *); 144 145 void com_config(struct com_softc *); 146 void com_shutdown(struct com_softc *); 147 int comspeed(long, long, int); 148 static u_char cflag2lcr(tcflag_t); 149 int comparam(struct tty *, struct termios *); 150 void comstart(struct tty *); 151 int comhwiflow(struct tty *, int); 152 153 void com_loadchannelregs(struct com_softc *); 154 void com_hwiflow(struct com_softc *); 155 void com_break(struct com_softc *, int); 156 void com_modem(struct com_softc *, int); 157 void tiocm_to_com(struct com_softc *, u_long, int); 158 int com_to_tiocm(struct com_softc *); 159 void com_iflush(struct com_softc *); 160 161 int com_common_getc(dev_t, struct com_regs *); 162 static void com_common_putc(dev_t, struct com_regs *, int, int); 163 164 int cominit(struct com_regs *, int, int, int, tcflag_t); 165 166 static int comcnreattach(void); 167 168 int comcngetc(dev_t); 169 void comcnputc(dev_t, int); 170 void comcnpollc(dev_t, int); 171 172 #define integrate static inline 173 void comsoft(void *); 174 integrate void com_rxsoft(struct com_softc *, struct tty *); 175 integrate void com_txsoft(struct com_softc *, struct tty *); 176 integrate void com_stsoft(struct com_softc *, struct tty *); 177 integrate void com_schedrx(struct com_softc *); 178 void comdiag(void *); 179 180 dev_type_open(comopen); 181 dev_type_close(comclose); 182 dev_type_read(comread); 183 dev_type_write(comwrite); 184 dev_type_ioctl(comioctl); 185 dev_type_stop(comstop); 186 dev_type_tty(comtty); 187 dev_type_poll(compoll); 188 189 static struct comcons_info comcons_info; 190 191 /* 192 * Following are all routines needed for COM to act as console 193 */ 194 static struct consdev comcons = { 195 .cn_getc = comcngetc, 196 .cn_putc = comcnputc, 197 .cn_pollc = comcnpollc, 198 .cn_dev = NODEV, 199 .cn_pri = CN_NORMAL 200 }; 201 202 203 const struct cdevsw com_cdevsw = { 204 .d_open = comopen, 205 .d_close = comclose, 206 .d_read = comread, 207 .d_write = comwrite, 208 .d_ioctl = comioctl, 209 .d_stop = comstop, 210 .d_tty = comtty, 211 .d_poll = compoll, 212 .d_mmap = nommap, 213 .d_kqfilter = ttykqfilter, 214 .d_discard = nodiscard, 215 .d_flag = D_TTY 216 }; 217 218 /* 219 * Make this an option variable one can patch. 220 * But be warned: this must be a power of 2! 221 */ 222 u_int com_rbuf_size = COM_RING_SIZE; 223 224 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 225 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 226 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 227 228 static int comconsattached; 229 static struct cnm_state com_cnm_state; 230 231 #ifdef KGDB 232 #include <sys/kgdb.h> 233 234 static struct com_regs comkgdbregs; 235 static int com_kgdb_attached; 236 237 int com_kgdb_getc(void *); 238 void com_kgdb_putc(void *, int); 239 #endif /* KGDB */ 240 241 /* initializer for typical 16550-ish hardware */ 242 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 243 [COM_REG_RXDATA] = com_data, 244 [COM_REG_TXDATA] = com_data, 245 [COM_REG_DLBL] = com_dlbl, 246 [COM_REG_DLBH] = com_dlbh, 247 [COM_REG_IER] = com_ier, 248 [COM_REG_IIR] = com_iir, 249 [COM_REG_FIFO] = com_fifo, 250 [COM_REG_TCR] = com_fifo, 251 [COM_REG_EFR] = com_efr, 252 [COM_REG_TLR] = com_efr, 253 [COM_REG_LCR] = com_lcr, 254 [COM_REG_MCR] = com_mcr, 255 [COM_REG_LSR] = com_lsr, 256 [COM_REG_MSR] = com_msr, 257 [COM_REG_USR] = com_usr, 258 [COM_REG_TFL] = com_tfl, 259 [COM_REG_RFL] = com_rfl, 260 [COM_REG_HALT] = com_halt, 261 [COM_REG_MDR1] = com_mdr1, 262 }; 263 264 #define COMDIALOUT_MASK TTDIALOUT_MASK 265 266 #define COMUNIT(x) TTUNIT(x) 267 #define COMDIALOUT(x) TTDIALOUT(x) 268 269 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 270 device_is_active((sc)->sc_dev)) 271 272 #define BR BUS_SPACE_BARRIER_READ 273 #define BW BUS_SPACE_BARRIER_WRITE 274 #define COM_BARRIER(r, f) \ 275 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 276 277 /* 278 * com_init_regs -- 279 * Driver front-ends use this to initialize our register map 280 * in the standard fashion. They may then tailor the map to 281 * their own particular requirements. 282 */ 283 void 284 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 285 bus_addr_t addr) 286 { 287 288 memset(regs, 0, sizeof(*regs)); 289 regs->cr_iot = st; 290 regs->cr_ioh = sh; 291 regs->cr_iobase = addr; 292 regs->cr_nports = COM_NPORTS; 293 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 294 } 295 296 /* 297 * com_init_regs_stride -- 298 * Convenience function for front-ends that have a stride between 299 * registers. 300 */ 301 void 302 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 303 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 304 { 305 306 com_init_regs(regs, st, sh, addr); 307 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 308 regs->cr_map[i] <<= regshift; 309 } 310 regs->cr_nports <<= regshift; 311 } 312 313 /*ARGSUSED*/ 314 int 315 comspeed(long speed, long frequency, int type) 316 { 317 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 318 319 int x, err; 320 int divisor = 16; 321 322 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 323 divisor = 13; 324 } 325 326 if (speed == 0) 327 return (0); 328 if (speed < 0) 329 return (-1); 330 x = divrnd(frequency / divisor, speed); 331 if (x <= 0) 332 return (-1); 333 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 334 if (err < 0) 335 err = -err; 336 if (err > COM_TOLERANCE) 337 return (-1); 338 return (x); 339 340 #undef divrnd 341 } 342 343 #ifdef COM_DEBUG 344 int com_debug = 0; 345 346 void comstatus(struct com_softc *, const char *); 347 void 348 comstatus(struct com_softc *sc, const char *str) 349 { 350 struct tty *tp = sc->sc_tty; 351 352 aprint_normal_dev(sc->sc_dev, 353 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 354 str, 355 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 356 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 357 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 358 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 359 sc->sc_tx_stopped ? '+' : '-'); 360 361 aprint_normal_dev(sc->sc_dev, 362 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 363 str, 364 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 365 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 366 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 367 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 368 sc->sc_rx_flags); 369 } 370 #endif 371 372 int 373 com_probe_subr(struct com_regs *regs) 374 { 375 376 /* force access to id reg */ 377 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 378 CSR_WRITE_1(regs, COM_REG_IIR, 0); 379 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 380 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 381 return (0); 382 383 return (1); 384 } 385 386 int 387 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 388 { 389 struct com_regs regs; 390 391 com_init_regs(®s, iot, ioh, 0/*XXX*/); 392 393 return com_probe_subr(®s); 394 } 395 396 /* 397 * No locking in this routine; it is only called during attach, 398 * or with the port already locked. 399 */ 400 static void 401 com_enable_debugport(struct com_softc *sc) 402 { 403 404 /* Turn on line break interrupt, set carrier. */ 405 sc->sc_ier = IER_ERLS; 406 if (sc->sc_type == COM_TYPE_PXA2x0) 407 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 408 if (sc->sc_type == COM_TYPE_INGENIC || 409 sc->sc_type == COM_TYPE_TEGRA) 410 sc->sc_ier |= IER_ERXTOUT; 411 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 412 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 413 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 414 } 415 416 static void 417 com_intr_poll(void *arg) 418 { 419 struct com_softc * const sc = arg; 420 421 comintr(sc); 422 423 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 424 } 425 426 void 427 com_attach_subr(struct com_softc *sc) 428 { 429 struct com_regs *regsp = &sc->sc_regs; 430 struct tty *tp; 431 uint32_t cpr; 432 uint8_t lcr; 433 const char *fifo_msg = NULL; 434 prop_dictionary_t dict; 435 bool is_console = true; 436 bool force_console = false; 437 438 aprint_naive("\n"); 439 440 dict = device_properties(sc->sc_dev); 441 prop_dictionary_get_bool(dict, "is_console", &is_console); 442 prop_dictionary_get_bool(dict, "force_console", &force_console); 443 callout_init(&sc->sc_diag_callout, 0); 444 callout_init(&sc->sc_poll_callout, 0); 445 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 446 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 447 448 #if defined(COM_16650) 449 sc->sc_type = COM_TYPE_16650; 450 #elif defined(COM_16750) 451 sc->sc_type = COM_TYPE_16750; 452 #elif defined(COM_HAYESP) 453 sc->sc_type = COM_TYPE_HAYESP; 454 #elif defined(COM_PXA2X0) 455 sc->sc_type = COM_TYPE_PXA2x0; 456 #endif 457 458 /* Disable interrupts before configuring the device. */ 459 if (sc->sc_type == COM_TYPE_PXA2x0) 460 sc->sc_ier = IER_EUART; 461 else 462 sc->sc_ier = 0; 463 464 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 465 466 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 467 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 468 comconsattached = 1; 469 470 if (force_console) 471 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 472 473 if (cn_tab == NULL && comcnreattach() != 0) { 474 printf("can't re-init serial console @%lx\n", 475 (u_long)comcons_info.regs.cr_iobase); 476 } 477 478 switch (sc->sc_type) { 479 case COM_TYPE_16750: 480 case COM_TYPE_DW_APB: 481 /* Use in comintr(). */ 482 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 483 break; 484 } 485 486 /* Make sure the console is always "hardwired". */ 487 delay(10000); /* wait for output to finish */ 488 if (is_console) { 489 SET(sc->sc_hwflags, COM_HW_CONSOLE); 490 } 491 492 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 493 } 494 495 /* Probe for FIFO */ 496 switch (sc->sc_type) { 497 case COM_TYPE_HAYESP: 498 goto fifodone; 499 500 case COM_TYPE_AU1x00: 501 sc->sc_fifolen = 16; 502 fifo_msg = "Au1X00 UART"; 503 SET(sc->sc_hwflags, COM_HW_FIFO); 504 goto fifodelay; 505 506 case COM_TYPE_16550_NOERS: 507 sc->sc_fifolen = 16; 508 fifo_msg = "ns16650, no ERS"; 509 SET(sc->sc_hwflags, COM_HW_FIFO); 510 goto fifodelay; 511 512 case COM_TYPE_OMAP: 513 sc->sc_fifolen = 64; 514 fifo_msg = "OMAP UART"; 515 SET(sc->sc_hwflags, COM_HW_FIFO); 516 goto fifodelay; 517 518 case COM_TYPE_INGENIC: 519 sc->sc_fifolen = 16; 520 fifo_msg = "Ingenic UART"; 521 SET(sc->sc_hwflags, COM_HW_FIFO); 522 SET(sc->sc_hwflags, COM_HW_NOIEN); 523 goto fifodelay; 524 525 case COM_TYPE_TEGRA: 526 sc->sc_fifolen = 8; 527 fifo_msg = "Tegra UART"; 528 SET(sc->sc_hwflags, COM_HW_FIFO); 529 CSR_WRITE_1(regsp, COM_REG_FIFO, 530 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 531 goto fifodelay; 532 533 case COM_TYPE_BCMAUXUART: 534 sc->sc_fifolen = 1; 535 fifo_msg = "BCM AUX UART"; 536 SET(sc->sc_hwflags, COM_HW_FIFO); 537 CSR_WRITE_1(regsp, COM_REG_FIFO, 538 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 539 goto fifodelay; 540 541 case COM_TYPE_DW_APB: 542 cpr = bus_space_read_4(sc->sc_regs.cr_iot, sc->sc_regs.cr_ioh, 543 DW_APB_UART_CPR); 544 sc->sc_fifolen = __SHIFTOUT(cpr, UART_CPR_FIFO_MODE) * 16; 545 if (sc->sc_fifolen == 0) { 546 sc->sc_fifolen = 1; 547 fifo_msg = "DesignWare APB UART, no fifo"; 548 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 549 } else { 550 fifo_msg = "DesignWare APB UART"; 551 SET(sc->sc_hwflags, COM_HW_FIFO); 552 CSR_WRITE_1(regsp, COM_REG_FIFO, 553 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 554 } 555 goto fifodelay; 556 } 557 558 sc->sc_fifolen = 1; 559 /* look for a NS 16550AF UART with FIFOs */ 560 if (sc->sc_type == COM_TYPE_INGENIC) { 561 CSR_WRITE_1(regsp, COM_REG_FIFO, 562 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 563 FIFO_TRIGGER_14 | FIFO_UART_ON); 564 } else 565 CSR_WRITE_1(regsp, COM_REG_FIFO, 566 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 567 delay(100); 568 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 569 == IIR_FIFO_MASK) 570 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 571 == FIFO_TRIGGER_14) { 572 SET(sc->sc_hwflags, COM_HW_FIFO); 573 574 fifo_msg = "ns16550a"; 575 576 /* 577 * IIR changes into the EFR if LCR is set to LCR_EERS 578 * on 16650s. We also know IIR != 0 at this point. 579 * Write 0 into the EFR, and read it. If the result 580 * is 0, we have a 16650. 581 * 582 * Older 16650s were broken; the test to detect them 583 * is taken from the Linux driver. Apparently 584 * setting DLAB enable gives access to the EFR on 585 * these chips. 586 */ 587 if (sc->sc_type == COM_TYPE_16650) { 588 lcr = CSR_READ_1(regsp, COM_REG_LCR); 589 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 590 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 591 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 592 CSR_WRITE_1(regsp, COM_REG_LCR, 593 lcr | LCR_DLAB); 594 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 595 CLR(sc->sc_hwflags, COM_HW_FIFO); 596 sc->sc_fifolen = 0; 597 } else { 598 SET(sc->sc_hwflags, COM_HW_FLOW); 599 sc->sc_fifolen = 32; 600 } 601 } else 602 sc->sc_fifolen = 16; 603 604 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 605 if (sc->sc_fifolen == 0) 606 fifo_msg = "st16650, broken fifo"; 607 else if (sc->sc_fifolen == 32) 608 fifo_msg = "st16650a"; 609 else 610 fifo_msg = "ns16550a"; 611 } 612 613 /* 614 * TL16C750 can enable 64byte FIFO, only when DLAB 615 * is 1. However, some 16750 may always enable. For 616 * example, restrictions according to DLAB in a data 617 * sheet for SC16C750 were not described. 618 * Please enable 'options COM_16650', supposing you 619 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 620 * should become effective. 621 */ 622 if (sc->sc_type == COM_TYPE_16750) { 623 uint8_t iir1, iir2; 624 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 625 626 lcr = CSR_READ_1(regsp, COM_REG_LCR); 627 CSR_WRITE_1(regsp, COM_REG_LCR, 628 lcr & ~LCR_DLAB); 629 CSR_WRITE_1(regsp, COM_REG_FIFO, 630 fcr | FIFO_64B_ENABLE); 631 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 632 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 633 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 634 CSR_WRITE_1(regsp, COM_REG_FIFO, 635 fcr | FIFO_64B_ENABLE); 636 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 637 638 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 639 640 if (!ISSET(iir1, IIR_64B_FIFO) && 641 ISSET(iir2, IIR_64B_FIFO)) { 642 /* It is TL16C750. */ 643 sc->sc_fifolen = 64; 644 SET(sc->sc_hwflags, COM_HW_AFE); 645 } else 646 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 647 648 if (sc->sc_fifolen == 64) 649 fifo_msg = "tl16c750"; 650 else 651 fifo_msg = "ns16750"; 652 } 653 } else 654 fifo_msg = "ns16550, broken fifo"; 655 else 656 fifo_msg = "ns8250 or ns16450, no fifo"; 657 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 658 659 fifodelay: 660 /* 661 * Some chips will clear down both Tx and Rx FIFOs when zero is 662 * written to com_fifo. If this chip is the console, writing zero 663 * results in some of the chip/FIFO description being lost, so delay 664 * printing it until now. 665 */ 666 delay(10); 667 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 668 aprint_normal(": %s, %d-byte FIFO\n", fifo_msg, sc->sc_fifolen); 669 } else { 670 aprint_normal(": %s\n", fifo_msg); 671 } 672 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 673 sc->sc_fifolen = 1; 674 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 675 } 676 677 fifodone: 678 679 tp = tty_alloc(); 680 tp->t_oproc = comstart; 681 tp->t_param = comparam; 682 tp->t_hwiflow = comhwiflow; 683 tp->t_softc = sc; 684 685 sc->sc_tty = tp; 686 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK); 687 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 688 sc->sc_rbavail = com_rbuf_size; 689 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 690 691 tty_attach(tp); 692 693 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 694 SET(sc->sc_mcr, MCR_IENABLE); 695 696 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 697 int maj; 698 699 /* locate the major number */ 700 maj = cdevsw_lookup_major(&com_cdevsw); 701 702 tp->t_dev = cn_tab->cn_dev = makedev(maj, 703 device_unit(sc->sc_dev)); 704 705 aprint_normal_dev(sc->sc_dev, "console\n"); 706 } 707 708 #ifdef KGDB 709 /* 710 * Allow kgdb to "take over" this port. If this is 711 * not the console and is the kgdb device, it has 712 * exclusive use. If it's the console _and_ the 713 * kgdb device, it doesn't. 714 */ 715 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 716 regsp->cr_iobase == comkgdbregs.cr_iobase) { 717 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 718 com_kgdb_attached = 1; 719 720 SET(sc->sc_hwflags, COM_HW_KGDB); 721 } 722 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 723 } 724 #endif 725 726 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 727 728 #ifdef RND_COM 729 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 730 RND_TYPE_TTY, RND_FLAG_DEFAULT); 731 #endif 732 733 /* if there are no enable/disable functions, assume the device 734 is always enabled */ 735 if (!sc->enable) 736 sc->enabled = 1; 737 738 com_config(sc); 739 740 SET(sc->sc_hwflags, COM_HW_DEV_OK); 741 742 if (sc->sc_poll_ticks != 0) 743 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 744 } 745 746 void 747 com_config(struct com_softc *sc) 748 { 749 struct com_regs *regsp = &sc->sc_regs; 750 751 /* Disable interrupts before configuring the device. */ 752 if (sc->sc_type == COM_TYPE_PXA2x0) 753 sc->sc_ier = IER_EUART; 754 else 755 sc->sc_ier = 0; 756 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 757 (void) CSR_READ_1(regsp, COM_REG_IIR); 758 759 /* Look for a Hayes ESP board. */ 760 if (sc->sc_type == COM_TYPE_HAYESP) { 761 762 /* Set 16550 compatibility mode */ 763 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 764 HAYESP_SETMODE); 765 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 766 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 767 HAYESP_MODE_SCALE); 768 769 /* Set RTS/CTS flow control */ 770 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 771 HAYESP_SETFLOWTYPE); 772 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 773 HAYESP_FLOW_RTS); 774 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 775 HAYESP_FLOW_CTS); 776 777 /* Set flow control levels */ 778 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 779 HAYESP_SETRXFLOW); 780 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 781 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 782 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 783 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 784 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 785 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 786 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 787 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 788 } 789 790 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 791 com_enable_debugport(sc); 792 } 793 794 #if 0 795 static int 796 comcngetc_detached(dev_t dev) 797 { 798 return 0; 799 } 800 801 static void 802 comcnputc_detached(dev_t dev, int c) 803 { 804 } 805 #endif 806 807 int 808 com_detach(device_t self, int flags) 809 { 810 struct com_softc *sc = device_private(self); 811 int maj, mn; 812 813 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 814 return EBUSY; 815 816 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 817 (flags & DETACH_SHUTDOWN) != 0) 818 return EBUSY; 819 820 if (sc->disable != NULL && sc->enabled != 0) { 821 (*sc->disable)(sc); 822 sc->enabled = 0; 823 } 824 825 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 826 comconsattached = 0; 827 cn_tab = NULL; 828 } 829 830 /* locate the major number */ 831 maj = cdevsw_lookup_major(&com_cdevsw); 832 833 /* Nuke the vnodes for any open instances. */ 834 mn = device_unit(self); 835 vdevgone(maj, mn, mn, VCHR); 836 837 mn |= COMDIALOUT_MASK; 838 vdevgone(maj, mn, mn, VCHR); 839 840 if (sc->sc_rbuf == NULL) { 841 /* 842 * Ring buffer allocation failed in the com_attach_subr, 843 * only the tty is allocated, and nothing else. 844 */ 845 tty_free(sc->sc_tty); 846 return 0; 847 } 848 849 /* Free the receive buffer. */ 850 free(sc->sc_rbuf, M_DEVBUF); 851 852 /* Detach and free the tty. */ 853 tty_detach(sc->sc_tty); 854 tty_free(sc->sc_tty); 855 856 /* Unhook the soft interrupt handler. */ 857 softint_disestablish(sc->sc_si); 858 859 #ifdef RND_COM 860 /* Unhook the entropy source. */ 861 rnd_detach_source(&sc->rnd_source); 862 #endif 863 callout_destroy(&sc->sc_diag_callout); 864 865 /* Destroy the lock. */ 866 mutex_destroy(&sc->sc_lock); 867 868 return (0); 869 } 870 871 void 872 com_shutdown(struct com_softc *sc) 873 { 874 struct tty *tp = sc->sc_tty; 875 876 mutex_spin_enter(&sc->sc_lock); 877 878 /* If we were asserting flow control, then deassert it. */ 879 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 880 com_hwiflow(sc); 881 882 /* Clear any break condition set with TIOCSBRK. */ 883 com_break(sc, 0); 884 885 /* 886 * Hang up if necessary. Wait a bit, so the other side has time to 887 * notice even if we immediately open the port again. 888 * Avoid tsleeping above splhigh(). 889 */ 890 if (ISSET(tp->t_cflag, HUPCL)) { 891 com_modem(sc, 0); 892 mutex_spin_exit(&sc->sc_lock); 893 /* XXX will only timeout */ 894 (void) kpause(ttclos, false, hz, NULL); 895 mutex_spin_enter(&sc->sc_lock); 896 } 897 898 /* Turn off interrupts. */ 899 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 900 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 901 if ((sc->sc_type == COM_TYPE_PXA2x0) || 902 (sc->sc_type == COM_TYPE_INGENIC) || 903 (sc->sc_type == COM_TYPE_TEGRA)) 904 sc->sc_ier |= IER_ERXTOUT; 905 } else 906 sc->sc_ier = 0; 907 908 if (sc->sc_type == COM_TYPE_PXA2x0) 909 sc->sc_ier |= IER_EUART; 910 911 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 912 913 mutex_spin_exit(&sc->sc_lock); 914 915 if (sc->disable) { 916 #ifdef DIAGNOSTIC 917 if (!sc->enabled) 918 panic("com_shutdown: not enabled?"); 919 #endif 920 (*sc->disable)(sc); 921 sc->enabled = 0; 922 } 923 } 924 925 int 926 comopen(dev_t dev, int flag, int mode, struct lwp *l) 927 { 928 struct com_softc *sc; 929 struct tty *tp; 930 int s; 931 int error; 932 933 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 934 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 935 sc->sc_rbuf == NULL) 936 return (ENXIO); 937 938 if (!device_is_active(sc->sc_dev)) 939 return (ENXIO); 940 941 #ifdef KGDB 942 /* 943 * If this is the kgdb port, no other use is permitted. 944 */ 945 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 946 return (EBUSY); 947 #endif 948 949 tp = sc->sc_tty; 950 951 /* 952 * If the device is exclusively for kernel use, deny userland 953 * open. 954 */ 955 if (ISSET(tp->t_state, TS_KERN_ONLY)) 956 return (EBUSY); 957 958 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 959 return (EBUSY); 960 961 s = spltty(); 962 963 /* 964 * Do the following iff this is a first open. 965 */ 966 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 967 struct termios t; 968 969 tp->t_dev = dev; 970 971 if (sc->enable) { 972 if ((*sc->enable)(sc)) { 973 splx(s); 974 aprint_error_dev(sc->sc_dev, 975 "device enable failed\n"); 976 return (EIO); 977 } 978 mutex_spin_enter(&sc->sc_lock); 979 sc->enabled = 1; 980 com_config(sc); 981 } else { 982 mutex_spin_enter(&sc->sc_lock); 983 } 984 985 /* Turn on interrupts. */ 986 sc->sc_ier = IER_ERXRDY | IER_ERLS; 987 if (!ISSET(tp->t_cflag, CLOCAL)) 988 sc->sc_ier |= IER_EMSC; 989 990 if (sc->sc_type == COM_TYPE_PXA2x0) 991 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 992 else if (sc->sc_type == COM_TYPE_INGENIC || 993 sc->sc_type == COM_TYPE_TEGRA) 994 sc->sc_ier |= IER_ERXTOUT; 995 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 996 997 /* Fetch the current modem control status, needed later. */ 998 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 999 1000 /* Clear PPS capture state on first open. */ 1001 mutex_spin_enter(&timecounter_lock); 1002 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 1003 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1004 pps_init(&sc->sc_pps_state); 1005 mutex_spin_exit(&timecounter_lock); 1006 1007 mutex_spin_exit(&sc->sc_lock); 1008 1009 /* 1010 * Initialize the termios status to the defaults. Add in the 1011 * sticky bits from TIOCSFLAGS. 1012 */ 1013 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1014 t.c_ospeed = comcons_info.rate; 1015 t.c_cflag = comcons_info.cflag; 1016 } else { 1017 t.c_ospeed = TTYDEF_SPEED; 1018 t.c_cflag = TTYDEF_CFLAG; 1019 } 1020 t.c_ispeed = t.c_ospeed; 1021 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1022 SET(t.c_cflag, CLOCAL); 1023 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1024 SET(t.c_cflag, CRTSCTS); 1025 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1026 SET(t.c_cflag, MDMBUF); 1027 /* Make sure comparam() will do something. */ 1028 tp->t_ospeed = 0; 1029 (void) comparam(tp, &t); 1030 tp->t_iflag = TTYDEF_IFLAG; 1031 tp->t_oflag = TTYDEF_OFLAG; 1032 tp->t_lflag = TTYDEF_LFLAG; 1033 ttychars(tp); 1034 ttsetwater(tp); 1035 1036 mutex_spin_enter(&sc->sc_lock); 1037 1038 /* 1039 * Turn on DTR. We must always do this, even if carrier is not 1040 * present, because otherwise we'd have to use TIOCSDTR 1041 * immediately after setting CLOCAL, which applications do not 1042 * expect. We always assert DTR while the device is open 1043 * unless explicitly requested to deassert it. 1044 */ 1045 com_modem(sc, 1); 1046 1047 /* Clear the input ring, and unblock. */ 1048 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1049 sc->sc_rbavail = com_rbuf_size; 1050 com_iflush(sc); 1051 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1052 com_hwiflow(sc); 1053 1054 #ifdef COM_DEBUG 1055 if (com_debug) 1056 comstatus(sc, "comopen "); 1057 #endif 1058 1059 mutex_spin_exit(&sc->sc_lock); 1060 } 1061 1062 splx(s); 1063 1064 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1065 if (error) 1066 goto bad; 1067 1068 error = (*tp->t_linesw->l_open)(dev, tp); 1069 if (error) 1070 goto bad; 1071 1072 return (0); 1073 1074 bad: 1075 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1076 /* 1077 * We failed to open the device, and nobody else had it opened. 1078 * Clean up the state as appropriate. 1079 */ 1080 com_shutdown(sc); 1081 } 1082 1083 return (error); 1084 } 1085 1086 int 1087 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1088 { 1089 struct com_softc *sc = 1090 device_lookup_private(&com_cd, COMUNIT(dev)); 1091 struct tty *tp = sc->sc_tty; 1092 1093 /* XXX This is for cons.c. */ 1094 if (!ISSET(tp->t_state, TS_ISOPEN)) 1095 return (0); 1096 /* 1097 * If the device is exclusively for kernel use, deny userland 1098 * close. 1099 */ 1100 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1101 return (0); 1102 1103 (*tp->t_linesw->l_close)(tp, flag); 1104 ttyclose(tp); 1105 1106 if (COM_ISALIVE(sc) == 0) 1107 return (0); 1108 1109 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1110 /* 1111 * Although we got a last close, the device may still be in 1112 * use; e.g. if this was the dialout node, and there are still 1113 * processes waiting for carrier on the non-dialout node. 1114 */ 1115 com_shutdown(sc); 1116 } 1117 1118 return (0); 1119 } 1120 1121 int 1122 comread(dev_t dev, struct uio *uio, int flag) 1123 { 1124 struct com_softc *sc = 1125 device_lookup_private(&com_cd, COMUNIT(dev)); 1126 struct tty *tp = sc->sc_tty; 1127 1128 if (COM_ISALIVE(sc) == 0) 1129 return (EIO); 1130 1131 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1132 } 1133 1134 int 1135 comwrite(dev_t dev, struct uio *uio, int flag) 1136 { 1137 struct com_softc *sc = 1138 device_lookup_private(&com_cd, COMUNIT(dev)); 1139 struct tty *tp = sc->sc_tty; 1140 1141 if (COM_ISALIVE(sc) == 0) 1142 return (EIO); 1143 1144 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1145 } 1146 1147 int 1148 compoll(dev_t dev, int events, struct lwp *l) 1149 { 1150 struct com_softc *sc = 1151 device_lookup_private(&com_cd, COMUNIT(dev)); 1152 struct tty *tp = sc->sc_tty; 1153 1154 if (COM_ISALIVE(sc) == 0) 1155 return (POLLHUP); 1156 1157 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1158 } 1159 1160 struct tty * 1161 comtty(dev_t dev) 1162 { 1163 struct com_softc *sc = 1164 device_lookup_private(&com_cd, COMUNIT(dev)); 1165 struct tty *tp = sc->sc_tty; 1166 1167 return (tp); 1168 } 1169 1170 int 1171 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1172 { 1173 struct com_softc *sc; 1174 struct tty *tp; 1175 int error; 1176 1177 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1178 if (sc == NULL) 1179 return ENXIO; 1180 if (COM_ISALIVE(sc) == 0) 1181 return (EIO); 1182 1183 tp = sc->sc_tty; 1184 1185 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1186 if (error != EPASSTHROUGH) 1187 return (error); 1188 1189 error = ttioctl(tp, cmd, data, flag, l); 1190 if (error != EPASSTHROUGH) 1191 return (error); 1192 1193 error = 0; 1194 switch (cmd) { 1195 case TIOCSFLAGS: 1196 error = kauth_authorize_device_tty(l->l_cred, 1197 KAUTH_DEVICE_TTY_PRIVSET, tp); 1198 break; 1199 default: 1200 /* nothing */ 1201 break; 1202 } 1203 if (error) { 1204 return error; 1205 } 1206 1207 mutex_spin_enter(&sc->sc_lock); 1208 1209 switch (cmd) { 1210 case TIOCSBRK: 1211 com_break(sc, 1); 1212 break; 1213 1214 case TIOCCBRK: 1215 com_break(sc, 0); 1216 break; 1217 1218 case TIOCSDTR: 1219 com_modem(sc, 1); 1220 break; 1221 1222 case TIOCCDTR: 1223 com_modem(sc, 0); 1224 break; 1225 1226 case TIOCGFLAGS: 1227 *(int *)data = sc->sc_swflags; 1228 break; 1229 1230 case TIOCSFLAGS: 1231 sc->sc_swflags = *(int *)data; 1232 break; 1233 1234 case TIOCMSET: 1235 case TIOCMBIS: 1236 case TIOCMBIC: 1237 tiocm_to_com(sc, cmd, *(int *)data); 1238 break; 1239 1240 case TIOCMGET: 1241 *(int *)data = com_to_tiocm(sc); 1242 break; 1243 1244 case PPS_IOC_CREATE: 1245 case PPS_IOC_DESTROY: 1246 case PPS_IOC_GETPARAMS: 1247 case PPS_IOC_SETPARAMS: 1248 case PPS_IOC_GETCAP: 1249 case PPS_IOC_FETCH: 1250 #ifdef PPS_SYNC 1251 case PPS_IOC_KCBIND: 1252 #endif 1253 mutex_spin_enter(&timecounter_lock); 1254 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1255 mutex_spin_exit(&timecounter_lock); 1256 break; 1257 1258 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1259 mutex_spin_enter(&timecounter_lock); 1260 #ifndef PPS_TRAILING_EDGE 1261 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1262 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1263 #else 1264 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1265 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1266 #endif 1267 mutex_spin_exit(&timecounter_lock); 1268 break; 1269 1270 default: 1271 error = EPASSTHROUGH; 1272 break; 1273 } 1274 1275 mutex_spin_exit(&sc->sc_lock); 1276 1277 #ifdef COM_DEBUG 1278 if (com_debug) 1279 comstatus(sc, "comioctl "); 1280 #endif 1281 1282 return (error); 1283 } 1284 1285 integrate void 1286 com_schedrx(struct com_softc *sc) 1287 { 1288 1289 sc->sc_rx_ready = 1; 1290 1291 /* Wake up the poller. */ 1292 softint_schedule(sc->sc_si); 1293 } 1294 1295 void 1296 com_break(struct com_softc *sc, int onoff) 1297 { 1298 1299 if (onoff) 1300 SET(sc->sc_lcr, LCR_SBREAK); 1301 else 1302 CLR(sc->sc_lcr, LCR_SBREAK); 1303 1304 if (!sc->sc_heldchange) { 1305 if (sc->sc_tx_busy) { 1306 sc->sc_heldtbc = sc->sc_tbc; 1307 sc->sc_tbc = 0; 1308 sc->sc_heldchange = 1; 1309 } else 1310 com_loadchannelregs(sc); 1311 } 1312 } 1313 1314 void 1315 com_modem(struct com_softc *sc, int onoff) 1316 { 1317 1318 if (sc->sc_mcr_dtr == 0) 1319 return; 1320 1321 if (onoff) 1322 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1323 else 1324 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1325 1326 if (!sc->sc_heldchange) { 1327 if (sc->sc_tx_busy) { 1328 sc->sc_heldtbc = sc->sc_tbc; 1329 sc->sc_tbc = 0; 1330 sc->sc_heldchange = 1; 1331 } else 1332 com_loadchannelregs(sc); 1333 } 1334 } 1335 1336 void 1337 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1338 { 1339 u_char combits; 1340 1341 combits = 0; 1342 if (ISSET(ttybits, TIOCM_DTR)) 1343 SET(combits, MCR_DTR); 1344 if (ISSET(ttybits, TIOCM_RTS)) 1345 SET(combits, MCR_RTS); 1346 1347 switch (how) { 1348 case TIOCMBIC: 1349 CLR(sc->sc_mcr, combits); 1350 break; 1351 1352 case TIOCMBIS: 1353 SET(sc->sc_mcr, combits); 1354 break; 1355 1356 case TIOCMSET: 1357 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1358 SET(sc->sc_mcr, combits); 1359 break; 1360 } 1361 1362 if (!sc->sc_heldchange) { 1363 if (sc->sc_tx_busy) { 1364 sc->sc_heldtbc = sc->sc_tbc; 1365 sc->sc_tbc = 0; 1366 sc->sc_heldchange = 1; 1367 } else 1368 com_loadchannelregs(sc); 1369 } 1370 } 1371 1372 int 1373 com_to_tiocm(struct com_softc *sc) 1374 { 1375 u_char combits; 1376 int ttybits = 0; 1377 1378 combits = sc->sc_mcr; 1379 if (ISSET(combits, MCR_DTR)) 1380 SET(ttybits, TIOCM_DTR); 1381 if (ISSET(combits, MCR_RTS)) 1382 SET(ttybits, TIOCM_RTS); 1383 1384 combits = sc->sc_msr; 1385 if (sc->sc_type == COM_TYPE_INGENIC) { 1386 SET(ttybits, TIOCM_CD); 1387 } else { 1388 if (ISSET(combits, MSR_DCD)) 1389 SET(ttybits, TIOCM_CD); 1390 } 1391 if (ISSET(combits, MSR_CTS)) 1392 SET(ttybits, TIOCM_CTS); 1393 if (ISSET(combits, MSR_DSR)) 1394 SET(ttybits, TIOCM_DSR); 1395 if (ISSET(combits, MSR_RI | MSR_TERI)) 1396 SET(ttybits, TIOCM_RI); 1397 1398 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1399 SET(ttybits, TIOCM_LE); 1400 1401 return (ttybits); 1402 } 1403 1404 static u_char 1405 cflag2lcr(tcflag_t cflag) 1406 { 1407 u_char lcr = 0; 1408 1409 switch (ISSET(cflag, CSIZE)) { 1410 case CS5: 1411 SET(lcr, LCR_5BITS); 1412 break; 1413 case CS6: 1414 SET(lcr, LCR_6BITS); 1415 break; 1416 case CS7: 1417 SET(lcr, LCR_7BITS); 1418 break; 1419 case CS8: 1420 SET(lcr, LCR_8BITS); 1421 break; 1422 } 1423 if (ISSET(cflag, PARENB)) { 1424 SET(lcr, LCR_PENAB); 1425 if (!ISSET(cflag, PARODD)) 1426 SET(lcr, LCR_PEVEN); 1427 } 1428 if (ISSET(cflag, CSTOPB)) 1429 SET(lcr, LCR_STOPB); 1430 1431 return (lcr); 1432 } 1433 1434 int 1435 comparam(struct tty *tp, struct termios *t) 1436 { 1437 struct com_softc *sc = 1438 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1439 int ospeed; 1440 u_char lcr; 1441 1442 if (COM_ISALIVE(sc) == 0) 1443 return (EIO); 1444 1445 if (sc->sc_type == COM_TYPE_HAYESP) { 1446 int prescaler, speed; 1447 1448 /* 1449 * Calculate UART clock prescaler. It should be in 1450 * range of 0 .. 3. 1451 */ 1452 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1453 prescaler++, speed /= 2) 1454 if ((ospeed = comspeed(speed, sc->sc_frequency, 1455 sc->sc_type)) > 0) 1456 break; 1457 1458 if (prescaler == 4) 1459 return (EINVAL); 1460 sc->sc_prescaler = prescaler; 1461 } else 1462 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1463 1464 /* Check requested parameters. */ 1465 if (ospeed < 0) 1466 return (EINVAL); 1467 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1468 return (EINVAL); 1469 1470 /* 1471 * For the console, always force CLOCAL and !HUPCL, so that the port 1472 * is always active. 1473 */ 1474 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1475 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1476 SET(t->c_cflag, CLOCAL); 1477 CLR(t->c_cflag, HUPCL); 1478 } 1479 1480 /* 1481 * If there were no changes, don't do anything. This avoids dropping 1482 * input and improves performance when all we did was frob things like 1483 * VMIN and VTIME. 1484 */ 1485 if (tp->t_ospeed == t->c_ospeed && 1486 tp->t_cflag == t->c_cflag) 1487 return (0); 1488 1489 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1490 1491 mutex_spin_enter(&sc->sc_lock); 1492 1493 sc->sc_lcr = lcr; 1494 1495 /* 1496 * If we're not in a mode that assumes a connection is present, then 1497 * ignore carrier changes. 1498 */ 1499 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1500 sc->sc_msr_dcd = 0; 1501 else 1502 sc->sc_msr_dcd = MSR_DCD; 1503 /* 1504 * Set the flow control pins depending on the current flow control 1505 * mode. 1506 */ 1507 if (ISSET(t->c_cflag, CRTSCTS)) { 1508 sc->sc_mcr_dtr = MCR_DTR; 1509 sc->sc_mcr_rts = MCR_RTS; 1510 sc->sc_msr_cts = MSR_CTS; 1511 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1512 SET(sc->sc_mcr, MCR_AFE); 1513 } else { 1514 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1515 } 1516 } else if (ISSET(t->c_cflag, MDMBUF)) { 1517 /* 1518 * For DTR/DCD flow control, make sure we don't toggle DTR for 1519 * carrier detection. 1520 */ 1521 sc->sc_mcr_dtr = 0; 1522 sc->sc_mcr_rts = MCR_DTR; 1523 sc->sc_msr_cts = MSR_DCD; 1524 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1525 CLR(sc->sc_mcr, MCR_AFE); 1526 } else { 1527 sc->sc_efr = 0; 1528 } 1529 } else { 1530 /* 1531 * If no flow control, then always set RTS. This will make 1532 * the other side happy if it mistakenly thinks we're doing 1533 * RTS/CTS flow control. 1534 */ 1535 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1536 sc->sc_mcr_rts = 0; 1537 sc->sc_msr_cts = 0; 1538 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1539 CLR(sc->sc_mcr, MCR_AFE); 1540 } else { 1541 sc->sc_efr = 0; 1542 } 1543 if (ISSET(sc->sc_mcr, MCR_DTR)) 1544 SET(sc->sc_mcr, MCR_RTS); 1545 else 1546 CLR(sc->sc_mcr, MCR_RTS); 1547 } 1548 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1549 1550 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1551 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1552 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1553 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1554 1555 sc->sc_dlbl = ospeed; 1556 sc->sc_dlbh = ospeed >> 8; 1557 1558 /* 1559 * Set the FIFO threshold based on the receive speed. 1560 * 1561 * * If it's a low speed, it's probably a mouse or some other 1562 * interactive device, so set the threshold low. 1563 * * If it's a high speed, trim the trigger level down to prevent 1564 * overflows. 1565 * * Otherwise set it a bit higher. 1566 */ 1567 if (sc->sc_type == COM_TYPE_HAYESP) { 1568 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1569 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1570 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1571 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1572 if (t->c_ospeed <= 1200) 1573 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1574 else if (t->c_ospeed <= 38400) 1575 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1576 else 1577 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1578 } else { 1579 sc->sc_fifo = 0; 1580 } 1581 1582 if (sc->sc_type == COM_TYPE_INGENIC) 1583 sc->sc_fifo |= FIFO_UART_ON; 1584 1585 /* And copy to tty. */ 1586 tp->t_ispeed = t->c_ospeed; 1587 tp->t_ospeed = t->c_ospeed; 1588 tp->t_cflag = t->c_cflag; 1589 1590 if (!sc->sc_heldchange) { 1591 if (sc->sc_tx_busy) { 1592 sc->sc_heldtbc = sc->sc_tbc; 1593 sc->sc_tbc = 0; 1594 sc->sc_heldchange = 1; 1595 } else 1596 com_loadchannelregs(sc); 1597 } 1598 1599 if (!ISSET(t->c_cflag, CHWFLOW)) { 1600 /* Disable the high water mark. */ 1601 sc->sc_r_hiwat = 0; 1602 sc->sc_r_lowat = 0; 1603 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1604 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1605 com_schedrx(sc); 1606 } 1607 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1608 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1609 com_hwiflow(sc); 1610 } 1611 } else { 1612 sc->sc_r_hiwat = com_rbuf_hiwat; 1613 sc->sc_r_lowat = com_rbuf_lowat; 1614 } 1615 1616 mutex_spin_exit(&sc->sc_lock); 1617 1618 /* 1619 * Update the tty layer's idea of the carrier bit, in case we changed 1620 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1621 * explicit request. 1622 */ 1623 if (sc->sc_type == COM_TYPE_INGENIC) { 1624 /* no DCD here */ 1625 (void) (*tp->t_linesw->l_modem)(tp, 1); 1626 } else 1627 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1628 1629 #ifdef COM_DEBUG 1630 if (com_debug) 1631 comstatus(sc, "comparam "); 1632 #endif 1633 1634 if (!ISSET(t->c_cflag, CHWFLOW)) { 1635 if (sc->sc_tx_stopped) { 1636 sc->sc_tx_stopped = 0; 1637 comstart(tp); 1638 } 1639 } 1640 1641 return (0); 1642 } 1643 1644 void 1645 com_iflush(struct com_softc *sc) 1646 { 1647 struct com_regs *regsp = &sc->sc_regs; 1648 uint8_t fifo; 1649 #ifdef DIAGNOSTIC 1650 int reg; 1651 #endif 1652 int timo; 1653 1654 #ifdef DIAGNOSTIC 1655 reg = 0xffff; 1656 #endif 1657 timo = 50000; 1658 /* flush any pending I/O */ 1659 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1660 && --timo) 1661 #ifdef DIAGNOSTIC 1662 reg = 1663 #else 1664 (void) 1665 #endif 1666 CSR_READ_1(regsp, COM_REG_RXDATA); 1667 #ifdef DIAGNOSTIC 1668 if (!timo) 1669 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1670 #endif 1671 1672 switch (sc->sc_type) { 1673 case COM_TYPE_16750: 1674 case COM_TYPE_DW_APB: 1675 /* 1676 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1677 * This should prevent triggering busy interrupt while 1678 * manipulating divisors. 1679 */ 1680 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1681 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1682 CSR_WRITE_1(regsp, COM_REG_FIFO, 1683 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1684 delay(100); 1685 break; 1686 } 1687 } 1688 1689 void 1690 com_loadchannelregs(struct com_softc *sc) 1691 { 1692 struct com_regs *regsp = &sc->sc_regs; 1693 1694 /* XXXXX necessary? */ 1695 com_iflush(sc); 1696 1697 if (sc->sc_type == COM_TYPE_PXA2x0) 1698 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1699 else 1700 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1701 1702 if (sc->sc_type == COM_TYPE_OMAP) { 1703 /* disable before changing settings */ 1704 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1705 } 1706 1707 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1708 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1709 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1710 /* no EFR on alchemy */ 1711 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1712 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1713 } 1714 if (sc->sc_type == COM_TYPE_AU1x00) { 1715 /* alchemy has single separate 16-bit clock divisor register */ 1716 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1717 (sc->sc_dlbh << 8)); 1718 } else { 1719 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1720 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1721 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1722 } 1723 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1724 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1725 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1726 if (sc->sc_type == COM_TYPE_HAYESP) { 1727 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1728 HAYESP_SETPRESCALER); 1729 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1730 sc->sc_prescaler); 1731 } 1732 if (sc->sc_type == COM_TYPE_OMAP) { 1733 /* setup the fifos. the FCR value is not used as long 1734 as SCR[6] and SCR[7] are 0, which they are at reset 1735 and we never touch the SCR register */ 1736 uint8_t rx_fifo_trig = 40; 1737 uint8_t tx_fifo_trig = 60; 1738 uint8_t rx_start = 8; 1739 uint8_t rx_halt = 60; 1740 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1741 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1742 1743 /* enable access to TCR & TLR */ 1744 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1745 1746 /* write tcr and tlr values */ 1747 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1748 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1749 1750 /* disable access to TCR & TLR */ 1751 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1752 1753 /* enable again, but mode is based on speed */ 1754 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1755 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1756 } else { 1757 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1758 } 1759 } 1760 1761 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1762 } 1763 1764 int 1765 comhwiflow(struct tty *tp, int block) 1766 { 1767 struct com_softc *sc = 1768 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1769 1770 if (COM_ISALIVE(sc) == 0) 1771 return (0); 1772 1773 if (sc->sc_mcr_rts == 0) 1774 return (0); 1775 1776 mutex_spin_enter(&sc->sc_lock); 1777 1778 if (block) { 1779 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1780 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1781 com_hwiflow(sc); 1782 } 1783 } else { 1784 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1785 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1786 com_schedrx(sc); 1787 } 1788 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1789 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1790 com_hwiflow(sc); 1791 } 1792 } 1793 1794 mutex_spin_exit(&sc->sc_lock); 1795 return (1); 1796 } 1797 1798 /* 1799 * (un)block input via hw flowcontrol 1800 */ 1801 void 1802 com_hwiflow(struct com_softc *sc) 1803 { 1804 struct com_regs *regsp= &sc->sc_regs; 1805 1806 if (sc->sc_mcr_rts == 0) 1807 return; 1808 1809 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1810 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1811 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1812 } else { 1813 SET(sc->sc_mcr, sc->sc_mcr_rts); 1814 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1815 } 1816 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1817 } 1818 1819 1820 void 1821 comstart(struct tty *tp) 1822 { 1823 struct com_softc *sc = 1824 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1825 struct com_regs *regsp = &sc->sc_regs; 1826 int s; 1827 1828 if (COM_ISALIVE(sc) == 0) 1829 return; 1830 1831 s = spltty(); 1832 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1833 goto out; 1834 if (sc->sc_tx_stopped) 1835 goto out; 1836 if (!ttypull(tp)) 1837 goto out; 1838 1839 /* Grab the first contiguous region of buffer space. */ 1840 { 1841 u_char *tba; 1842 int tbc; 1843 1844 tba = tp->t_outq.c_cf; 1845 tbc = ndqb(&tp->t_outq, 0); 1846 1847 mutex_spin_enter(&sc->sc_lock); 1848 1849 sc->sc_tba = tba; 1850 sc->sc_tbc = tbc; 1851 } 1852 1853 SET(tp->t_state, TS_BUSY); 1854 sc->sc_tx_busy = 1; 1855 1856 /* Enable transmit completion interrupts if necessary. */ 1857 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1858 SET(sc->sc_ier, IER_ETXRDY); 1859 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1860 } 1861 1862 /* Output the first chunk of the contiguous buffer. */ 1863 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1864 u_int n; 1865 1866 n = sc->sc_tbc; 1867 if (n > sc->sc_fifolen) 1868 n = sc->sc_fifolen; 1869 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1870 sc->sc_tbc -= n; 1871 sc->sc_tba += n; 1872 } 1873 1874 mutex_spin_exit(&sc->sc_lock); 1875 out: 1876 splx(s); 1877 return; 1878 } 1879 1880 /* 1881 * Stop output on a line. 1882 */ 1883 void 1884 comstop(struct tty *tp, int flag) 1885 { 1886 struct com_softc *sc = 1887 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1888 1889 mutex_spin_enter(&sc->sc_lock); 1890 if (ISSET(tp->t_state, TS_BUSY)) { 1891 /* Stop transmitting at the next chunk. */ 1892 sc->sc_tbc = 0; 1893 sc->sc_heldtbc = 0; 1894 if (!ISSET(tp->t_state, TS_TTSTOP)) 1895 SET(tp->t_state, TS_FLUSH); 1896 } 1897 mutex_spin_exit(&sc->sc_lock); 1898 } 1899 1900 void 1901 comdiag(void *arg) 1902 { 1903 struct com_softc *sc = arg; 1904 int overflows, floods; 1905 1906 mutex_spin_enter(&sc->sc_lock); 1907 overflows = sc->sc_overflows; 1908 sc->sc_overflows = 0; 1909 floods = sc->sc_floods; 1910 sc->sc_floods = 0; 1911 sc->sc_errors = 0; 1912 mutex_spin_exit(&sc->sc_lock); 1913 1914 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1915 device_xname(sc->sc_dev), 1916 overflows, overflows == 1 ? "" : "s", 1917 floods, floods == 1 ? "" : "s"); 1918 } 1919 1920 integrate void 1921 com_rxsoft(struct com_softc *sc, struct tty *tp) 1922 { 1923 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1924 u_char *get, *end; 1925 u_int cc, scc; 1926 u_char lsr; 1927 int code; 1928 1929 end = sc->sc_ebuf; 1930 get = sc->sc_rbget; 1931 scc = cc = com_rbuf_size - sc->sc_rbavail; 1932 1933 if (cc == com_rbuf_size) { 1934 sc->sc_floods++; 1935 if (sc->sc_errors++ == 0) 1936 callout_reset(&sc->sc_diag_callout, 60 * hz, 1937 comdiag, sc); 1938 } 1939 1940 /* If not yet open, drop the entire buffer content here */ 1941 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1942 get += cc << 1; 1943 if (get >= end) 1944 get -= com_rbuf_size << 1; 1945 cc = 0; 1946 } 1947 while (cc) { 1948 code = get[0]; 1949 lsr = get[1]; 1950 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1951 if (ISSET(lsr, LSR_OE)) { 1952 sc->sc_overflows++; 1953 if (sc->sc_errors++ == 0) 1954 callout_reset(&sc->sc_diag_callout, 1955 60 * hz, comdiag, sc); 1956 } 1957 if (ISSET(lsr, LSR_BI | LSR_FE)) 1958 SET(code, TTY_FE); 1959 if (ISSET(lsr, LSR_PE)) 1960 SET(code, TTY_PE); 1961 } 1962 if ((*rint)(code, tp) == -1) { 1963 /* 1964 * The line discipline's buffer is out of space. 1965 */ 1966 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1967 /* 1968 * We're either not using flow control, or the 1969 * line discipline didn't tell us to block for 1970 * some reason. Either way, we have no way to 1971 * know when there's more space available, so 1972 * just drop the rest of the data. 1973 */ 1974 get += cc << 1; 1975 if (get >= end) 1976 get -= com_rbuf_size << 1; 1977 cc = 0; 1978 } else { 1979 /* 1980 * Don't schedule any more receive processing 1981 * until the line discipline tells us there's 1982 * space available (through comhwiflow()). 1983 * Leave the rest of the data in the input 1984 * buffer. 1985 */ 1986 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1987 } 1988 break; 1989 } 1990 get += 2; 1991 if (get >= end) 1992 get = sc->sc_rbuf; 1993 cc--; 1994 } 1995 1996 if (cc != scc) { 1997 sc->sc_rbget = get; 1998 mutex_spin_enter(&sc->sc_lock); 1999 2000 cc = sc->sc_rbavail += scc - cc; 2001 /* Buffers should be ok again, release possible block. */ 2002 if (cc >= sc->sc_r_lowat) { 2003 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2004 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2005 SET(sc->sc_ier, IER_ERXRDY); 2006 if (sc->sc_type == COM_TYPE_PXA2x0) 2007 SET(sc->sc_ier, IER_ERXTOUT); 2008 if (sc->sc_type == COM_TYPE_INGENIC || 2009 sc->sc_type == COM_TYPE_TEGRA) 2010 SET(sc->sc_ier, IER_ERXTOUT); 2011 2012 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 2013 sc->sc_ier); 2014 } 2015 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 2016 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2017 com_hwiflow(sc); 2018 } 2019 } 2020 mutex_spin_exit(&sc->sc_lock); 2021 } 2022 } 2023 2024 integrate void 2025 com_txsoft(struct com_softc *sc, struct tty *tp) 2026 { 2027 2028 CLR(tp->t_state, TS_BUSY); 2029 if (ISSET(tp->t_state, TS_FLUSH)) 2030 CLR(tp->t_state, TS_FLUSH); 2031 else 2032 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2033 (*tp->t_linesw->l_start)(tp); 2034 } 2035 2036 integrate void 2037 com_stsoft(struct com_softc *sc, struct tty *tp) 2038 { 2039 u_char msr, delta; 2040 2041 mutex_spin_enter(&sc->sc_lock); 2042 msr = sc->sc_msr; 2043 delta = sc->sc_msr_delta; 2044 sc->sc_msr_delta = 0; 2045 mutex_spin_exit(&sc->sc_lock); 2046 2047 if (ISSET(delta, sc->sc_msr_dcd)) { 2048 /* 2049 * Inform the tty layer that carrier detect changed. 2050 */ 2051 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2052 } 2053 2054 if (ISSET(delta, sc->sc_msr_cts)) { 2055 /* Block or unblock output according to flow control. */ 2056 if (ISSET(msr, sc->sc_msr_cts)) { 2057 sc->sc_tx_stopped = 0; 2058 (*tp->t_linesw->l_start)(tp); 2059 } else { 2060 sc->sc_tx_stopped = 1; 2061 } 2062 } 2063 2064 #ifdef COM_DEBUG 2065 if (com_debug) 2066 comstatus(sc, "com_stsoft"); 2067 #endif 2068 } 2069 2070 void 2071 comsoft(void *arg) 2072 { 2073 struct com_softc *sc = arg; 2074 struct tty *tp; 2075 2076 if (COM_ISALIVE(sc) == 0) 2077 return; 2078 2079 tp = sc->sc_tty; 2080 2081 if (sc->sc_rx_ready) { 2082 sc->sc_rx_ready = 0; 2083 com_rxsoft(sc, tp); 2084 } 2085 2086 if (sc->sc_st_check) { 2087 sc->sc_st_check = 0; 2088 com_stsoft(sc, tp); 2089 } 2090 2091 if (sc->sc_tx_done) { 2092 sc->sc_tx_done = 0; 2093 com_txsoft(sc, tp); 2094 } 2095 } 2096 2097 int 2098 comintr(void *arg) 2099 { 2100 struct com_softc *sc = arg; 2101 struct com_regs *regsp = &sc->sc_regs; 2102 2103 u_char *put, *end; 2104 u_int cc; 2105 u_char lsr, iir; 2106 2107 if (COM_ISALIVE(sc) == 0) 2108 return (0); 2109 2110 KASSERT(regsp != NULL); 2111 2112 mutex_spin_enter(&sc->sc_lock); 2113 iir = CSR_READ_1(regsp, COM_REG_IIR); 2114 2115 /* Handle ns16750-specific busy interrupt. */ 2116 if (sc->sc_type == COM_TYPE_16750 && 2117 (iir & IIR_BUSY) == IIR_BUSY) { 2118 for (int timeout = 10000; 2119 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2120 if (timeout <= 0) { 2121 aprint_error_dev(sc->sc_dev, 2122 "timeout while waiting for BUSY interrupt " 2123 "acknowledge\n"); 2124 mutex_spin_exit(&sc->sc_lock); 2125 return (0); 2126 } 2127 2128 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2129 iir = CSR_READ_1(regsp, COM_REG_IIR); 2130 } 2131 2132 /* DesignWare APB UART BUSY interrupt */ 2133 if (sc->sc_type == COM_TYPE_DW_APB && 2134 (iir & IIR_BUSY) == IIR_BUSY) { 2135 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2136 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2137 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2138 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2139 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2140 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2141 CSR_WRITE_1(regsp, COM_REG_HALT, 2142 HALT_CHCFG_EN | HALT_CHCFG_UD); 2143 for (int timeout = 10000000; 2144 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2145 timeout--) { 2146 if (timeout <= 0) { 2147 aprint_error_dev(sc->sc_dev, 2148 "timeout while waiting for HALT " 2149 "update acknowledge 0x%x 0x%x\n", 2150 CSR_READ_1(regsp, COM_REG_HALT), 2151 CSR_READ_1(regsp, COM_REG_USR)); 2152 break; 2153 } 2154 } 2155 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2156 (void)CSR_READ_1(regsp, COM_REG_USR); 2157 } else { 2158 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2159 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2160 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2161 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2162 } 2163 } 2164 2165 if (ISSET(iir, IIR_NOPEND)) { 2166 mutex_spin_exit(&sc->sc_lock); 2167 return (0); 2168 } 2169 2170 end = sc->sc_ebuf; 2171 put = sc->sc_rbput; 2172 cc = sc->sc_rbavail; 2173 2174 again: do { 2175 u_char msr, delta; 2176 2177 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2178 if (ISSET(lsr, LSR_BI)) { 2179 int cn_trapped = 0; /* see above: cn_trap() */ 2180 2181 cn_check_magic(sc->sc_tty->t_dev, 2182 CNC_BREAK, com_cnm_state); 2183 if (cn_trapped) 2184 continue; 2185 #if defined(KGDB) && !defined(DDB) 2186 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2187 kgdb_connect(1); 2188 continue; 2189 } 2190 #endif 2191 } 2192 2193 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2194 lsr |= LSR_RXRDY; 2195 2196 if (ISSET(lsr, LSR_RCV_MASK) && 2197 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2198 while (cc > 0) { 2199 int cn_trapped = 0; 2200 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2201 put[1] = lsr; 2202 cn_check_magic(sc->sc_tty->t_dev, 2203 put[0], com_cnm_state); 2204 if (cn_trapped) 2205 goto next; 2206 put += 2; 2207 if (put >= end) 2208 put = sc->sc_rbuf; 2209 cc--; 2210 next: 2211 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2212 if (!ISSET(lsr, LSR_RCV_MASK)) 2213 break; 2214 } 2215 2216 /* 2217 * Current string of incoming characters ended because 2218 * no more data was available or we ran out of space. 2219 * Schedule a receive event if any data was received. 2220 * If we're out of space, turn off receive interrupts. 2221 */ 2222 sc->sc_rbput = put; 2223 sc->sc_rbavail = cc; 2224 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2225 sc->sc_rx_ready = 1; 2226 2227 /* 2228 * See if we are in danger of overflowing a buffer. If 2229 * so, use hardware flow control to ease the pressure. 2230 */ 2231 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2232 cc < sc->sc_r_hiwat) { 2233 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2234 com_hwiflow(sc); 2235 } 2236 2237 /* 2238 * If we're out of space, disable receive interrupts 2239 * until the queue has drained a bit. 2240 */ 2241 if (!cc) { 2242 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2243 switch (sc->sc_type) { 2244 case COM_TYPE_PXA2x0: 2245 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2246 break; 2247 case COM_TYPE_INGENIC: 2248 case COM_TYPE_TEGRA: 2249 CLR(sc->sc_ier, 2250 IER_ERXRDY | IER_ERXTOUT); 2251 break; 2252 default: 2253 CLR(sc->sc_ier, IER_ERXRDY); 2254 break; 2255 } 2256 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2257 } 2258 } else { 2259 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2260 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2261 continue; 2262 } 2263 } 2264 2265 msr = CSR_READ_1(regsp, COM_REG_MSR); 2266 delta = msr ^ sc->sc_msr; 2267 sc->sc_msr = msr; 2268 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2269 (delta & MSR_DCD)) { 2270 mutex_spin_enter(&timecounter_lock); 2271 pps_capture(&sc->sc_pps_state); 2272 pps_event(&sc->sc_pps_state, 2273 (msr & MSR_DCD) ? 2274 PPS_CAPTUREASSERT : 2275 PPS_CAPTURECLEAR); 2276 mutex_spin_exit(&timecounter_lock); 2277 } 2278 2279 /* 2280 * Process normal status changes 2281 */ 2282 if (ISSET(delta, sc->sc_msr_mask)) { 2283 SET(sc->sc_msr_delta, delta); 2284 2285 /* 2286 * Stop output immediately if we lose the output 2287 * flow control signal or carrier detect. 2288 */ 2289 if (ISSET(~msr, sc->sc_msr_mask)) { 2290 sc->sc_tbc = 0; 2291 sc->sc_heldtbc = 0; 2292 #ifdef COM_DEBUG 2293 if (com_debug) 2294 comstatus(sc, "comintr "); 2295 #endif 2296 } 2297 2298 sc->sc_st_check = 1; 2299 } 2300 } while (!ISSET((iir = 2301 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2302 /* 2303 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2304 * by IIR read, so we can't do this way: `process all interrupts, 2305 * then do TX if possible'. 2306 */ 2307 (iir & IIR_IMASK) != IIR_TXRDY); 2308 2309 /* 2310 * Read LSR again, since there may be an interrupt between 2311 * the last LSR read and IIR read above. 2312 */ 2313 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2314 2315 /* 2316 * See if data can be transmitted as well. 2317 * Schedule tx done event if no data left 2318 * and tty was marked busy. 2319 */ 2320 if (ISSET(lsr, LSR_TXRDY)) { 2321 /* 2322 * If we've delayed a parameter change, do it now, and restart 2323 * output. 2324 */ 2325 if (sc->sc_heldchange) { 2326 com_loadchannelregs(sc); 2327 sc->sc_heldchange = 0; 2328 sc->sc_tbc = sc->sc_heldtbc; 2329 sc->sc_heldtbc = 0; 2330 } 2331 2332 /* Output the next chunk of the contiguous buffer, if any. */ 2333 if (sc->sc_tbc > 0) { 2334 u_int n; 2335 2336 n = sc->sc_tbc; 2337 if (n > sc->sc_fifolen) 2338 n = sc->sc_fifolen; 2339 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2340 sc->sc_tbc -= n; 2341 sc->sc_tba += n; 2342 } else { 2343 /* Disable transmit completion interrupts if necessary. */ 2344 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2345 CLR(sc->sc_ier, IER_ETXRDY); 2346 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2347 } 2348 if (sc->sc_tx_busy) { 2349 sc->sc_tx_busy = 0; 2350 sc->sc_tx_done = 1; 2351 } 2352 } 2353 } 2354 2355 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2356 goto again; 2357 2358 mutex_spin_exit(&sc->sc_lock); 2359 2360 /* Wake up the poller. */ 2361 softint_schedule(sc->sc_si); 2362 2363 #ifdef RND_COM 2364 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2365 #endif 2366 2367 return (1); 2368 } 2369 2370 /* 2371 * The following functions are polled getc and putc routines, shared 2372 * by the console and kgdb glue. 2373 * 2374 * The read-ahead code is so that you can detect pending in-band 2375 * cn_magic in polled mode while doing output rather than having to 2376 * wait until the kernel decides it needs input. 2377 */ 2378 2379 #define MAX_READAHEAD 20 2380 static int com_readahead[MAX_READAHEAD]; 2381 static int com_readaheadcount = 0; 2382 2383 int 2384 com_common_getc(dev_t dev, struct com_regs *regsp) 2385 { 2386 int s = splserial(); 2387 u_char stat, c; 2388 2389 /* got a character from reading things earlier */ 2390 if (com_readaheadcount > 0) { 2391 int i; 2392 2393 c = com_readahead[0]; 2394 for (i = 1; i < com_readaheadcount; i++) { 2395 com_readahead[i-1] = com_readahead[i]; 2396 } 2397 com_readaheadcount--; 2398 splx(s); 2399 return (c); 2400 } 2401 2402 /* don't block until a character becomes available */ 2403 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2404 splx(s); 2405 return -1; 2406 } 2407 2408 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2409 stat = CSR_READ_1(regsp, COM_REG_IIR); 2410 { 2411 int cn_trapped = 0; /* required by cn_trap, see above */ 2412 #ifdef DDB 2413 extern int db_active; 2414 if (!db_active) 2415 #endif 2416 cn_check_magic(dev, c, com_cnm_state); 2417 } 2418 splx(s); 2419 return (c); 2420 } 2421 2422 static void 2423 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead) 2424 { 2425 int s = splserial(); 2426 int cin, stat, timo; 2427 2428 if (with_readahead && com_readaheadcount < MAX_READAHEAD 2429 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2430 int cn_trapped = 0; 2431 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2432 stat = CSR_READ_1(regsp, COM_REG_IIR); 2433 cn_check_magic(dev, cin, com_cnm_state); 2434 com_readahead[com_readaheadcount++] = cin; 2435 } 2436 2437 /* wait for any pending transmission to finish */ 2438 timo = 150000; 2439 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2440 continue; 2441 2442 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2443 COM_BARRIER(regsp, BR | BW); 2444 2445 splx(s); 2446 } 2447 2448 /* 2449 * Initialize UART for use as console or KGDB line. 2450 */ 2451 int 2452 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2453 tcflag_t cflag) 2454 { 2455 2456 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2457 ®sp->cr_ioh)) 2458 return (ENOMEM); /* ??? */ 2459 2460 if (type == COM_TYPE_OMAP) { 2461 /* disable before changing settings */ 2462 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2463 } 2464 2465 rate = comspeed(rate, frequency, type); 2466 if (rate != -1) { 2467 if (type == COM_TYPE_AU1x00) { 2468 /* no EFR on alchemy */ 2469 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2470 } else { 2471 if ((type != COM_TYPE_16550_NOERS) && 2472 (type != COM_TYPE_INGENIC)) { 2473 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2474 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2475 } 2476 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2477 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2478 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2479 } 2480 } 2481 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2482 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2483 2484 if (type == COM_TYPE_INGENIC) { 2485 CSR_WRITE_1(regsp, COM_REG_FIFO, 2486 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2487 FIFO_TRIGGER_1 | FIFO_UART_ON); 2488 } else { 2489 CSR_WRITE_1(regsp, COM_REG_FIFO, 2490 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2491 FIFO_TRIGGER_1); 2492 } 2493 2494 if (type == COM_TYPE_OMAP) { 2495 /* setup the fifos. the FCR value is not used as long 2496 as SCR[6] and SCR[7] are 0, which they are at reset 2497 and we never touch the SCR register */ 2498 uint8_t rx_fifo_trig = 40; 2499 uint8_t tx_fifo_trig = 60; 2500 uint8_t rx_start = 8; 2501 uint8_t rx_halt = 60; 2502 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2503 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2504 2505 /* enable access to TCR & TLR */ 2506 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2507 2508 /* write tcr and tlr values */ 2509 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2510 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2511 2512 /* disable access to TCR & TLR */ 2513 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2514 2515 /* enable again, but mode is based on speed */ 2516 if (rate > 230400) { 2517 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2518 } else { 2519 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2520 } 2521 } 2522 2523 if (type == COM_TYPE_PXA2x0) 2524 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2525 else 2526 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2527 2528 return (0); 2529 } 2530 2531 int 2532 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2533 tcflag_t cflag) 2534 { 2535 int res; 2536 2537 comcons_info.regs = *regsp; 2538 2539 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2540 if (res) 2541 return (res); 2542 2543 cn_tab = &comcons; 2544 cn_init_magic(&com_cnm_state); 2545 cn_set_magic("\047\001"); /* default magic is BREAK */ 2546 2547 comcons_info.frequency = frequency; 2548 comcons_info.type = type; 2549 comcons_info.rate = rate; 2550 comcons_info.cflag = cflag; 2551 2552 return (0); 2553 } 2554 2555 int 2556 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2557 int type, tcflag_t cflag) 2558 { 2559 struct com_regs regs; 2560 2561 /*XXX*/ 2562 bus_space_handle_t dummy_bsh; 2563 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2564 2565 /* 2566 * dummy_bsh required because com_init_regs() wants it. A 2567 * real bus_space_handle will be filled in by cominit() later. 2568 * XXXJRT Detangle this mess eventually, plz. 2569 */ 2570 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2571 2572 return comcnattach1(®s, rate, frequency, type, cflag); 2573 } 2574 2575 static int 2576 comcnreattach(void) 2577 { 2578 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2579 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2580 } 2581 2582 int 2583 comcngetc(dev_t dev) 2584 { 2585 2586 return (com_common_getc(dev, &comcons_info.regs)); 2587 } 2588 2589 /* 2590 * Console kernel output character routine. 2591 */ 2592 void 2593 comcnputc(dev_t dev, int c) 2594 { 2595 2596 com_common_putc(dev, &comcons_info.regs, c, cold); 2597 } 2598 2599 void 2600 comcnpollc(dev_t dev, int on) 2601 { 2602 2603 com_readaheadcount = 0; 2604 } 2605 2606 #ifdef KGDB 2607 int 2608 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2609 tcflag_t cflag) 2610 { 2611 int res; 2612 2613 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2614 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2615 #if !defined(DDB) 2616 return (EBUSY); /* cannot share with console */ 2617 #else 2618 comkgdbregs = *regsp; 2619 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2620 #endif 2621 } else { 2622 comkgdbregs = *regsp; 2623 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2624 if (res) 2625 return (res); 2626 2627 /* 2628 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2629 * expects this to be initialized 2630 */ 2631 cn_init_magic(&com_cnm_state); 2632 cn_set_magic("\047\001"); 2633 } 2634 2635 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2636 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2637 2638 return (0); 2639 } 2640 2641 int 2642 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2643 int frequency, int type, tcflag_t cflag) 2644 { 2645 struct com_regs regs; 2646 2647 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2648 2649 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2650 } 2651 2652 /* ARGSUSED */ 2653 int 2654 com_kgdb_getc(void *arg) 2655 { 2656 2657 return (com_common_getc(NODEV, &comkgdbregs)); 2658 } 2659 2660 /* ARGSUSED */ 2661 void 2662 com_kgdb_putc(void *arg, int c) 2663 { 2664 2665 com_common_putc(NODEV, &comkgdbregs, c, 0); 2666 } 2667 #endif /* KGDB */ 2668 2669 /* helper function to identify the com ports used by 2670 console or KGDB (and not yet autoconf attached) */ 2671 int 2672 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2673 { 2674 bus_space_handle_t help; 2675 2676 if (!comconsattached && 2677 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2678 iobase == comcons_info.regs.cr_iobase) 2679 help = comcons_info.regs.cr_ioh; 2680 #ifdef KGDB 2681 else if (!com_kgdb_attached && 2682 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2683 iobase == comkgdbregs.cr_iobase) 2684 help = comkgdbregs.cr_ioh; 2685 #endif 2686 else 2687 return (0); 2688 2689 if (ioh) 2690 *ioh = help; 2691 return (1); 2692 } 2693 2694 /* 2695 * this routine exists to serve as a shutdown hook for systems that 2696 * have firmware which doesn't interact properly with a com device in 2697 * FIFO mode. 2698 */ 2699 bool 2700 com_cleanup(device_t self, int how) 2701 { 2702 struct com_softc *sc = device_private(self); 2703 2704 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2705 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2706 2707 return true; 2708 } 2709 2710 bool 2711 com_suspend(device_t self, const pmf_qual_t *qual) 2712 { 2713 struct com_softc *sc = device_private(self); 2714 2715 #if 0 2716 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2717 cn_tab = &comcons_suspend; 2718 #endif 2719 2720 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2721 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2722 2723 return true; 2724 } 2725 2726 bool 2727 com_resume(device_t self, const pmf_qual_t *qual) 2728 { 2729 struct com_softc *sc = device_private(self); 2730 2731 mutex_spin_enter(&sc->sc_lock); 2732 com_loadchannelregs(sc); 2733 mutex_spin_exit(&sc->sc_lock); 2734 2735 return true; 2736 } 2737
Indexes created Thu Sep 25 16:09:42 GMT 2025