com.c revision 1.363.2.1
1 /* $NetBSD: com.c,v 1.363.2.1 2021/08/01 22:42:23 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.363.2.1 2021/08/01 22:42:23 thorpej Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #define CSR_WRITE_1(r, o, v) \ 132 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 133 #define CSR_READ_1(r, o) \ 134 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 135 #define CSR_WRITE_2(r, o, v) \ 136 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 137 #define CSR_READ_2(r, o) \ 138 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 139 #define CSR_WRITE_MULTI(r, o, p, n) \ 140 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 141 142 143 static void com_enable_debugport(struct com_softc *); 144 145 void com_config(struct com_softc *); 146 void com_shutdown(struct com_softc *); 147 int comspeed(long, long, int); 148 static u_char cflag2lcr(tcflag_t); 149 int comparam(struct tty *, struct termios *); 150 void comstart(struct tty *); 151 int comhwiflow(struct tty *, int); 152 153 void com_loadchannelregs(struct com_softc *); 154 void com_hwiflow(struct com_softc *); 155 void com_break(struct com_softc *, int); 156 void com_modem(struct com_softc *, int); 157 void tiocm_to_com(struct com_softc *, u_long, int); 158 int com_to_tiocm(struct com_softc *); 159 void com_iflush(struct com_softc *); 160 161 int com_common_getc(dev_t, struct com_regs *); 162 static void com_common_putc(dev_t, struct com_regs *, int, int); 163 164 int cominit(struct com_regs *, int, int, int, tcflag_t); 165 166 static int comcnreattach(void); 167 168 int comcngetc(dev_t); 169 void comcnputc(dev_t, int); 170 void comcnpollc(dev_t, int); 171 172 #define integrate static inline 173 void comsoft(void *); 174 integrate void com_rxsoft(struct com_softc *, struct tty *); 175 integrate void com_txsoft(struct com_softc *, struct tty *); 176 integrate void com_stsoft(struct com_softc *, struct tty *); 177 integrate void com_schedrx(struct com_softc *); 178 void comdiag(void *); 179 180 dev_type_open(comopen); 181 dev_type_close(comclose); 182 dev_type_read(comread); 183 dev_type_write(comwrite); 184 dev_type_ioctl(comioctl); 185 dev_type_stop(comstop); 186 dev_type_tty(comtty); 187 dev_type_poll(compoll); 188 189 static struct comcons_info comcons_info; 190 191 /* 192 * Following are all routines needed for COM to act as console 193 */ 194 static struct consdev comcons = { 195 .cn_getc = comcngetc, 196 .cn_putc = comcnputc, 197 .cn_pollc = comcnpollc, 198 .cn_dev = NODEV, 199 .cn_pri = CN_NORMAL 200 }; 201 202 203 const struct cdevsw com_cdevsw = { 204 .d_open = comopen, 205 .d_close = comclose, 206 .d_read = comread, 207 .d_write = comwrite, 208 .d_ioctl = comioctl, 209 .d_stop = comstop, 210 .d_tty = comtty, 211 .d_poll = compoll, 212 .d_mmap = nommap, 213 .d_kqfilter = ttykqfilter, 214 .d_discard = nodiscard, 215 .d_flag = D_TTY 216 }; 217 218 /* 219 * Make this an option variable one can patch. 220 * But be warned: this must be a power of 2! 221 */ 222 u_int com_rbuf_size = COM_RING_SIZE; 223 224 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 225 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 226 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 227 228 static int comconsattached; 229 static struct cnm_state com_cnm_state; 230 231 #ifdef KGDB 232 #include <sys/kgdb.h> 233 234 static struct com_regs comkgdbregs; 235 static int com_kgdb_attached; 236 237 int com_kgdb_getc(void *); 238 void com_kgdb_putc(void *, int); 239 #endif /* KGDB */ 240 241 /* initializer for typical 16550-ish hardware */ 242 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 243 [COM_REG_RXDATA] = com_data, 244 [COM_REG_TXDATA] = com_data, 245 [COM_REG_DLBL] = com_dlbl, 246 [COM_REG_DLBH] = com_dlbh, 247 [COM_REG_IER] = com_ier, 248 [COM_REG_IIR] = com_iir, 249 [COM_REG_FIFO] = com_fifo, 250 [COM_REG_TCR] = com_fifo, 251 [COM_REG_EFR] = com_efr, 252 [COM_REG_TLR] = com_efr, 253 [COM_REG_LCR] = com_lcr, 254 [COM_REG_MCR] = com_mcr, 255 [COM_REG_LSR] = com_lsr, 256 [COM_REG_MSR] = com_msr, 257 [COM_REG_USR] = com_usr, 258 [COM_REG_TFL] = com_tfl, 259 [COM_REG_RFL] = com_rfl, 260 [COM_REG_HALT] = com_halt, 261 [COM_REG_MDR1] = com_mdr1, 262 }; 263 264 #define COMDIALOUT_MASK TTDIALOUT_MASK 265 266 #define COMUNIT(x) TTUNIT(x) 267 #define COMDIALOUT(x) TTDIALOUT(x) 268 269 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 270 device_is_active((sc)->sc_dev)) 271 272 #define BR BUS_SPACE_BARRIER_READ 273 #define BW BUS_SPACE_BARRIER_WRITE 274 #define COM_BARRIER(r, f) \ 275 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 276 277 /* 278 * com_init_regs -- 279 * Driver front-ends use this to initialize our register map 280 * in the standard fashion. They may then tailor the map to 281 * their own particular requirements. 282 */ 283 void 284 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 285 bus_addr_t addr) 286 { 287 288 memset(regs, 0, sizeof(*regs)); 289 regs->cr_iot = st; 290 regs->cr_ioh = sh; 291 regs->cr_iobase = addr; 292 regs->cr_nports = COM_NPORTS; 293 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 294 } 295 296 /* 297 * com_init_regs_stride -- 298 * Convenience function for front-ends that have a stride between 299 * registers. 300 */ 301 void 302 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 303 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 304 { 305 306 com_init_regs(regs, st, sh, addr); 307 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 308 regs->cr_map[i] <<= regshift; 309 } 310 regs->cr_nports <<= regshift; 311 } 312 313 /*ARGSUSED*/ 314 int 315 comspeed(long speed, long frequency, int type) 316 { 317 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 318 319 int x, err; 320 int divisor = 16; 321 322 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 323 divisor = 13; 324 } 325 326 if (speed == 0) 327 return (0); 328 if (speed < 0) 329 return (-1); 330 x = divrnd(frequency / divisor, speed); 331 if (x <= 0) 332 return (-1); 333 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 334 if (err < 0) 335 err = -err; 336 if (err > COM_TOLERANCE) 337 return (-1); 338 return (x); 339 340 #undef divrnd 341 } 342 343 #ifdef COM_DEBUG 344 int com_debug = 0; 345 346 void comstatus(struct com_softc *, const char *); 347 void 348 comstatus(struct com_softc *sc, const char *str) 349 { 350 struct tty *tp = sc->sc_tty; 351 352 aprint_normal_dev(sc->sc_dev, 353 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 354 str, 355 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 356 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 357 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 358 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 359 sc->sc_tx_stopped ? '+' : '-'); 360 361 aprint_normal_dev(sc->sc_dev, 362 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 363 str, 364 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 365 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 366 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 367 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 368 sc->sc_rx_flags); 369 } 370 #endif 371 372 int 373 com_probe_subr(struct com_regs *regs) 374 { 375 376 /* force access to id reg */ 377 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 378 CSR_WRITE_1(regs, COM_REG_IIR, 0); 379 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 380 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 381 return (0); 382 383 return (1); 384 } 385 386 int 387 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 388 { 389 struct com_regs regs; 390 391 com_init_regs(®s, iot, ioh, 0/*XXX*/); 392 393 return com_probe_subr(®s); 394 } 395 396 /* 397 * No locking in this routine; it is only called during attach, 398 * or with the port already locked. 399 */ 400 static void 401 com_enable_debugport(struct com_softc *sc) 402 { 403 404 /* Turn on line break interrupt, set carrier. */ 405 sc->sc_ier = IER_ERLS; 406 if (sc->sc_type == COM_TYPE_PXA2x0) 407 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 408 if (sc->sc_type == COM_TYPE_INGENIC || 409 sc->sc_type == COM_TYPE_TEGRA) 410 sc->sc_ier |= IER_ERXTOUT; 411 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 412 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 413 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 414 } 415 416 static void 417 com_intr_poll(void *arg) 418 { 419 struct com_softc * const sc = arg; 420 421 comintr(sc); 422 423 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 424 } 425 426 void 427 com_attach_subr(struct com_softc *sc) 428 { 429 struct com_regs *regsp = &sc->sc_regs; 430 struct tty *tp; 431 uint32_t cpr; 432 uint8_t lcr; 433 const char *fifo_msg = NULL; 434 prop_dictionary_t dict; 435 bool is_console = true; 436 bool force_console = false; 437 438 aprint_naive("\n"); 439 440 dict = device_properties(sc->sc_dev); 441 prop_dictionary_get_bool(dict, "is_console", &is_console); 442 prop_dictionary_get_bool(dict, "force_console", &force_console); 443 callout_init(&sc->sc_diag_callout, 0); 444 callout_init(&sc->sc_poll_callout, 0); 445 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 446 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 447 448 #if defined(COM_16650) 449 sc->sc_type = COM_TYPE_16650; 450 #elif defined(COM_16750) 451 sc->sc_type = COM_TYPE_16750; 452 #elif defined(COM_HAYESP) 453 sc->sc_type = COM_TYPE_HAYESP; 454 #elif defined(COM_PXA2X0) 455 sc->sc_type = COM_TYPE_PXA2x0; 456 #endif 457 458 /* Disable interrupts before configuring the device. */ 459 if (sc->sc_type == COM_TYPE_PXA2x0) 460 sc->sc_ier = IER_EUART; 461 else 462 sc->sc_ier = 0; 463 464 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 465 466 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 467 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 468 comconsattached = 1; 469 470 if (force_console) 471 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 472 473 if (cn_tab == NULL && comcnreattach() != 0) { 474 printf("can't re-init serial console @%lx\n", 475 (u_long)comcons_info.regs.cr_iobase); 476 } 477 478 switch (sc->sc_type) { 479 case COM_TYPE_16750: 480 case COM_TYPE_DW_APB: 481 /* Use in comintr(). */ 482 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 483 break; 484 } 485 486 /* Make sure the console is always "hardwired". */ 487 delay(10000); /* wait for output to finish */ 488 if (is_console) { 489 SET(sc->sc_hwflags, COM_HW_CONSOLE); 490 } 491 492 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 493 } 494 495 /* Probe for FIFO */ 496 switch (sc->sc_type) { 497 case COM_TYPE_HAYESP: 498 goto fifodone; 499 500 case COM_TYPE_AU1x00: 501 sc->sc_fifolen = 16; 502 fifo_msg = "Au1X00 UART"; 503 SET(sc->sc_hwflags, COM_HW_FIFO); 504 goto fifodelay; 505 506 case COM_TYPE_16550_NOERS: 507 sc->sc_fifolen = 16; 508 fifo_msg = "ns16650, no ERS"; 509 SET(sc->sc_hwflags, COM_HW_FIFO); 510 goto fifodelay; 511 512 case COM_TYPE_OMAP: 513 sc->sc_fifolen = 64; 514 fifo_msg = "OMAP UART"; 515 SET(sc->sc_hwflags, COM_HW_FIFO); 516 goto fifodelay; 517 518 case COM_TYPE_INGENIC: 519 sc->sc_fifolen = 16; 520 fifo_msg = "Ingenic UART"; 521 SET(sc->sc_hwflags, COM_HW_FIFO); 522 SET(sc->sc_hwflags, COM_HW_NOIEN); 523 goto fifodelay; 524 525 case COM_TYPE_TEGRA: 526 sc->sc_fifolen = 8; 527 fifo_msg = "Tegra UART"; 528 SET(sc->sc_hwflags, COM_HW_FIFO); 529 CSR_WRITE_1(regsp, COM_REG_FIFO, 530 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 531 goto fifodelay; 532 533 case COM_TYPE_BCMAUXUART: 534 sc->sc_fifolen = 1; 535 fifo_msg = "BCM AUX UART"; 536 SET(sc->sc_hwflags, COM_HW_FIFO); 537 CSR_WRITE_1(regsp, COM_REG_FIFO, 538 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 539 goto fifodelay; 540 541 case COM_TYPE_DW_APB: 542 if (!prop_dictionary_get_uint(dict, "fifolen", &sc->sc_fifolen)) { 543 cpr = bus_space_read_4(sc->sc_regs.cr_iot, 544 sc->sc_regs.cr_ioh, DW_APB_UART_CPR); 545 sc->sc_fifolen = __SHIFTOUT(cpr, UART_CPR_FIFO_MODE) * 16; 546 } 547 if (sc->sc_fifolen == 0) { 548 sc->sc_fifolen = 1; 549 fifo_msg = "DesignWare APB UART, no fifo"; 550 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 551 } else { 552 fifo_msg = "DesignWare APB UART"; 553 SET(sc->sc_hwflags, COM_HW_FIFO); 554 CSR_WRITE_1(regsp, COM_REG_FIFO, 555 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 556 } 557 goto fifodelay; 558 } 559 560 sc->sc_fifolen = 1; 561 /* look for a NS 16550AF UART with FIFOs */ 562 if (sc->sc_type == COM_TYPE_INGENIC) { 563 CSR_WRITE_1(regsp, COM_REG_FIFO, 564 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 565 FIFO_TRIGGER_14 | FIFO_UART_ON); 566 } else 567 CSR_WRITE_1(regsp, COM_REG_FIFO, 568 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 569 delay(100); 570 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 571 == IIR_FIFO_MASK) 572 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 573 == FIFO_TRIGGER_14) { 574 SET(sc->sc_hwflags, COM_HW_FIFO); 575 576 fifo_msg = "ns16550a"; 577 578 /* 579 * IIR changes into the EFR if LCR is set to LCR_EERS 580 * on 16650s. We also know IIR != 0 at this point. 581 * Write 0 into the EFR, and read it. If the result 582 * is 0, we have a 16650. 583 * 584 * Older 16650s were broken; the test to detect them 585 * is taken from the Linux driver. Apparently 586 * setting DLAB enable gives access to the EFR on 587 * these chips. 588 */ 589 if (sc->sc_type == COM_TYPE_16650) { 590 lcr = CSR_READ_1(regsp, COM_REG_LCR); 591 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 592 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 593 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 594 CSR_WRITE_1(regsp, COM_REG_LCR, 595 lcr | LCR_DLAB); 596 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 597 CLR(sc->sc_hwflags, COM_HW_FIFO); 598 sc->sc_fifolen = 0; 599 } else { 600 SET(sc->sc_hwflags, COM_HW_FLOW); 601 sc->sc_fifolen = 32; 602 } 603 } else 604 sc->sc_fifolen = 16; 605 606 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 607 if (sc->sc_fifolen == 0) 608 fifo_msg = "st16650, broken fifo"; 609 else if (sc->sc_fifolen == 32) 610 fifo_msg = "st16650a"; 611 else 612 fifo_msg = "ns16550a"; 613 } 614 615 /* 616 * TL16C750 can enable 64byte FIFO, only when DLAB 617 * is 1. However, some 16750 may always enable. For 618 * example, restrictions according to DLAB in a data 619 * sheet for SC16C750 were not described. 620 * Please enable 'options COM_16650', supposing you 621 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 622 * should become effective. 623 */ 624 if (sc->sc_type == COM_TYPE_16750) { 625 uint8_t iir1, iir2; 626 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 627 628 lcr = CSR_READ_1(regsp, COM_REG_LCR); 629 CSR_WRITE_1(regsp, COM_REG_LCR, 630 lcr & ~LCR_DLAB); 631 CSR_WRITE_1(regsp, COM_REG_FIFO, 632 fcr | FIFO_64B_ENABLE); 633 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 634 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 635 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 636 CSR_WRITE_1(regsp, COM_REG_FIFO, 637 fcr | FIFO_64B_ENABLE); 638 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 639 640 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 641 642 if (!ISSET(iir1, IIR_64B_FIFO) && 643 ISSET(iir2, IIR_64B_FIFO)) { 644 /* It is TL16C750. */ 645 sc->sc_fifolen = 64; 646 SET(sc->sc_hwflags, COM_HW_AFE); 647 } else 648 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 649 650 if (sc->sc_fifolen == 64) 651 fifo_msg = "tl16c750"; 652 else 653 fifo_msg = "ns16750"; 654 } 655 } else 656 fifo_msg = "ns16550, broken fifo"; 657 else 658 fifo_msg = "ns8250 or ns16450, no fifo"; 659 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 660 661 fifodelay: 662 /* 663 * Some chips will clear down both Tx and Rx FIFOs when zero is 664 * written to com_fifo. If this chip is the console, writing zero 665 * results in some of the chip/FIFO description being lost, so delay 666 * printing it until now. 667 */ 668 delay(10); 669 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 670 aprint_normal(": %s, %d-byte FIFO\n", fifo_msg, sc->sc_fifolen); 671 } else { 672 aprint_normal(": %s\n", fifo_msg); 673 } 674 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 675 sc->sc_fifolen = 1; 676 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 677 } 678 679 fifodone: 680 681 tp = tty_alloc(); 682 tp->t_oproc = comstart; 683 tp->t_param = comparam; 684 tp->t_hwiflow = comhwiflow; 685 tp->t_softc = sc; 686 687 sc->sc_tty = tp; 688 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK); 689 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 690 sc->sc_rbavail = com_rbuf_size; 691 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 692 693 tty_attach(tp); 694 695 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 696 SET(sc->sc_mcr, MCR_IENABLE); 697 698 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 699 int maj; 700 701 /* locate the major number */ 702 maj = cdevsw_lookup_major(&com_cdevsw); 703 704 tp->t_dev = cn_tab->cn_dev = makedev(maj, 705 device_unit(sc->sc_dev)); 706 707 aprint_normal_dev(sc->sc_dev, "console\n"); 708 } 709 710 #ifdef KGDB 711 /* 712 * Allow kgdb to "take over" this port. If this is 713 * not the console and is the kgdb device, it has 714 * exclusive use. If it's the console _and_ the 715 * kgdb device, it doesn't. 716 */ 717 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 718 regsp->cr_iobase == comkgdbregs.cr_iobase) { 719 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 720 com_kgdb_attached = 1; 721 722 SET(sc->sc_hwflags, COM_HW_KGDB); 723 } 724 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 725 } 726 #endif 727 728 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 729 730 #ifdef RND_COM 731 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 732 RND_TYPE_TTY, RND_FLAG_DEFAULT); 733 #endif 734 735 /* if there are no enable/disable functions, assume the device 736 is always enabled */ 737 if (!sc->enable) 738 sc->enabled = 1; 739 740 com_config(sc); 741 742 SET(sc->sc_hwflags, COM_HW_DEV_OK); 743 744 if (sc->sc_poll_ticks != 0) 745 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 746 } 747 748 void 749 com_config(struct com_softc *sc) 750 { 751 struct com_regs *regsp = &sc->sc_regs; 752 753 /* Disable interrupts before configuring the device. */ 754 if (sc->sc_type == COM_TYPE_PXA2x0) 755 sc->sc_ier = IER_EUART; 756 else 757 sc->sc_ier = 0; 758 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 759 (void) CSR_READ_1(regsp, COM_REG_IIR); 760 761 /* Look for a Hayes ESP board. */ 762 if (sc->sc_type == COM_TYPE_HAYESP) { 763 764 /* Set 16550 compatibility mode */ 765 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 766 HAYESP_SETMODE); 767 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 768 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 769 HAYESP_MODE_SCALE); 770 771 /* Set RTS/CTS flow control */ 772 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 773 HAYESP_SETFLOWTYPE); 774 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 775 HAYESP_FLOW_RTS); 776 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 777 HAYESP_FLOW_CTS); 778 779 /* Set flow control levels */ 780 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 781 HAYESP_SETRXFLOW); 782 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 783 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 784 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 785 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 786 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 787 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 788 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 789 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 790 } 791 792 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 793 com_enable_debugport(sc); 794 } 795 796 #if 0 797 static int 798 comcngetc_detached(dev_t dev) 799 { 800 return 0; 801 } 802 803 static void 804 comcnputc_detached(dev_t dev, int c) 805 { 806 } 807 #endif 808 809 int 810 com_detach(device_t self, int flags) 811 { 812 struct com_softc *sc = device_private(self); 813 int maj, mn; 814 815 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 816 return EBUSY; 817 818 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 819 (flags & DETACH_SHUTDOWN) != 0) 820 return EBUSY; 821 822 if (sc->disable != NULL && sc->enabled != 0) { 823 (*sc->disable)(sc); 824 sc->enabled = 0; 825 } 826 827 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 828 comconsattached = 0; 829 cn_tab = NULL; 830 } 831 832 /* locate the major number */ 833 maj = cdevsw_lookup_major(&com_cdevsw); 834 835 /* Nuke the vnodes for any open instances. */ 836 mn = device_unit(self); 837 vdevgone(maj, mn, mn, VCHR); 838 839 mn |= COMDIALOUT_MASK; 840 vdevgone(maj, mn, mn, VCHR); 841 842 if (sc->sc_rbuf == NULL) { 843 /* 844 * Ring buffer allocation failed in the com_attach_subr, 845 * only the tty is allocated, and nothing else. 846 */ 847 tty_free(sc->sc_tty); 848 return 0; 849 } 850 851 /* Free the receive buffer. */ 852 free(sc->sc_rbuf, M_DEVBUF); 853 854 /* Detach and free the tty. */ 855 tty_detach(sc->sc_tty); 856 tty_free(sc->sc_tty); 857 858 /* Unhook the soft interrupt handler. */ 859 softint_disestablish(sc->sc_si); 860 861 #ifdef RND_COM 862 /* Unhook the entropy source. */ 863 rnd_detach_source(&sc->rnd_source); 864 #endif 865 callout_destroy(&sc->sc_diag_callout); 866 867 /* Destroy the lock. */ 868 mutex_destroy(&sc->sc_lock); 869 870 return (0); 871 } 872 873 void 874 com_shutdown(struct com_softc *sc) 875 { 876 struct tty *tp = sc->sc_tty; 877 878 mutex_spin_enter(&sc->sc_lock); 879 880 /* If we were asserting flow control, then deassert it. */ 881 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 882 com_hwiflow(sc); 883 884 /* Clear any break condition set with TIOCSBRK. */ 885 com_break(sc, 0); 886 887 /* 888 * Hang up if necessary. Wait a bit, so the other side has time to 889 * notice even if we immediately open the port again. 890 * Avoid tsleeping above splhigh(). 891 */ 892 if (ISSET(tp->t_cflag, HUPCL)) { 893 com_modem(sc, 0); 894 mutex_spin_exit(&sc->sc_lock); 895 /* XXX will only timeout */ 896 (void) kpause(ttclos, false, hz, NULL); 897 mutex_spin_enter(&sc->sc_lock); 898 } 899 900 /* Turn off interrupts. */ 901 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 902 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 903 if ((sc->sc_type == COM_TYPE_PXA2x0) || 904 (sc->sc_type == COM_TYPE_INGENIC) || 905 (sc->sc_type == COM_TYPE_TEGRA)) 906 sc->sc_ier |= IER_ERXTOUT; 907 } else 908 sc->sc_ier = 0; 909 910 if (sc->sc_type == COM_TYPE_PXA2x0) 911 sc->sc_ier |= IER_EUART; 912 913 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 914 915 mutex_spin_exit(&sc->sc_lock); 916 917 if (sc->disable) { 918 #ifdef DIAGNOSTIC 919 if (!sc->enabled) 920 panic("com_shutdown: not enabled?"); 921 #endif 922 (*sc->disable)(sc); 923 sc->enabled = 0; 924 } 925 } 926 927 int 928 comopen(dev_t dev, int flag, int mode, struct lwp *l) 929 { 930 struct com_softc *sc; 931 struct tty *tp; 932 int s; 933 int error; 934 935 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 936 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 937 sc->sc_rbuf == NULL) 938 return (ENXIO); 939 940 if (!device_is_active(sc->sc_dev)) 941 return (ENXIO); 942 943 #ifdef KGDB 944 /* 945 * If this is the kgdb port, no other use is permitted. 946 */ 947 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 948 return (EBUSY); 949 #endif 950 951 tp = sc->sc_tty; 952 953 /* 954 * If the device is exclusively for kernel use, deny userland 955 * open. 956 */ 957 if (ISSET(tp->t_state, TS_KERN_ONLY)) 958 return (EBUSY); 959 960 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 961 return (EBUSY); 962 963 s = spltty(); 964 965 /* 966 * Do the following iff this is a first open. 967 */ 968 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 969 struct termios t; 970 971 tp->t_dev = dev; 972 973 if (sc->enable) { 974 if ((*sc->enable)(sc)) { 975 splx(s); 976 aprint_error_dev(sc->sc_dev, 977 "device enable failed\n"); 978 return (EIO); 979 } 980 mutex_spin_enter(&sc->sc_lock); 981 sc->enabled = 1; 982 com_config(sc); 983 } else { 984 mutex_spin_enter(&sc->sc_lock); 985 } 986 987 /* Turn on interrupts. */ 988 sc->sc_ier = IER_ERXRDY | IER_ERLS; 989 if (!ISSET(tp->t_cflag, CLOCAL)) 990 sc->sc_ier |= IER_EMSC; 991 992 if (sc->sc_type == COM_TYPE_PXA2x0) 993 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 994 else if (sc->sc_type == COM_TYPE_INGENIC || 995 sc->sc_type == COM_TYPE_TEGRA) 996 sc->sc_ier |= IER_ERXTOUT; 997 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 998 999 /* Fetch the current modem control status, needed later. */ 1000 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 1001 1002 /* Clear PPS capture state on first open. */ 1003 mutex_spin_enter(&timecounter_lock); 1004 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 1005 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1006 pps_init(&sc->sc_pps_state); 1007 mutex_spin_exit(&timecounter_lock); 1008 1009 mutex_spin_exit(&sc->sc_lock); 1010 1011 /* 1012 * Initialize the termios status to the defaults. Add in the 1013 * sticky bits from TIOCSFLAGS. 1014 */ 1015 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1016 t.c_ospeed = comcons_info.rate; 1017 t.c_cflag = comcons_info.cflag; 1018 } else { 1019 t.c_ospeed = TTYDEF_SPEED; 1020 t.c_cflag = TTYDEF_CFLAG; 1021 } 1022 t.c_ispeed = t.c_ospeed; 1023 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1024 SET(t.c_cflag, CLOCAL); 1025 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1026 SET(t.c_cflag, CRTSCTS); 1027 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1028 SET(t.c_cflag, MDMBUF); 1029 /* Make sure comparam() will do something. */ 1030 tp->t_ospeed = 0; 1031 (void) comparam(tp, &t); 1032 tp->t_iflag = TTYDEF_IFLAG; 1033 tp->t_oflag = TTYDEF_OFLAG; 1034 tp->t_lflag = TTYDEF_LFLAG; 1035 ttychars(tp); 1036 ttsetwater(tp); 1037 1038 mutex_spin_enter(&sc->sc_lock); 1039 1040 /* 1041 * Turn on DTR. We must always do this, even if carrier is not 1042 * present, because otherwise we'd have to use TIOCSDTR 1043 * immediately after setting CLOCAL, which applications do not 1044 * expect. We always assert DTR while the device is open 1045 * unless explicitly requested to deassert it. 1046 */ 1047 com_modem(sc, 1); 1048 1049 /* Clear the input ring, and unblock. */ 1050 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1051 sc->sc_rbavail = com_rbuf_size; 1052 com_iflush(sc); 1053 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1054 com_hwiflow(sc); 1055 1056 #ifdef COM_DEBUG 1057 if (com_debug) 1058 comstatus(sc, "comopen "); 1059 #endif 1060 1061 mutex_spin_exit(&sc->sc_lock); 1062 } 1063 1064 splx(s); 1065 1066 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1067 if (error) 1068 goto bad; 1069 1070 error = (*tp->t_linesw->l_open)(dev, tp); 1071 if (error) 1072 goto bad; 1073 1074 return (0); 1075 1076 bad: 1077 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1078 /* 1079 * We failed to open the device, and nobody else had it opened. 1080 * Clean up the state as appropriate. 1081 */ 1082 com_shutdown(sc); 1083 } 1084 1085 return (error); 1086 } 1087 1088 int 1089 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1090 { 1091 struct com_softc *sc = 1092 device_lookup_private(&com_cd, COMUNIT(dev)); 1093 struct tty *tp = sc->sc_tty; 1094 1095 /* XXX This is for cons.c. */ 1096 if (!ISSET(tp->t_state, TS_ISOPEN)) 1097 return (0); 1098 /* 1099 * If the device is exclusively for kernel use, deny userland 1100 * close. 1101 */ 1102 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1103 return (0); 1104 1105 (*tp->t_linesw->l_close)(tp, flag); 1106 ttyclose(tp); 1107 1108 if (COM_ISALIVE(sc) == 0) 1109 return (0); 1110 1111 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1112 /* 1113 * Although we got a last close, the device may still be in 1114 * use; e.g. if this was the dialout node, and there are still 1115 * processes waiting for carrier on the non-dialout node. 1116 */ 1117 com_shutdown(sc); 1118 } 1119 1120 return (0); 1121 } 1122 1123 int 1124 comread(dev_t dev, struct uio *uio, int flag) 1125 { 1126 struct com_softc *sc = 1127 device_lookup_private(&com_cd, COMUNIT(dev)); 1128 struct tty *tp = sc->sc_tty; 1129 1130 if (COM_ISALIVE(sc) == 0) 1131 return (EIO); 1132 1133 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1134 } 1135 1136 int 1137 comwrite(dev_t dev, struct uio *uio, int flag) 1138 { 1139 struct com_softc *sc = 1140 device_lookup_private(&com_cd, COMUNIT(dev)); 1141 struct tty *tp = sc->sc_tty; 1142 1143 if (COM_ISALIVE(sc) == 0) 1144 return (EIO); 1145 1146 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1147 } 1148 1149 int 1150 compoll(dev_t dev, int events, struct lwp *l) 1151 { 1152 struct com_softc *sc = 1153 device_lookup_private(&com_cd, COMUNIT(dev)); 1154 struct tty *tp = sc->sc_tty; 1155 1156 if (COM_ISALIVE(sc) == 0) 1157 return (POLLHUP); 1158 1159 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1160 } 1161 1162 struct tty * 1163 comtty(dev_t dev) 1164 { 1165 struct com_softc *sc = 1166 device_lookup_private(&com_cd, COMUNIT(dev)); 1167 struct tty *tp = sc->sc_tty; 1168 1169 return (tp); 1170 } 1171 1172 int 1173 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1174 { 1175 struct com_softc *sc; 1176 struct tty *tp; 1177 int error; 1178 1179 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1180 if (sc == NULL) 1181 return ENXIO; 1182 if (COM_ISALIVE(sc) == 0) 1183 return (EIO); 1184 1185 tp = sc->sc_tty; 1186 1187 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1188 if (error != EPASSTHROUGH) 1189 return (error); 1190 1191 error = ttioctl(tp, cmd, data, flag, l); 1192 if (error != EPASSTHROUGH) 1193 return (error); 1194 1195 error = 0; 1196 switch (cmd) { 1197 case TIOCSFLAGS: 1198 error = kauth_authorize_device_tty(l->l_cred, 1199 KAUTH_DEVICE_TTY_PRIVSET, tp); 1200 break; 1201 default: 1202 /* nothing */ 1203 break; 1204 } 1205 if (error) { 1206 return error; 1207 } 1208 1209 mutex_spin_enter(&sc->sc_lock); 1210 1211 switch (cmd) { 1212 case TIOCSBRK: 1213 com_break(sc, 1); 1214 break; 1215 1216 case TIOCCBRK: 1217 com_break(sc, 0); 1218 break; 1219 1220 case TIOCSDTR: 1221 com_modem(sc, 1); 1222 break; 1223 1224 case TIOCCDTR: 1225 com_modem(sc, 0); 1226 break; 1227 1228 case TIOCGFLAGS: 1229 *(int *)data = sc->sc_swflags; 1230 break; 1231 1232 case TIOCSFLAGS: 1233 sc->sc_swflags = *(int *)data; 1234 break; 1235 1236 case TIOCMSET: 1237 case TIOCMBIS: 1238 case TIOCMBIC: 1239 tiocm_to_com(sc, cmd, *(int *)data); 1240 break; 1241 1242 case TIOCMGET: 1243 *(int *)data = com_to_tiocm(sc); 1244 break; 1245 1246 case PPS_IOC_CREATE: 1247 case PPS_IOC_DESTROY: 1248 case PPS_IOC_GETPARAMS: 1249 case PPS_IOC_SETPARAMS: 1250 case PPS_IOC_GETCAP: 1251 case PPS_IOC_FETCH: 1252 #ifdef PPS_SYNC 1253 case PPS_IOC_KCBIND: 1254 #endif 1255 mutex_spin_enter(&timecounter_lock); 1256 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1257 mutex_spin_exit(&timecounter_lock); 1258 break; 1259 1260 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1261 mutex_spin_enter(&timecounter_lock); 1262 #ifndef PPS_TRAILING_EDGE 1263 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1264 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1265 #else 1266 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1267 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1268 #endif 1269 mutex_spin_exit(&timecounter_lock); 1270 break; 1271 1272 default: 1273 error = EPASSTHROUGH; 1274 break; 1275 } 1276 1277 mutex_spin_exit(&sc->sc_lock); 1278 1279 #ifdef COM_DEBUG 1280 if (com_debug) 1281 comstatus(sc, "comioctl "); 1282 #endif 1283 1284 return (error); 1285 } 1286 1287 integrate void 1288 com_schedrx(struct com_softc *sc) 1289 { 1290 1291 sc->sc_rx_ready = 1; 1292 1293 /* Wake up the poller. */ 1294 softint_schedule(sc->sc_si); 1295 } 1296 1297 void 1298 com_break(struct com_softc *sc, int onoff) 1299 { 1300 1301 if (onoff) 1302 SET(sc->sc_lcr, LCR_SBREAK); 1303 else 1304 CLR(sc->sc_lcr, LCR_SBREAK); 1305 1306 if (!sc->sc_heldchange) { 1307 if (sc->sc_tx_busy) { 1308 sc->sc_heldtbc = sc->sc_tbc; 1309 sc->sc_tbc = 0; 1310 sc->sc_heldchange = 1; 1311 } else 1312 com_loadchannelregs(sc); 1313 } 1314 } 1315 1316 void 1317 com_modem(struct com_softc *sc, int onoff) 1318 { 1319 1320 if (sc->sc_mcr_dtr == 0) 1321 return; 1322 1323 if (onoff) 1324 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1325 else 1326 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1327 1328 if (!sc->sc_heldchange) { 1329 if (sc->sc_tx_busy) { 1330 sc->sc_heldtbc = sc->sc_tbc; 1331 sc->sc_tbc = 0; 1332 sc->sc_heldchange = 1; 1333 } else 1334 com_loadchannelregs(sc); 1335 } 1336 } 1337 1338 void 1339 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1340 { 1341 u_char combits; 1342 1343 combits = 0; 1344 if (ISSET(ttybits, TIOCM_DTR)) 1345 SET(combits, MCR_DTR); 1346 if (ISSET(ttybits, TIOCM_RTS)) 1347 SET(combits, MCR_RTS); 1348 1349 switch (how) { 1350 case TIOCMBIC: 1351 CLR(sc->sc_mcr, combits); 1352 break; 1353 1354 case TIOCMBIS: 1355 SET(sc->sc_mcr, combits); 1356 break; 1357 1358 case TIOCMSET: 1359 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1360 SET(sc->sc_mcr, combits); 1361 break; 1362 } 1363 1364 if (!sc->sc_heldchange) { 1365 if (sc->sc_tx_busy) { 1366 sc->sc_heldtbc = sc->sc_tbc; 1367 sc->sc_tbc = 0; 1368 sc->sc_heldchange = 1; 1369 } else 1370 com_loadchannelregs(sc); 1371 } 1372 } 1373 1374 int 1375 com_to_tiocm(struct com_softc *sc) 1376 { 1377 u_char combits; 1378 int ttybits = 0; 1379 1380 combits = sc->sc_mcr; 1381 if (ISSET(combits, MCR_DTR)) 1382 SET(ttybits, TIOCM_DTR); 1383 if (ISSET(combits, MCR_RTS)) 1384 SET(ttybits, TIOCM_RTS); 1385 1386 combits = sc->sc_msr; 1387 if (sc->sc_type == COM_TYPE_INGENIC) { 1388 SET(ttybits, TIOCM_CD); 1389 } else { 1390 if (ISSET(combits, MSR_DCD)) 1391 SET(ttybits, TIOCM_CD); 1392 } 1393 if (ISSET(combits, MSR_CTS)) 1394 SET(ttybits, TIOCM_CTS); 1395 if (ISSET(combits, MSR_DSR)) 1396 SET(ttybits, TIOCM_DSR); 1397 if (ISSET(combits, MSR_RI | MSR_TERI)) 1398 SET(ttybits, TIOCM_RI); 1399 1400 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1401 SET(ttybits, TIOCM_LE); 1402 1403 return (ttybits); 1404 } 1405 1406 static u_char 1407 cflag2lcr(tcflag_t cflag) 1408 { 1409 u_char lcr = 0; 1410 1411 switch (ISSET(cflag, CSIZE)) { 1412 case CS5: 1413 SET(lcr, LCR_5BITS); 1414 break; 1415 case CS6: 1416 SET(lcr, LCR_6BITS); 1417 break; 1418 case CS7: 1419 SET(lcr, LCR_7BITS); 1420 break; 1421 case CS8: 1422 SET(lcr, LCR_8BITS); 1423 break; 1424 } 1425 if (ISSET(cflag, PARENB)) { 1426 SET(lcr, LCR_PENAB); 1427 if (!ISSET(cflag, PARODD)) 1428 SET(lcr, LCR_PEVEN); 1429 } 1430 if (ISSET(cflag, CSTOPB)) 1431 SET(lcr, LCR_STOPB); 1432 1433 return (lcr); 1434 } 1435 1436 int 1437 comparam(struct tty *tp, struct termios *t) 1438 { 1439 struct com_softc *sc = 1440 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1441 int ospeed; 1442 u_char lcr; 1443 1444 if (COM_ISALIVE(sc) == 0) 1445 return (EIO); 1446 1447 if (sc->sc_type == COM_TYPE_HAYESP) { 1448 int prescaler, speed; 1449 1450 /* 1451 * Calculate UART clock prescaler. It should be in 1452 * range of 0 .. 3. 1453 */ 1454 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1455 prescaler++, speed /= 2) 1456 if ((ospeed = comspeed(speed, sc->sc_frequency, 1457 sc->sc_type)) > 0) 1458 break; 1459 1460 if (prescaler == 4) 1461 return (EINVAL); 1462 sc->sc_prescaler = prescaler; 1463 } else 1464 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1465 1466 /* Check requested parameters. */ 1467 if (ospeed < 0) 1468 return (EINVAL); 1469 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1470 return (EINVAL); 1471 1472 /* 1473 * For the console, always force CLOCAL and !HUPCL, so that the port 1474 * is always active. 1475 */ 1476 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1477 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1478 SET(t->c_cflag, CLOCAL); 1479 CLR(t->c_cflag, HUPCL); 1480 } 1481 1482 /* 1483 * If there were no changes, don't do anything. This avoids dropping 1484 * input and improves performance when all we did was frob things like 1485 * VMIN and VTIME. 1486 */ 1487 if (tp->t_ospeed == t->c_ospeed && 1488 tp->t_cflag == t->c_cflag) 1489 return (0); 1490 1491 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1492 1493 mutex_spin_enter(&sc->sc_lock); 1494 1495 sc->sc_lcr = lcr; 1496 1497 /* 1498 * If we're not in a mode that assumes a connection is present, then 1499 * ignore carrier changes. 1500 */ 1501 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1502 sc->sc_msr_dcd = 0; 1503 else 1504 sc->sc_msr_dcd = MSR_DCD; 1505 /* 1506 * Set the flow control pins depending on the current flow control 1507 * mode. 1508 */ 1509 if (ISSET(t->c_cflag, CRTSCTS)) { 1510 sc->sc_mcr_dtr = MCR_DTR; 1511 sc->sc_mcr_rts = MCR_RTS; 1512 sc->sc_msr_cts = MSR_CTS; 1513 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1514 SET(sc->sc_mcr, MCR_AFE); 1515 } else { 1516 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1517 } 1518 } else if (ISSET(t->c_cflag, MDMBUF)) { 1519 /* 1520 * For DTR/DCD flow control, make sure we don't toggle DTR for 1521 * carrier detection. 1522 */ 1523 sc->sc_mcr_dtr = 0; 1524 sc->sc_mcr_rts = MCR_DTR; 1525 sc->sc_msr_cts = MSR_DCD; 1526 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1527 CLR(sc->sc_mcr, MCR_AFE); 1528 } else { 1529 sc->sc_efr = 0; 1530 } 1531 } else { 1532 /* 1533 * If no flow control, then always set RTS. This will make 1534 * the other side happy if it mistakenly thinks we're doing 1535 * RTS/CTS flow control. 1536 */ 1537 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1538 sc->sc_mcr_rts = 0; 1539 sc->sc_msr_cts = 0; 1540 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1541 CLR(sc->sc_mcr, MCR_AFE); 1542 } else { 1543 sc->sc_efr = 0; 1544 } 1545 if (ISSET(sc->sc_mcr, MCR_DTR)) 1546 SET(sc->sc_mcr, MCR_RTS); 1547 else 1548 CLR(sc->sc_mcr, MCR_RTS); 1549 } 1550 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1551 1552 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1553 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1554 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1555 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1556 1557 sc->sc_dlbl = ospeed; 1558 sc->sc_dlbh = ospeed >> 8; 1559 1560 /* 1561 * Set the FIFO threshold based on the receive speed. 1562 * 1563 * * If it's a low speed, it's probably a mouse or some other 1564 * interactive device, so set the threshold low. 1565 * * If it's a high speed, trim the trigger level down to prevent 1566 * overflows. 1567 * * Otherwise set it a bit higher. 1568 */ 1569 if (sc->sc_type == COM_TYPE_HAYESP) { 1570 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1571 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1572 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1573 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1574 if (t->c_ospeed <= 1200) 1575 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1576 else if (t->c_ospeed <= 38400) 1577 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1578 else 1579 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1580 } else { 1581 sc->sc_fifo = 0; 1582 } 1583 1584 if (sc->sc_type == COM_TYPE_INGENIC) 1585 sc->sc_fifo |= FIFO_UART_ON; 1586 1587 /* And copy to tty. */ 1588 tp->t_ispeed = t->c_ospeed; 1589 tp->t_ospeed = t->c_ospeed; 1590 tp->t_cflag = t->c_cflag; 1591 1592 if (!sc->sc_heldchange) { 1593 if (sc->sc_tx_busy) { 1594 sc->sc_heldtbc = sc->sc_tbc; 1595 sc->sc_tbc = 0; 1596 sc->sc_heldchange = 1; 1597 } else 1598 com_loadchannelregs(sc); 1599 } 1600 1601 if (!ISSET(t->c_cflag, CHWFLOW)) { 1602 /* Disable the high water mark. */ 1603 sc->sc_r_hiwat = 0; 1604 sc->sc_r_lowat = 0; 1605 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1606 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1607 com_schedrx(sc); 1608 } 1609 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1610 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1611 com_hwiflow(sc); 1612 } 1613 } else { 1614 sc->sc_r_hiwat = com_rbuf_hiwat; 1615 sc->sc_r_lowat = com_rbuf_lowat; 1616 } 1617 1618 mutex_spin_exit(&sc->sc_lock); 1619 1620 /* 1621 * Update the tty layer's idea of the carrier bit, in case we changed 1622 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1623 * explicit request. 1624 */ 1625 if (sc->sc_type == COM_TYPE_INGENIC) { 1626 /* no DCD here */ 1627 (void) (*tp->t_linesw->l_modem)(tp, 1); 1628 } else 1629 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1630 1631 #ifdef COM_DEBUG 1632 if (com_debug) 1633 comstatus(sc, "comparam "); 1634 #endif 1635 1636 if (!ISSET(t->c_cflag, CHWFLOW)) { 1637 if (sc->sc_tx_stopped) { 1638 sc->sc_tx_stopped = 0; 1639 comstart(tp); 1640 } 1641 } 1642 1643 return (0); 1644 } 1645 1646 void 1647 com_iflush(struct com_softc *sc) 1648 { 1649 struct com_regs *regsp = &sc->sc_regs; 1650 uint8_t fifo; 1651 #ifdef DIAGNOSTIC 1652 int reg; 1653 #endif 1654 int timo; 1655 1656 #ifdef DIAGNOSTIC 1657 reg = 0xffff; 1658 #endif 1659 timo = 50000; 1660 /* flush any pending I/O */ 1661 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1662 && --timo) 1663 #ifdef DIAGNOSTIC 1664 reg = 1665 #else 1666 (void) 1667 #endif 1668 CSR_READ_1(regsp, COM_REG_RXDATA); 1669 #ifdef DIAGNOSTIC 1670 if (!timo) 1671 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1672 #endif 1673 1674 switch (sc->sc_type) { 1675 case COM_TYPE_16750: 1676 case COM_TYPE_DW_APB: 1677 /* 1678 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1679 * This should prevent triggering busy interrupt while 1680 * manipulating divisors. 1681 */ 1682 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1683 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1684 CSR_WRITE_1(regsp, COM_REG_FIFO, 1685 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1686 delay(100); 1687 break; 1688 } 1689 } 1690 1691 void 1692 com_loadchannelregs(struct com_softc *sc) 1693 { 1694 struct com_regs *regsp = &sc->sc_regs; 1695 1696 /* XXXXX necessary? */ 1697 com_iflush(sc); 1698 1699 if (sc->sc_type == COM_TYPE_PXA2x0) 1700 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1701 else 1702 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1703 1704 if (sc->sc_type == COM_TYPE_OMAP) { 1705 /* disable before changing settings */ 1706 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1707 } 1708 1709 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1710 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1711 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1712 /* no EFR on alchemy */ 1713 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1714 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1715 } 1716 if (sc->sc_type == COM_TYPE_AU1x00) { 1717 /* alchemy has single separate 16-bit clock divisor register */ 1718 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1719 (sc->sc_dlbh << 8)); 1720 } else { 1721 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1722 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1723 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1724 } 1725 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1726 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1727 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1728 if (sc->sc_type == COM_TYPE_HAYESP) { 1729 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1730 HAYESP_SETPRESCALER); 1731 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1732 sc->sc_prescaler); 1733 } 1734 if (sc->sc_type == COM_TYPE_OMAP) { 1735 /* setup the fifos. the FCR value is not used as long 1736 as SCR[6] and SCR[7] are 0, which they are at reset 1737 and we never touch the SCR register */ 1738 uint8_t rx_fifo_trig = 40; 1739 uint8_t tx_fifo_trig = 60; 1740 uint8_t rx_start = 8; 1741 uint8_t rx_halt = 60; 1742 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1743 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1744 1745 /* enable access to TCR & TLR */ 1746 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1747 1748 /* write tcr and tlr values */ 1749 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1750 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1751 1752 /* disable access to TCR & TLR */ 1753 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1754 1755 /* enable again, but mode is based on speed */ 1756 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1757 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1758 } else { 1759 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1760 } 1761 } 1762 1763 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1764 } 1765 1766 int 1767 comhwiflow(struct tty *tp, int block) 1768 { 1769 struct com_softc *sc = 1770 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1771 1772 if (COM_ISALIVE(sc) == 0) 1773 return (0); 1774 1775 if (sc->sc_mcr_rts == 0) 1776 return (0); 1777 1778 mutex_spin_enter(&sc->sc_lock); 1779 1780 if (block) { 1781 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1782 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1783 com_hwiflow(sc); 1784 } 1785 } else { 1786 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1787 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1788 com_schedrx(sc); 1789 } 1790 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1791 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1792 com_hwiflow(sc); 1793 } 1794 } 1795 1796 mutex_spin_exit(&sc->sc_lock); 1797 return (1); 1798 } 1799 1800 /* 1801 * (un)block input via hw flowcontrol 1802 */ 1803 void 1804 com_hwiflow(struct com_softc *sc) 1805 { 1806 struct com_regs *regsp= &sc->sc_regs; 1807 1808 if (sc->sc_mcr_rts == 0) 1809 return; 1810 1811 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1812 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1813 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1814 } else { 1815 SET(sc->sc_mcr, sc->sc_mcr_rts); 1816 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1817 } 1818 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1819 } 1820 1821 1822 void 1823 comstart(struct tty *tp) 1824 { 1825 struct com_softc *sc = 1826 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1827 struct com_regs *regsp = &sc->sc_regs; 1828 int s; 1829 1830 if (COM_ISALIVE(sc) == 0) 1831 return; 1832 1833 s = spltty(); 1834 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1835 goto out; 1836 if (sc->sc_tx_stopped) 1837 goto out; 1838 if (!ttypull(tp)) 1839 goto out; 1840 1841 /* Grab the first contiguous region of buffer space. */ 1842 { 1843 u_char *tba; 1844 int tbc; 1845 1846 tba = tp->t_outq.c_cf; 1847 tbc = ndqb(&tp->t_outq, 0); 1848 1849 mutex_spin_enter(&sc->sc_lock); 1850 1851 sc->sc_tba = tba; 1852 sc->sc_tbc = tbc; 1853 } 1854 1855 SET(tp->t_state, TS_BUSY); 1856 sc->sc_tx_busy = 1; 1857 1858 /* Enable transmit completion interrupts if necessary. */ 1859 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1860 SET(sc->sc_ier, IER_ETXRDY); 1861 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1862 } 1863 1864 /* Output the first chunk of the contiguous buffer. */ 1865 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1866 u_int n; 1867 1868 n = sc->sc_tbc; 1869 if (n > sc->sc_fifolen) 1870 n = sc->sc_fifolen; 1871 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1872 sc->sc_tbc -= n; 1873 sc->sc_tba += n; 1874 } 1875 1876 mutex_spin_exit(&sc->sc_lock); 1877 out: 1878 splx(s); 1879 return; 1880 } 1881 1882 /* 1883 * Stop output on a line. 1884 */ 1885 void 1886 comstop(struct tty *tp, int flag) 1887 { 1888 struct com_softc *sc = 1889 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1890 1891 mutex_spin_enter(&sc->sc_lock); 1892 if (ISSET(tp->t_state, TS_BUSY)) { 1893 /* Stop transmitting at the next chunk. */ 1894 sc->sc_tbc = 0; 1895 sc->sc_heldtbc = 0; 1896 if (!ISSET(tp->t_state, TS_TTSTOP)) 1897 SET(tp->t_state, TS_FLUSH); 1898 } 1899 mutex_spin_exit(&sc->sc_lock); 1900 } 1901 1902 void 1903 comdiag(void *arg) 1904 { 1905 struct com_softc *sc = arg; 1906 int overflows, floods; 1907 1908 mutex_spin_enter(&sc->sc_lock); 1909 overflows = sc->sc_overflows; 1910 sc->sc_overflows = 0; 1911 floods = sc->sc_floods; 1912 sc->sc_floods = 0; 1913 sc->sc_errors = 0; 1914 mutex_spin_exit(&sc->sc_lock); 1915 1916 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1917 device_xname(sc->sc_dev), 1918 overflows, overflows == 1 ? "" : "s", 1919 floods, floods == 1 ? "" : "s"); 1920 } 1921 1922 integrate void 1923 com_rxsoft(struct com_softc *sc, struct tty *tp) 1924 { 1925 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1926 u_char *get, *end; 1927 u_int cc, scc; 1928 u_char lsr; 1929 int code; 1930 1931 end = sc->sc_ebuf; 1932 get = sc->sc_rbget; 1933 scc = cc = com_rbuf_size - sc->sc_rbavail; 1934 1935 if (cc == com_rbuf_size) { 1936 sc->sc_floods++; 1937 if (sc->sc_errors++ == 0) 1938 callout_reset(&sc->sc_diag_callout, 60 * hz, 1939 comdiag, sc); 1940 } 1941 1942 /* If not yet open, drop the entire buffer content here */ 1943 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1944 get += cc << 1; 1945 if (get >= end) 1946 get -= com_rbuf_size << 1; 1947 cc = 0; 1948 } 1949 while (cc) { 1950 code = get[0]; 1951 lsr = get[1]; 1952 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1953 if (ISSET(lsr, LSR_OE)) { 1954 sc->sc_overflows++; 1955 if (sc->sc_errors++ == 0) 1956 callout_reset(&sc->sc_diag_callout, 1957 60 * hz, comdiag, sc); 1958 } 1959 if (ISSET(lsr, LSR_BI | LSR_FE)) 1960 SET(code, TTY_FE); 1961 if (ISSET(lsr, LSR_PE)) 1962 SET(code, TTY_PE); 1963 } 1964 if ((*rint)(code, tp) == -1) { 1965 /* 1966 * The line discipline's buffer is out of space. 1967 */ 1968 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1969 /* 1970 * We're either not using flow control, or the 1971 * line discipline didn't tell us to block for 1972 * some reason. Either way, we have no way to 1973 * know when there's more space available, so 1974 * just drop the rest of the data. 1975 */ 1976 get += cc << 1; 1977 if (get >= end) 1978 get -= com_rbuf_size << 1; 1979 cc = 0; 1980 } else { 1981 /* 1982 * Don't schedule any more receive processing 1983 * until the line discipline tells us there's 1984 * space available (through comhwiflow()). 1985 * Leave the rest of the data in the input 1986 * buffer. 1987 */ 1988 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1989 } 1990 break; 1991 } 1992 get += 2; 1993 if (get >= end) 1994 get = sc->sc_rbuf; 1995 cc--; 1996 } 1997 1998 if (cc != scc) { 1999 sc->sc_rbget = get; 2000 mutex_spin_enter(&sc->sc_lock); 2001 2002 cc = sc->sc_rbavail += scc - cc; 2003 /* Buffers should be ok again, release possible block. */ 2004 if (cc >= sc->sc_r_lowat) { 2005 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2006 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2007 SET(sc->sc_ier, IER_ERXRDY); 2008 if (sc->sc_type == COM_TYPE_PXA2x0) 2009 SET(sc->sc_ier, IER_ERXTOUT); 2010 if (sc->sc_type == COM_TYPE_INGENIC || 2011 sc->sc_type == COM_TYPE_TEGRA) 2012 SET(sc->sc_ier, IER_ERXTOUT); 2013 2014 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 2015 sc->sc_ier); 2016 } 2017 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 2018 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2019 com_hwiflow(sc); 2020 } 2021 } 2022 mutex_spin_exit(&sc->sc_lock); 2023 } 2024 } 2025 2026 integrate void 2027 com_txsoft(struct com_softc *sc, struct tty *tp) 2028 { 2029 2030 CLR(tp->t_state, TS_BUSY); 2031 if (ISSET(tp->t_state, TS_FLUSH)) 2032 CLR(tp->t_state, TS_FLUSH); 2033 else 2034 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2035 (*tp->t_linesw->l_start)(tp); 2036 } 2037 2038 integrate void 2039 com_stsoft(struct com_softc *sc, struct tty *tp) 2040 { 2041 u_char msr, delta; 2042 2043 mutex_spin_enter(&sc->sc_lock); 2044 msr = sc->sc_msr; 2045 delta = sc->sc_msr_delta; 2046 sc->sc_msr_delta = 0; 2047 mutex_spin_exit(&sc->sc_lock); 2048 2049 if (ISSET(delta, sc->sc_msr_dcd)) { 2050 /* 2051 * Inform the tty layer that carrier detect changed. 2052 */ 2053 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2054 } 2055 2056 if (ISSET(delta, sc->sc_msr_cts)) { 2057 /* Block or unblock output according to flow control. */ 2058 if (ISSET(msr, sc->sc_msr_cts)) { 2059 sc->sc_tx_stopped = 0; 2060 (*tp->t_linesw->l_start)(tp); 2061 } else { 2062 sc->sc_tx_stopped = 1; 2063 } 2064 } 2065 2066 #ifdef COM_DEBUG 2067 if (com_debug) 2068 comstatus(sc, "com_stsoft"); 2069 #endif 2070 } 2071 2072 void 2073 comsoft(void *arg) 2074 { 2075 struct com_softc *sc = arg; 2076 struct tty *tp; 2077 2078 if (COM_ISALIVE(sc) == 0) 2079 return; 2080 2081 tp = sc->sc_tty; 2082 2083 if (sc->sc_rx_ready) { 2084 sc->sc_rx_ready = 0; 2085 com_rxsoft(sc, tp); 2086 } 2087 2088 if (sc->sc_st_check) { 2089 sc->sc_st_check = 0; 2090 com_stsoft(sc, tp); 2091 } 2092 2093 if (sc->sc_tx_done) { 2094 sc->sc_tx_done = 0; 2095 com_txsoft(sc, tp); 2096 } 2097 } 2098 2099 int 2100 comintr(void *arg) 2101 { 2102 struct com_softc *sc = arg; 2103 struct com_regs *regsp = &sc->sc_regs; 2104 2105 u_char *put, *end; 2106 u_int cc; 2107 u_char lsr, iir; 2108 2109 if (COM_ISALIVE(sc) == 0) 2110 return (0); 2111 2112 KASSERT(regsp != NULL); 2113 2114 mutex_spin_enter(&sc->sc_lock); 2115 iir = CSR_READ_1(regsp, COM_REG_IIR); 2116 2117 /* Handle ns16750-specific busy interrupt. */ 2118 if (sc->sc_type == COM_TYPE_16750 && 2119 (iir & IIR_BUSY) == IIR_BUSY) { 2120 for (int timeout = 10000; 2121 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2122 if (timeout <= 0) { 2123 aprint_error_dev(sc->sc_dev, 2124 "timeout while waiting for BUSY interrupt " 2125 "acknowledge\n"); 2126 mutex_spin_exit(&sc->sc_lock); 2127 return (0); 2128 } 2129 2130 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2131 iir = CSR_READ_1(regsp, COM_REG_IIR); 2132 } 2133 2134 /* DesignWare APB UART BUSY interrupt */ 2135 if (sc->sc_type == COM_TYPE_DW_APB && 2136 (iir & IIR_BUSY) == IIR_BUSY) { 2137 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2138 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2139 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2140 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2141 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2142 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2143 CSR_WRITE_1(regsp, COM_REG_HALT, 2144 HALT_CHCFG_EN | HALT_CHCFG_UD); 2145 for (int timeout = 10000000; 2146 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2147 timeout--) { 2148 if (timeout <= 0) { 2149 aprint_error_dev(sc->sc_dev, 2150 "timeout while waiting for HALT " 2151 "update acknowledge 0x%x 0x%x\n", 2152 CSR_READ_1(regsp, COM_REG_HALT), 2153 CSR_READ_1(regsp, COM_REG_USR)); 2154 break; 2155 } 2156 } 2157 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2158 (void)CSR_READ_1(regsp, COM_REG_USR); 2159 } else { 2160 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2161 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2162 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2163 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2164 } 2165 } 2166 2167 end = sc->sc_ebuf; 2168 put = sc->sc_rbput; 2169 cc = sc->sc_rbavail; 2170 2171 if (ISSET(iir, IIR_NOPEND)) { 2172 if (ISSET(sc->sc_hwflags, COM_HW_BROKEN_ETXRDY)) 2173 goto do_tx; 2174 mutex_spin_exit(&sc->sc_lock); 2175 return (0); 2176 } 2177 2178 again: do { 2179 u_char msr, delta; 2180 2181 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2182 if (ISSET(lsr, LSR_BI)) { 2183 int cn_trapped = 0; /* see above: cn_trap() */ 2184 2185 cn_check_magic(sc->sc_tty->t_dev, 2186 CNC_BREAK, com_cnm_state); 2187 if (cn_trapped) 2188 continue; 2189 #if defined(KGDB) && !defined(DDB) 2190 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2191 kgdb_connect(1); 2192 continue; 2193 } 2194 #endif 2195 } 2196 2197 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2198 lsr |= LSR_RXRDY; 2199 2200 if (ISSET(lsr, LSR_RCV_MASK) && 2201 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2202 while (cc > 0) { 2203 int cn_trapped = 0; 2204 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2205 put[1] = lsr; 2206 cn_check_magic(sc->sc_tty->t_dev, 2207 put[0], com_cnm_state); 2208 if (cn_trapped) 2209 goto next; 2210 put += 2; 2211 if (put >= end) 2212 put = sc->sc_rbuf; 2213 cc--; 2214 next: 2215 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2216 if (!ISSET(lsr, LSR_RCV_MASK)) 2217 break; 2218 } 2219 2220 /* 2221 * Current string of incoming characters ended because 2222 * no more data was available or we ran out of space. 2223 * Schedule a receive event if any data was received. 2224 * If we're out of space, turn off receive interrupts. 2225 */ 2226 sc->sc_rbput = put; 2227 sc->sc_rbavail = cc; 2228 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2229 sc->sc_rx_ready = 1; 2230 2231 /* 2232 * See if we are in danger of overflowing a buffer. If 2233 * so, use hardware flow control to ease the pressure. 2234 */ 2235 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2236 cc < sc->sc_r_hiwat) { 2237 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2238 com_hwiflow(sc); 2239 } 2240 2241 /* 2242 * If we're out of space, disable receive interrupts 2243 * until the queue has drained a bit. 2244 */ 2245 if (!cc) { 2246 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2247 switch (sc->sc_type) { 2248 case COM_TYPE_PXA2x0: 2249 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2250 break; 2251 case COM_TYPE_INGENIC: 2252 case COM_TYPE_TEGRA: 2253 CLR(sc->sc_ier, 2254 IER_ERXRDY | IER_ERXTOUT); 2255 break; 2256 default: 2257 CLR(sc->sc_ier, IER_ERXRDY); 2258 break; 2259 } 2260 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2261 } 2262 } else { 2263 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2264 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2265 continue; 2266 } 2267 } 2268 2269 msr = CSR_READ_1(regsp, COM_REG_MSR); 2270 delta = msr ^ sc->sc_msr; 2271 sc->sc_msr = msr; 2272 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2273 (delta & MSR_DCD)) { 2274 mutex_spin_enter(&timecounter_lock); 2275 pps_capture(&sc->sc_pps_state); 2276 pps_event(&sc->sc_pps_state, 2277 (msr & MSR_DCD) ? 2278 PPS_CAPTUREASSERT : 2279 PPS_CAPTURECLEAR); 2280 mutex_spin_exit(&timecounter_lock); 2281 } 2282 2283 /* 2284 * Process normal status changes 2285 */ 2286 if (ISSET(delta, sc->sc_msr_mask)) { 2287 SET(sc->sc_msr_delta, delta); 2288 2289 /* 2290 * Stop output immediately if we lose the output 2291 * flow control signal or carrier detect. 2292 */ 2293 if (ISSET(~msr, sc->sc_msr_mask)) { 2294 sc->sc_tbc = 0; 2295 sc->sc_heldtbc = 0; 2296 #ifdef COM_DEBUG 2297 if (com_debug) 2298 comstatus(sc, "comintr "); 2299 #endif 2300 } 2301 2302 sc->sc_st_check = 1; 2303 } 2304 } while (!ISSET((iir = 2305 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2306 /* 2307 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2308 * by IIR read, so we can't do this way: `process all interrupts, 2309 * then do TX if possible'. 2310 */ 2311 (iir & IIR_IMASK) != IIR_TXRDY); 2312 2313 do_tx: 2314 /* 2315 * Read LSR again, since there may be an interrupt between 2316 * the last LSR read and IIR read above. 2317 */ 2318 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2319 2320 /* 2321 * See if data can be transmitted as well. 2322 * Schedule tx done event if no data left 2323 * and tty was marked busy. 2324 */ 2325 if (ISSET(lsr, LSR_TXRDY)) { 2326 /* 2327 * If we've delayed a parameter change, do it now, and restart 2328 * output. 2329 */ 2330 if (sc->sc_heldchange) { 2331 com_loadchannelregs(sc); 2332 sc->sc_heldchange = 0; 2333 sc->sc_tbc = sc->sc_heldtbc; 2334 sc->sc_heldtbc = 0; 2335 } 2336 2337 /* Output the next chunk of the contiguous buffer, if any. */ 2338 if (sc->sc_tbc > 0) { 2339 u_int n; 2340 2341 n = sc->sc_tbc; 2342 if (n > sc->sc_fifolen) 2343 n = sc->sc_fifolen; 2344 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2345 sc->sc_tbc -= n; 2346 sc->sc_tba += n; 2347 } else { 2348 /* Disable transmit completion interrupts if necessary. */ 2349 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2350 CLR(sc->sc_ier, IER_ETXRDY); 2351 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2352 } 2353 if (sc->sc_tx_busy) { 2354 sc->sc_tx_busy = 0; 2355 sc->sc_tx_done = 1; 2356 } 2357 } 2358 } 2359 2360 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2361 goto again; 2362 2363 mutex_spin_exit(&sc->sc_lock); 2364 2365 /* Wake up the poller. */ 2366 if ((sc->sc_rx_ready | sc->sc_st_check | sc->sc_tx_done) != 0) 2367 softint_schedule(sc->sc_si); 2368 2369 #ifdef RND_COM 2370 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2371 #endif 2372 2373 return (1); 2374 } 2375 2376 /* 2377 * The following functions are polled getc and putc routines, shared 2378 * by the console and kgdb glue. 2379 * 2380 * The read-ahead code is so that you can detect pending in-band 2381 * cn_magic in polled mode while doing output rather than having to 2382 * wait until the kernel decides it needs input. 2383 */ 2384 2385 #define MAX_READAHEAD 20 2386 static int com_readahead[MAX_READAHEAD]; 2387 static int com_readaheadcount = 0; 2388 2389 int 2390 com_common_getc(dev_t dev, struct com_regs *regsp) 2391 { 2392 int s = splserial(); 2393 u_char stat, c; 2394 2395 /* got a character from reading things earlier */ 2396 if (com_readaheadcount > 0) { 2397 int i; 2398 2399 c = com_readahead[0]; 2400 for (i = 1; i < com_readaheadcount; i++) { 2401 com_readahead[i-1] = com_readahead[i]; 2402 } 2403 com_readaheadcount--; 2404 splx(s); 2405 return (c); 2406 } 2407 2408 /* don't block until a character becomes available */ 2409 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2410 splx(s); 2411 return -1; 2412 } 2413 2414 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2415 stat = CSR_READ_1(regsp, COM_REG_IIR); 2416 { 2417 int cn_trapped = 0; /* required by cn_trap, see above */ 2418 #ifdef DDB 2419 extern int db_active; 2420 if (!db_active) 2421 #endif 2422 cn_check_magic(dev, c, com_cnm_state); 2423 } 2424 splx(s); 2425 return (c); 2426 } 2427 2428 static void 2429 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead) 2430 { 2431 int s = splserial(); 2432 int cin, stat, timo; 2433 2434 if (with_readahead && com_readaheadcount < MAX_READAHEAD 2435 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2436 int cn_trapped = 0; 2437 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2438 stat = CSR_READ_1(regsp, COM_REG_IIR); 2439 cn_check_magic(dev, cin, com_cnm_state); 2440 com_readahead[com_readaheadcount++] = cin; 2441 } 2442 2443 /* wait for any pending transmission to finish */ 2444 timo = 150000; 2445 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2446 continue; 2447 2448 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2449 COM_BARRIER(regsp, BR | BW); 2450 2451 splx(s); 2452 } 2453 2454 /* 2455 * Initialize UART for use as console or KGDB line. 2456 */ 2457 int 2458 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2459 tcflag_t cflag) 2460 { 2461 2462 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2463 ®sp->cr_ioh)) 2464 return (ENOMEM); /* ??? */ 2465 2466 if (type == COM_TYPE_OMAP) { 2467 /* disable before changing settings */ 2468 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2469 } 2470 2471 rate = comspeed(rate, frequency, type); 2472 if (rate != -1) { 2473 if (type == COM_TYPE_AU1x00) { 2474 /* no EFR on alchemy */ 2475 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2476 } else { 2477 if ((type != COM_TYPE_16550_NOERS) && 2478 (type != COM_TYPE_INGENIC)) { 2479 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2480 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2481 } 2482 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2483 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2484 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2485 } 2486 } 2487 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2488 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2489 2490 if (type == COM_TYPE_INGENIC) { 2491 CSR_WRITE_1(regsp, COM_REG_FIFO, 2492 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2493 FIFO_TRIGGER_1 | FIFO_UART_ON); 2494 } else { 2495 CSR_WRITE_1(regsp, COM_REG_FIFO, 2496 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2497 FIFO_TRIGGER_1); 2498 } 2499 2500 if (type == COM_TYPE_OMAP) { 2501 /* setup the fifos. the FCR value is not used as long 2502 as SCR[6] and SCR[7] are 0, which they are at reset 2503 and we never touch the SCR register */ 2504 uint8_t rx_fifo_trig = 40; 2505 uint8_t tx_fifo_trig = 60; 2506 uint8_t rx_start = 8; 2507 uint8_t rx_halt = 60; 2508 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2509 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2510 2511 /* enable access to TCR & TLR */ 2512 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2513 2514 /* write tcr and tlr values */ 2515 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2516 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2517 2518 /* disable access to TCR & TLR */ 2519 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2520 2521 /* enable again, but mode is based on speed */ 2522 if (rate > 230400) { 2523 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2524 } else { 2525 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2526 } 2527 } 2528 2529 if (type == COM_TYPE_PXA2x0) 2530 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2531 else 2532 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2533 2534 return (0); 2535 } 2536 2537 int 2538 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2539 tcflag_t cflag) 2540 { 2541 int res; 2542 2543 comcons_info.regs = *regsp; 2544 2545 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2546 if (res) 2547 return (res); 2548 2549 cn_tab = &comcons; 2550 cn_init_magic(&com_cnm_state); 2551 cn_set_magic("\047\001"); /* default magic is BREAK */ 2552 2553 comcons_info.frequency = frequency; 2554 comcons_info.type = type; 2555 comcons_info.rate = rate; 2556 comcons_info.cflag = cflag; 2557 2558 return (0); 2559 } 2560 2561 int 2562 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2563 int type, tcflag_t cflag) 2564 { 2565 struct com_regs regs; 2566 2567 /*XXX*/ 2568 bus_space_handle_t dummy_bsh; 2569 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2570 2571 /* 2572 * dummy_bsh required because com_init_regs() wants it. A 2573 * real bus_space_handle will be filled in by cominit() later. 2574 * XXXJRT Detangle this mess eventually, plz. 2575 */ 2576 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2577 2578 return comcnattach1(®s, rate, frequency, type, cflag); 2579 } 2580 2581 static int 2582 comcnreattach(void) 2583 { 2584 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2585 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2586 } 2587 2588 int 2589 comcngetc(dev_t dev) 2590 { 2591 2592 return (com_common_getc(dev, &comcons_info.regs)); 2593 } 2594 2595 /* 2596 * Console kernel output character routine. 2597 */ 2598 void 2599 comcnputc(dev_t dev, int c) 2600 { 2601 2602 com_common_putc(dev, &comcons_info.regs, c, cold); 2603 } 2604 2605 void 2606 comcnpollc(dev_t dev, int on) 2607 { 2608 2609 com_readaheadcount = 0; 2610 } 2611 2612 #ifdef KGDB 2613 int 2614 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2615 tcflag_t cflag) 2616 { 2617 int res; 2618 2619 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2620 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2621 #if !defined(DDB) 2622 return (EBUSY); /* cannot share with console */ 2623 #else 2624 comkgdbregs = *regsp; 2625 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2626 #endif 2627 } else { 2628 comkgdbregs = *regsp; 2629 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2630 if (res) 2631 return (res); 2632 2633 /* 2634 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2635 * expects this to be initialized 2636 */ 2637 cn_init_magic(&com_cnm_state); 2638 cn_set_magic("\047\001"); 2639 } 2640 2641 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2642 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2643 2644 return (0); 2645 } 2646 2647 int 2648 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2649 int frequency, int type, tcflag_t cflag) 2650 { 2651 struct com_regs regs; 2652 2653 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2654 2655 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2656 } 2657 2658 /* ARGSUSED */ 2659 int 2660 com_kgdb_getc(void *arg) 2661 { 2662 2663 return (com_common_getc(NODEV, &comkgdbregs)); 2664 } 2665 2666 /* ARGSUSED */ 2667 void 2668 com_kgdb_putc(void *arg, int c) 2669 { 2670 2671 com_common_putc(NODEV, &comkgdbregs, c, 0); 2672 } 2673 #endif /* KGDB */ 2674 2675 /* helper function to identify the com ports used by 2676 console or KGDB (and not yet autoconf attached) */ 2677 int 2678 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2679 { 2680 bus_space_handle_t help; 2681 2682 if (!comconsattached && 2683 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2684 iobase == comcons_info.regs.cr_iobase) 2685 help = comcons_info.regs.cr_ioh; 2686 #ifdef KGDB 2687 else if (!com_kgdb_attached && 2688 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2689 iobase == comkgdbregs.cr_iobase) 2690 help = comkgdbregs.cr_ioh; 2691 #endif 2692 else 2693 return (0); 2694 2695 if (ioh) 2696 *ioh = help; 2697 return (1); 2698 } 2699 2700 /* 2701 * this routine exists to serve as a shutdown hook for systems that 2702 * have firmware which doesn't interact properly with a com device in 2703 * FIFO mode. 2704 */ 2705 bool 2706 com_cleanup(device_t self, int how) 2707 { 2708 struct com_softc *sc = device_private(self); 2709 2710 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2711 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2712 2713 return true; 2714 } 2715 2716 bool 2717 com_suspend(device_t self, const pmf_qual_t *qual) 2718 { 2719 struct com_softc *sc = device_private(self); 2720 2721 #if 0 2722 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2723 cn_tab = &comcons_suspend; 2724 #endif 2725 2726 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2727 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2728 2729 return true; 2730 } 2731 2732 bool 2733 com_resume(device_t self, const pmf_qual_t *qual) 2734 { 2735 struct com_softc *sc = device_private(self); 2736 2737 mutex_spin_enter(&sc->sc_lock); 2738 com_loadchannelregs(sc); 2739 mutex_spin_exit(&sc->sc_lock); 2740 2741 return true; 2742 } 2743
Indexes created Mon Oct 20 08:09:54 GMT 2025