com.c revision 1.367
1 /* $NetBSD: com.c,v 1.367 2021/10/12 06:25:17 kre Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.367 2021/10/12 06:25:17 kre Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #define CSR_WRITE_1(r, o, v) \ 132 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 133 #define CSR_READ_1(r, o) \ 134 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 135 #define CSR_WRITE_2(r, o, v) \ 136 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 137 #define CSR_READ_2(r, o) \ 138 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 139 #define CSR_WRITE_MULTI(r, o, p, n) \ 140 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 141 142 143 static void com_enable_debugport(struct com_softc *); 144 145 void com_config(struct com_softc *); 146 void com_shutdown(struct com_softc *); 147 int comspeed(long, long, int); 148 static u_char cflag2lcr(tcflag_t); 149 int comparam(struct tty *, struct termios *); 150 void comstart(struct tty *); 151 int comhwiflow(struct tty *, int); 152 153 void com_loadchannelregs(struct com_softc *); 154 void com_hwiflow(struct com_softc *); 155 void com_break(struct com_softc *, int); 156 void com_modem(struct com_softc *, int); 157 void tiocm_to_com(struct com_softc *, u_long, int); 158 int com_to_tiocm(struct com_softc *); 159 void com_iflush(struct com_softc *); 160 161 int com_common_getc(dev_t, struct com_regs *); 162 static void com_common_putc(dev_t, struct com_regs *, int, int); 163 164 int cominit(struct com_regs *, int, int, int, tcflag_t); 165 166 static int comcnreattach(void); 167 168 int comcngetc(dev_t); 169 void comcnputc(dev_t, int); 170 void comcnpollc(dev_t, int); 171 172 #define integrate static inline 173 void comsoft(void *); 174 integrate void com_rxsoft(struct com_softc *, struct tty *); 175 integrate void com_txsoft(struct com_softc *, struct tty *); 176 integrate void com_stsoft(struct com_softc *, struct tty *); 177 integrate void com_schedrx(struct com_softc *); 178 void comdiag(void *); 179 180 dev_type_open(comopen); 181 dev_type_close(comclose); 182 dev_type_read(comread); 183 dev_type_write(comwrite); 184 dev_type_ioctl(comioctl); 185 dev_type_stop(comstop); 186 dev_type_tty(comtty); 187 dev_type_poll(compoll); 188 189 static struct comcons_info comcons_info; 190 191 /* 192 * Following are all routines needed for COM to act as console 193 */ 194 static struct consdev comcons = { 195 .cn_getc = comcngetc, 196 .cn_putc = comcnputc, 197 .cn_pollc = comcnpollc, 198 .cn_dev = NODEV, 199 .cn_pri = CN_NORMAL 200 }; 201 202 203 const struct cdevsw com_cdevsw = { 204 .d_open = comopen, 205 .d_close = comclose, 206 .d_read = comread, 207 .d_write = comwrite, 208 .d_ioctl = comioctl, 209 .d_stop = comstop, 210 .d_tty = comtty, 211 .d_poll = compoll, 212 .d_mmap = nommap, 213 .d_kqfilter = ttykqfilter, 214 .d_discard = nodiscard, 215 .d_flag = D_TTY 216 }; 217 218 /* 219 * Make this an option variable one can patch. 220 * But be warned: this must be a power of 2! 221 */ 222 u_int com_rbuf_size = COM_RING_SIZE; 223 224 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 225 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 226 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 227 228 static int comconsattached; 229 static struct cnm_state com_cnm_state; 230 231 #ifdef KGDB 232 #include <sys/kgdb.h> 233 234 static struct com_regs comkgdbregs; 235 static int com_kgdb_attached; 236 237 int com_kgdb_getc(void *); 238 void com_kgdb_putc(void *, int); 239 #endif /* KGDB */ 240 241 /* initializer for typical 16550-ish hardware */ 242 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 243 [COM_REG_RXDATA] = com_data, 244 [COM_REG_TXDATA] = com_data, 245 [COM_REG_DLBL] = com_dlbl, 246 [COM_REG_DLBH] = com_dlbh, 247 [COM_REG_IER] = com_ier, 248 [COM_REG_IIR] = com_iir, 249 [COM_REG_FIFO] = com_fifo, 250 [COM_REG_TCR] = com_fifo, 251 [COM_REG_EFR] = com_efr, 252 [COM_REG_TLR] = com_efr, 253 [COM_REG_LCR] = com_lcr, 254 [COM_REG_MCR] = com_mcr, 255 [COM_REG_LSR] = com_lsr, 256 [COM_REG_MSR] = com_msr, 257 [COM_REG_USR] = com_usr, 258 [COM_REG_TFL] = com_tfl, 259 [COM_REG_RFL] = com_rfl, 260 [COM_REG_HALT] = com_halt, 261 [COM_REG_MDR1] = com_mdr1, 262 }; 263 264 #define COMDIALOUT_MASK TTDIALOUT_MASK 265 266 #define COMUNIT(x) TTUNIT(x) 267 #define COMDIALOUT(x) TTDIALOUT(x) 268 269 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 270 device_is_active((sc)->sc_dev)) 271 272 #define BR BUS_SPACE_BARRIER_READ 273 #define BW BUS_SPACE_BARRIER_WRITE 274 #define COM_BARRIER(r, f) \ 275 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 276 277 /* 278 * com_init_regs -- 279 * Driver front-ends use this to initialize our register map 280 * in the standard fashion. They may then tailor the map to 281 * their own particular requirements. 282 */ 283 void 284 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 285 bus_addr_t addr) 286 { 287 288 memset(regs, 0, sizeof(*regs)); 289 regs->cr_iot = st; 290 regs->cr_ioh = sh; 291 regs->cr_iobase = addr; 292 regs->cr_nports = COM_NPORTS; 293 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 294 } 295 296 /* 297 * com_init_regs_stride -- 298 * Convenience function for front-ends that have a stride between 299 * registers. 300 */ 301 void 302 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 303 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 304 { 305 306 com_init_regs(regs, st, sh, addr); 307 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 308 regs->cr_map[i] <<= regshift; 309 } 310 regs->cr_nports <<= regshift; 311 } 312 313 /*ARGSUSED*/ 314 int 315 comspeed(long speed, long frequency, int type) 316 { 317 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 318 319 int x, err; 320 int divisor = 16; 321 322 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 323 divisor = 13; 324 } 325 326 if (speed == 0) 327 return (0); 328 if (speed < 0) 329 return (-1); 330 x = divrnd(frequency / divisor, speed); 331 if (x <= 0) 332 return (-1); 333 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 334 if (err < 0) 335 err = -err; 336 if (err > COM_TOLERANCE) 337 return (-1); 338 return (x); 339 340 #undef divrnd 341 } 342 343 #ifdef COM_DEBUG 344 int com_debug = 0; 345 346 void comstatus(struct com_softc *, const char *); 347 void 348 comstatus(struct com_softc *sc, const char *str) 349 { 350 struct tty *tp = sc->sc_tty; 351 352 aprint_normal_dev(sc->sc_dev, 353 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 354 str, 355 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 356 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 357 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 358 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 359 sc->sc_tx_stopped ? '+' : '-'); 360 361 aprint_normal_dev(sc->sc_dev, 362 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 363 str, 364 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 365 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 366 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 367 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 368 sc->sc_rx_flags); 369 } 370 #endif 371 372 int 373 com_probe_subr(struct com_regs *regs) 374 { 375 376 /* force access to id reg */ 377 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 378 CSR_WRITE_1(regs, COM_REG_IIR, 0); 379 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 380 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 381 return (0); 382 383 return (1); 384 } 385 386 int 387 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 388 { 389 struct com_regs regs; 390 391 com_init_regs(®s, iot, ioh, 0/*XXX*/); 392 393 return com_probe_subr(®s); 394 } 395 396 /* 397 * No locking in this routine; it is only called during attach, 398 * or with the port already locked. 399 */ 400 static void 401 com_enable_debugport(struct com_softc *sc) 402 { 403 404 /* Turn on line break interrupt, set carrier. */ 405 sc->sc_ier = IER_ERLS; 406 if (sc->sc_type == COM_TYPE_PXA2x0) 407 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 408 if (sc->sc_type == COM_TYPE_INGENIC || 409 sc->sc_type == COM_TYPE_TEGRA) 410 sc->sc_ier |= IER_ERXTOUT; 411 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 412 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 413 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 414 } 415 416 static void 417 com_intr_poll(void *arg) 418 { 419 struct com_softc * const sc = arg; 420 421 comintr(sc); 422 423 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 424 } 425 426 void 427 com_attach_subr(struct com_softc *sc) 428 { 429 struct com_regs *regsp = &sc->sc_regs; 430 struct tty *tp; 431 uint32_t cpr; 432 uint8_t lcr; 433 const char *fifo_msg = NULL; 434 prop_dictionary_t dict; 435 bool is_console = true; 436 bool force_console = false; 437 438 aprint_naive("\n"); 439 440 dict = device_properties(sc->sc_dev); 441 prop_dictionary_get_bool(dict, "is_console", &is_console); 442 prop_dictionary_get_bool(dict, "force_console", &force_console); 443 callout_init(&sc->sc_diag_callout, 0); 444 callout_init(&sc->sc_poll_callout, 0); 445 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 446 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 447 448 #if defined(COM_16650) 449 sc->sc_type = COM_TYPE_16650; 450 #elif defined(COM_16750) 451 sc->sc_type = COM_TYPE_16750; 452 #elif defined(COM_HAYESP) 453 sc->sc_type = COM_TYPE_HAYESP; 454 #elif defined(COM_PXA2X0) 455 sc->sc_type = COM_TYPE_PXA2x0; 456 #endif 457 458 /* Disable interrupts before configuring the device. */ 459 if (sc->sc_type == COM_TYPE_PXA2x0) 460 sc->sc_ier = IER_EUART; 461 else 462 sc->sc_ier = 0; 463 464 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 465 466 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 467 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 468 comconsattached = 1; 469 470 if (force_console) 471 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 472 473 if (cn_tab == NULL && comcnreattach() != 0) { 474 printf("can't re-init serial console @%lx\n", 475 (u_long)comcons_info.regs.cr_iobase); 476 } 477 478 switch (sc->sc_type) { 479 case COM_TYPE_16750: 480 case COM_TYPE_DW_APB: 481 /* Use in comintr(). */ 482 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 483 break; 484 } 485 486 /* Make sure the console is always "hardwired". */ 487 delay(10000); /* wait for output to finish */ 488 if (is_console) { 489 SET(sc->sc_hwflags, COM_HW_CONSOLE); 490 } 491 492 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 493 } 494 495 /* Probe for FIFO */ 496 switch (sc->sc_type) { 497 case COM_TYPE_HAYESP: 498 goto fifodone; 499 500 case COM_TYPE_AU1x00: 501 sc->sc_fifolen = 16; 502 fifo_msg = "Au1X00 UART"; 503 SET(sc->sc_hwflags, COM_HW_FIFO); 504 goto fifodelay; 505 506 case COM_TYPE_16550_NOERS: 507 sc->sc_fifolen = 16; 508 fifo_msg = "ns16650, no ERS"; 509 SET(sc->sc_hwflags, COM_HW_FIFO); 510 goto fifodelay; 511 512 case COM_TYPE_OMAP: 513 sc->sc_fifolen = 64; 514 fifo_msg = "OMAP UART"; 515 SET(sc->sc_hwflags, COM_HW_FIFO); 516 goto fifodelay; 517 518 case COM_TYPE_INGENIC: 519 sc->sc_fifolen = 16; 520 fifo_msg = "Ingenic UART"; 521 SET(sc->sc_hwflags, COM_HW_FIFO); 522 SET(sc->sc_hwflags, COM_HW_NOIEN); 523 goto fifodelay; 524 525 case COM_TYPE_TEGRA: 526 sc->sc_fifolen = 8; 527 fifo_msg = "Tegra UART"; 528 SET(sc->sc_hwflags, COM_HW_FIFO); 529 CSR_WRITE_1(regsp, COM_REG_FIFO, 530 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 531 goto fifodelay; 532 533 case COM_TYPE_BCMAUXUART: 534 sc->sc_fifolen = 1; 535 fifo_msg = "BCM AUX UART"; 536 SET(sc->sc_hwflags, COM_HW_FIFO); 537 CSR_WRITE_1(regsp, COM_REG_FIFO, 538 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 539 goto fifodelay; 540 541 case COM_TYPE_DW_APB: 542 if (!prop_dictionary_get_uint(dict, "fifolen", &sc->sc_fifolen)) { 543 cpr = bus_space_read_4(sc->sc_regs.cr_iot, 544 sc->sc_regs.cr_ioh, DW_APB_UART_CPR); 545 sc->sc_fifolen = __SHIFTOUT(cpr, UART_CPR_FIFO_MODE) * 16; 546 } 547 if (sc->sc_fifolen == 0) { 548 sc->sc_fifolen = 1; 549 fifo_msg = "DesignWare APB UART, no fifo"; 550 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 551 } else { 552 fifo_msg = "DesignWare APB UART"; 553 SET(sc->sc_hwflags, COM_HW_FIFO); 554 CSR_WRITE_1(regsp, COM_REG_FIFO, 555 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 556 } 557 goto fifodelay; 558 } 559 560 sc->sc_fifolen = 1; 561 /* look for a NS 16550AF UART with FIFOs */ 562 if (sc->sc_type == COM_TYPE_INGENIC) { 563 CSR_WRITE_1(regsp, COM_REG_FIFO, 564 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 565 FIFO_TRIGGER_14 | FIFO_UART_ON); 566 } else 567 CSR_WRITE_1(regsp, COM_REG_FIFO, 568 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 569 delay(100); 570 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 571 == IIR_FIFO_MASK) 572 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 573 == FIFO_TRIGGER_14) { 574 SET(sc->sc_hwflags, COM_HW_FIFO); 575 576 fifo_msg = "ns16550a"; 577 578 /* 579 * IIR changes into the EFR if LCR is set to LCR_EERS 580 * on 16650s. We also know IIR != 0 at this point. 581 * Write 0 into the EFR, and read it. If the result 582 * is 0, we have a 16650. 583 * 584 * Older 16650s were broken; the test to detect them 585 * is taken from the Linux driver. Apparently 586 * setting DLAB enable gives access to the EFR on 587 * these chips. 588 */ 589 if (sc->sc_type == COM_TYPE_16650) { 590 lcr = CSR_READ_1(regsp, COM_REG_LCR); 591 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 592 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 593 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 594 CSR_WRITE_1(regsp, COM_REG_LCR, 595 lcr | LCR_DLAB); 596 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 597 CLR(sc->sc_hwflags, COM_HW_FIFO); 598 sc->sc_fifolen = 0; 599 } else { 600 SET(sc->sc_hwflags, COM_HW_FLOW); 601 sc->sc_fifolen = 32; 602 } 603 } else 604 sc->sc_fifolen = 16; 605 606 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 607 if (sc->sc_fifolen == 0) 608 fifo_msg = "st16650, broken fifo"; 609 else if (sc->sc_fifolen == 32) 610 fifo_msg = "st16650a"; 611 else 612 fifo_msg = "ns16550a"; 613 } 614 615 /* 616 * TL16C750 can enable 64byte FIFO, only when DLAB 617 * is 1. However, some 16750 may always enable. For 618 * example, restrictions according to DLAB in a data 619 * sheet for SC16C750 were not described. 620 * Please enable 'options COM_16650', supposing you 621 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 622 * should become effective. 623 */ 624 if (sc->sc_type == COM_TYPE_16750) { 625 uint8_t iir1, iir2; 626 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 627 628 lcr = CSR_READ_1(regsp, COM_REG_LCR); 629 CSR_WRITE_1(regsp, COM_REG_LCR, 630 lcr & ~LCR_DLAB); 631 CSR_WRITE_1(regsp, COM_REG_FIFO, 632 fcr | FIFO_64B_ENABLE); 633 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 634 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 635 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 636 CSR_WRITE_1(regsp, COM_REG_FIFO, 637 fcr | FIFO_64B_ENABLE); 638 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 639 640 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 641 642 if (!ISSET(iir1, IIR_64B_FIFO) && 643 ISSET(iir2, IIR_64B_FIFO)) { 644 /* It is TL16C750. */ 645 sc->sc_fifolen = 64; 646 SET(sc->sc_hwflags, COM_HW_AFE); 647 } else 648 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 649 650 if (sc->sc_fifolen == 64) 651 fifo_msg = "tl16c750"; 652 else 653 fifo_msg = "ns16750"; 654 } 655 } else 656 fifo_msg = "ns16550, broken fifo"; 657 else 658 fifo_msg = "ns8250 or ns16450, no fifo"; 659 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 660 661 fifodelay: 662 /* 663 * Some chips will clear down both Tx and Rx FIFOs when zero is 664 * written to com_fifo. If this chip is the console, writing zero 665 * results in some of the chip/FIFO description being lost, so delay 666 * printing it until now. 667 */ 668 delay(10); 669 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 670 aprint_normal(": %s, %d-byte FIFO\n", fifo_msg, sc->sc_fifolen); 671 } else { 672 aprint_normal(": %s\n", fifo_msg); 673 } 674 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 675 sc->sc_fifolen = 1; 676 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 677 } 678 679 fifodone: 680 681 tp = tty_alloc(); 682 tp->t_oproc = comstart; 683 tp->t_param = comparam; 684 tp->t_hwiflow = comhwiflow; 685 tp->t_softc = sc; 686 687 sc->sc_tty = tp; 688 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK); 689 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 690 sc->sc_rbavail = com_rbuf_size; 691 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 692 693 tty_attach(tp); 694 695 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 696 SET(sc->sc_mcr, MCR_IENABLE); 697 698 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 699 int maj; 700 701 /* locate the major number */ 702 maj = cdevsw_lookup_major(&com_cdevsw); 703 704 tp->t_dev = cn_tab->cn_dev = makedev(maj, 705 device_unit(sc->sc_dev)); 706 707 aprint_normal_dev(sc->sc_dev, "console\n"); 708 } 709 710 #ifdef KGDB 711 /* 712 * Allow kgdb to "take over" this port. If this is 713 * not the console and is the kgdb device, it has 714 * exclusive use. If it's the console _and_ the 715 * kgdb device, it doesn't. 716 */ 717 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 718 regsp->cr_iobase == comkgdbregs.cr_iobase) { 719 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 720 com_kgdb_attached = 1; 721 722 SET(sc->sc_hwflags, COM_HW_KGDB); 723 } 724 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 725 } 726 #endif 727 728 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 729 730 #ifdef RND_COM 731 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 732 RND_TYPE_TTY, RND_FLAG_DEFAULT); 733 #endif 734 735 /* if there are no enable/disable functions, assume the device 736 is always enabled */ 737 if (!sc->enable) 738 sc->enabled = 1; 739 740 com_config(sc); 741 742 SET(sc->sc_hwflags, COM_HW_DEV_OK); 743 744 if (sc->sc_poll_ticks != 0) 745 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 746 } 747 748 void 749 com_config(struct com_softc *sc) 750 { 751 struct com_regs *regsp = &sc->sc_regs; 752 753 /* Disable interrupts before configuring the device. */ 754 if (sc->sc_type == COM_TYPE_PXA2x0) 755 sc->sc_ier = IER_EUART; 756 else 757 sc->sc_ier = 0; 758 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 759 (void) CSR_READ_1(regsp, COM_REG_IIR); 760 761 /* Look for a Hayes ESP board. */ 762 if (sc->sc_type == COM_TYPE_HAYESP) { 763 764 /* Set 16550 compatibility mode */ 765 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 766 HAYESP_SETMODE); 767 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 768 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 769 HAYESP_MODE_SCALE); 770 771 /* Set RTS/CTS flow control */ 772 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 773 HAYESP_SETFLOWTYPE); 774 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 775 HAYESP_FLOW_RTS); 776 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 777 HAYESP_FLOW_CTS); 778 779 /* Set flow control levels */ 780 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 781 HAYESP_SETRXFLOW); 782 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 783 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 784 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 785 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 786 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 787 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 788 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 789 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 790 } 791 792 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 793 com_enable_debugport(sc); 794 } 795 796 #if 0 797 static int 798 comcngetc_detached(dev_t dev) 799 { 800 return 0; 801 } 802 803 static void 804 comcnputc_detached(dev_t dev, int c) 805 { 806 } 807 #endif 808 809 int 810 com_detach(device_t self, int flags) 811 { 812 struct com_softc *sc = device_private(self); 813 int maj, mn; 814 815 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 816 return EBUSY; 817 818 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 819 (flags & DETACH_SHUTDOWN) != 0) 820 return EBUSY; 821 822 if (sc->disable != NULL && sc->enabled != 0) { 823 (*sc->disable)(sc); 824 sc->enabled = 0; 825 } 826 827 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 828 comconsattached = 0; 829 cn_tab = NULL; 830 } 831 832 /* locate the major number */ 833 maj = cdevsw_lookup_major(&com_cdevsw); 834 835 /* Nuke the vnodes for any open instances. */ 836 mn = device_unit(self); 837 vdevgone(maj, mn, mn, VCHR); 838 839 mn |= COMDIALOUT_MASK; 840 vdevgone(maj, mn, mn, VCHR); 841 842 if (sc->sc_rbuf == NULL) { 843 /* 844 * Ring buffer allocation failed in the com_attach_subr, 845 * only the tty is allocated, and nothing else. 846 */ 847 tty_free(sc->sc_tty); 848 return 0; 849 } 850 851 /* Free the receive buffer. */ 852 free(sc->sc_rbuf, M_DEVBUF); 853 854 /* Detach and free the tty. */ 855 tty_detach(sc->sc_tty); 856 tty_free(sc->sc_tty); 857 858 /* Unhook the soft interrupt handler. */ 859 softint_disestablish(sc->sc_si); 860 861 #ifdef RND_COM 862 /* Unhook the entropy source. */ 863 rnd_detach_source(&sc->rnd_source); 864 #endif 865 callout_destroy(&sc->sc_diag_callout); 866 867 /* Destroy the lock. */ 868 mutex_destroy(&sc->sc_lock); 869 870 return (0); 871 } 872 873 void 874 com_shutdown(struct com_softc *sc) 875 { 876 struct tty *tp = sc->sc_tty; 877 878 mutex_spin_enter(&sc->sc_lock); 879 880 /* If we were asserting flow control, then deassert it. */ 881 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 882 com_hwiflow(sc); 883 884 /* Clear any break condition set with TIOCSBRK. */ 885 com_break(sc, 0); 886 887 /* 888 * Hang up if necessary. Wait a bit, so the other side has time to 889 * notice even if we immediately open the port again. 890 * Avoid tsleeping above splhigh(). 891 */ 892 if (ISSET(tp->t_cflag, HUPCL)) { 893 com_modem(sc, 0); 894 getmicrotime(&sc->sc_hup_pending); 895 sc->sc_hup_pending.tv_sec++; 896 } 897 898 /* Turn off interrupts. */ 899 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 900 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 901 if ((sc->sc_type == COM_TYPE_PXA2x0) || 902 (sc->sc_type == COM_TYPE_INGENIC) || 903 (sc->sc_type == COM_TYPE_TEGRA)) 904 sc->sc_ier |= IER_ERXTOUT; 905 } else 906 sc->sc_ier = 0; 907 908 if (sc->sc_type == COM_TYPE_PXA2x0) 909 sc->sc_ier |= IER_EUART; 910 911 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 912 913 mutex_spin_exit(&sc->sc_lock); 914 915 if (sc->disable) { 916 #ifdef DIAGNOSTIC 917 if (!sc->enabled) 918 panic("com_shutdown: not enabled?"); 919 #endif 920 (*sc->disable)(sc); 921 sc->enabled = 0; 922 } 923 } 924 925 int 926 comopen(dev_t dev, int flag, int mode, struct lwp *l) 927 { 928 struct com_softc *sc; 929 struct tty *tp; 930 int s; 931 int error; 932 933 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 934 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 935 sc->sc_rbuf == NULL) 936 return (ENXIO); 937 938 if (!device_is_active(sc->sc_dev)) 939 return (ENXIO); 940 941 #ifdef KGDB 942 /* 943 * If this is the kgdb port, no other use is permitted. 944 */ 945 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 946 return (EBUSY); 947 #endif 948 949 tp = sc->sc_tty; 950 951 /* 952 * If the device is exclusively for kernel use, deny userland 953 * open. 954 */ 955 if (ISSET(tp->t_state, TS_KERN_ONLY)) 956 return (EBUSY); 957 958 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 959 return (EBUSY); 960 961 s = spltty(); 962 963 /* 964 * Do the following iff this is a first open. 965 */ 966 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 967 struct termios t; 968 struct timeval now, diff; 969 970 tp->t_dev = dev; 971 972 if (sc->enable) { 973 if ((*sc->enable)(sc)) { 974 splx(s); 975 aprint_error_dev(sc->sc_dev, 976 "device enable failed\n"); 977 return (EIO); 978 } 979 mutex_spin_enter(&sc->sc_lock); 980 sc->enabled = 1; 981 com_config(sc); 982 } else { 983 mutex_spin_enter(&sc->sc_lock); 984 } 985 986 if (timerisset(&sc->sc_hup_pending)) { 987 getmicrotime(&now); 988 while (timercmp(&now, &sc->sc_hup_pending, <)) { 989 int ms; 990 991 992 timersub(&sc->sc_hup_pending, &now, &diff); 993 ms = diff.tv_sec * 1000 + 994 uimax(diff.tv_usec / 1000, 1); 995 kpause("comopen", false, mstohz(ms), 996 &sc->sc_lock); 997 } 998 timerclear(&sc->sc_hup_pending); 999 } 1000 1001 /* Turn on interrupts. */ 1002 sc->sc_ier = IER_ERXRDY | IER_ERLS; 1003 if (!ISSET(tp->t_cflag, CLOCAL)) 1004 sc->sc_ier |= IER_EMSC; 1005 1006 if (sc->sc_type == COM_TYPE_PXA2x0) 1007 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 1008 else if (sc->sc_type == COM_TYPE_INGENIC || 1009 sc->sc_type == COM_TYPE_TEGRA) 1010 sc->sc_ier |= IER_ERXTOUT; 1011 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1012 1013 /* Fetch the current modem control status, needed later. */ 1014 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 1015 1016 /* Clear PPS capture state on first open. */ 1017 mutex_spin_enter(&timecounter_lock); 1018 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 1019 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1020 pps_init(&sc->sc_pps_state); 1021 mutex_spin_exit(&timecounter_lock); 1022 1023 mutex_spin_exit(&sc->sc_lock); 1024 1025 /* 1026 * Initialize the termios status to the defaults. Add in the 1027 * sticky bits from TIOCSFLAGS. 1028 */ 1029 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1030 t.c_ospeed = comcons_info.rate; 1031 t.c_cflag = comcons_info.cflag; 1032 } else { 1033 t.c_ospeed = TTYDEF_SPEED; 1034 t.c_cflag = TTYDEF_CFLAG; 1035 } 1036 t.c_ispeed = t.c_ospeed; 1037 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1038 SET(t.c_cflag, CLOCAL); 1039 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1040 SET(t.c_cflag, CRTSCTS); 1041 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1042 SET(t.c_cflag, MDMBUF); 1043 /* Make sure comparam() will do something. */ 1044 tp->t_ospeed = 0; 1045 (void) comparam(tp, &t); 1046 tp->t_iflag = TTYDEF_IFLAG; 1047 tp->t_oflag = TTYDEF_OFLAG; 1048 tp->t_lflag = TTYDEF_LFLAG; 1049 ttychars(tp); 1050 ttsetwater(tp); 1051 1052 mutex_spin_enter(&sc->sc_lock); 1053 1054 /* 1055 * Turn on DTR. We must always do this, even if carrier is not 1056 * present, because otherwise we'd have to use TIOCSDTR 1057 * immediately after setting CLOCAL, which applications do not 1058 * expect. We always assert DTR while the device is open 1059 * unless explicitly requested to deassert it. 1060 */ 1061 com_modem(sc, 1); 1062 1063 /* Clear the input ring, and unblock. */ 1064 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1065 sc->sc_rbavail = com_rbuf_size; 1066 com_iflush(sc); 1067 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1068 com_hwiflow(sc); 1069 1070 #ifdef COM_DEBUG 1071 if (com_debug) 1072 comstatus(sc, "comopen "); 1073 #endif 1074 1075 mutex_spin_exit(&sc->sc_lock); 1076 } 1077 1078 splx(s); 1079 1080 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1081 if (error) 1082 goto bad; 1083 1084 error = (*tp->t_linesw->l_open)(dev, tp); 1085 if (error) 1086 goto bad; 1087 1088 return (0); 1089 1090 bad: 1091 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1092 /* 1093 * We failed to open the device, and nobody else had it opened. 1094 * Clean up the state as appropriate. 1095 */ 1096 com_shutdown(sc); 1097 } 1098 1099 return (error); 1100 } 1101 1102 int 1103 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1104 { 1105 struct com_softc *sc = 1106 device_lookup_private(&com_cd, COMUNIT(dev)); 1107 struct tty *tp = sc->sc_tty; 1108 1109 /* XXX This is for cons.c. */ 1110 if (!ISSET(tp->t_state, TS_ISOPEN)) 1111 return (0); 1112 /* 1113 * If the device is exclusively for kernel use, deny userland 1114 * close. 1115 */ 1116 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1117 return (0); 1118 1119 (*tp->t_linesw->l_close)(tp, flag); 1120 ttyclose(tp); 1121 1122 if (COM_ISALIVE(sc) == 0) 1123 return (0); 1124 1125 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1126 /* 1127 * Although we got a last close, the device may still be in 1128 * use; e.g. if this was the dialout node, and there are still 1129 * processes waiting for carrier on the non-dialout node. 1130 */ 1131 com_shutdown(sc); 1132 } 1133 1134 return (0); 1135 } 1136 1137 int 1138 comread(dev_t dev, struct uio *uio, int flag) 1139 { 1140 struct com_softc *sc = 1141 device_lookup_private(&com_cd, COMUNIT(dev)); 1142 struct tty *tp = sc->sc_tty; 1143 1144 if (COM_ISALIVE(sc) == 0) 1145 return (EIO); 1146 1147 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1148 } 1149 1150 int 1151 comwrite(dev_t dev, struct uio *uio, int flag) 1152 { 1153 struct com_softc *sc = 1154 device_lookup_private(&com_cd, COMUNIT(dev)); 1155 struct tty *tp = sc->sc_tty; 1156 1157 if (COM_ISALIVE(sc) == 0) 1158 return (EIO); 1159 1160 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1161 } 1162 1163 int 1164 compoll(dev_t dev, int events, struct lwp *l) 1165 { 1166 struct com_softc *sc = 1167 device_lookup_private(&com_cd, COMUNIT(dev)); 1168 struct tty *tp = sc->sc_tty; 1169 1170 if (COM_ISALIVE(sc) == 0) 1171 return (POLLHUP); 1172 1173 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1174 } 1175 1176 struct tty * 1177 comtty(dev_t dev) 1178 { 1179 struct com_softc *sc = 1180 device_lookup_private(&com_cd, COMUNIT(dev)); 1181 struct tty *tp = sc->sc_tty; 1182 1183 return (tp); 1184 } 1185 1186 int 1187 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1188 { 1189 struct com_softc *sc; 1190 struct tty *tp; 1191 int error; 1192 1193 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1194 if (sc == NULL) 1195 return ENXIO; 1196 if (COM_ISALIVE(sc) == 0) 1197 return (EIO); 1198 1199 tp = sc->sc_tty; 1200 1201 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1202 if (error != EPASSTHROUGH) 1203 return (error); 1204 1205 error = ttioctl(tp, cmd, data, flag, l); 1206 if (error != EPASSTHROUGH) 1207 return (error); 1208 1209 error = 0; 1210 switch (cmd) { 1211 case TIOCSFLAGS: 1212 error = kauth_authorize_device_tty(l->l_cred, 1213 KAUTH_DEVICE_TTY_PRIVSET, tp); 1214 break; 1215 default: 1216 /* nothing */ 1217 break; 1218 } 1219 if (error) { 1220 return error; 1221 } 1222 1223 mutex_spin_enter(&sc->sc_lock); 1224 1225 switch (cmd) { 1226 case TIOCSBRK: 1227 com_break(sc, 1); 1228 break; 1229 1230 case TIOCCBRK: 1231 com_break(sc, 0); 1232 break; 1233 1234 case TIOCSDTR: 1235 com_modem(sc, 1); 1236 break; 1237 1238 case TIOCCDTR: 1239 com_modem(sc, 0); 1240 break; 1241 1242 case TIOCGFLAGS: 1243 *(int *)data = sc->sc_swflags; 1244 break; 1245 1246 case TIOCSFLAGS: 1247 sc->sc_swflags = *(int *)data; 1248 break; 1249 1250 case TIOCMSET: 1251 case TIOCMBIS: 1252 case TIOCMBIC: 1253 tiocm_to_com(sc, cmd, *(int *)data); 1254 break; 1255 1256 case TIOCMGET: 1257 *(int *)data = com_to_tiocm(sc); 1258 break; 1259 1260 case PPS_IOC_CREATE: 1261 case PPS_IOC_DESTROY: 1262 case PPS_IOC_GETPARAMS: 1263 case PPS_IOC_SETPARAMS: 1264 case PPS_IOC_GETCAP: 1265 case PPS_IOC_FETCH: 1266 #ifdef PPS_SYNC 1267 case PPS_IOC_KCBIND: 1268 #endif 1269 mutex_spin_enter(&timecounter_lock); 1270 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1271 mutex_spin_exit(&timecounter_lock); 1272 break; 1273 1274 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1275 mutex_spin_enter(&timecounter_lock); 1276 #ifndef PPS_TRAILING_EDGE 1277 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1278 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1279 #else 1280 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1281 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1282 #endif 1283 mutex_spin_exit(&timecounter_lock); 1284 break; 1285 1286 default: 1287 error = EPASSTHROUGH; 1288 break; 1289 } 1290 1291 mutex_spin_exit(&sc->sc_lock); 1292 1293 #ifdef COM_DEBUG 1294 if (com_debug) 1295 comstatus(sc, "comioctl "); 1296 #endif 1297 1298 return (error); 1299 } 1300 1301 integrate void 1302 com_schedrx(struct com_softc *sc) 1303 { 1304 1305 sc->sc_rx_ready = 1; 1306 1307 /* Wake up the poller. */ 1308 softint_schedule(sc->sc_si); 1309 } 1310 1311 void 1312 com_break(struct com_softc *sc, int onoff) 1313 { 1314 1315 if (onoff) 1316 SET(sc->sc_lcr, LCR_SBREAK); 1317 else 1318 CLR(sc->sc_lcr, LCR_SBREAK); 1319 1320 if (!sc->sc_heldchange) { 1321 if (sc->sc_tx_busy) { 1322 sc->sc_heldtbc = sc->sc_tbc; 1323 sc->sc_tbc = 0; 1324 sc->sc_heldchange = 1; 1325 } else 1326 com_loadchannelregs(sc); 1327 } 1328 } 1329 1330 void 1331 com_modem(struct com_softc *sc, int onoff) 1332 { 1333 1334 if (sc->sc_mcr_dtr == 0) 1335 return; 1336 1337 if (onoff) 1338 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1339 else 1340 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1341 1342 if (!sc->sc_heldchange) { 1343 if (sc->sc_tx_busy) { 1344 sc->sc_heldtbc = sc->sc_tbc; 1345 sc->sc_tbc = 0; 1346 sc->sc_heldchange = 1; 1347 } else 1348 com_loadchannelregs(sc); 1349 } 1350 } 1351 1352 void 1353 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1354 { 1355 u_char combits; 1356 1357 combits = 0; 1358 if (ISSET(ttybits, TIOCM_DTR)) 1359 SET(combits, MCR_DTR); 1360 if (ISSET(ttybits, TIOCM_RTS)) 1361 SET(combits, MCR_RTS); 1362 1363 switch (how) { 1364 case TIOCMBIC: 1365 CLR(sc->sc_mcr, combits); 1366 break; 1367 1368 case TIOCMBIS: 1369 SET(sc->sc_mcr, combits); 1370 break; 1371 1372 case TIOCMSET: 1373 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1374 SET(sc->sc_mcr, combits); 1375 break; 1376 } 1377 1378 if (!sc->sc_heldchange) { 1379 if (sc->sc_tx_busy) { 1380 sc->sc_heldtbc = sc->sc_tbc; 1381 sc->sc_tbc = 0; 1382 sc->sc_heldchange = 1; 1383 } else 1384 com_loadchannelregs(sc); 1385 } 1386 } 1387 1388 int 1389 com_to_tiocm(struct com_softc *sc) 1390 { 1391 u_char combits; 1392 int ttybits = 0; 1393 1394 combits = sc->sc_mcr; 1395 if (ISSET(combits, MCR_DTR)) 1396 SET(ttybits, TIOCM_DTR); 1397 if (ISSET(combits, MCR_RTS)) 1398 SET(ttybits, TIOCM_RTS); 1399 1400 combits = sc->sc_msr; 1401 if (sc->sc_type == COM_TYPE_INGENIC) { 1402 SET(ttybits, TIOCM_CD); 1403 } else { 1404 if (ISSET(combits, MSR_DCD)) 1405 SET(ttybits, TIOCM_CD); 1406 } 1407 if (ISSET(combits, MSR_CTS)) 1408 SET(ttybits, TIOCM_CTS); 1409 if (ISSET(combits, MSR_DSR)) 1410 SET(ttybits, TIOCM_DSR); 1411 if (ISSET(combits, MSR_RI | MSR_TERI)) 1412 SET(ttybits, TIOCM_RI); 1413 1414 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1415 SET(ttybits, TIOCM_LE); 1416 1417 return (ttybits); 1418 } 1419 1420 static u_char 1421 cflag2lcr(tcflag_t cflag) 1422 { 1423 u_char lcr = 0; 1424 1425 switch (ISSET(cflag, CSIZE)) { 1426 case CS5: 1427 SET(lcr, LCR_5BITS); 1428 break; 1429 case CS6: 1430 SET(lcr, LCR_6BITS); 1431 break; 1432 case CS7: 1433 SET(lcr, LCR_7BITS); 1434 break; 1435 case CS8: 1436 SET(lcr, LCR_8BITS); 1437 break; 1438 } 1439 if (ISSET(cflag, PARENB)) { 1440 SET(lcr, LCR_PENAB); 1441 if (!ISSET(cflag, PARODD)) 1442 SET(lcr, LCR_PEVEN); 1443 } 1444 if (ISSET(cflag, CSTOPB)) 1445 SET(lcr, LCR_STOPB); 1446 1447 return (lcr); 1448 } 1449 1450 int 1451 comparam(struct tty *tp, struct termios *t) 1452 { 1453 struct com_softc *sc = 1454 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1455 int ospeed; 1456 u_char lcr; 1457 1458 if (COM_ISALIVE(sc) == 0) 1459 return (EIO); 1460 1461 if (sc->sc_type == COM_TYPE_HAYESP) { 1462 int prescaler, speed; 1463 1464 /* 1465 * Calculate UART clock prescaler. It should be in 1466 * range of 0 .. 3. 1467 */ 1468 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1469 prescaler++, speed /= 2) 1470 if ((ospeed = comspeed(speed, sc->sc_frequency, 1471 sc->sc_type)) > 0) 1472 break; 1473 1474 if (prescaler == 4) 1475 return (EINVAL); 1476 sc->sc_prescaler = prescaler; 1477 } else 1478 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1479 1480 /* Check requested parameters. */ 1481 if (ospeed < 0) 1482 return (EINVAL); 1483 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1484 return (EINVAL); 1485 1486 /* 1487 * For the console, always force CLOCAL and !HUPCL, so that the port 1488 * is always active. 1489 */ 1490 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1491 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1492 SET(t->c_cflag, CLOCAL); 1493 CLR(t->c_cflag, HUPCL); 1494 } 1495 1496 /* 1497 * If there were no changes, don't do anything. This avoids dropping 1498 * input and improves performance when all we did was frob things like 1499 * VMIN and VTIME. 1500 */ 1501 if (tp->t_ospeed == t->c_ospeed && 1502 tp->t_cflag == t->c_cflag) 1503 return (0); 1504 1505 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1506 1507 mutex_spin_enter(&sc->sc_lock); 1508 1509 sc->sc_lcr = lcr; 1510 1511 /* 1512 * If we're not in a mode that assumes a connection is present, then 1513 * ignore carrier changes. 1514 */ 1515 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1516 sc->sc_msr_dcd = 0; 1517 else 1518 sc->sc_msr_dcd = MSR_DCD; 1519 /* 1520 * Set the flow control pins depending on the current flow control 1521 * mode. 1522 */ 1523 if (ISSET(t->c_cflag, CRTSCTS)) { 1524 sc->sc_mcr_dtr = MCR_DTR; 1525 sc->sc_mcr_rts = MCR_RTS; 1526 sc->sc_msr_cts = MSR_CTS; 1527 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1528 SET(sc->sc_mcr, MCR_AFE); 1529 } else { 1530 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1531 } 1532 } else if (ISSET(t->c_cflag, MDMBUF)) { 1533 /* 1534 * For DTR/DCD flow control, make sure we don't toggle DTR for 1535 * carrier detection. 1536 */ 1537 sc->sc_mcr_dtr = 0; 1538 sc->sc_mcr_rts = MCR_DTR; 1539 sc->sc_msr_cts = MSR_DCD; 1540 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1541 CLR(sc->sc_mcr, MCR_AFE); 1542 } else { 1543 sc->sc_efr = 0; 1544 } 1545 } else { 1546 /* 1547 * If no flow control, then always set RTS. This will make 1548 * the other side happy if it mistakenly thinks we're doing 1549 * RTS/CTS flow control. 1550 */ 1551 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1552 sc->sc_mcr_rts = 0; 1553 sc->sc_msr_cts = 0; 1554 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1555 CLR(sc->sc_mcr, MCR_AFE); 1556 } else { 1557 sc->sc_efr = 0; 1558 } 1559 if (ISSET(sc->sc_mcr, MCR_DTR)) 1560 SET(sc->sc_mcr, MCR_RTS); 1561 else 1562 CLR(sc->sc_mcr, MCR_RTS); 1563 } 1564 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1565 1566 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1567 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1568 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1569 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1570 1571 sc->sc_dlbl = ospeed; 1572 sc->sc_dlbh = ospeed >> 8; 1573 1574 /* 1575 * Set the FIFO threshold based on the receive speed. 1576 * 1577 * * If it's a low speed, it's probably a mouse or some other 1578 * interactive device, so set the threshold low. 1579 * * If it's a high speed, trim the trigger level down to prevent 1580 * overflows. 1581 * * Otherwise set it a bit higher. 1582 */ 1583 if (sc->sc_type == COM_TYPE_HAYESP) { 1584 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1585 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1586 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1587 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1588 if (t->c_ospeed <= 1200) 1589 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1590 else if (t->c_ospeed <= 38400) 1591 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1592 else 1593 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1594 } else { 1595 sc->sc_fifo = 0; 1596 } 1597 1598 if (sc->sc_type == COM_TYPE_INGENIC) 1599 sc->sc_fifo |= FIFO_UART_ON; 1600 1601 /* And copy to tty. */ 1602 tp->t_ispeed = t->c_ospeed; 1603 tp->t_ospeed = t->c_ospeed; 1604 tp->t_cflag = t->c_cflag; 1605 1606 if (!sc->sc_heldchange) { 1607 if (sc->sc_tx_busy) { 1608 sc->sc_heldtbc = sc->sc_tbc; 1609 sc->sc_tbc = 0; 1610 sc->sc_heldchange = 1; 1611 } else 1612 com_loadchannelregs(sc); 1613 } 1614 1615 if (!ISSET(t->c_cflag, CHWFLOW)) { 1616 /* Disable the high water mark. */ 1617 sc->sc_r_hiwat = 0; 1618 sc->sc_r_lowat = 0; 1619 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1620 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1621 com_schedrx(sc); 1622 } 1623 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1624 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1625 com_hwiflow(sc); 1626 } 1627 } else { 1628 sc->sc_r_hiwat = com_rbuf_hiwat; 1629 sc->sc_r_lowat = com_rbuf_lowat; 1630 } 1631 1632 mutex_spin_exit(&sc->sc_lock); 1633 1634 /* 1635 * Update the tty layer's idea of the carrier bit, in case we changed 1636 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1637 * explicit request. 1638 */ 1639 if (sc->sc_type == COM_TYPE_INGENIC) { 1640 /* no DCD here */ 1641 (void) (*tp->t_linesw->l_modem)(tp, 1); 1642 } else 1643 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1644 1645 #ifdef COM_DEBUG 1646 if (com_debug) 1647 comstatus(sc, "comparam "); 1648 #endif 1649 1650 if (!ISSET(t->c_cflag, CHWFLOW)) { 1651 if (sc->sc_tx_stopped) { 1652 sc->sc_tx_stopped = 0; 1653 comstart(tp); 1654 } 1655 } 1656 1657 return (0); 1658 } 1659 1660 void 1661 com_iflush(struct com_softc *sc) 1662 { 1663 struct com_regs *regsp = &sc->sc_regs; 1664 uint8_t fifo; 1665 #ifdef DIAGNOSTIC 1666 int reg; 1667 #endif 1668 int timo; 1669 1670 #ifdef DIAGNOSTIC 1671 reg = 0xffff; 1672 #endif 1673 timo = 50000; 1674 /* flush any pending I/O */ 1675 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1676 && --timo) 1677 #ifdef DIAGNOSTIC 1678 reg = 1679 #else 1680 (void) 1681 #endif 1682 CSR_READ_1(regsp, COM_REG_RXDATA); 1683 #ifdef DIAGNOSTIC 1684 if (!timo) 1685 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1686 #endif 1687 1688 switch (sc->sc_type) { 1689 case COM_TYPE_16750: 1690 case COM_TYPE_DW_APB: 1691 /* 1692 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1693 * This should prevent triggering busy interrupt while 1694 * manipulating divisors. 1695 */ 1696 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1697 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1698 CSR_WRITE_1(regsp, COM_REG_FIFO, 1699 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1700 delay(100); 1701 break; 1702 } 1703 } 1704 1705 void 1706 com_loadchannelregs(struct com_softc *sc) 1707 { 1708 struct com_regs *regsp = &sc->sc_regs; 1709 1710 /* XXXXX necessary? */ 1711 com_iflush(sc); 1712 1713 if (sc->sc_type == COM_TYPE_PXA2x0) 1714 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1715 else 1716 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1717 1718 if (sc->sc_type == COM_TYPE_OMAP) { 1719 /* disable before changing settings */ 1720 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1721 } 1722 1723 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1724 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1725 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1726 /* no EFR on alchemy */ 1727 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1728 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1729 } 1730 if (sc->sc_type == COM_TYPE_AU1x00) { 1731 /* alchemy has single separate 16-bit clock divisor register */ 1732 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1733 (sc->sc_dlbh << 8)); 1734 } else { 1735 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1736 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1737 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1738 } 1739 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1740 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1741 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1742 if (sc->sc_type == COM_TYPE_HAYESP) { 1743 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1744 HAYESP_SETPRESCALER); 1745 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1746 sc->sc_prescaler); 1747 } 1748 if (sc->sc_type == COM_TYPE_OMAP) { 1749 /* setup the fifos. the FCR value is not used as long 1750 as SCR[6] and SCR[7] are 0, which they are at reset 1751 and we never touch the SCR register */ 1752 uint8_t rx_fifo_trig = 40; 1753 uint8_t tx_fifo_trig = 60; 1754 uint8_t rx_start = 8; 1755 uint8_t rx_halt = 60; 1756 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1757 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1758 1759 /* enable access to TCR & TLR */ 1760 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1761 1762 /* write tcr and tlr values */ 1763 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1764 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1765 1766 /* disable access to TCR & TLR */ 1767 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1768 1769 /* enable again, but mode is based on speed */ 1770 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1771 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1772 } else { 1773 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1774 } 1775 } 1776 1777 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1778 } 1779 1780 int 1781 comhwiflow(struct tty *tp, int block) 1782 { 1783 struct com_softc *sc = 1784 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1785 1786 if (COM_ISALIVE(sc) == 0) 1787 return (0); 1788 1789 if (sc->sc_mcr_rts == 0) 1790 return (0); 1791 1792 mutex_spin_enter(&sc->sc_lock); 1793 1794 if (block) { 1795 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1796 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1797 com_hwiflow(sc); 1798 } 1799 } else { 1800 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1801 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1802 com_schedrx(sc); 1803 } 1804 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1805 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1806 com_hwiflow(sc); 1807 } 1808 } 1809 1810 mutex_spin_exit(&sc->sc_lock); 1811 return (1); 1812 } 1813 1814 /* 1815 * (un)block input via hw flowcontrol 1816 */ 1817 void 1818 com_hwiflow(struct com_softc *sc) 1819 { 1820 struct com_regs *regsp= &sc->sc_regs; 1821 1822 if (sc->sc_mcr_rts == 0) 1823 return; 1824 1825 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1826 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1827 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1828 } else { 1829 SET(sc->sc_mcr, sc->sc_mcr_rts); 1830 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1831 } 1832 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1833 } 1834 1835 1836 void 1837 comstart(struct tty *tp) 1838 { 1839 struct com_softc *sc = 1840 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1841 struct com_regs *regsp = &sc->sc_regs; 1842 int s; 1843 1844 if (COM_ISALIVE(sc) == 0) 1845 return; 1846 1847 s = spltty(); 1848 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1849 goto out; 1850 if (sc->sc_tx_stopped) 1851 goto out; 1852 if (!ttypull(tp)) 1853 goto out; 1854 1855 /* Grab the first contiguous region of buffer space. */ 1856 { 1857 u_char *tba; 1858 int tbc; 1859 1860 tba = tp->t_outq.c_cf; 1861 tbc = ndqb(&tp->t_outq, 0); 1862 1863 mutex_spin_enter(&sc->sc_lock); 1864 1865 sc->sc_tba = tba; 1866 sc->sc_tbc = tbc; 1867 } 1868 1869 SET(tp->t_state, TS_BUSY); 1870 sc->sc_tx_busy = 1; 1871 1872 /* Enable transmit completion interrupts if necessary. */ 1873 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1874 SET(sc->sc_ier, IER_ETXRDY); 1875 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1876 } 1877 1878 /* Output the first chunk of the contiguous buffer. */ 1879 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1880 u_int n; 1881 1882 n = sc->sc_tbc; 1883 if (n > sc->sc_fifolen) 1884 n = sc->sc_fifolen; 1885 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1886 sc->sc_tbc -= n; 1887 sc->sc_tba += n; 1888 } 1889 1890 mutex_spin_exit(&sc->sc_lock); 1891 out: 1892 splx(s); 1893 return; 1894 } 1895 1896 /* 1897 * Stop output on a line. 1898 */ 1899 void 1900 comstop(struct tty *tp, int flag) 1901 { 1902 struct com_softc *sc = 1903 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1904 1905 mutex_spin_enter(&sc->sc_lock); 1906 if (ISSET(tp->t_state, TS_BUSY)) { 1907 /* Stop transmitting at the next chunk. */ 1908 sc->sc_tbc = 0; 1909 sc->sc_heldtbc = 0; 1910 if (!ISSET(tp->t_state, TS_TTSTOP)) 1911 SET(tp->t_state, TS_FLUSH); 1912 } 1913 mutex_spin_exit(&sc->sc_lock); 1914 } 1915 1916 void 1917 comdiag(void *arg) 1918 { 1919 struct com_softc *sc = arg; 1920 int overflows, floods; 1921 1922 mutex_spin_enter(&sc->sc_lock); 1923 overflows = sc->sc_overflows; 1924 sc->sc_overflows = 0; 1925 floods = sc->sc_floods; 1926 sc->sc_floods = 0; 1927 sc->sc_errors = 0; 1928 mutex_spin_exit(&sc->sc_lock); 1929 1930 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1931 device_xname(sc->sc_dev), 1932 overflows, overflows == 1 ? "" : "s", 1933 floods, floods == 1 ? "" : "s"); 1934 } 1935 1936 integrate void 1937 com_rxsoft(struct com_softc *sc, struct tty *tp) 1938 { 1939 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1940 u_char *get, *end; 1941 u_int cc, scc; 1942 u_char lsr; 1943 int code; 1944 1945 end = sc->sc_ebuf; 1946 get = sc->sc_rbget; 1947 scc = cc = com_rbuf_size - sc->sc_rbavail; 1948 1949 if (cc == com_rbuf_size) { 1950 sc->sc_floods++; 1951 if (sc->sc_errors++ == 0) 1952 callout_reset(&sc->sc_diag_callout, 60 * hz, 1953 comdiag, sc); 1954 } 1955 1956 /* If not yet open, drop the entire buffer content here */ 1957 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1958 get += cc << 1; 1959 if (get >= end) 1960 get -= com_rbuf_size << 1; 1961 cc = 0; 1962 } 1963 while (cc) { 1964 code = get[0]; 1965 lsr = get[1]; 1966 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1967 if (ISSET(lsr, LSR_OE)) { 1968 sc->sc_overflows++; 1969 if (sc->sc_errors++ == 0) 1970 callout_reset(&sc->sc_diag_callout, 1971 60 * hz, comdiag, sc); 1972 } 1973 if (ISSET(lsr, LSR_BI | LSR_FE)) 1974 SET(code, TTY_FE); 1975 if (ISSET(lsr, LSR_PE)) 1976 SET(code, TTY_PE); 1977 } 1978 if ((*rint)(code, tp) == -1) { 1979 /* 1980 * The line discipline's buffer is out of space. 1981 */ 1982 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1983 /* 1984 * We're either not using flow control, or the 1985 * line discipline didn't tell us to block for 1986 * some reason. Either way, we have no way to 1987 * know when there's more space available, so 1988 * just drop the rest of the data. 1989 */ 1990 get += cc << 1; 1991 if (get >= end) 1992 get -= com_rbuf_size << 1; 1993 cc = 0; 1994 } else { 1995 /* 1996 * Don't schedule any more receive processing 1997 * until the line discipline tells us there's 1998 * space available (through comhwiflow()). 1999 * Leave the rest of the data in the input 2000 * buffer. 2001 */ 2002 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 2003 } 2004 break; 2005 } 2006 get += 2; 2007 if (get >= end) 2008 get = sc->sc_rbuf; 2009 cc--; 2010 } 2011 2012 if (cc != scc) { 2013 sc->sc_rbget = get; 2014 mutex_spin_enter(&sc->sc_lock); 2015 2016 cc = sc->sc_rbavail += scc - cc; 2017 /* Buffers should be ok again, release possible block. */ 2018 if (cc >= sc->sc_r_lowat) { 2019 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2020 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2021 SET(sc->sc_ier, IER_ERXRDY); 2022 if (sc->sc_type == COM_TYPE_PXA2x0) 2023 SET(sc->sc_ier, IER_ERXTOUT); 2024 if (sc->sc_type == COM_TYPE_INGENIC || 2025 sc->sc_type == COM_TYPE_TEGRA) 2026 SET(sc->sc_ier, IER_ERXTOUT); 2027 2028 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 2029 sc->sc_ier); 2030 } 2031 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 2032 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2033 com_hwiflow(sc); 2034 } 2035 } 2036 mutex_spin_exit(&sc->sc_lock); 2037 } 2038 } 2039 2040 integrate void 2041 com_txsoft(struct com_softc *sc, struct tty *tp) 2042 { 2043 2044 CLR(tp->t_state, TS_BUSY); 2045 if (ISSET(tp->t_state, TS_FLUSH)) 2046 CLR(tp->t_state, TS_FLUSH); 2047 else 2048 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2049 (*tp->t_linesw->l_start)(tp); 2050 } 2051 2052 integrate void 2053 com_stsoft(struct com_softc *sc, struct tty *tp) 2054 { 2055 u_char msr, delta; 2056 2057 mutex_spin_enter(&sc->sc_lock); 2058 msr = sc->sc_msr; 2059 delta = sc->sc_msr_delta; 2060 sc->sc_msr_delta = 0; 2061 mutex_spin_exit(&sc->sc_lock); 2062 2063 if (ISSET(delta, sc->sc_msr_dcd)) { 2064 /* 2065 * Inform the tty layer that carrier detect changed. 2066 */ 2067 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2068 } 2069 2070 if (ISSET(delta, sc->sc_msr_cts)) { 2071 /* Block or unblock output according to flow control. */ 2072 if (ISSET(msr, sc->sc_msr_cts)) { 2073 sc->sc_tx_stopped = 0; 2074 (*tp->t_linesw->l_start)(tp); 2075 } else { 2076 sc->sc_tx_stopped = 1; 2077 } 2078 } 2079 2080 #ifdef COM_DEBUG 2081 if (com_debug) 2082 comstatus(sc, "com_stsoft"); 2083 #endif 2084 } 2085 2086 void 2087 comsoft(void *arg) 2088 { 2089 struct com_softc *sc = arg; 2090 struct tty *tp; 2091 2092 if (COM_ISALIVE(sc) == 0) 2093 return; 2094 2095 tp = sc->sc_tty; 2096 2097 if (sc->sc_rx_ready) { 2098 sc->sc_rx_ready = 0; 2099 com_rxsoft(sc, tp); 2100 } 2101 2102 if (sc->sc_st_check) { 2103 sc->sc_st_check = 0; 2104 com_stsoft(sc, tp); 2105 } 2106 2107 if (sc->sc_tx_done) { 2108 sc->sc_tx_done = 0; 2109 com_txsoft(sc, tp); 2110 } 2111 } 2112 2113 int 2114 comintr(void *arg) 2115 { 2116 struct com_softc *sc = arg; 2117 struct com_regs *regsp = &sc->sc_regs; 2118 2119 u_char *put, *end; 2120 u_int cc; 2121 u_char lsr, iir; 2122 2123 if (COM_ISALIVE(sc) == 0) 2124 return (0); 2125 2126 KASSERT(regsp != NULL); 2127 2128 mutex_spin_enter(&sc->sc_lock); 2129 iir = CSR_READ_1(regsp, COM_REG_IIR); 2130 2131 /* Handle ns16750-specific busy interrupt. */ 2132 if (sc->sc_type == COM_TYPE_16750 && 2133 (iir & IIR_BUSY) == IIR_BUSY) { 2134 for (int timeout = 10000; 2135 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2136 if (timeout <= 0) { 2137 aprint_error_dev(sc->sc_dev, 2138 "timeout while waiting for BUSY interrupt " 2139 "acknowledge\n"); 2140 mutex_spin_exit(&sc->sc_lock); 2141 return (0); 2142 } 2143 2144 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2145 iir = CSR_READ_1(regsp, COM_REG_IIR); 2146 } 2147 2148 /* DesignWare APB UART BUSY interrupt */ 2149 if (sc->sc_type == COM_TYPE_DW_APB && 2150 (iir & IIR_BUSY) == IIR_BUSY) { 2151 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2152 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2153 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2154 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2155 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2156 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2157 CSR_WRITE_1(regsp, COM_REG_HALT, 2158 HALT_CHCFG_EN | HALT_CHCFG_UD); 2159 for (int timeout = 10000000; 2160 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2161 timeout--) { 2162 if (timeout <= 0) { 2163 aprint_error_dev(sc->sc_dev, 2164 "timeout while waiting for HALT " 2165 "update acknowledge 0x%x 0x%x\n", 2166 CSR_READ_1(regsp, COM_REG_HALT), 2167 CSR_READ_1(regsp, COM_REG_USR)); 2168 break; 2169 } 2170 } 2171 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2172 (void)CSR_READ_1(regsp, COM_REG_USR); 2173 } else { 2174 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2175 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2176 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2177 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2178 } 2179 } 2180 2181 end = sc->sc_ebuf; 2182 put = sc->sc_rbput; 2183 cc = sc->sc_rbavail; 2184 2185 if (ISSET(iir, IIR_NOPEND)) { 2186 if (ISSET(sc->sc_hwflags, COM_HW_BROKEN_ETXRDY)) 2187 goto do_tx; 2188 mutex_spin_exit(&sc->sc_lock); 2189 return (0); 2190 } 2191 2192 again: do { 2193 u_char msr, delta; 2194 2195 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2196 if (ISSET(lsr, LSR_BI)) { 2197 int cn_trapped = 0; /* see above: cn_trap() */ 2198 2199 cn_check_magic(sc->sc_tty->t_dev, 2200 CNC_BREAK, com_cnm_state); 2201 if (cn_trapped) 2202 continue; 2203 #if defined(KGDB) && !defined(DDB) 2204 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2205 kgdb_connect(1); 2206 continue; 2207 } 2208 #endif 2209 } 2210 2211 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2212 lsr |= LSR_RXRDY; 2213 2214 if (ISSET(lsr, LSR_RCV_MASK) && 2215 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2216 while (cc > 0) { 2217 int cn_trapped = 0; 2218 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2219 put[1] = lsr; 2220 cn_check_magic(sc->sc_tty->t_dev, 2221 put[0], com_cnm_state); 2222 if (cn_trapped) 2223 goto next; 2224 put += 2; 2225 if (put >= end) 2226 put = sc->sc_rbuf; 2227 cc--; 2228 next: 2229 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2230 if (!ISSET(lsr, LSR_RCV_MASK)) 2231 break; 2232 } 2233 2234 /* 2235 * Current string of incoming characters ended because 2236 * no more data was available or we ran out of space. 2237 * Schedule a receive event if any data was received. 2238 * If we're out of space, turn off receive interrupts. 2239 */ 2240 sc->sc_rbput = put; 2241 sc->sc_rbavail = cc; 2242 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2243 sc->sc_rx_ready = 1; 2244 2245 /* 2246 * See if we are in danger of overflowing a buffer. If 2247 * so, use hardware flow control to ease the pressure. 2248 */ 2249 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2250 cc < sc->sc_r_hiwat) { 2251 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2252 com_hwiflow(sc); 2253 } 2254 2255 /* 2256 * If we're out of space, disable receive interrupts 2257 * until the queue has drained a bit. 2258 */ 2259 if (!cc) { 2260 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2261 switch (sc->sc_type) { 2262 case COM_TYPE_PXA2x0: 2263 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2264 break; 2265 case COM_TYPE_INGENIC: 2266 case COM_TYPE_TEGRA: 2267 CLR(sc->sc_ier, 2268 IER_ERXRDY | IER_ERXTOUT); 2269 break; 2270 default: 2271 CLR(sc->sc_ier, IER_ERXRDY); 2272 break; 2273 } 2274 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2275 } 2276 } else { 2277 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2278 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2279 continue; 2280 } 2281 } 2282 2283 msr = CSR_READ_1(regsp, COM_REG_MSR); 2284 delta = msr ^ sc->sc_msr; 2285 sc->sc_msr = msr; 2286 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2287 (delta & MSR_DCD)) { 2288 mutex_spin_enter(&timecounter_lock); 2289 pps_capture(&sc->sc_pps_state); 2290 pps_event(&sc->sc_pps_state, 2291 (msr & MSR_DCD) ? 2292 PPS_CAPTUREASSERT : 2293 PPS_CAPTURECLEAR); 2294 mutex_spin_exit(&timecounter_lock); 2295 } 2296 2297 /* 2298 * Process normal status changes 2299 */ 2300 if (ISSET(delta, sc->sc_msr_mask)) { 2301 SET(sc->sc_msr_delta, delta); 2302 2303 /* 2304 * Stop output immediately if we lose the output 2305 * flow control signal or carrier detect. 2306 */ 2307 if (ISSET(~msr, sc->sc_msr_mask)) { 2308 sc->sc_tbc = 0; 2309 sc->sc_heldtbc = 0; 2310 #ifdef COM_DEBUG 2311 if (com_debug) 2312 comstatus(sc, "comintr "); 2313 #endif 2314 } 2315 2316 sc->sc_st_check = 1; 2317 } 2318 } while (!ISSET((iir = 2319 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2320 /* 2321 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2322 * by IIR read, so we can't do this way: `process all interrupts, 2323 * then do TX if possible'. 2324 */ 2325 (iir & IIR_IMASK) != IIR_TXRDY); 2326 2327 do_tx: 2328 /* 2329 * Read LSR again, since there may be an interrupt between 2330 * the last LSR read and IIR read above. 2331 */ 2332 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2333 2334 /* 2335 * See if data can be transmitted as well. 2336 * Schedule tx done event if no data left 2337 * and tty was marked busy. 2338 */ 2339 if (ISSET(lsr, LSR_TXRDY)) { 2340 /* 2341 * If we've delayed a parameter change, do it now, and restart 2342 * output. 2343 */ 2344 if (sc->sc_heldchange) { 2345 com_loadchannelregs(sc); 2346 sc->sc_heldchange = 0; 2347 sc->sc_tbc = sc->sc_heldtbc; 2348 sc->sc_heldtbc = 0; 2349 } 2350 2351 /* Output the next chunk of the contiguous buffer, if any. */ 2352 if (sc->sc_tbc > 0) { 2353 u_int n; 2354 2355 n = sc->sc_tbc; 2356 if (n > sc->sc_fifolen) 2357 n = sc->sc_fifolen; 2358 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2359 sc->sc_tbc -= n; 2360 sc->sc_tba += n; 2361 } else { 2362 /* Disable transmit completion interrupts if necessary. */ 2363 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2364 CLR(sc->sc_ier, IER_ETXRDY); 2365 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2366 } 2367 if (sc->sc_tx_busy) { 2368 sc->sc_tx_busy = 0; 2369 sc->sc_tx_done = 1; 2370 } 2371 } 2372 } 2373 2374 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2375 goto again; 2376 2377 mutex_spin_exit(&sc->sc_lock); 2378 2379 /* Wake up the poller. */ 2380 if ((sc->sc_rx_ready | sc->sc_st_check | sc->sc_tx_done) != 0) 2381 softint_schedule(sc->sc_si); 2382 2383 #ifdef RND_COM 2384 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2385 #endif 2386 2387 return (1); 2388 } 2389 2390 /* 2391 * The following functions are polled getc and putc routines, shared 2392 * by the console and kgdb glue. 2393 * 2394 * The read-ahead code is so that you can detect pending in-band 2395 * cn_magic in polled mode while doing output rather than having to 2396 * wait until the kernel decides it needs input. 2397 */ 2398 2399 #define MAX_READAHEAD 20 2400 static int com_readahead[MAX_READAHEAD]; 2401 static int com_readaheadcount = 0; 2402 2403 int 2404 com_common_getc(dev_t dev, struct com_regs *regsp) 2405 { 2406 int s = splserial(); 2407 u_char stat, c; 2408 2409 /* got a character from reading things earlier */ 2410 if (com_readaheadcount > 0) { 2411 int i; 2412 2413 c = com_readahead[0]; 2414 for (i = 1; i < com_readaheadcount; i++) { 2415 com_readahead[i-1] = com_readahead[i]; 2416 } 2417 com_readaheadcount--; 2418 splx(s); 2419 return (c); 2420 } 2421 2422 /* don't block until a character becomes available */ 2423 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2424 splx(s); 2425 return -1; 2426 } 2427 2428 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2429 stat = CSR_READ_1(regsp, COM_REG_IIR); 2430 { 2431 int cn_trapped = 0; /* required by cn_trap, see above */ 2432 #ifdef DDB 2433 extern int db_active; 2434 if (!db_active) 2435 #endif 2436 cn_check_magic(dev, c, com_cnm_state); 2437 } 2438 splx(s); 2439 return (c); 2440 } 2441 2442 static void 2443 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead) 2444 { 2445 int s = splserial(); 2446 int cin, stat, timo; 2447 2448 if (with_readahead && com_readaheadcount < MAX_READAHEAD 2449 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2450 int cn_trapped = 0; 2451 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2452 stat = CSR_READ_1(regsp, COM_REG_IIR); 2453 cn_check_magic(dev, cin, com_cnm_state); 2454 com_readahead[com_readaheadcount++] = cin; 2455 } 2456 2457 /* wait for any pending transmission to finish */ 2458 timo = 150000; 2459 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2460 continue; 2461 2462 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2463 COM_BARRIER(regsp, BR | BW); 2464 2465 splx(s); 2466 } 2467 2468 /* 2469 * Initialize UART for use as console or KGDB line. 2470 */ 2471 int 2472 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2473 tcflag_t cflag) 2474 { 2475 2476 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2477 ®sp->cr_ioh)) 2478 return (ENOMEM); /* ??? */ 2479 2480 if (type == COM_TYPE_OMAP) { 2481 /* disable before changing settings */ 2482 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2483 } 2484 2485 rate = comspeed(rate, frequency, type); 2486 if (rate != -1) { 2487 if (type == COM_TYPE_AU1x00) { 2488 /* no EFR on alchemy */ 2489 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2490 } else { 2491 if ((type != COM_TYPE_16550_NOERS) && 2492 (type != COM_TYPE_INGENIC)) { 2493 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2494 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2495 } 2496 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2497 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2498 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2499 } 2500 } 2501 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2502 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2503 2504 if (type == COM_TYPE_INGENIC) { 2505 CSR_WRITE_1(regsp, COM_REG_FIFO, 2506 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2507 FIFO_TRIGGER_1 | FIFO_UART_ON); 2508 } else { 2509 CSR_WRITE_1(regsp, COM_REG_FIFO, 2510 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2511 FIFO_TRIGGER_1); 2512 } 2513 2514 if (type == COM_TYPE_OMAP) { 2515 /* setup the fifos. the FCR value is not used as long 2516 as SCR[6] and SCR[7] are 0, which they are at reset 2517 and we never touch the SCR register */ 2518 uint8_t rx_fifo_trig = 40; 2519 uint8_t tx_fifo_trig = 60; 2520 uint8_t rx_start = 8; 2521 uint8_t rx_halt = 60; 2522 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2523 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2524 2525 /* enable access to TCR & TLR */ 2526 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2527 2528 /* write tcr and tlr values */ 2529 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2530 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2531 2532 /* disable access to TCR & TLR */ 2533 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2534 2535 /* enable again, but mode is based on speed */ 2536 if (rate > 230400) { 2537 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2538 } else { 2539 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2540 } 2541 } 2542 2543 if (type == COM_TYPE_PXA2x0) 2544 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2545 else 2546 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2547 2548 return (0); 2549 } 2550 2551 int 2552 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2553 tcflag_t cflag) 2554 { 2555 int res; 2556 2557 comcons_info.regs = *regsp; 2558 2559 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2560 if (res) 2561 return (res); 2562 2563 cn_tab = &comcons; 2564 cn_init_magic(&com_cnm_state); 2565 cn_set_magic("\047\001"); /* default magic is BREAK */ 2566 2567 comcons_info.frequency = frequency; 2568 comcons_info.type = type; 2569 comcons_info.rate = rate; 2570 comcons_info.cflag = cflag; 2571 2572 return (0); 2573 } 2574 2575 int 2576 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2577 int type, tcflag_t cflag) 2578 { 2579 struct com_regs regs; 2580 2581 /*XXX*/ 2582 bus_space_handle_t dummy_bsh; 2583 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2584 2585 /* 2586 * dummy_bsh required because com_init_regs() wants it. A 2587 * real bus_space_handle will be filled in by cominit() later. 2588 * XXXJRT Detangle this mess eventually, plz. 2589 */ 2590 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2591 2592 return comcnattach1(®s, rate, frequency, type, cflag); 2593 } 2594 2595 static int 2596 comcnreattach(void) 2597 { 2598 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2599 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2600 } 2601 2602 int 2603 comcngetc(dev_t dev) 2604 { 2605 2606 return (com_common_getc(dev, &comcons_info.regs)); 2607 } 2608 2609 /* 2610 * Console kernel output character routine. 2611 */ 2612 void 2613 comcnputc(dev_t dev, int c) 2614 { 2615 2616 com_common_putc(dev, &comcons_info.regs, c, cold); 2617 } 2618 2619 void 2620 comcnpollc(dev_t dev, int on) 2621 { 2622 2623 com_readaheadcount = 0; 2624 } 2625 2626 #ifdef KGDB 2627 int 2628 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2629 tcflag_t cflag) 2630 { 2631 int res; 2632 2633 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2634 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2635 #if !defined(DDB) 2636 return (EBUSY); /* cannot share with console */ 2637 #else 2638 comkgdbregs = *regsp; 2639 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2640 #endif 2641 } else { 2642 comkgdbregs = *regsp; 2643 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2644 if (res) 2645 return (res); 2646 2647 /* 2648 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2649 * expects this to be initialized 2650 */ 2651 cn_init_magic(&com_cnm_state); 2652 cn_set_magic("\047\001"); 2653 } 2654 2655 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2656 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2657 2658 return (0); 2659 } 2660 2661 int 2662 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2663 int frequency, int type, tcflag_t cflag) 2664 { 2665 struct com_regs regs; 2666 2667 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2668 2669 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2670 } 2671 2672 /* ARGSUSED */ 2673 int 2674 com_kgdb_getc(void *arg) 2675 { 2676 2677 return (com_common_getc(NODEV, &comkgdbregs)); 2678 } 2679 2680 /* ARGSUSED */ 2681 void 2682 com_kgdb_putc(void *arg, int c) 2683 { 2684 2685 com_common_putc(NODEV, &comkgdbregs, c, 0); 2686 } 2687 #endif /* KGDB */ 2688 2689 /* helper function to identify the com ports used by 2690 console or KGDB (and not yet autoconf attached) */ 2691 int 2692 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2693 { 2694 bus_space_handle_t help; 2695 2696 if (!comconsattached && 2697 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2698 iobase == comcons_info.regs.cr_iobase) 2699 help = comcons_info.regs.cr_ioh; 2700 #ifdef KGDB 2701 else if (!com_kgdb_attached && 2702 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2703 iobase == comkgdbregs.cr_iobase) 2704 help = comkgdbregs.cr_ioh; 2705 #endif 2706 else 2707 return (0); 2708 2709 if (ioh) 2710 *ioh = help; 2711 return (1); 2712 } 2713 2714 /* 2715 * this routine exists to serve as a shutdown hook for systems that 2716 * have firmware which doesn't interact properly with a com device in 2717 * FIFO mode. 2718 */ 2719 bool 2720 com_cleanup(device_t self, int how) 2721 { 2722 struct com_softc *sc = device_private(self); 2723 2724 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2725 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2726 2727 return true; 2728 } 2729 2730 bool 2731 com_suspend(device_t self, const pmf_qual_t *qual) 2732 { 2733 struct com_softc *sc = device_private(self); 2734 2735 #if 0 2736 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2737 cn_tab = &comcons_suspend; 2738 #endif 2739 2740 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2741 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2742 2743 return true; 2744 } 2745 2746 bool 2747 com_resume(device_t self, const pmf_qual_t *qual) 2748 { 2749 struct com_softc *sc = device_private(self); 2750 2751 mutex_spin_enter(&sc->sc_lock); 2752 com_loadchannelregs(sc); 2753 mutex_spin_exit(&sc->sc_lock); 2754 2755 return true; 2756 } 2757
Indexes created Wed Sep 24 15:09:51 GMT 2025