com.c revision 1.368
1 /* $NetBSD: com.c,v 1.368 2021/10/12 08:09:50 kre Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.368 2021/10/12 08:09:50 kre Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #define CSR_WRITE_1(r, o, v) \ 132 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 133 #define CSR_READ_1(r, o) \ 134 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 135 #define CSR_WRITE_2(r, o, v) \ 136 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 137 #define CSR_READ_2(r, o) \ 138 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 139 #define CSR_WRITE_MULTI(r, o, p, n) \ 140 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 141 142 143 static void com_enable_debugport(struct com_softc *); 144 145 void com_config(struct com_softc *); 146 void com_shutdown(struct com_softc *); 147 int comspeed(long, long, int); 148 static u_char cflag2lcr(tcflag_t); 149 int comparam(struct tty *, struct termios *); 150 void comstart(struct tty *); 151 int comhwiflow(struct tty *, int); 152 153 void com_loadchannelregs(struct com_softc *); 154 void com_hwiflow(struct com_softc *); 155 void com_break(struct com_softc *, int); 156 void com_modem(struct com_softc *, int); 157 void tiocm_to_com(struct com_softc *, u_long, int); 158 int com_to_tiocm(struct com_softc *); 159 void com_iflush(struct com_softc *); 160 161 int com_common_getc(dev_t, struct com_regs *); 162 static void com_common_putc(dev_t, struct com_regs *, int, int); 163 164 int cominit(struct com_regs *, int, int, int, tcflag_t); 165 166 static int comcnreattach(void); 167 168 int comcngetc(dev_t); 169 void comcnputc(dev_t, int); 170 void comcnpollc(dev_t, int); 171 172 #define integrate static inline 173 void comsoft(void *); 174 integrate void com_rxsoft(struct com_softc *, struct tty *); 175 integrate void com_txsoft(struct com_softc *, struct tty *); 176 integrate void com_stsoft(struct com_softc *, struct tty *); 177 integrate void com_schedrx(struct com_softc *); 178 void comdiag(void *); 179 180 dev_type_open(comopen); 181 dev_type_close(comclose); 182 dev_type_read(comread); 183 dev_type_write(comwrite); 184 dev_type_ioctl(comioctl); 185 dev_type_stop(comstop); 186 dev_type_tty(comtty); 187 dev_type_poll(compoll); 188 189 static struct comcons_info comcons_info; 190 191 /* 192 * Following are all routines needed for COM to act as console 193 */ 194 static struct consdev comcons = { 195 .cn_getc = comcngetc, 196 .cn_putc = comcnputc, 197 .cn_pollc = comcnpollc, 198 .cn_dev = NODEV, 199 .cn_pri = CN_NORMAL 200 }; 201 202 203 const struct cdevsw com_cdevsw = { 204 .d_open = comopen, 205 .d_close = comclose, 206 .d_read = comread, 207 .d_write = comwrite, 208 .d_ioctl = comioctl, 209 .d_stop = comstop, 210 .d_tty = comtty, 211 .d_poll = compoll, 212 .d_mmap = nommap, 213 .d_kqfilter = ttykqfilter, 214 .d_discard = nodiscard, 215 .d_flag = D_TTY 216 }; 217 218 /* 219 * Make this an option variable one can patch. 220 * But be warned: this must be a power of 2! 221 */ 222 u_int com_rbuf_size = COM_RING_SIZE; 223 224 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 225 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 226 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 227 228 static int comconsattached; 229 static struct cnm_state com_cnm_state; 230 231 #ifdef KGDB 232 #include <sys/kgdb.h> 233 234 static struct com_regs comkgdbregs; 235 static int com_kgdb_attached; 236 237 int com_kgdb_getc(void *); 238 void com_kgdb_putc(void *, int); 239 #endif /* KGDB */ 240 241 /* initializer for typical 16550-ish hardware */ 242 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 243 [COM_REG_RXDATA] = com_data, 244 [COM_REG_TXDATA] = com_data, 245 [COM_REG_DLBL] = com_dlbl, 246 [COM_REG_DLBH] = com_dlbh, 247 [COM_REG_IER] = com_ier, 248 [COM_REG_IIR] = com_iir, 249 [COM_REG_FIFO] = com_fifo, 250 [COM_REG_TCR] = com_fifo, 251 [COM_REG_EFR] = com_efr, 252 [COM_REG_TLR] = com_efr, 253 [COM_REG_LCR] = com_lcr, 254 [COM_REG_MCR] = com_mcr, 255 [COM_REG_LSR] = com_lsr, 256 [COM_REG_MSR] = com_msr, 257 [COM_REG_USR] = com_usr, 258 [COM_REG_TFL] = com_tfl, 259 [COM_REG_RFL] = com_rfl, 260 [COM_REG_HALT] = com_halt, 261 [COM_REG_MDR1] = com_mdr1, 262 }; 263 264 #define COMDIALOUT_MASK TTDIALOUT_MASK 265 266 #define COMUNIT(x) TTUNIT(x) 267 #define COMDIALOUT(x) TTDIALOUT(x) 268 269 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 270 device_is_active((sc)->sc_dev)) 271 272 #define BR BUS_SPACE_BARRIER_READ 273 #define BW BUS_SPACE_BARRIER_WRITE 274 #define COM_BARRIER(r, f) \ 275 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 276 277 /* 278 * com_init_regs -- 279 * Driver front-ends use this to initialize our register map 280 * in the standard fashion. They may then tailor the map to 281 * their own particular requirements. 282 */ 283 void 284 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 285 bus_addr_t addr) 286 { 287 288 memset(regs, 0, sizeof(*regs)); 289 regs->cr_iot = st; 290 regs->cr_ioh = sh; 291 regs->cr_iobase = addr; 292 regs->cr_nports = COM_NPORTS; 293 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 294 } 295 296 /* 297 * com_init_regs_stride -- 298 * Convenience function for front-ends that have a stride between 299 * registers. 300 */ 301 void 302 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 303 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 304 { 305 306 com_init_regs(regs, st, sh, addr); 307 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 308 regs->cr_map[i] <<= regshift; 309 } 310 regs->cr_nports <<= regshift; 311 } 312 313 /*ARGSUSED*/ 314 int 315 comspeed(long speed, long frequency, int type) 316 { 317 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 318 319 int x, err; 320 int divisor = 16; 321 322 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 323 divisor = 13; 324 } 325 326 if (speed == 0) 327 return (0); 328 if (speed < 0) 329 return (-1); 330 x = divrnd(frequency / divisor, speed); 331 if (x <= 0) 332 return (-1); 333 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 334 if (err < 0) 335 err = -err; 336 if (err > COM_TOLERANCE) 337 return (-1); 338 return (x); 339 340 #undef divrnd 341 } 342 343 #ifdef COM_DEBUG 344 int com_debug = 0; 345 346 void comstatus(struct com_softc *, const char *); 347 void 348 comstatus(struct com_softc *sc, const char *str) 349 { 350 struct tty *tp = sc->sc_tty; 351 352 aprint_normal_dev(sc->sc_dev, 353 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 354 str, 355 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 356 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 357 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 358 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 359 sc->sc_tx_stopped ? '+' : '-'); 360 361 aprint_normal_dev(sc->sc_dev, 362 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 363 str, 364 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 365 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 366 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 367 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 368 sc->sc_rx_flags); 369 } 370 #endif 371 372 int 373 com_probe_subr(struct com_regs *regs) 374 { 375 376 /* force access to id reg */ 377 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 378 CSR_WRITE_1(regs, COM_REG_IIR, 0); 379 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 380 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 381 return (0); 382 383 return (1); 384 } 385 386 int 387 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 388 { 389 struct com_regs regs; 390 391 com_init_regs(®s, iot, ioh, 0/*XXX*/); 392 393 return com_probe_subr(®s); 394 } 395 396 /* 397 * No locking in this routine; it is only called during attach, 398 * or with the port already locked. 399 */ 400 static void 401 com_enable_debugport(struct com_softc *sc) 402 { 403 404 /* Turn on line break interrupt, set carrier. */ 405 sc->sc_ier = IER_ERLS; 406 if (sc->sc_type == COM_TYPE_PXA2x0) 407 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 408 if (sc->sc_type == COM_TYPE_INGENIC || 409 sc->sc_type == COM_TYPE_TEGRA) 410 sc->sc_ier |= IER_ERXTOUT; 411 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 412 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 413 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 414 } 415 416 static void 417 com_intr_poll(void *arg) 418 { 419 struct com_softc * const sc = arg; 420 421 comintr(sc); 422 423 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 424 } 425 426 void 427 com_attach_subr(struct com_softc *sc) 428 { 429 struct com_regs *regsp = &sc->sc_regs; 430 struct tty *tp; 431 uint32_t cpr; 432 uint8_t lcr; 433 const char *fifo_msg = NULL; 434 prop_dictionary_t dict; 435 bool is_console = true; 436 bool force_console = false; 437 438 aprint_naive("\n"); 439 440 dict = device_properties(sc->sc_dev); 441 prop_dictionary_get_bool(dict, "is_console", &is_console); 442 prop_dictionary_get_bool(dict, "force_console", &force_console); 443 callout_init(&sc->sc_diag_callout, 0); 444 callout_init(&sc->sc_poll_callout, 0); 445 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 446 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 447 448 #if defined(COM_16650) 449 sc->sc_type = COM_TYPE_16650; 450 #elif defined(COM_16750) 451 sc->sc_type = COM_TYPE_16750; 452 #elif defined(COM_HAYESP) 453 sc->sc_type = COM_TYPE_HAYESP; 454 #elif defined(COM_PXA2X0) 455 sc->sc_type = COM_TYPE_PXA2x0; 456 #endif 457 458 /* Disable interrupts before configuring the device. */ 459 if (sc->sc_type == COM_TYPE_PXA2x0) 460 sc->sc_ier = IER_EUART; 461 else 462 sc->sc_ier = 0; 463 464 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 465 466 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 467 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 468 comconsattached = 1; 469 470 if (force_console) 471 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 472 473 if (cn_tab == NULL && comcnreattach() != 0) { 474 printf("can't re-init serial console @%lx\n", 475 (u_long)comcons_info.regs.cr_iobase); 476 } 477 478 switch (sc->sc_type) { 479 case COM_TYPE_16750: 480 case COM_TYPE_DW_APB: 481 /* Use in comintr(). */ 482 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 483 break; 484 } 485 486 /* Make sure the console is always "hardwired". */ 487 delay(10000); /* wait for output to finish */ 488 if (is_console) { 489 SET(sc->sc_hwflags, COM_HW_CONSOLE); 490 } 491 492 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 493 } 494 495 /* Probe for FIFO */ 496 switch (sc->sc_type) { 497 case COM_TYPE_HAYESP: 498 goto fifodone; 499 500 case COM_TYPE_AU1x00: 501 sc->sc_fifolen = 16; 502 fifo_msg = "Au1X00 UART"; 503 SET(sc->sc_hwflags, COM_HW_FIFO); 504 goto fifodelay; 505 506 case COM_TYPE_16550_NOERS: 507 sc->sc_fifolen = 16; 508 fifo_msg = "ns16650, no ERS"; 509 SET(sc->sc_hwflags, COM_HW_FIFO); 510 goto fifodelay; 511 512 case COM_TYPE_OMAP: 513 sc->sc_fifolen = 64; 514 fifo_msg = "OMAP UART"; 515 SET(sc->sc_hwflags, COM_HW_FIFO); 516 goto fifodelay; 517 518 case COM_TYPE_INGENIC: 519 sc->sc_fifolen = 16; 520 fifo_msg = "Ingenic UART"; 521 SET(sc->sc_hwflags, COM_HW_FIFO); 522 SET(sc->sc_hwflags, COM_HW_NOIEN); 523 goto fifodelay; 524 525 case COM_TYPE_TEGRA: 526 sc->sc_fifolen = 8; 527 fifo_msg = "Tegra UART"; 528 SET(sc->sc_hwflags, COM_HW_FIFO); 529 CSR_WRITE_1(regsp, COM_REG_FIFO, 530 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 531 goto fifodelay; 532 533 case COM_TYPE_BCMAUXUART: 534 sc->sc_fifolen = 1; 535 fifo_msg = "BCM AUX UART"; 536 SET(sc->sc_hwflags, COM_HW_FIFO); 537 CSR_WRITE_1(regsp, COM_REG_FIFO, 538 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 539 goto fifodelay; 540 541 case COM_TYPE_DW_APB: 542 if (!prop_dictionary_get_uint(dict, "fifolen", &sc->sc_fifolen)) { 543 cpr = bus_space_read_4(sc->sc_regs.cr_iot, 544 sc->sc_regs.cr_ioh, DW_APB_UART_CPR); 545 sc->sc_fifolen = __SHIFTOUT(cpr, UART_CPR_FIFO_MODE) * 16; 546 } 547 if (sc->sc_fifolen == 0) { 548 sc->sc_fifolen = 1; 549 fifo_msg = "DesignWare APB UART, no fifo"; 550 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 551 } else { 552 fifo_msg = "DesignWare APB UART"; 553 SET(sc->sc_hwflags, COM_HW_FIFO); 554 CSR_WRITE_1(regsp, COM_REG_FIFO, 555 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 556 } 557 goto fifodelay; 558 } 559 560 sc->sc_fifolen = 1; 561 /* look for a NS 16550AF UART with FIFOs */ 562 if (sc->sc_type == COM_TYPE_INGENIC) { 563 CSR_WRITE_1(regsp, COM_REG_FIFO, 564 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 565 FIFO_TRIGGER_14 | FIFO_UART_ON); 566 } else 567 CSR_WRITE_1(regsp, COM_REG_FIFO, 568 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 569 delay(100); 570 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 571 == IIR_FIFO_MASK) 572 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 573 == FIFO_TRIGGER_14) { 574 SET(sc->sc_hwflags, COM_HW_FIFO); 575 576 fifo_msg = "ns16550a"; 577 578 /* 579 * IIR changes into the EFR if LCR is set to LCR_EERS 580 * on 16650s. We also know IIR != 0 at this point. 581 * Write 0 into the EFR, and read it. If the result 582 * is 0, we have a 16650. 583 * 584 * Older 16650s were broken; the test to detect them 585 * is taken from the Linux driver. Apparently 586 * setting DLAB enable gives access to the EFR on 587 * these chips. 588 */ 589 if (sc->sc_type == COM_TYPE_16650) { 590 lcr = CSR_READ_1(regsp, COM_REG_LCR); 591 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 592 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 593 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 594 CSR_WRITE_1(regsp, COM_REG_LCR, 595 lcr | LCR_DLAB); 596 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 597 CLR(sc->sc_hwflags, COM_HW_FIFO); 598 sc->sc_fifolen = 0; 599 } else { 600 SET(sc->sc_hwflags, COM_HW_FLOW); 601 sc->sc_fifolen = 32; 602 } 603 } else 604 sc->sc_fifolen = 16; 605 606 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 607 if (sc->sc_fifolen == 0) 608 fifo_msg = "st16650, broken fifo"; 609 else if (sc->sc_fifolen == 32) 610 fifo_msg = "st16650a"; 611 else 612 fifo_msg = "ns16550a"; 613 } 614 615 /* 616 * TL16C750 can enable 64byte FIFO, only when DLAB 617 * is 1. However, some 16750 may always enable. For 618 * example, restrictions according to DLAB in a data 619 * sheet for SC16C750 were not described. 620 * Please enable 'options COM_16650', supposing you 621 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 622 * should become effective. 623 */ 624 if (sc->sc_type == COM_TYPE_16750) { 625 uint8_t iir1, iir2; 626 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 627 628 lcr = CSR_READ_1(regsp, COM_REG_LCR); 629 CSR_WRITE_1(regsp, COM_REG_LCR, 630 lcr & ~LCR_DLAB); 631 CSR_WRITE_1(regsp, COM_REG_FIFO, 632 fcr | FIFO_64B_ENABLE); 633 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 634 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 635 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 636 CSR_WRITE_1(regsp, COM_REG_FIFO, 637 fcr | FIFO_64B_ENABLE); 638 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 639 640 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 641 642 if (!ISSET(iir1, IIR_64B_FIFO) && 643 ISSET(iir2, IIR_64B_FIFO)) { 644 /* It is TL16C750. */ 645 sc->sc_fifolen = 64; 646 SET(sc->sc_hwflags, COM_HW_AFE); 647 } else 648 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 649 650 if (sc->sc_fifolen == 64) 651 fifo_msg = "tl16c750"; 652 else 653 fifo_msg = "ns16750"; 654 } 655 } else 656 fifo_msg = "ns16550, broken fifo"; 657 else 658 fifo_msg = "ns8250 or ns16450, no fifo"; 659 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 660 661 fifodelay: 662 /* 663 * Some chips will clear down both Tx and Rx FIFOs when zero is 664 * written to com_fifo. If this chip is the console, writing zero 665 * results in some of the chip/FIFO description being lost, so delay 666 * printing it until now. 667 */ 668 delay(10); 669 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 670 aprint_normal(": %s, %d-byte FIFO\n", fifo_msg, sc->sc_fifolen); 671 } else { 672 aprint_normal(": %s\n", fifo_msg); 673 } 674 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 675 sc->sc_fifolen = 1; 676 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 677 } 678 679 fifodone: 680 681 tp = tty_alloc(); 682 tp->t_oproc = comstart; 683 tp->t_param = comparam; 684 tp->t_hwiflow = comhwiflow; 685 tp->t_softc = sc; 686 687 sc->sc_tty = tp; 688 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK); 689 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 690 sc->sc_rbavail = com_rbuf_size; 691 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 692 693 tty_attach(tp); 694 695 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 696 SET(sc->sc_mcr, MCR_IENABLE); 697 698 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 699 int maj; 700 701 /* locate the major number */ 702 maj = cdevsw_lookup_major(&com_cdevsw); 703 704 tp->t_dev = cn_tab->cn_dev = makedev(maj, 705 device_unit(sc->sc_dev)); 706 707 aprint_normal_dev(sc->sc_dev, "console\n"); 708 } 709 710 #ifdef KGDB 711 /* 712 * Allow kgdb to "take over" this port. If this is 713 * not the console and is the kgdb device, it has 714 * exclusive use. If it's the console _and_ the 715 * kgdb device, it doesn't. 716 */ 717 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 718 regsp->cr_iobase == comkgdbregs.cr_iobase) { 719 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 720 com_kgdb_attached = 1; 721 722 SET(sc->sc_hwflags, COM_HW_KGDB); 723 } 724 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 725 } 726 #endif 727 728 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 729 730 #ifdef RND_COM 731 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 732 RND_TYPE_TTY, RND_FLAG_DEFAULT); 733 #endif 734 735 /* if there are no enable/disable functions, assume the device 736 is always enabled */ 737 if (!sc->enable) 738 sc->enabled = 1; 739 740 com_config(sc); 741 742 SET(sc->sc_hwflags, COM_HW_DEV_OK); 743 744 if (sc->sc_poll_ticks != 0) 745 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 746 } 747 748 void 749 com_config(struct com_softc *sc) 750 { 751 struct com_regs *regsp = &sc->sc_regs; 752 753 /* Disable interrupts before configuring the device. */ 754 if (sc->sc_type == COM_TYPE_PXA2x0) 755 sc->sc_ier = IER_EUART; 756 else 757 sc->sc_ier = 0; 758 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 759 (void) CSR_READ_1(regsp, COM_REG_IIR); 760 761 /* Look for a Hayes ESP board. */ 762 if (sc->sc_type == COM_TYPE_HAYESP) { 763 764 /* Set 16550 compatibility mode */ 765 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 766 HAYESP_SETMODE); 767 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 768 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 769 HAYESP_MODE_SCALE); 770 771 /* Set RTS/CTS flow control */ 772 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 773 HAYESP_SETFLOWTYPE); 774 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 775 HAYESP_FLOW_RTS); 776 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 777 HAYESP_FLOW_CTS); 778 779 /* Set flow control levels */ 780 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 781 HAYESP_SETRXFLOW); 782 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 783 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 784 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 785 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 786 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 787 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 788 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 789 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 790 } 791 792 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 793 com_enable_debugport(sc); 794 } 795 796 #if 0 797 static int 798 comcngetc_detached(dev_t dev) 799 { 800 return 0; 801 } 802 803 static void 804 comcnputc_detached(dev_t dev, int c) 805 { 806 } 807 #endif 808 809 int 810 com_detach(device_t self, int flags) 811 { 812 struct com_softc *sc = device_private(self); 813 int maj, mn; 814 815 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 816 return EBUSY; 817 818 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 819 (flags & DETACH_SHUTDOWN) != 0) 820 return EBUSY; 821 822 if (sc->disable != NULL && sc->enabled != 0) { 823 (*sc->disable)(sc); 824 sc->enabled = 0; 825 } 826 827 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 828 comconsattached = 0; 829 cn_tab = NULL; 830 } 831 832 /* locate the major number */ 833 maj = cdevsw_lookup_major(&com_cdevsw); 834 835 /* Nuke the vnodes for any open instances. */ 836 mn = device_unit(self); 837 vdevgone(maj, mn, mn, VCHR); 838 839 mn |= COMDIALOUT_MASK; 840 vdevgone(maj, mn, mn, VCHR); 841 842 if (sc->sc_rbuf == NULL) { 843 /* 844 * Ring buffer allocation failed in the com_attach_subr, 845 * only the tty is allocated, and nothing else. 846 */ 847 tty_free(sc->sc_tty); 848 return 0; 849 } 850 851 /* Free the receive buffer. */ 852 free(sc->sc_rbuf, M_DEVBUF); 853 854 /* Detach and free the tty. */ 855 tty_detach(sc->sc_tty); 856 tty_free(sc->sc_tty); 857 858 /* Unhook the soft interrupt handler. */ 859 softint_disestablish(sc->sc_si); 860 861 #ifdef RND_COM 862 /* Unhook the entropy source. */ 863 rnd_detach_source(&sc->rnd_source); 864 #endif 865 callout_destroy(&sc->sc_diag_callout); 866 867 /* Destroy the lock. */ 868 mutex_destroy(&sc->sc_lock); 869 870 return (0); 871 } 872 873 void 874 com_shutdown(struct com_softc *sc) 875 { 876 struct tty *tp = sc->sc_tty; 877 878 mutex_spin_enter(&sc->sc_lock); 879 880 /* If we were asserting flow control, then deassert it. */ 881 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 882 com_hwiflow(sc); 883 884 /* Clear any break condition set with TIOCSBRK. */ 885 com_break(sc, 0); 886 887 /* 888 * Hang up if necessary. Wait a bit, so the other side has time to 889 * notice even if we immediately open the port again. 890 * Avoid tsleeping above splhigh(). 891 */ 892 if (ISSET(tp->t_cflag, HUPCL)) { 893 com_modem(sc, 0); 894 getmicrotime(&sc->sc_hup_pending); 895 sc->sc_hup_pending.tv_sec++; 896 } 897 898 /* Turn off interrupts. */ 899 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 900 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 901 if ((sc->sc_type == COM_TYPE_PXA2x0) || 902 (sc->sc_type == COM_TYPE_INGENIC) || 903 (sc->sc_type == COM_TYPE_TEGRA)) 904 sc->sc_ier |= IER_ERXTOUT; 905 } else 906 sc->sc_ier = 0; 907 908 if (sc->sc_type == COM_TYPE_PXA2x0) 909 sc->sc_ier |= IER_EUART; 910 911 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 912 913 mutex_spin_exit(&sc->sc_lock); 914 915 if (sc->disable) { 916 #ifdef DIAGNOSTIC 917 if (!sc->enabled) 918 panic("com_shutdown: not enabled?"); 919 #endif 920 (*sc->disable)(sc); 921 sc->enabled = 0; 922 } 923 } 924 925 int 926 comopen(dev_t dev, int flag, int mode, struct lwp *l) 927 { 928 struct com_softc *sc; 929 struct tty *tp; 930 int s; 931 int error; 932 933 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 934 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 935 sc->sc_rbuf == NULL) 936 return (ENXIO); 937 938 if (!device_is_active(sc->sc_dev)) 939 return (ENXIO); 940 941 #ifdef KGDB 942 /* 943 * If this is the kgdb port, no other use is permitted. 944 */ 945 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 946 return (EBUSY); 947 #endif 948 949 tp = sc->sc_tty; 950 951 /* 952 * If the device is exclusively for kernel use, deny userland 953 * open. 954 */ 955 if (ISSET(tp->t_state, TS_KERN_ONLY)) 956 return (EBUSY); 957 958 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 959 return (EBUSY); 960 961 s = spltty(); 962 963 /* 964 * Do the following iff this is a first open. 965 */ 966 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 967 struct termios t; 968 struct timeval now, diff; 969 970 tp->t_dev = dev; 971 972 if (sc->enable) { 973 if ((*sc->enable)(sc)) { 974 splx(s); 975 aprint_error_dev(sc->sc_dev, 976 "device enable failed\n"); 977 return (EIO); 978 } 979 mutex_spin_enter(&sc->sc_lock); 980 sc->enabled = 1; 981 com_config(sc); 982 } else { 983 mutex_spin_enter(&sc->sc_lock); 984 } 985 986 if (timerisset(&sc->sc_hup_pending)) { 987 getmicrotime(&now); 988 while (timercmp(&now, &sc->sc_hup_pending, <)) { 989 int ms; 990 991 992 timersub(&sc->sc_hup_pending, &now, &diff); 993 ms = diff.tv_sec * 1000 + 994 uimax(diff.tv_usec / 1000, 1); 995 kpause("comopen", false, mstohz(ms), 996 &sc->sc_lock); 997 getmicrotime(&now); 998 } 999 timerclear(&sc->sc_hup_pending); 1000 } 1001 1002 /* Turn on interrupts. */ 1003 sc->sc_ier = IER_ERXRDY | IER_ERLS; 1004 if (!ISSET(tp->t_cflag, CLOCAL)) 1005 sc->sc_ier |= IER_EMSC; 1006 1007 if (sc->sc_type == COM_TYPE_PXA2x0) 1008 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 1009 else if (sc->sc_type == COM_TYPE_INGENIC || 1010 sc->sc_type == COM_TYPE_TEGRA) 1011 sc->sc_ier |= IER_ERXTOUT; 1012 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1013 1014 /* Fetch the current modem control status, needed later. */ 1015 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 1016 1017 /* Clear PPS capture state on first open. */ 1018 mutex_spin_enter(&timecounter_lock); 1019 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 1020 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1021 pps_init(&sc->sc_pps_state); 1022 mutex_spin_exit(&timecounter_lock); 1023 1024 mutex_spin_exit(&sc->sc_lock); 1025 1026 /* 1027 * Initialize the termios status to the defaults. Add in the 1028 * sticky bits from TIOCSFLAGS. 1029 */ 1030 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1031 t.c_ospeed = comcons_info.rate; 1032 t.c_cflag = comcons_info.cflag; 1033 } else { 1034 t.c_ospeed = TTYDEF_SPEED; 1035 t.c_cflag = TTYDEF_CFLAG; 1036 } 1037 t.c_ispeed = t.c_ospeed; 1038 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1039 SET(t.c_cflag, CLOCAL); 1040 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1041 SET(t.c_cflag, CRTSCTS); 1042 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1043 SET(t.c_cflag, MDMBUF); 1044 /* Make sure comparam() will do something. */ 1045 tp->t_ospeed = 0; 1046 (void) comparam(tp, &t); 1047 tp->t_iflag = TTYDEF_IFLAG; 1048 tp->t_oflag = TTYDEF_OFLAG; 1049 tp->t_lflag = TTYDEF_LFLAG; 1050 ttychars(tp); 1051 ttsetwater(tp); 1052 1053 mutex_spin_enter(&sc->sc_lock); 1054 1055 /* 1056 * Turn on DTR. We must always do this, even if carrier is not 1057 * present, because otherwise we'd have to use TIOCSDTR 1058 * immediately after setting CLOCAL, which applications do not 1059 * expect. We always assert DTR while the device is open 1060 * unless explicitly requested to deassert it. 1061 */ 1062 com_modem(sc, 1); 1063 1064 /* Clear the input ring, and unblock. */ 1065 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1066 sc->sc_rbavail = com_rbuf_size; 1067 com_iflush(sc); 1068 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1069 com_hwiflow(sc); 1070 1071 #ifdef COM_DEBUG 1072 if (com_debug) 1073 comstatus(sc, "comopen "); 1074 #endif 1075 1076 mutex_spin_exit(&sc->sc_lock); 1077 } 1078 1079 splx(s); 1080 1081 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1082 if (error) 1083 goto bad; 1084 1085 error = (*tp->t_linesw->l_open)(dev, tp); 1086 if (error) 1087 goto bad; 1088 1089 return (0); 1090 1091 bad: 1092 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1093 /* 1094 * We failed to open the device, and nobody else had it opened. 1095 * Clean up the state as appropriate. 1096 */ 1097 com_shutdown(sc); 1098 } 1099 1100 return (error); 1101 } 1102 1103 int 1104 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1105 { 1106 struct com_softc *sc = 1107 device_lookup_private(&com_cd, COMUNIT(dev)); 1108 struct tty *tp = sc->sc_tty; 1109 1110 /* XXX This is for cons.c. */ 1111 if (!ISSET(tp->t_state, TS_ISOPEN)) 1112 return (0); 1113 /* 1114 * If the device is exclusively for kernel use, deny userland 1115 * close. 1116 */ 1117 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1118 return (0); 1119 1120 (*tp->t_linesw->l_close)(tp, flag); 1121 ttyclose(tp); 1122 1123 if (COM_ISALIVE(sc) == 0) 1124 return (0); 1125 1126 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1127 /* 1128 * Although we got a last close, the device may still be in 1129 * use; e.g. if this was the dialout node, and there are still 1130 * processes waiting for carrier on the non-dialout node. 1131 */ 1132 com_shutdown(sc); 1133 } 1134 1135 return (0); 1136 } 1137 1138 int 1139 comread(dev_t dev, struct uio *uio, int flag) 1140 { 1141 struct com_softc *sc = 1142 device_lookup_private(&com_cd, COMUNIT(dev)); 1143 struct tty *tp = sc->sc_tty; 1144 1145 if (COM_ISALIVE(sc) == 0) 1146 return (EIO); 1147 1148 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1149 } 1150 1151 int 1152 comwrite(dev_t dev, struct uio *uio, int flag) 1153 { 1154 struct com_softc *sc = 1155 device_lookup_private(&com_cd, COMUNIT(dev)); 1156 struct tty *tp = sc->sc_tty; 1157 1158 if (COM_ISALIVE(sc) == 0) 1159 return (EIO); 1160 1161 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1162 } 1163 1164 int 1165 compoll(dev_t dev, int events, struct lwp *l) 1166 { 1167 struct com_softc *sc = 1168 device_lookup_private(&com_cd, COMUNIT(dev)); 1169 struct tty *tp = sc->sc_tty; 1170 1171 if (COM_ISALIVE(sc) == 0) 1172 return (POLLHUP); 1173 1174 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1175 } 1176 1177 struct tty * 1178 comtty(dev_t dev) 1179 { 1180 struct com_softc *sc = 1181 device_lookup_private(&com_cd, COMUNIT(dev)); 1182 struct tty *tp = sc->sc_tty; 1183 1184 return (tp); 1185 } 1186 1187 int 1188 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1189 { 1190 struct com_softc *sc; 1191 struct tty *tp; 1192 int error; 1193 1194 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1195 if (sc == NULL) 1196 return ENXIO; 1197 if (COM_ISALIVE(sc) == 0) 1198 return (EIO); 1199 1200 tp = sc->sc_tty; 1201 1202 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1203 if (error != EPASSTHROUGH) 1204 return (error); 1205 1206 error = ttioctl(tp, cmd, data, flag, l); 1207 if (error != EPASSTHROUGH) 1208 return (error); 1209 1210 error = 0; 1211 switch (cmd) { 1212 case TIOCSFLAGS: 1213 error = kauth_authorize_device_tty(l->l_cred, 1214 KAUTH_DEVICE_TTY_PRIVSET, tp); 1215 break; 1216 default: 1217 /* nothing */ 1218 break; 1219 } 1220 if (error) { 1221 return error; 1222 } 1223 1224 mutex_spin_enter(&sc->sc_lock); 1225 1226 switch (cmd) { 1227 case TIOCSBRK: 1228 com_break(sc, 1); 1229 break; 1230 1231 case TIOCCBRK: 1232 com_break(sc, 0); 1233 break; 1234 1235 case TIOCSDTR: 1236 com_modem(sc, 1); 1237 break; 1238 1239 case TIOCCDTR: 1240 com_modem(sc, 0); 1241 break; 1242 1243 case TIOCGFLAGS: 1244 *(int *)data = sc->sc_swflags; 1245 break; 1246 1247 case TIOCSFLAGS: 1248 sc->sc_swflags = *(int *)data; 1249 break; 1250 1251 case TIOCMSET: 1252 case TIOCMBIS: 1253 case TIOCMBIC: 1254 tiocm_to_com(sc, cmd, *(int *)data); 1255 break; 1256 1257 case TIOCMGET: 1258 *(int *)data = com_to_tiocm(sc); 1259 break; 1260 1261 case PPS_IOC_CREATE: 1262 case PPS_IOC_DESTROY: 1263 case PPS_IOC_GETPARAMS: 1264 case PPS_IOC_SETPARAMS: 1265 case PPS_IOC_GETCAP: 1266 case PPS_IOC_FETCH: 1267 #ifdef PPS_SYNC 1268 case PPS_IOC_KCBIND: 1269 #endif 1270 mutex_spin_enter(&timecounter_lock); 1271 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1272 mutex_spin_exit(&timecounter_lock); 1273 break; 1274 1275 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1276 mutex_spin_enter(&timecounter_lock); 1277 #ifndef PPS_TRAILING_EDGE 1278 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1279 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1280 #else 1281 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1282 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1283 #endif 1284 mutex_spin_exit(&timecounter_lock); 1285 break; 1286 1287 default: 1288 error = EPASSTHROUGH; 1289 break; 1290 } 1291 1292 mutex_spin_exit(&sc->sc_lock); 1293 1294 #ifdef COM_DEBUG 1295 if (com_debug) 1296 comstatus(sc, "comioctl "); 1297 #endif 1298 1299 return (error); 1300 } 1301 1302 integrate void 1303 com_schedrx(struct com_softc *sc) 1304 { 1305 1306 sc->sc_rx_ready = 1; 1307 1308 /* Wake up the poller. */ 1309 softint_schedule(sc->sc_si); 1310 } 1311 1312 void 1313 com_break(struct com_softc *sc, int onoff) 1314 { 1315 1316 if (onoff) 1317 SET(sc->sc_lcr, LCR_SBREAK); 1318 else 1319 CLR(sc->sc_lcr, LCR_SBREAK); 1320 1321 if (!sc->sc_heldchange) { 1322 if (sc->sc_tx_busy) { 1323 sc->sc_heldtbc = sc->sc_tbc; 1324 sc->sc_tbc = 0; 1325 sc->sc_heldchange = 1; 1326 } else 1327 com_loadchannelregs(sc); 1328 } 1329 } 1330 1331 void 1332 com_modem(struct com_softc *sc, int onoff) 1333 { 1334 1335 if (sc->sc_mcr_dtr == 0) 1336 return; 1337 1338 if (onoff) 1339 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1340 else 1341 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1342 1343 if (!sc->sc_heldchange) { 1344 if (sc->sc_tx_busy) { 1345 sc->sc_heldtbc = sc->sc_tbc; 1346 sc->sc_tbc = 0; 1347 sc->sc_heldchange = 1; 1348 } else 1349 com_loadchannelregs(sc); 1350 } 1351 } 1352 1353 void 1354 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1355 { 1356 u_char combits; 1357 1358 combits = 0; 1359 if (ISSET(ttybits, TIOCM_DTR)) 1360 SET(combits, MCR_DTR); 1361 if (ISSET(ttybits, TIOCM_RTS)) 1362 SET(combits, MCR_RTS); 1363 1364 switch (how) { 1365 case TIOCMBIC: 1366 CLR(sc->sc_mcr, combits); 1367 break; 1368 1369 case TIOCMBIS: 1370 SET(sc->sc_mcr, combits); 1371 break; 1372 1373 case TIOCMSET: 1374 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1375 SET(sc->sc_mcr, combits); 1376 break; 1377 } 1378 1379 if (!sc->sc_heldchange) { 1380 if (sc->sc_tx_busy) { 1381 sc->sc_heldtbc = sc->sc_tbc; 1382 sc->sc_tbc = 0; 1383 sc->sc_heldchange = 1; 1384 } else 1385 com_loadchannelregs(sc); 1386 } 1387 } 1388 1389 int 1390 com_to_tiocm(struct com_softc *sc) 1391 { 1392 u_char combits; 1393 int ttybits = 0; 1394 1395 combits = sc->sc_mcr; 1396 if (ISSET(combits, MCR_DTR)) 1397 SET(ttybits, TIOCM_DTR); 1398 if (ISSET(combits, MCR_RTS)) 1399 SET(ttybits, TIOCM_RTS); 1400 1401 combits = sc->sc_msr; 1402 if (sc->sc_type == COM_TYPE_INGENIC) { 1403 SET(ttybits, TIOCM_CD); 1404 } else { 1405 if (ISSET(combits, MSR_DCD)) 1406 SET(ttybits, TIOCM_CD); 1407 } 1408 if (ISSET(combits, MSR_CTS)) 1409 SET(ttybits, TIOCM_CTS); 1410 if (ISSET(combits, MSR_DSR)) 1411 SET(ttybits, TIOCM_DSR); 1412 if (ISSET(combits, MSR_RI | MSR_TERI)) 1413 SET(ttybits, TIOCM_RI); 1414 1415 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1416 SET(ttybits, TIOCM_LE); 1417 1418 return (ttybits); 1419 } 1420 1421 static u_char 1422 cflag2lcr(tcflag_t cflag) 1423 { 1424 u_char lcr = 0; 1425 1426 switch (ISSET(cflag, CSIZE)) { 1427 case CS5: 1428 SET(lcr, LCR_5BITS); 1429 break; 1430 case CS6: 1431 SET(lcr, LCR_6BITS); 1432 break; 1433 case CS7: 1434 SET(lcr, LCR_7BITS); 1435 break; 1436 case CS8: 1437 SET(lcr, LCR_8BITS); 1438 break; 1439 } 1440 if (ISSET(cflag, PARENB)) { 1441 SET(lcr, LCR_PENAB); 1442 if (!ISSET(cflag, PARODD)) 1443 SET(lcr, LCR_PEVEN); 1444 } 1445 if (ISSET(cflag, CSTOPB)) 1446 SET(lcr, LCR_STOPB); 1447 1448 return (lcr); 1449 } 1450 1451 int 1452 comparam(struct tty *tp, struct termios *t) 1453 { 1454 struct com_softc *sc = 1455 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1456 int ospeed; 1457 u_char lcr; 1458 1459 if (COM_ISALIVE(sc) == 0) 1460 return (EIO); 1461 1462 if (sc->sc_type == COM_TYPE_HAYESP) { 1463 int prescaler, speed; 1464 1465 /* 1466 * Calculate UART clock prescaler. It should be in 1467 * range of 0 .. 3. 1468 */ 1469 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1470 prescaler++, speed /= 2) 1471 if ((ospeed = comspeed(speed, sc->sc_frequency, 1472 sc->sc_type)) > 0) 1473 break; 1474 1475 if (prescaler == 4) 1476 return (EINVAL); 1477 sc->sc_prescaler = prescaler; 1478 } else 1479 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1480 1481 /* Check requested parameters. */ 1482 if (ospeed < 0) 1483 return (EINVAL); 1484 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1485 return (EINVAL); 1486 1487 /* 1488 * For the console, always force CLOCAL and !HUPCL, so that the port 1489 * is always active. 1490 */ 1491 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1492 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1493 SET(t->c_cflag, CLOCAL); 1494 CLR(t->c_cflag, HUPCL); 1495 } 1496 1497 /* 1498 * If there were no changes, don't do anything. This avoids dropping 1499 * input and improves performance when all we did was frob things like 1500 * VMIN and VTIME. 1501 */ 1502 if (tp->t_ospeed == t->c_ospeed && 1503 tp->t_cflag == t->c_cflag) 1504 return (0); 1505 1506 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1507 1508 mutex_spin_enter(&sc->sc_lock); 1509 1510 sc->sc_lcr = lcr; 1511 1512 /* 1513 * If we're not in a mode that assumes a connection is present, then 1514 * ignore carrier changes. 1515 */ 1516 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1517 sc->sc_msr_dcd = 0; 1518 else 1519 sc->sc_msr_dcd = MSR_DCD; 1520 /* 1521 * Set the flow control pins depending on the current flow control 1522 * mode. 1523 */ 1524 if (ISSET(t->c_cflag, CRTSCTS)) { 1525 sc->sc_mcr_dtr = MCR_DTR; 1526 sc->sc_mcr_rts = MCR_RTS; 1527 sc->sc_msr_cts = MSR_CTS; 1528 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1529 SET(sc->sc_mcr, MCR_AFE); 1530 } else { 1531 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1532 } 1533 } else if (ISSET(t->c_cflag, MDMBUF)) { 1534 /* 1535 * For DTR/DCD flow control, make sure we don't toggle DTR for 1536 * carrier detection. 1537 */ 1538 sc->sc_mcr_dtr = 0; 1539 sc->sc_mcr_rts = MCR_DTR; 1540 sc->sc_msr_cts = MSR_DCD; 1541 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1542 CLR(sc->sc_mcr, MCR_AFE); 1543 } else { 1544 sc->sc_efr = 0; 1545 } 1546 } else { 1547 /* 1548 * If no flow control, then always set RTS. This will make 1549 * the other side happy if it mistakenly thinks we're doing 1550 * RTS/CTS flow control. 1551 */ 1552 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1553 sc->sc_mcr_rts = 0; 1554 sc->sc_msr_cts = 0; 1555 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1556 CLR(sc->sc_mcr, MCR_AFE); 1557 } else { 1558 sc->sc_efr = 0; 1559 } 1560 if (ISSET(sc->sc_mcr, MCR_DTR)) 1561 SET(sc->sc_mcr, MCR_RTS); 1562 else 1563 CLR(sc->sc_mcr, MCR_RTS); 1564 } 1565 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1566 1567 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1568 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1569 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1570 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1571 1572 sc->sc_dlbl = ospeed; 1573 sc->sc_dlbh = ospeed >> 8; 1574 1575 /* 1576 * Set the FIFO threshold based on the receive speed. 1577 * 1578 * * If it's a low speed, it's probably a mouse or some other 1579 * interactive device, so set the threshold low. 1580 * * If it's a high speed, trim the trigger level down to prevent 1581 * overflows. 1582 * * Otherwise set it a bit higher. 1583 */ 1584 if (sc->sc_type == COM_TYPE_HAYESP) { 1585 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1586 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1587 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1588 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1589 if (t->c_ospeed <= 1200) 1590 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1591 else if (t->c_ospeed <= 38400) 1592 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1593 else 1594 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1595 } else { 1596 sc->sc_fifo = 0; 1597 } 1598 1599 if (sc->sc_type == COM_TYPE_INGENIC) 1600 sc->sc_fifo |= FIFO_UART_ON; 1601 1602 /* And copy to tty. */ 1603 tp->t_ispeed = t->c_ospeed; 1604 tp->t_ospeed = t->c_ospeed; 1605 tp->t_cflag = t->c_cflag; 1606 1607 if (!sc->sc_heldchange) { 1608 if (sc->sc_tx_busy) { 1609 sc->sc_heldtbc = sc->sc_tbc; 1610 sc->sc_tbc = 0; 1611 sc->sc_heldchange = 1; 1612 } else 1613 com_loadchannelregs(sc); 1614 } 1615 1616 if (!ISSET(t->c_cflag, CHWFLOW)) { 1617 /* Disable the high water mark. */ 1618 sc->sc_r_hiwat = 0; 1619 sc->sc_r_lowat = 0; 1620 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1621 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1622 com_schedrx(sc); 1623 } 1624 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1625 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1626 com_hwiflow(sc); 1627 } 1628 } else { 1629 sc->sc_r_hiwat = com_rbuf_hiwat; 1630 sc->sc_r_lowat = com_rbuf_lowat; 1631 } 1632 1633 mutex_spin_exit(&sc->sc_lock); 1634 1635 /* 1636 * Update the tty layer's idea of the carrier bit, in case we changed 1637 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1638 * explicit request. 1639 */ 1640 if (sc->sc_type == COM_TYPE_INGENIC) { 1641 /* no DCD here */ 1642 (void) (*tp->t_linesw->l_modem)(tp, 1); 1643 } else 1644 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1645 1646 #ifdef COM_DEBUG 1647 if (com_debug) 1648 comstatus(sc, "comparam "); 1649 #endif 1650 1651 if (!ISSET(t->c_cflag, CHWFLOW)) { 1652 if (sc->sc_tx_stopped) { 1653 sc->sc_tx_stopped = 0; 1654 comstart(tp); 1655 } 1656 } 1657 1658 return (0); 1659 } 1660 1661 void 1662 com_iflush(struct com_softc *sc) 1663 { 1664 struct com_regs *regsp = &sc->sc_regs; 1665 uint8_t fifo; 1666 #ifdef DIAGNOSTIC 1667 int reg; 1668 #endif 1669 int timo; 1670 1671 #ifdef DIAGNOSTIC 1672 reg = 0xffff; 1673 #endif 1674 timo = 50000; 1675 /* flush any pending I/O */ 1676 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1677 && --timo) 1678 #ifdef DIAGNOSTIC 1679 reg = 1680 #else 1681 (void) 1682 #endif 1683 CSR_READ_1(regsp, COM_REG_RXDATA); 1684 #ifdef DIAGNOSTIC 1685 if (!timo) 1686 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1687 #endif 1688 1689 switch (sc->sc_type) { 1690 case COM_TYPE_16750: 1691 case COM_TYPE_DW_APB: 1692 /* 1693 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1694 * This should prevent triggering busy interrupt while 1695 * manipulating divisors. 1696 */ 1697 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1698 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1699 CSR_WRITE_1(regsp, COM_REG_FIFO, 1700 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1701 delay(100); 1702 break; 1703 } 1704 } 1705 1706 void 1707 com_loadchannelregs(struct com_softc *sc) 1708 { 1709 struct com_regs *regsp = &sc->sc_regs; 1710 1711 /* XXXXX necessary? */ 1712 com_iflush(sc); 1713 1714 if (sc->sc_type == COM_TYPE_PXA2x0) 1715 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1716 else 1717 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1718 1719 if (sc->sc_type == COM_TYPE_OMAP) { 1720 /* disable before changing settings */ 1721 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1722 } 1723 1724 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1725 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1726 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1727 /* no EFR on alchemy */ 1728 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1729 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1730 } 1731 if (sc->sc_type == COM_TYPE_AU1x00) { 1732 /* alchemy has single separate 16-bit clock divisor register */ 1733 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1734 (sc->sc_dlbh << 8)); 1735 } else { 1736 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1737 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1738 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1739 } 1740 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1741 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1742 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1743 if (sc->sc_type == COM_TYPE_HAYESP) { 1744 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1745 HAYESP_SETPRESCALER); 1746 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1747 sc->sc_prescaler); 1748 } 1749 if (sc->sc_type == COM_TYPE_OMAP) { 1750 /* setup the fifos. the FCR value is not used as long 1751 as SCR[6] and SCR[7] are 0, which they are at reset 1752 and we never touch the SCR register */ 1753 uint8_t rx_fifo_trig = 40; 1754 uint8_t tx_fifo_trig = 60; 1755 uint8_t rx_start = 8; 1756 uint8_t rx_halt = 60; 1757 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1758 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1759 1760 /* enable access to TCR & TLR */ 1761 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1762 1763 /* write tcr and tlr values */ 1764 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1765 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1766 1767 /* disable access to TCR & TLR */ 1768 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1769 1770 /* enable again, but mode is based on speed */ 1771 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1772 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1773 } else { 1774 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1775 } 1776 } 1777 1778 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1779 } 1780 1781 int 1782 comhwiflow(struct tty *tp, int block) 1783 { 1784 struct com_softc *sc = 1785 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1786 1787 if (COM_ISALIVE(sc) == 0) 1788 return (0); 1789 1790 if (sc->sc_mcr_rts == 0) 1791 return (0); 1792 1793 mutex_spin_enter(&sc->sc_lock); 1794 1795 if (block) { 1796 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1797 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1798 com_hwiflow(sc); 1799 } 1800 } else { 1801 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1802 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1803 com_schedrx(sc); 1804 } 1805 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1806 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1807 com_hwiflow(sc); 1808 } 1809 } 1810 1811 mutex_spin_exit(&sc->sc_lock); 1812 return (1); 1813 } 1814 1815 /* 1816 * (un)block input via hw flowcontrol 1817 */ 1818 void 1819 com_hwiflow(struct com_softc *sc) 1820 { 1821 struct com_regs *regsp= &sc->sc_regs; 1822 1823 if (sc->sc_mcr_rts == 0) 1824 return; 1825 1826 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1827 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1828 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1829 } else { 1830 SET(sc->sc_mcr, sc->sc_mcr_rts); 1831 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1832 } 1833 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1834 } 1835 1836 1837 void 1838 comstart(struct tty *tp) 1839 { 1840 struct com_softc *sc = 1841 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1842 struct com_regs *regsp = &sc->sc_regs; 1843 int s; 1844 1845 if (COM_ISALIVE(sc) == 0) 1846 return; 1847 1848 s = spltty(); 1849 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1850 goto out; 1851 if (sc->sc_tx_stopped) 1852 goto out; 1853 if (!ttypull(tp)) 1854 goto out; 1855 1856 /* Grab the first contiguous region of buffer space. */ 1857 { 1858 u_char *tba; 1859 int tbc; 1860 1861 tba = tp->t_outq.c_cf; 1862 tbc = ndqb(&tp->t_outq, 0); 1863 1864 mutex_spin_enter(&sc->sc_lock); 1865 1866 sc->sc_tba = tba; 1867 sc->sc_tbc = tbc; 1868 } 1869 1870 SET(tp->t_state, TS_BUSY); 1871 sc->sc_tx_busy = 1; 1872 1873 /* Enable transmit completion interrupts if necessary. */ 1874 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1875 SET(sc->sc_ier, IER_ETXRDY); 1876 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1877 } 1878 1879 /* Output the first chunk of the contiguous buffer. */ 1880 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1881 u_int n; 1882 1883 n = sc->sc_tbc; 1884 if (n > sc->sc_fifolen) 1885 n = sc->sc_fifolen; 1886 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1887 sc->sc_tbc -= n; 1888 sc->sc_tba += n; 1889 } 1890 1891 mutex_spin_exit(&sc->sc_lock); 1892 out: 1893 splx(s); 1894 return; 1895 } 1896 1897 /* 1898 * Stop output on a line. 1899 */ 1900 void 1901 comstop(struct tty *tp, int flag) 1902 { 1903 struct com_softc *sc = 1904 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1905 1906 mutex_spin_enter(&sc->sc_lock); 1907 if (ISSET(tp->t_state, TS_BUSY)) { 1908 /* Stop transmitting at the next chunk. */ 1909 sc->sc_tbc = 0; 1910 sc->sc_heldtbc = 0; 1911 if (!ISSET(tp->t_state, TS_TTSTOP)) 1912 SET(tp->t_state, TS_FLUSH); 1913 } 1914 mutex_spin_exit(&sc->sc_lock); 1915 } 1916 1917 void 1918 comdiag(void *arg) 1919 { 1920 struct com_softc *sc = arg; 1921 int overflows, floods; 1922 1923 mutex_spin_enter(&sc->sc_lock); 1924 overflows = sc->sc_overflows; 1925 sc->sc_overflows = 0; 1926 floods = sc->sc_floods; 1927 sc->sc_floods = 0; 1928 sc->sc_errors = 0; 1929 mutex_spin_exit(&sc->sc_lock); 1930 1931 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1932 device_xname(sc->sc_dev), 1933 overflows, overflows == 1 ? "" : "s", 1934 floods, floods == 1 ? "" : "s"); 1935 } 1936 1937 integrate void 1938 com_rxsoft(struct com_softc *sc, struct tty *tp) 1939 { 1940 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1941 u_char *get, *end; 1942 u_int cc, scc; 1943 u_char lsr; 1944 int code; 1945 1946 end = sc->sc_ebuf; 1947 get = sc->sc_rbget; 1948 scc = cc = com_rbuf_size - sc->sc_rbavail; 1949 1950 if (cc == com_rbuf_size) { 1951 sc->sc_floods++; 1952 if (sc->sc_errors++ == 0) 1953 callout_reset(&sc->sc_diag_callout, 60 * hz, 1954 comdiag, sc); 1955 } 1956 1957 /* If not yet open, drop the entire buffer content here */ 1958 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1959 get += cc << 1; 1960 if (get >= end) 1961 get -= com_rbuf_size << 1; 1962 cc = 0; 1963 } 1964 while (cc) { 1965 code = get[0]; 1966 lsr = get[1]; 1967 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1968 if (ISSET(lsr, LSR_OE)) { 1969 sc->sc_overflows++; 1970 if (sc->sc_errors++ == 0) 1971 callout_reset(&sc->sc_diag_callout, 1972 60 * hz, comdiag, sc); 1973 } 1974 if (ISSET(lsr, LSR_BI | LSR_FE)) 1975 SET(code, TTY_FE); 1976 if (ISSET(lsr, LSR_PE)) 1977 SET(code, TTY_PE); 1978 } 1979 if ((*rint)(code, tp) == -1) { 1980 /* 1981 * The line discipline's buffer is out of space. 1982 */ 1983 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1984 /* 1985 * We're either not using flow control, or the 1986 * line discipline didn't tell us to block for 1987 * some reason. Either way, we have no way to 1988 * know when there's more space available, so 1989 * just drop the rest of the data. 1990 */ 1991 get += cc << 1; 1992 if (get >= end) 1993 get -= com_rbuf_size << 1; 1994 cc = 0; 1995 } else { 1996 /* 1997 * Don't schedule any more receive processing 1998 * until the line discipline tells us there's 1999 * space available (through comhwiflow()). 2000 * Leave the rest of the data in the input 2001 * buffer. 2002 */ 2003 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 2004 } 2005 break; 2006 } 2007 get += 2; 2008 if (get >= end) 2009 get = sc->sc_rbuf; 2010 cc--; 2011 } 2012 2013 if (cc != scc) { 2014 sc->sc_rbget = get; 2015 mutex_spin_enter(&sc->sc_lock); 2016 2017 cc = sc->sc_rbavail += scc - cc; 2018 /* Buffers should be ok again, release possible block. */ 2019 if (cc >= sc->sc_r_lowat) { 2020 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2021 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2022 SET(sc->sc_ier, IER_ERXRDY); 2023 if (sc->sc_type == COM_TYPE_PXA2x0) 2024 SET(sc->sc_ier, IER_ERXTOUT); 2025 if (sc->sc_type == COM_TYPE_INGENIC || 2026 sc->sc_type == COM_TYPE_TEGRA) 2027 SET(sc->sc_ier, IER_ERXTOUT); 2028 2029 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 2030 sc->sc_ier); 2031 } 2032 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 2033 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2034 com_hwiflow(sc); 2035 } 2036 } 2037 mutex_spin_exit(&sc->sc_lock); 2038 } 2039 } 2040 2041 integrate void 2042 com_txsoft(struct com_softc *sc, struct tty *tp) 2043 { 2044 2045 CLR(tp->t_state, TS_BUSY); 2046 if (ISSET(tp->t_state, TS_FLUSH)) 2047 CLR(tp->t_state, TS_FLUSH); 2048 else 2049 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2050 (*tp->t_linesw->l_start)(tp); 2051 } 2052 2053 integrate void 2054 com_stsoft(struct com_softc *sc, struct tty *tp) 2055 { 2056 u_char msr, delta; 2057 2058 mutex_spin_enter(&sc->sc_lock); 2059 msr = sc->sc_msr; 2060 delta = sc->sc_msr_delta; 2061 sc->sc_msr_delta = 0; 2062 mutex_spin_exit(&sc->sc_lock); 2063 2064 if (ISSET(delta, sc->sc_msr_dcd)) { 2065 /* 2066 * Inform the tty layer that carrier detect changed. 2067 */ 2068 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2069 } 2070 2071 if (ISSET(delta, sc->sc_msr_cts)) { 2072 /* Block or unblock output according to flow control. */ 2073 if (ISSET(msr, sc->sc_msr_cts)) { 2074 sc->sc_tx_stopped = 0; 2075 (*tp->t_linesw->l_start)(tp); 2076 } else { 2077 sc->sc_tx_stopped = 1; 2078 } 2079 } 2080 2081 #ifdef COM_DEBUG 2082 if (com_debug) 2083 comstatus(sc, "com_stsoft"); 2084 #endif 2085 } 2086 2087 void 2088 comsoft(void *arg) 2089 { 2090 struct com_softc *sc = arg; 2091 struct tty *tp; 2092 2093 if (COM_ISALIVE(sc) == 0) 2094 return; 2095 2096 tp = sc->sc_tty; 2097 2098 if (sc->sc_rx_ready) { 2099 sc->sc_rx_ready = 0; 2100 com_rxsoft(sc, tp); 2101 } 2102 2103 if (sc->sc_st_check) { 2104 sc->sc_st_check = 0; 2105 com_stsoft(sc, tp); 2106 } 2107 2108 if (sc->sc_tx_done) { 2109 sc->sc_tx_done = 0; 2110 com_txsoft(sc, tp); 2111 } 2112 } 2113 2114 int 2115 comintr(void *arg) 2116 { 2117 struct com_softc *sc = arg; 2118 struct com_regs *regsp = &sc->sc_regs; 2119 2120 u_char *put, *end; 2121 u_int cc; 2122 u_char lsr, iir; 2123 2124 if (COM_ISALIVE(sc) == 0) 2125 return (0); 2126 2127 KASSERT(regsp != NULL); 2128 2129 mutex_spin_enter(&sc->sc_lock); 2130 iir = CSR_READ_1(regsp, COM_REG_IIR); 2131 2132 /* Handle ns16750-specific busy interrupt. */ 2133 if (sc->sc_type == COM_TYPE_16750 && 2134 (iir & IIR_BUSY) == IIR_BUSY) { 2135 for (int timeout = 10000; 2136 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2137 if (timeout <= 0) { 2138 aprint_error_dev(sc->sc_dev, 2139 "timeout while waiting for BUSY interrupt " 2140 "acknowledge\n"); 2141 mutex_spin_exit(&sc->sc_lock); 2142 return (0); 2143 } 2144 2145 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2146 iir = CSR_READ_1(regsp, COM_REG_IIR); 2147 } 2148 2149 /* DesignWare APB UART BUSY interrupt */ 2150 if (sc->sc_type == COM_TYPE_DW_APB && 2151 (iir & IIR_BUSY) == IIR_BUSY) { 2152 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2153 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2154 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2155 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2156 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2157 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2158 CSR_WRITE_1(regsp, COM_REG_HALT, 2159 HALT_CHCFG_EN | HALT_CHCFG_UD); 2160 for (int timeout = 10000000; 2161 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2162 timeout--) { 2163 if (timeout <= 0) { 2164 aprint_error_dev(sc->sc_dev, 2165 "timeout while waiting for HALT " 2166 "update acknowledge 0x%x 0x%x\n", 2167 CSR_READ_1(regsp, COM_REG_HALT), 2168 CSR_READ_1(regsp, COM_REG_USR)); 2169 break; 2170 } 2171 } 2172 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2173 (void)CSR_READ_1(regsp, COM_REG_USR); 2174 } else { 2175 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2176 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2177 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2178 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2179 } 2180 } 2181 2182 end = sc->sc_ebuf; 2183 put = sc->sc_rbput; 2184 cc = sc->sc_rbavail; 2185 2186 if (ISSET(iir, IIR_NOPEND)) { 2187 if (ISSET(sc->sc_hwflags, COM_HW_BROKEN_ETXRDY)) 2188 goto do_tx; 2189 mutex_spin_exit(&sc->sc_lock); 2190 return (0); 2191 } 2192 2193 again: do { 2194 u_char msr, delta; 2195 2196 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2197 if (ISSET(lsr, LSR_BI)) { 2198 int cn_trapped = 0; /* see above: cn_trap() */ 2199 2200 cn_check_magic(sc->sc_tty->t_dev, 2201 CNC_BREAK, com_cnm_state); 2202 if (cn_trapped) 2203 continue; 2204 #if defined(KGDB) && !defined(DDB) 2205 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2206 kgdb_connect(1); 2207 continue; 2208 } 2209 #endif 2210 } 2211 2212 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2213 lsr |= LSR_RXRDY; 2214 2215 if (ISSET(lsr, LSR_RCV_MASK) && 2216 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2217 while (cc > 0) { 2218 int cn_trapped = 0; 2219 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2220 put[1] = lsr; 2221 cn_check_magic(sc->sc_tty->t_dev, 2222 put[0], com_cnm_state); 2223 if (cn_trapped) 2224 goto next; 2225 put += 2; 2226 if (put >= end) 2227 put = sc->sc_rbuf; 2228 cc--; 2229 next: 2230 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2231 if (!ISSET(lsr, LSR_RCV_MASK)) 2232 break; 2233 } 2234 2235 /* 2236 * Current string of incoming characters ended because 2237 * no more data was available or we ran out of space. 2238 * Schedule a receive event if any data was received. 2239 * If we're out of space, turn off receive interrupts. 2240 */ 2241 sc->sc_rbput = put; 2242 sc->sc_rbavail = cc; 2243 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2244 sc->sc_rx_ready = 1; 2245 2246 /* 2247 * See if we are in danger of overflowing a buffer. If 2248 * so, use hardware flow control to ease the pressure. 2249 */ 2250 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2251 cc < sc->sc_r_hiwat) { 2252 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2253 com_hwiflow(sc); 2254 } 2255 2256 /* 2257 * If we're out of space, disable receive interrupts 2258 * until the queue has drained a bit. 2259 */ 2260 if (!cc) { 2261 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2262 switch (sc->sc_type) { 2263 case COM_TYPE_PXA2x0: 2264 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2265 break; 2266 case COM_TYPE_INGENIC: 2267 case COM_TYPE_TEGRA: 2268 CLR(sc->sc_ier, 2269 IER_ERXRDY | IER_ERXTOUT); 2270 break; 2271 default: 2272 CLR(sc->sc_ier, IER_ERXRDY); 2273 break; 2274 } 2275 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2276 } 2277 } else { 2278 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2279 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2280 continue; 2281 } 2282 } 2283 2284 msr = CSR_READ_1(regsp, COM_REG_MSR); 2285 delta = msr ^ sc->sc_msr; 2286 sc->sc_msr = msr; 2287 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2288 (delta & MSR_DCD)) { 2289 mutex_spin_enter(&timecounter_lock); 2290 pps_capture(&sc->sc_pps_state); 2291 pps_event(&sc->sc_pps_state, 2292 (msr & MSR_DCD) ? 2293 PPS_CAPTUREASSERT : 2294 PPS_CAPTURECLEAR); 2295 mutex_spin_exit(&timecounter_lock); 2296 } 2297 2298 /* 2299 * Process normal status changes 2300 */ 2301 if (ISSET(delta, sc->sc_msr_mask)) { 2302 SET(sc->sc_msr_delta, delta); 2303 2304 /* 2305 * Stop output immediately if we lose the output 2306 * flow control signal or carrier detect. 2307 */ 2308 if (ISSET(~msr, sc->sc_msr_mask)) { 2309 sc->sc_tbc = 0; 2310 sc->sc_heldtbc = 0; 2311 #ifdef COM_DEBUG 2312 if (com_debug) 2313 comstatus(sc, "comintr "); 2314 #endif 2315 } 2316 2317 sc->sc_st_check = 1; 2318 } 2319 } while (!ISSET((iir = 2320 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2321 /* 2322 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2323 * by IIR read, so we can't do this way: `process all interrupts, 2324 * then do TX if possible'. 2325 */ 2326 (iir & IIR_IMASK) != IIR_TXRDY); 2327 2328 do_tx: 2329 /* 2330 * Read LSR again, since there may be an interrupt between 2331 * the last LSR read and IIR read above. 2332 */ 2333 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2334 2335 /* 2336 * See if data can be transmitted as well. 2337 * Schedule tx done event if no data left 2338 * and tty was marked busy. 2339 */ 2340 if (ISSET(lsr, LSR_TXRDY)) { 2341 /* 2342 * If we've delayed a parameter change, do it now, and restart 2343 * output. 2344 */ 2345 if (sc->sc_heldchange) { 2346 com_loadchannelregs(sc); 2347 sc->sc_heldchange = 0; 2348 sc->sc_tbc = sc->sc_heldtbc; 2349 sc->sc_heldtbc = 0; 2350 } 2351 2352 /* Output the next chunk of the contiguous buffer, if any. */ 2353 if (sc->sc_tbc > 0) { 2354 u_int n; 2355 2356 n = sc->sc_tbc; 2357 if (n > sc->sc_fifolen) 2358 n = sc->sc_fifolen; 2359 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2360 sc->sc_tbc -= n; 2361 sc->sc_tba += n; 2362 } else { 2363 /* Disable transmit completion interrupts if necessary. */ 2364 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2365 CLR(sc->sc_ier, IER_ETXRDY); 2366 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2367 } 2368 if (sc->sc_tx_busy) { 2369 sc->sc_tx_busy = 0; 2370 sc->sc_tx_done = 1; 2371 } 2372 } 2373 } 2374 2375 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2376 goto again; 2377 2378 mutex_spin_exit(&sc->sc_lock); 2379 2380 /* Wake up the poller. */ 2381 if ((sc->sc_rx_ready | sc->sc_st_check | sc->sc_tx_done) != 0) 2382 softint_schedule(sc->sc_si); 2383 2384 #ifdef RND_COM 2385 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2386 #endif 2387 2388 return (1); 2389 } 2390 2391 /* 2392 * The following functions are polled getc and putc routines, shared 2393 * by the console and kgdb glue. 2394 * 2395 * The read-ahead code is so that you can detect pending in-band 2396 * cn_magic in polled mode while doing output rather than having to 2397 * wait until the kernel decides it needs input. 2398 */ 2399 2400 #define MAX_READAHEAD 20 2401 static int com_readahead[MAX_READAHEAD]; 2402 static int com_readaheadcount = 0; 2403 2404 int 2405 com_common_getc(dev_t dev, struct com_regs *regsp) 2406 { 2407 int s = splserial(); 2408 u_char stat, c; 2409 2410 /* got a character from reading things earlier */ 2411 if (com_readaheadcount > 0) { 2412 int i; 2413 2414 c = com_readahead[0]; 2415 for (i = 1; i < com_readaheadcount; i++) { 2416 com_readahead[i-1] = com_readahead[i]; 2417 } 2418 com_readaheadcount--; 2419 splx(s); 2420 return (c); 2421 } 2422 2423 /* don't block until a character becomes available */ 2424 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2425 splx(s); 2426 return -1; 2427 } 2428 2429 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2430 stat = CSR_READ_1(regsp, COM_REG_IIR); 2431 { 2432 int cn_trapped = 0; /* required by cn_trap, see above */ 2433 #ifdef DDB 2434 extern int db_active; 2435 if (!db_active) 2436 #endif 2437 cn_check_magic(dev, c, com_cnm_state); 2438 } 2439 splx(s); 2440 return (c); 2441 } 2442 2443 static void 2444 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead) 2445 { 2446 int s = splserial(); 2447 int cin, stat, timo; 2448 2449 if (with_readahead && com_readaheadcount < MAX_READAHEAD 2450 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2451 int cn_trapped = 0; 2452 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2453 stat = CSR_READ_1(regsp, COM_REG_IIR); 2454 cn_check_magic(dev, cin, com_cnm_state); 2455 com_readahead[com_readaheadcount++] = cin; 2456 } 2457 2458 /* wait for any pending transmission to finish */ 2459 timo = 150000; 2460 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2461 continue; 2462 2463 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2464 COM_BARRIER(regsp, BR | BW); 2465 2466 splx(s); 2467 } 2468 2469 /* 2470 * Initialize UART for use as console or KGDB line. 2471 */ 2472 int 2473 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2474 tcflag_t cflag) 2475 { 2476 2477 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2478 ®sp->cr_ioh)) 2479 return (ENOMEM); /* ??? */ 2480 2481 if (type == COM_TYPE_OMAP) { 2482 /* disable before changing settings */ 2483 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2484 } 2485 2486 rate = comspeed(rate, frequency, type); 2487 if (rate != -1) { 2488 if (type == COM_TYPE_AU1x00) { 2489 /* no EFR on alchemy */ 2490 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2491 } else { 2492 if ((type != COM_TYPE_16550_NOERS) && 2493 (type != COM_TYPE_INGENIC)) { 2494 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2495 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2496 } 2497 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2498 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2499 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2500 } 2501 } 2502 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2503 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2504 2505 if (type == COM_TYPE_INGENIC) { 2506 CSR_WRITE_1(regsp, COM_REG_FIFO, 2507 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2508 FIFO_TRIGGER_1 | FIFO_UART_ON); 2509 } else { 2510 CSR_WRITE_1(regsp, COM_REG_FIFO, 2511 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2512 FIFO_TRIGGER_1); 2513 } 2514 2515 if (type == COM_TYPE_OMAP) { 2516 /* setup the fifos. the FCR value is not used as long 2517 as SCR[6] and SCR[7] are 0, which they are at reset 2518 and we never touch the SCR register */ 2519 uint8_t rx_fifo_trig = 40; 2520 uint8_t tx_fifo_trig = 60; 2521 uint8_t rx_start = 8; 2522 uint8_t rx_halt = 60; 2523 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2524 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2525 2526 /* enable access to TCR & TLR */ 2527 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2528 2529 /* write tcr and tlr values */ 2530 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2531 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2532 2533 /* disable access to TCR & TLR */ 2534 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2535 2536 /* enable again, but mode is based on speed */ 2537 if (rate > 230400) { 2538 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2539 } else { 2540 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2541 } 2542 } 2543 2544 if (type == COM_TYPE_PXA2x0) 2545 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2546 else 2547 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2548 2549 return (0); 2550 } 2551 2552 int 2553 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2554 tcflag_t cflag) 2555 { 2556 int res; 2557 2558 comcons_info.regs = *regsp; 2559 2560 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2561 if (res) 2562 return (res); 2563 2564 cn_tab = &comcons; 2565 cn_init_magic(&com_cnm_state); 2566 cn_set_magic("\047\001"); /* default magic is BREAK */ 2567 2568 comcons_info.frequency = frequency; 2569 comcons_info.type = type; 2570 comcons_info.rate = rate; 2571 comcons_info.cflag = cflag; 2572 2573 return (0); 2574 } 2575 2576 int 2577 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2578 int type, tcflag_t cflag) 2579 { 2580 struct com_regs regs; 2581 2582 /*XXX*/ 2583 bus_space_handle_t dummy_bsh; 2584 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2585 2586 /* 2587 * dummy_bsh required because com_init_regs() wants it. A 2588 * real bus_space_handle will be filled in by cominit() later. 2589 * XXXJRT Detangle this mess eventually, plz. 2590 */ 2591 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2592 2593 return comcnattach1(®s, rate, frequency, type, cflag); 2594 } 2595 2596 static int 2597 comcnreattach(void) 2598 { 2599 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2600 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2601 } 2602 2603 int 2604 comcngetc(dev_t dev) 2605 { 2606 2607 return (com_common_getc(dev, &comcons_info.regs)); 2608 } 2609 2610 /* 2611 * Console kernel output character routine. 2612 */ 2613 void 2614 comcnputc(dev_t dev, int c) 2615 { 2616 2617 com_common_putc(dev, &comcons_info.regs, c, cold); 2618 } 2619 2620 void 2621 comcnpollc(dev_t dev, int on) 2622 { 2623 2624 com_readaheadcount = 0; 2625 } 2626 2627 #ifdef KGDB 2628 int 2629 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2630 tcflag_t cflag) 2631 { 2632 int res; 2633 2634 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2635 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2636 #if !defined(DDB) 2637 return (EBUSY); /* cannot share with console */ 2638 #else 2639 comkgdbregs = *regsp; 2640 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2641 #endif 2642 } else { 2643 comkgdbregs = *regsp; 2644 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2645 if (res) 2646 return (res); 2647 2648 /* 2649 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2650 * expects this to be initialized 2651 */ 2652 cn_init_magic(&com_cnm_state); 2653 cn_set_magic("\047\001"); 2654 } 2655 2656 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2657 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2658 2659 return (0); 2660 } 2661 2662 int 2663 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2664 int frequency, int type, tcflag_t cflag) 2665 { 2666 struct com_regs regs; 2667 2668 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2669 2670 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2671 } 2672 2673 /* ARGSUSED */ 2674 int 2675 com_kgdb_getc(void *arg) 2676 { 2677 2678 return (com_common_getc(NODEV, &comkgdbregs)); 2679 } 2680 2681 /* ARGSUSED */ 2682 void 2683 com_kgdb_putc(void *arg, int c) 2684 { 2685 2686 com_common_putc(NODEV, &comkgdbregs, c, 0); 2687 } 2688 #endif /* KGDB */ 2689 2690 /* helper function to identify the com ports used by 2691 console or KGDB (and not yet autoconf attached) */ 2692 int 2693 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2694 { 2695 bus_space_handle_t help; 2696 2697 if (!comconsattached && 2698 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2699 iobase == comcons_info.regs.cr_iobase) 2700 help = comcons_info.regs.cr_ioh; 2701 #ifdef KGDB 2702 else if (!com_kgdb_attached && 2703 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2704 iobase == comkgdbregs.cr_iobase) 2705 help = comkgdbregs.cr_ioh; 2706 #endif 2707 else 2708 return (0); 2709 2710 if (ioh) 2711 *ioh = help; 2712 return (1); 2713 } 2714 2715 /* 2716 * this routine exists to serve as a shutdown hook for systems that 2717 * have firmware which doesn't interact properly with a com device in 2718 * FIFO mode. 2719 */ 2720 bool 2721 com_cleanup(device_t self, int how) 2722 { 2723 struct com_softc *sc = device_private(self); 2724 2725 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2726 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2727 2728 return true; 2729 } 2730 2731 bool 2732 com_suspend(device_t self, const pmf_qual_t *qual) 2733 { 2734 struct com_softc *sc = device_private(self); 2735 2736 #if 0 2737 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2738 cn_tab = &comcons_suspend; 2739 #endif 2740 2741 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2742 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2743 2744 return true; 2745 } 2746 2747 bool 2748 com_resume(device_t self, const pmf_qual_t *qual) 2749 { 2750 struct com_softc *sc = device_private(self); 2751 2752 mutex_spin_enter(&sc->sc_lock); 2753 com_loadchannelregs(sc); 2754 mutex_spin_exit(&sc->sc_lock); 2755 2756 return true; 2757 } 2758
Indexes created Mon Oct 20 20:10:13 GMT 2025