com.c revision 1.369
1 /* $NetBSD: com.c,v 1.369 2021/10/14 09:56:12 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.369 2021/10/14 09:56:12 jmcneill Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #define CSR_WRITE_1(r, o, v) \ 132 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 133 #define CSR_READ_1(r, o) \ 134 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 135 #define CSR_WRITE_2(r, o, v) \ 136 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 137 #define CSR_READ_2(r, o) \ 138 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 139 #define CSR_WRITE_MULTI(r, o, p, n) \ 140 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 141 142 143 static void com_enable_debugport(struct com_softc *); 144 145 void com_config(struct com_softc *); 146 void com_shutdown(struct com_softc *); 147 int comspeed(long, long, int); 148 static u_char cflag2lcr(tcflag_t); 149 int comparam(struct tty *, struct termios *); 150 void comstart(struct tty *); 151 int comhwiflow(struct tty *, int); 152 153 void com_loadchannelregs(struct com_softc *); 154 void com_hwiflow(struct com_softc *); 155 void com_break(struct com_softc *, int); 156 void com_modem(struct com_softc *, int); 157 void tiocm_to_com(struct com_softc *, u_long, int); 158 int com_to_tiocm(struct com_softc *); 159 void com_iflush(struct com_softc *); 160 161 int com_common_getc(dev_t, struct com_regs *); 162 static void com_common_putc(dev_t, struct com_regs *, int, int); 163 164 int cominit(struct com_regs *, int, int, int, tcflag_t); 165 166 static int comcnreattach(void); 167 168 int comcngetc(dev_t); 169 void comcnputc(dev_t, int); 170 void comcnpollc(dev_t, int); 171 172 #define integrate static inline 173 void comsoft(void *); 174 integrate void com_rxsoft(struct com_softc *, struct tty *); 175 integrate void com_txsoft(struct com_softc *, struct tty *); 176 integrate void com_stsoft(struct com_softc *, struct tty *); 177 integrate void com_schedrx(struct com_softc *); 178 void comdiag(void *); 179 180 dev_type_open(comopen); 181 dev_type_close(comclose); 182 dev_type_read(comread); 183 dev_type_write(comwrite); 184 dev_type_ioctl(comioctl); 185 dev_type_stop(comstop); 186 dev_type_tty(comtty); 187 dev_type_poll(compoll); 188 189 static struct comcons_info comcons_info; 190 191 /* 192 * Following are all routines needed for COM to act as console 193 */ 194 static struct consdev comcons = { 195 .cn_getc = comcngetc, 196 .cn_putc = comcnputc, 197 .cn_pollc = comcnpollc, 198 .cn_dev = NODEV, 199 .cn_pri = CN_NORMAL 200 }; 201 202 203 const struct cdevsw com_cdevsw = { 204 .d_open = comopen, 205 .d_close = comclose, 206 .d_read = comread, 207 .d_write = comwrite, 208 .d_ioctl = comioctl, 209 .d_stop = comstop, 210 .d_tty = comtty, 211 .d_poll = compoll, 212 .d_mmap = nommap, 213 .d_kqfilter = ttykqfilter, 214 .d_discard = nodiscard, 215 .d_flag = D_TTY 216 }; 217 218 /* 219 * Make this an option variable one can patch. 220 * But be warned: this must be a power of 2! 221 */ 222 u_int com_rbuf_size = COM_RING_SIZE; 223 224 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 225 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 226 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 227 228 static int comconsattached; 229 static struct cnm_state com_cnm_state; 230 231 #ifdef KGDB 232 #include <sys/kgdb.h> 233 234 static struct com_regs comkgdbregs; 235 static int com_kgdb_attached; 236 237 int com_kgdb_getc(void *); 238 void com_kgdb_putc(void *, int); 239 #endif /* KGDB */ 240 241 /* initializer for typical 16550-ish hardware */ 242 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 243 [COM_REG_RXDATA] = com_data, 244 [COM_REG_TXDATA] = com_data, 245 [COM_REG_DLBL] = com_dlbl, 246 [COM_REG_DLBH] = com_dlbh, 247 [COM_REG_IER] = com_ier, 248 [COM_REG_IIR] = com_iir, 249 [COM_REG_FIFO] = com_fifo, 250 [COM_REG_TCR] = com_fifo, 251 [COM_REG_EFR] = com_efr, 252 [COM_REG_TLR] = com_efr, 253 [COM_REG_LCR] = com_lcr, 254 [COM_REG_MCR] = com_mcr, 255 [COM_REG_LSR] = com_lsr, 256 [COM_REG_MSR] = com_msr, 257 [COM_REG_USR] = com_usr, 258 [COM_REG_TFL] = com_tfl, 259 [COM_REG_RFL] = com_rfl, 260 [COM_REG_HALT] = com_halt, 261 [COM_REG_MDR1] = com_mdr1, 262 }; 263 264 #define COMDIALOUT_MASK TTDIALOUT_MASK 265 266 #define COMUNIT(x) TTUNIT(x) 267 #define COMDIALOUT(x) TTDIALOUT(x) 268 269 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 270 device_is_active((sc)->sc_dev)) 271 272 #define BR BUS_SPACE_BARRIER_READ 273 #define BW BUS_SPACE_BARRIER_WRITE 274 #define COM_BARRIER(r, f) \ 275 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 276 277 /* 278 * com_init_regs -- 279 * Driver front-ends use this to initialize our register map 280 * in the standard fashion. They may then tailor the map to 281 * their own particular requirements. 282 */ 283 void 284 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 285 bus_addr_t addr) 286 { 287 288 memset(regs, 0, sizeof(*regs)); 289 regs->cr_iot = st; 290 regs->cr_ioh = sh; 291 regs->cr_iobase = addr; 292 regs->cr_nports = COM_NPORTS; 293 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 294 } 295 296 /* 297 * com_init_regs_stride -- 298 * Convenience function for front-ends that have a stride between 299 * registers. 300 */ 301 void 302 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 303 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 304 { 305 306 com_init_regs(regs, st, sh, addr); 307 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 308 regs->cr_map[i] <<= regshift; 309 } 310 regs->cr_nports <<= regshift; 311 } 312 313 /*ARGSUSED*/ 314 int 315 comspeed(long speed, long frequency, int type) 316 { 317 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 318 319 int x, err; 320 int divisor = 16; 321 322 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 323 divisor = 13; 324 } 325 326 if (speed == 0) 327 return (0); 328 if (speed < 0) 329 return (-1); 330 x = divrnd(frequency / divisor, speed); 331 if (x <= 0) 332 return (-1); 333 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 334 if (err < 0) 335 err = -err; 336 if (err > COM_TOLERANCE) 337 return (-1); 338 return (x); 339 340 #undef divrnd 341 } 342 343 #ifdef COM_DEBUG 344 int com_debug = 0; 345 346 void comstatus(struct com_softc *, const char *); 347 void 348 comstatus(struct com_softc *sc, const char *str) 349 { 350 struct tty *tp = sc->sc_tty; 351 352 aprint_normal_dev(sc->sc_dev, 353 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 354 str, 355 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 356 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 357 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 358 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 359 sc->sc_tx_stopped ? '+' : '-'); 360 361 aprint_normal_dev(sc->sc_dev, 362 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 363 str, 364 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 365 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 366 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 367 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 368 sc->sc_rx_flags); 369 } 370 #endif 371 372 int 373 com_probe_subr(struct com_regs *regs) 374 { 375 376 /* force access to id reg */ 377 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 378 CSR_WRITE_1(regs, COM_REG_IIR, 0); 379 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 380 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 381 return (0); 382 383 return (1); 384 } 385 386 int 387 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 388 { 389 struct com_regs regs; 390 391 com_init_regs(®s, iot, ioh, 0/*XXX*/); 392 393 return com_probe_subr(®s); 394 } 395 396 /* 397 * No locking in this routine; it is only called during attach, 398 * or with the port already locked. 399 */ 400 static void 401 com_enable_debugport(struct com_softc *sc) 402 { 403 404 /* Turn on line break interrupt, set carrier. */ 405 sc->sc_ier = IER_ERLS; 406 if (sc->sc_type == COM_TYPE_PXA2x0) 407 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 408 if (sc->sc_type == COM_TYPE_INGENIC || 409 sc->sc_type == COM_TYPE_TEGRA) 410 sc->sc_ier |= IER_ERXTOUT; 411 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 412 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 413 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 414 } 415 416 static void 417 com_intr_poll(void *arg) 418 { 419 struct com_softc * const sc = arg; 420 421 comintr(sc); 422 423 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 424 } 425 426 void 427 com_attach_subr(struct com_softc *sc) 428 { 429 struct com_regs *regsp = &sc->sc_regs; 430 struct tty *tp; 431 uint32_t cpr; 432 uint8_t lcr; 433 const char *fifo_msg = NULL; 434 prop_dictionary_t dict; 435 bool is_console = true; 436 bool force_console = false; 437 438 aprint_naive("\n"); 439 440 dict = device_properties(sc->sc_dev); 441 prop_dictionary_get_bool(dict, "is_console", &is_console); 442 prop_dictionary_get_bool(dict, "force_console", &force_console); 443 callout_init(&sc->sc_diag_callout, 0); 444 callout_init(&sc->sc_poll_callout, 0); 445 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 446 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 447 448 #if defined(COM_16650) 449 sc->sc_type = COM_TYPE_16650; 450 #elif defined(COM_16750) 451 sc->sc_type = COM_TYPE_16750; 452 #elif defined(COM_HAYESP) 453 sc->sc_type = COM_TYPE_HAYESP; 454 #elif defined(COM_PXA2X0) 455 sc->sc_type = COM_TYPE_PXA2x0; 456 #endif 457 458 /* Disable interrupts before configuring the device. */ 459 if (sc->sc_type == COM_TYPE_PXA2x0) 460 sc->sc_ier = IER_EUART; 461 else 462 sc->sc_ier = 0; 463 464 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 465 466 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 467 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 468 comconsattached = 1; 469 470 if (force_console) 471 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 472 473 if (cn_tab == NULL && comcnreattach() != 0) { 474 printf("can't re-init serial console @%lx\n", 475 (u_long)comcons_info.regs.cr_iobase); 476 } 477 478 switch (sc->sc_type) { 479 case COM_TYPE_16750: 480 case COM_TYPE_DW_APB: 481 /* Use in comintr(). */ 482 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 483 break; 484 } 485 486 /* Make sure the console is always "hardwired". */ 487 delay(10000); /* wait for output to finish */ 488 if (is_console) { 489 SET(sc->sc_hwflags, COM_HW_CONSOLE); 490 } 491 492 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 493 } 494 495 /* Probe for FIFO */ 496 switch (sc->sc_type) { 497 case COM_TYPE_HAYESP: 498 goto fifodone; 499 500 case COM_TYPE_AU1x00: 501 sc->sc_fifolen = 16; 502 fifo_msg = "Au1X00 UART"; 503 SET(sc->sc_hwflags, COM_HW_FIFO); 504 goto fifodelay; 505 506 case COM_TYPE_16550_NOERS: 507 sc->sc_fifolen = 16; 508 fifo_msg = "ns16650, no ERS"; 509 SET(sc->sc_hwflags, COM_HW_FIFO); 510 goto fifodelay; 511 512 case COM_TYPE_OMAP: 513 sc->sc_fifolen = 64; 514 fifo_msg = "OMAP UART"; 515 SET(sc->sc_hwflags, COM_HW_FIFO); 516 goto fifodelay; 517 518 case COM_TYPE_INGENIC: 519 sc->sc_fifolen = 16; 520 fifo_msg = "Ingenic UART"; 521 SET(sc->sc_hwflags, COM_HW_FIFO); 522 SET(sc->sc_hwflags, COM_HW_NOIEN); 523 goto fifodelay; 524 525 case COM_TYPE_TEGRA: 526 sc->sc_fifolen = 8; 527 fifo_msg = "Tegra UART"; 528 SET(sc->sc_hwflags, COM_HW_FIFO); 529 CSR_WRITE_1(regsp, COM_REG_FIFO, 530 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 531 goto fifodelay; 532 533 case COM_TYPE_BCMAUXUART: 534 sc->sc_fifolen = 1; 535 fifo_msg = "BCM AUX UART"; 536 SET(sc->sc_hwflags, COM_HW_FIFO); 537 CSR_WRITE_1(regsp, COM_REG_FIFO, 538 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 539 goto fifodelay; 540 541 case COM_TYPE_DW_APB: 542 if (!prop_dictionary_get_uint(dict, "fifolen", &sc->sc_fifolen)) { 543 cpr = bus_space_read_4(sc->sc_regs.cr_iot, 544 sc->sc_regs.cr_ioh, DW_APB_UART_CPR); 545 sc->sc_fifolen = __SHIFTOUT(cpr, UART_CPR_FIFO_MODE) * 16; 546 } 547 if (sc->sc_fifolen == 0) { 548 sc->sc_fifolen = 1; 549 fifo_msg = "DesignWare APB UART, no fifo"; 550 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 551 } else { 552 fifo_msg = "DesignWare APB UART"; 553 SET(sc->sc_hwflags, COM_HW_FIFO); 554 CSR_WRITE_1(regsp, COM_REG_FIFO, 555 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 556 } 557 goto fifodelay; 558 } 559 560 sc->sc_fifolen = 1; 561 /* look for a NS 16550AF UART with FIFOs */ 562 if (sc->sc_type == COM_TYPE_INGENIC) { 563 CSR_WRITE_1(regsp, COM_REG_FIFO, 564 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 565 FIFO_TRIGGER_14 | FIFO_UART_ON); 566 } else 567 CSR_WRITE_1(regsp, COM_REG_FIFO, 568 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 569 delay(100); 570 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 571 == IIR_FIFO_MASK) 572 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 573 == FIFO_TRIGGER_14) { 574 SET(sc->sc_hwflags, COM_HW_FIFO); 575 576 fifo_msg = "ns16550a"; 577 578 /* 579 * IIR changes into the EFR if LCR is set to LCR_EERS 580 * on 16650s. We also know IIR != 0 at this point. 581 * Write 0 into the EFR, and read it. If the result 582 * is 0, we have a 16650. 583 * 584 * Older 16650s were broken; the test to detect them 585 * is taken from the Linux driver. Apparently 586 * setting DLAB enable gives access to the EFR on 587 * these chips. 588 */ 589 if (sc->sc_type == COM_TYPE_16650) { 590 lcr = CSR_READ_1(regsp, COM_REG_LCR); 591 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 592 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 593 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 594 CSR_WRITE_1(regsp, COM_REG_LCR, 595 lcr | LCR_DLAB); 596 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 597 CLR(sc->sc_hwflags, COM_HW_FIFO); 598 sc->sc_fifolen = 0; 599 } else { 600 SET(sc->sc_hwflags, COM_HW_FLOW); 601 sc->sc_fifolen = 32; 602 } 603 } else 604 sc->sc_fifolen = 16; 605 606 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 607 if (sc->sc_fifolen == 0) 608 fifo_msg = "st16650, broken fifo"; 609 else if (sc->sc_fifolen == 32) 610 fifo_msg = "st16650a"; 611 else 612 fifo_msg = "ns16550a"; 613 } 614 615 /* 616 * TL16C750 can enable 64byte FIFO, only when DLAB 617 * is 1. However, some 16750 may always enable. For 618 * example, restrictions according to DLAB in a data 619 * sheet for SC16C750 were not described. 620 * Please enable 'options COM_16650', supposing you 621 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 622 * should become effective. 623 */ 624 if (sc->sc_type == COM_TYPE_16750) { 625 uint8_t iir1, iir2; 626 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 627 628 lcr = CSR_READ_1(regsp, COM_REG_LCR); 629 CSR_WRITE_1(regsp, COM_REG_LCR, 630 lcr & ~LCR_DLAB); 631 CSR_WRITE_1(regsp, COM_REG_FIFO, 632 fcr | FIFO_64B_ENABLE); 633 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 634 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 635 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 636 CSR_WRITE_1(regsp, COM_REG_FIFO, 637 fcr | FIFO_64B_ENABLE); 638 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 639 640 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 641 642 if (!ISSET(iir1, IIR_64B_FIFO) && 643 ISSET(iir2, IIR_64B_FIFO)) { 644 /* It is TL16C750. */ 645 sc->sc_fifolen = 64; 646 SET(sc->sc_hwflags, COM_HW_AFE); 647 } else 648 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 649 650 if (sc->sc_fifolen == 64) 651 fifo_msg = "tl16c750"; 652 else 653 fifo_msg = "ns16750"; 654 } 655 } else 656 fifo_msg = "ns16550, broken fifo"; 657 else 658 fifo_msg = "ns8250 or ns16450, no fifo"; 659 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 660 661 fifodelay: 662 /* 663 * Some chips will clear down both Tx and Rx FIFOs when zero is 664 * written to com_fifo. If this chip is the console, writing zero 665 * results in some of the chip/FIFO description being lost, so delay 666 * printing it until now. 667 */ 668 delay(10); 669 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 670 aprint_normal(": %s, %d-byte FIFO\n", fifo_msg, sc->sc_fifolen); 671 } else { 672 aprint_normal(": %s\n", fifo_msg); 673 } 674 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 675 sc->sc_fifolen = 1; 676 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 677 } 678 679 fifodone: 680 681 tp = tty_alloc(); 682 tp->t_oproc = comstart; 683 tp->t_param = comparam; 684 tp->t_hwiflow = comhwiflow; 685 tp->t_softc = sc; 686 687 sc->sc_tty = tp; 688 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK); 689 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 690 sc->sc_rbavail = com_rbuf_size; 691 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 692 693 tty_attach(tp); 694 695 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 696 SET(sc->sc_mcr, MCR_IENABLE); 697 698 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 699 int maj; 700 701 /* locate the major number */ 702 maj = cdevsw_lookup_major(&com_cdevsw); 703 704 tp->t_dev = cn_tab->cn_dev = makedev(maj, 705 device_unit(sc->sc_dev)); 706 707 aprint_normal_dev(sc->sc_dev, "console\n"); 708 } 709 710 #ifdef KGDB 711 /* 712 * Allow kgdb to "take over" this port. If this is 713 * not the console and is the kgdb device, it has 714 * exclusive use. If it's the console _and_ the 715 * kgdb device, it doesn't. 716 */ 717 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 718 regsp->cr_iobase == comkgdbregs.cr_iobase) { 719 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 720 com_kgdb_attached = 1; 721 722 SET(sc->sc_hwflags, COM_HW_KGDB); 723 } 724 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 725 } 726 #endif 727 728 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 729 730 #ifdef RND_COM 731 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 732 RND_TYPE_TTY, RND_FLAG_DEFAULT); 733 #endif 734 735 /* if there are no enable/disable functions, assume the device 736 is always enabled */ 737 if (!sc->enable) 738 sc->enabled = 1; 739 740 com_config(sc); 741 742 SET(sc->sc_hwflags, COM_HW_DEV_OK); 743 744 if (sc->sc_poll_ticks != 0) 745 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 746 } 747 748 void 749 com_config(struct com_softc *sc) 750 { 751 struct com_regs *regsp = &sc->sc_regs; 752 753 /* Disable interrupts before configuring the device. */ 754 if (sc->sc_type == COM_TYPE_PXA2x0) 755 sc->sc_ier = IER_EUART; 756 else 757 sc->sc_ier = 0; 758 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 759 (void) CSR_READ_1(regsp, COM_REG_IIR); 760 761 /* Look for a Hayes ESP board. */ 762 if (sc->sc_type == COM_TYPE_HAYESP) { 763 764 /* Set 16550 compatibility mode */ 765 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 766 HAYESP_SETMODE); 767 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 768 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 769 HAYESP_MODE_SCALE); 770 771 /* Set RTS/CTS flow control */ 772 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 773 HAYESP_SETFLOWTYPE); 774 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 775 HAYESP_FLOW_RTS); 776 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 777 HAYESP_FLOW_CTS); 778 779 /* Set flow control levels */ 780 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 781 HAYESP_SETRXFLOW); 782 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 783 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 784 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 785 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 786 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 787 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 788 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 789 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 790 } 791 792 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 793 com_enable_debugport(sc); 794 } 795 796 #if 0 797 static int 798 comcngetc_detached(dev_t dev) 799 { 800 return 0; 801 } 802 803 static void 804 comcnputc_detached(dev_t dev, int c) 805 { 806 } 807 #endif 808 809 int 810 com_detach(device_t self, int flags) 811 { 812 struct com_softc *sc = device_private(self); 813 int maj, mn; 814 815 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 816 return EBUSY; 817 818 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 819 (flags & DETACH_SHUTDOWN) != 0) 820 return EBUSY; 821 822 if (sc->disable != NULL && sc->enabled != 0) { 823 (*sc->disable)(sc); 824 sc->enabled = 0; 825 } 826 827 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 828 comconsattached = 0; 829 cn_tab = NULL; 830 } 831 832 /* locate the major number */ 833 maj = cdevsw_lookup_major(&com_cdevsw); 834 835 /* Nuke the vnodes for any open instances. */ 836 mn = device_unit(self); 837 vdevgone(maj, mn, mn, VCHR); 838 839 mn |= COMDIALOUT_MASK; 840 vdevgone(maj, mn, mn, VCHR); 841 842 if (sc->sc_rbuf == NULL) { 843 /* 844 * Ring buffer allocation failed in the com_attach_subr, 845 * only the tty is allocated, and nothing else. 846 */ 847 tty_free(sc->sc_tty); 848 return 0; 849 } 850 851 /* Free the receive buffer. */ 852 free(sc->sc_rbuf, M_DEVBUF); 853 854 /* Detach and free the tty. */ 855 tty_detach(sc->sc_tty); 856 tty_free(sc->sc_tty); 857 858 /* Unhook the soft interrupt handler. */ 859 softint_disestablish(sc->sc_si); 860 861 #ifdef RND_COM 862 /* Unhook the entropy source. */ 863 rnd_detach_source(&sc->rnd_source); 864 #endif 865 callout_destroy(&sc->sc_diag_callout); 866 867 /* Destroy the lock. */ 868 mutex_destroy(&sc->sc_lock); 869 870 return (0); 871 } 872 873 void 874 com_shutdown(struct com_softc *sc) 875 { 876 struct tty *tp = sc->sc_tty; 877 878 mutex_spin_enter(&sc->sc_lock); 879 880 /* If we were asserting flow control, then deassert it. */ 881 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 882 com_hwiflow(sc); 883 884 /* Clear any break condition set with TIOCSBRK. */ 885 com_break(sc, 0); 886 887 /* 888 * Hang up if necessary. Wait a bit, so the other side has time to 889 * notice even if we immediately open the port again. 890 * Avoid tsleeping above splhigh(). 891 */ 892 if (ISSET(tp->t_cflag, HUPCL)) { 893 com_modem(sc, 0); 894 microtime(&sc->sc_hup_pending); 895 sc->sc_hup_pending.tv_sec++; 896 } 897 898 /* Turn off interrupts. */ 899 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 900 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 901 if ((sc->sc_type == COM_TYPE_PXA2x0) || 902 (sc->sc_type == COM_TYPE_INGENIC) || 903 (sc->sc_type == COM_TYPE_TEGRA)) 904 sc->sc_ier |= IER_ERXTOUT; 905 } else 906 sc->sc_ier = 0; 907 908 if (sc->sc_type == COM_TYPE_PXA2x0) 909 sc->sc_ier |= IER_EUART; 910 911 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 912 913 mutex_spin_exit(&sc->sc_lock); 914 915 if (sc->disable) { 916 #ifdef DIAGNOSTIC 917 if (!sc->enabled) 918 panic("com_shutdown: not enabled?"); 919 #endif 920 (*sc->disable)(sc); 921 sc->enabled = 0; 922 } 923 } 924 925 int 926 comopen(dev_t dev, int flag, int mode, struct lwp *l) 927 { 928 struct com_softc *sc; 929 struct tty *tp; 930 int s; 931 int error; 932 933 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 934 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 935 sc->sc_rbuf == NULL) 936 return (ENXIO); 937 938 if (!device_is_active(sc->sc_dev)) 939 return (ENXIO); 940 941 #ifdef KGDB 942 /* 943 * If this is the kgdb port, no other use is permitted. 944 */ 945 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 946 return (EBUSY); 947 #endif 948 949 tp = sc->sc_tty; 950 951 /* 952 * If the device is exclusively for kernel use, deny userland 953 * open. 954 */ 955 if (ISSET(tp->t_state, TS_KERN_ONLY)) 956 return (EBUSY); 957 958 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 959 return (EBUSY); 960 961 s = spltty(); 962 963 /* 964 * Do the following iff this is a first open. 965 */ 966 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 967 struct termios t; 968 struct timeval now, diff; 969 970 tp->t_dev = dev; 971 972 if (sc->enable) { 973 if ((*sc->enable)(sc)) { 974 splx(s); 975 aprint_error_dev(sc->sc_dev, 976 "device enable failed\n"); 977 return (EIO); 978 } 979 mutex_spin_enter(&sc->sc_lock); 980 sc->enabled = 1; 981 com_config(sc); 982 } else { 983 mutex_spin_enter(&sc->sc_lock); 984 } 985 986 if (timerisset(&sc->sc_hup_pending)) { 987 microtime(&now); 988 while (timercmp(&now, &sc->sc_hup_pending, <)) { 989 timersub(&sc->sc_hup_pending, &now, &diff); 990 const int ms = diff.tv_sec * 1000 + 991 uimax(diff.tv_usec / 1000, 1); 992 kpause(ttclos, false, mstohz(ms), 993 &sc->sc_lock); 994 microtime(&now); 995 } 996 timerclear(&sc->sc_hup_pending); 997 } 998 999 /* Turn on interrupts. */ 1000 sc->sc_ier = IER_ERXRDY | IER_ERLS; 1001 if (!ISSET(tp->t_cflag, CLOCAL)) 1002 sc->sc_ier |= IER_EMSC; 1003 1004 if (sc->sc_type == COM_TYPE_PXA2x0) 1005 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 1006 else if (sc->sc_type == COM_TYPE_INGENIC || 1007 sc->sc_type == COM_TYPE_TEGRA) 1008 sc->sc_ier |= IER_ERXTOUT; 1009 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1010 1011 /* Fetch the current modem control status, needed later. */ 1012 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 1013 1014 /* Clear PPS capture state on first open. */ 1015 mutex_spin_enter(&timecounter_lock); 1016 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 1017 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1018 pps_init(&sc->sc_pps_state); 1019 mutex_spin_exit(&timecounter_lock); 1020 1021 mutex_spin_exit(&sc->sc_lock); 1022 1023 /* 1024 * Initialize the termios status to the defaults. Add in the 1025 * sticky bits from TIOCSFLAGS. 1026 */ 1027 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1028 t.c_ospeed = comcons_info.rate; 1029 t.c_cflag = comcons_info.cflag; 1030 } else { 1031 t.c_ospeed = TTYDEF_SPEED; 1032 t.c_cflag = TTYDEF_CFLAG; 1033 } 1034 t.c_ispeed = t.c_ospeed; 1035 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1036 SET(t.c_cflag, CLOCAL); 1037 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1038 SET(t.c_cflag, CRTSCTS); 1039 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1040 SET(t.c_cflag, MDMBUF); 1041 /* Make sure comparam() will do something. */ 1042 tp->t_ospeed = 0; 1043 (void) comparam(tp, &t); 1044 tp->t_iflag = TTYDEF_IFLAG; 1045 tp->t_oflag = TTYDEF_OFLAG; 1046 tp->t_lflag = TTYDEF_LFLAG; 1047 ttychars(tp); 1048 ttsetwater(tp); 1049 1050 mutex_spin_enter(&sc->sc_lock); 1051 1052 /* 1053 * Turn on DTR. We must always do this, even if carrier is not 1054 * present, because otherwise we'd have to use TIOCSDTR 1055 * immediately after setting CLOCAL, which applications do not 1056 * expect. We always assert DTR while the device is open 1057 * unless explicitly requested to deassert it. 1058 */ 1059 com_modem(sc, 1); 1060 1061 /* Clear the input ring, and unblock. */ 1062 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1063 sc->sc_rbavail = com_rbuf_size; 1064 com_iflush(sc); 1065 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1066 com_hwiflow(sc); 1067 1068 #ifdef COM_DEBUG 1069 if (com_debug) 1070 comstatus(sc, "comopen "); 1071 #endif 1072 1073 mutex_spin_exit(&sc->sc_lock); 1074 } 1075 1076 splx(s); 1077 1078 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1079 if (error) 1080 goto bad; 1081 1082 error = (*tp->t_linesw->l_open)(dev, tp); 1083 if (error) 1084 goto bad; 1085 1086 return (0); 1087 1088 bad: 1089 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1090 /* 1091 * We failed to open the device, and nobody else had it opened. 1092 * Clean up the state as appropriate. 1093 */ 1094 com_shutdown(sc); 1095 } 1096 1097 return (error); 1098 } 1099 1100 int 1101 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1102 { 1103 struct com_softc *sc = 1104 device_lookup_private(&com_cd, COMUNIT(dev)); 1105 struct tty *tp = sc->sc_tty; 1106 1107 /* XXX This is for cons.c. */ 1108 if (!ISSET(tp->t_state, TS_ISOPEN)) 1109 return (0); 1110 /* 1111 * If the device is exclusively for kernel use, deny userland 1112 * close. 1113 */ 1114 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1115 return (0); 1116 1117 (*tp->t_linesw->l_close)(tp, flag); 1118 ttyclose(tp); 1119 1120 if (COM_ISALIVE(sc) == 0) 1121 return (0); 1122 1123 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1124 /* 1125 * Although we got a last close, the device may still be in 1126 * use; e.g. if this was the dialout node, and there are still 1127 * processes waiting for carrier on the non-dialout node. 1128 */ 1129 com_shutdown(sc); 1130 } 1131 1132 return (0); 1133 } 1134 1135 int 1136 comread(dev_t dev, struct uio *uio, int flag) 1137 { 1138 struct com_softc *sc = 1139 device_lookup_private(&com_cd, COMUNIT(dev)); 1140 struct tty *tp = sc->sc_tty; 1141 1142 if (COM_ISALIVE(sc) == 0) 1143 return (EIO); 1144 1145 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1146 } 1147 1148 int 1149 comwrite(dev_t dev, struct uio *uio, int flag) 1150 { 1151 struct com_softc *sc = 1152 device_lookup_private(&com_cd, COMUNIT(dev)); 1153 struct tty *tp = sc->sc_tty; 1154 1155 if (COM_ISALIVE(sc) == 0) 1156 return (EIO); 1157 1158 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1159 } 1160 1161 int 1162 compoll(dev_t dev, int events, struct lwp *l) 1163 { 1164 struct com_softc *sc = 1165 device_lookup_private(&com_cd, COMUNIT(dev)); 1166 struct tty *tp = sc->sc_tty; 1167 1168 if (COM_ISALIVE(sc) == 0) 1169 return (POLLHUP); 1170 1171 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1172 } 1173 1174 struct tty * 1175 comtty(dev_t dev) 1176 { 1177 struct com_softc *sc = 1178 device_lookup_private(&com_cd, COMUNIT(dev)); 1179 struct tty *tp = sc->sc_tty; 1180 1181 return (tp); 1182 } 1183 1184 int 1185 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1186 { 1187 struct com_softc *sc; 1188 struct tty *tp; 1189 int error; 1190 1191 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1192 if (sc == NULL) 1193 return ENXIO; 1194 if (COM_ISALIVE(sc) == 0) 1195 return (EIO); 1196 1197 tp = sc->sc_tty; 1198 1199 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1200 if (error != EPASSTHROUGH) 1201 return (error); 1202 1203 error = ttioctl(tp, cmd, data, flag, l); 1204 if (error != EPASSTHROUGH) 1205 return (error); 1206 1207 error = 0; 1208 switch (cmd) { 1209 case TIOCSFLAGS: 1210 error = kauth_authorize_device_tty(l->l_cred, 1211 KAUTH_DEVICE_TTY_PRIVSET, tp); 1212 break; 1213 default: 1214 /* nothing */ 1215 break; 1216 } 1217 if (error) { 1218 return error; 1219 } 1220 1221 mutex_spin_enter(&sc->sc_lock); 1222 1223 switch (cmd) { 1224 case TIOCSBRK: 1225 com_break(sc, 1); 1226 break; 1227 1228 case TIOCCBRK: 1229 com_break(sc, 0); 1230 break; 1231 1232 case TIOCSDTR: 1233 com_modem(sc, 1); 1234 break; 1235 1236 case TIOCCDTR: 1237 com_modem(sc, 0); 1238 break; 1239 1240 case TIOCGFLAGS: 1241 *(int *)data = sc->sc_swflags; 1242 break; 1243 1244 case TIOCSFLAGS: 1245 sc->sc_swflags = *(int *)data; 1246 break; 1247 1248 case TIOCMSET: 1249 case TIOCMBIS: 1250 case TIOCMBIC: 1251 tiocm_to_com(sc, cmd, *(int *)data); 1252 break; 1253 1254 case TIOCMGET: 1255 *(int *)data = com_to_tiocm(sc); 1256 break; 1257 1258 case PPS_IOC_CREATE: 1259 case PPS_IOC_DESTROY: 1260 case PPS_IOC_GETPARAMS: 1261 case PPS_IOC_SETPARAMS: 1262 case PPS_IOC_GETCAP: 1263 case PPS_IOC_FETCH: 1264 #ifdef PPS_SYNC 1265 case PPS_IOC_KCBIND: 1266 #endif 1267 mutex_spin_enter(&timecounter_lock); 1268 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1269 mutex_spin_exit(&timecounter_lock); 1270 break; 1271 1272 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1273 mutex_spin_enter(&timecounter_lock); 1274 #ifndef PPS_TRAILING_EDGE 1275 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1276 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1277 #else 1278 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1279 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1280 #endif 1281 mutex_spin_exit(&timecounter_lock); 1282 break; 1283 1284 default: 1285 error = EPASSTHROUGH; 1286 break; 1287 } 1288 1289 mutex_spin_exit(&sc->sc_lock); 1290 1291 #ifdef COM_DEBUG 1292 if (com_debug) 1293 comstatus(sc, "comioctl "); 1294 #endif 1295 1296 return (error); 1297 } 1298 1299 integrate void 1300 com_schedrx(struct com_softc *sc) 1301 { 1302 1303 sc->sc_rx_ready = 1; 1304 1305 /* Wake up the poller. */ 1306 softint_schedule(sc->sc_si); 1307 } 1308 1309 void 1310 com_break(struct com_softc *sc, int onoff) 1311 { 1312 1313 if (onoff) 1314 SET(sc->sc_lcr, LCR_SBREAK); 1315 else 1316 CLR(sc->sc_lcr, LCR_SBREAK); 1317 1318 if (!sc->sc_heldchange) { 1319 if (sc->sc_tx_busy) { 1320 sc->sc_heldtbc = sc->sc_tbc; 1321 sc->sc_tbc = 0; 1322 sc->sc_heldchange = 1; 1323 } else 1324 com_loadchannelregs(sc); 1325 } 1326 } 1327 1328 void 1329 com_modem(struct com_softc *sc, int onoff) 1330 { 1331 1332 if (sc->sc_mcr_dtr == 0) 1333 return; 1334 1335 if (onoff) 1336 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1337 else 1338 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1339 1340 if (!sc->sc_heldchange) { 1341 if (sc->sc_tx_busy) { 1342 sc->sc_heldtbc = sc->sc_tbc; 1343 sc->sc_tbc = 0; 1344 sc->sc_heldchange = 1; 1345 } else 1346 com_loadchannelregs(sc); 1347 } 1348 } 1349 1350 void 1351 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1352 { 1353 u_char combits; 1354 1355 combits = 0; 1356 if (ISSET(ttybits, TIOCM_DTR)) 1357 SET(combits, MCR_DTR); 1358 if (ISSET(ttybits, TIOCM_RTS)) 1359 SET(combits, MCR_RTS); 1360 1361 switch (how) { 1362 case TIOCMBIC: 1363 CLR(sc->sc_mcr, combits); 1364 break; 1365 1366 case TIOCMBIS: 1367 SET(sc->sc_mcr, combits); 1368 break; 1369 1370 case TIOCMSET: 1371 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1372 SET(sc->sc_mcr, combits); 1373 break; 1374 } 1375 1376 if (!sc->sc_heldchange) { 1377 if (sc->sc_tx_busy) { 1378 sc->sc_heldtbc = sc->sc_tbc; 1379 sc->sc_tbc = 0; 1380 sc->sc_heldchange = 1; 1381 } else 1382 com_loadchannelregs(sc); 1383 } 1384 } 1385 1386 int 1387 com_to_tiocm(struct com_softc *sc) 1388 { 1389 u_char combits; 1390 int ttybits = 0; 1391 1392 combits = sc->sc_mcr; 1393 if (ISSET(combits, MCR_DTR)) 1394 SET(ttybits, TIOCM_DTR); 1395 if (ISSET(combits, MCR_RTS)) 1396 SET(ttybits, TIOCM_RTS); 1397 1398 combits = sc->sc_msr; 1399 if (sc->sc_type == COM_TYPE_INGENIC) { 1400 SET(ttybits, TIOCM_CD); 1401 } else { 1402 if (ISSET(combits, MSR_DCD)) 1403 SET(ttybits, TIOCM_CD); 1404 } 1405 if (ISSET(combits, MSR_CTS)) 1406 SET(ttybits, TIOCM_CTS); 1407 if (ISSET(combits, MSR_DSR)) 1408 SET(ttybits, TIOCM_DSR); 1409 if (ISSET(combits, MSR_RI | MSR_TERI)) 1410 SET(ttybits, TIOCM_RI); 1411 1412 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1413 SET(ttybits, TIOCM_LE); 1414 1415 return (ttybits); 1416 } 1417 1418 static u_char 1419 cflag2lcr(tcflag_t cflag) 1420 { 1421 u_char lcr = 0; 1422 1423 switch (ISSET(cflag, CSIZE)) { 1424 case CS5: 1425 SET(lcr, LCR_5BITS); 1426 break; 1427 case CS6: 1428 SET(lcr, LCR_6BITS); 1429 break; 1430 case CS7: 1431 SET(lcr, LCR_7BITS); 1432 break; 1433 case CS8: 1434 SET(lcr, LCR_8BITS); 1435 break; 1436 } 1437 if (ISSET(cflag, PARENB)) { 1438 SET(lcr, LCR_PENAB); 1439 if (!ISSET(cflag, PARODD)) 1440 SET(lcr, LCR_PEVEN); 1441 } 1442 if (ISSET(cflag, CSTOPB)) 1443 SET(lcr, LCR_STOPB); 1444 1445 return (lcr); 1446 } 1447 1448 int 1449 comparam(struct tty *tp, struct termios *t) 1450 { 1451 struct com_softc *sc = 1452 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1453 int ospeed; 1454 u_char lcr; 1455 1456 if (COM_ISALIVE(sc) == 0) 1457 return (EIO); 1458 1459 if (sc->sc_type == COM_TYPE_HAYESP) { 1460 int prescaler, speed; 1461 1462 /* 1463 * Calculate UART clock prescaler. It should be in 1464 * range of 0 .. 3. 1465 */ 1466 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1467 prescaler++, speed /= 2) 1468 if ((ospeed = comspeed(speed, sc->sc_frequency, 1469 sc->sc_type)) > 0) 1470 break; 1471 1472 if (prescaler == 4) 1473 return (EINVAL); 1474 sc->sc_prescaler = prescaler; 1475 } else 1476 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1477 1478 /* Check requested parameters. */ 1479 if (ospeed < 0) 1480 return (EINVAL); 1481 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1482 return (EINVAL); 1483 1484 /* 1485 * For the console, always force CLOCAL and !HUPCL, so that the port 1486 * is always active. 1487 */ 1488 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1489 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1490 SET(t->c_cflag, CLOCAL); 1491 CLR(t->c_cflag, HUPCL); 1492 } 1493 1494 /* 1495 * If there were no changes, don't do anything. This avoids dropping 1496 * input and improves performance when all we did was frob things like 1497 * VMIN and VTIME. 1498 */ 1499 if (tp->t_ospeed == t->c_ospeed && 1500 tp->t_cflag == t->c_cflag) 1501 return (0); 1502 1503 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1504 1505 mutex_spin_enter(&sc->sc_lock); 1506 1507 sc->sc_lcr = lcr; 1508 1509 /* 1510 * If we're not in a mode that assumes a connection is present, then 1511 * ignore carrier changes. 1512 */ 1513 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1514 sc->sc_msr_dcd = 0; 1515 else 1516 sc->sc_msr_dcd = MSR_DCD; 1517 /* 1518 * Set the flow control pins depending on the current flow control 1519 * mode. 1520 */ 1521 if (ISSET(t->c_cflag, CRTSCTS)) { 1522 sc->sc_mcr_dtr = MCR_DTR; 1523 sc->sc_mcr_rts = MCR_RTS; 1524 sc->sc_msr_cts = MSR_CTS; 1525 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1526 SET(sc->sc_mcr, MCR_AFE); 1527 } else { 1528 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1529 } 1530 } else if (ISSET(t->c_cflag, MDMBUF)) { 1531 /* 1532 * For DTR/DCD flow control, make sure we don't toggle DTR for 1533 * carrier detection. 1534 */ 1535 sc->sc_mcr_dtr = 0; 1536 sc->sc_mcr_rts = MCR_DTR; 1537 sc->sc_msr_cts = MSR_DCD; 1538 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1539 CLR(sc->sc_mcr, MCR_AFE); 1540 } else { 1541 sc->sc_efr = 0; 1542 } 1543 } else { 1544 /* 1545 * If no flow control, then always set RTS. This will make 1546 * the other side happy if it mistakenly thinks we're doing 1547 * RTS/CTS flow control. 1548 */ 1549 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1550 sc->sc_mcr_rts = 0; 1551 sc->sc_msr_cts = 0; 1552 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1553 CLR(sc->sc_mcr, MCR_AFE); 1554 } else { 1555 sc->sc_efr = 0; 1556 } 1557 if (ISSET(sc->sc_mcr, MCR_DTR)) 1558 SET(sc->sc_mcr, MCR_RTS); 1559 else 1560 CLR(sc->sc_mcr, MCR_RTS); 1561 } 1562 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1563 1564 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1565 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1566 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1567 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1568 1569 sc->sc_dlbl = ospeed; 1570 sc->sc_dlbh = ospeed >> 8; 1571 1572 /* 1573 * Set the FIFO threshold based on the receive speed. 1574 * 1575 * * If it's a low speed, it's probably a mouse or some other 1576 * interactive device, so set the threshold low. 1577 * * If it's a high speed, trim the trigger level down to prevent 1578 * overflows. 1579 * * Otherwise set it a bit higher. 1580 */ 1581 if (sc->sc_type == COM_TYPE_HAYESP) { 1582 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1583 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1584 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1585 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1586 if (t->c_ospeed <= 1200) 1587 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1588 else if (t->c_ospeed <= 38400) 1589 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1590 else 1591 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1592 } else { 1593 sc->sc_fifo = 0; 1594 } 1595 1596 if (sc->sc_type == COM_TYPE_INGENIC) 1597 sc->sc_fifo |= FIFO_UART_ON; 1598 1599 /* And copy to tty. */ 1600 tp->t_ispeed = t->c_ospeed; 1601 tp->t_ospeed = t->c_ospeed; 1602 tp->t_cflag = t->c_cflag; 1603 1604 if (!sc->sc_heldchange) { 1605 if (sc->sc_tx_busy) { 1606 sc->sc_heldtbc = sc->sc_tbc; 1607 sc->sc_tbc = 0; 1608 sc->sc_heldchange = 1; 1609 } else 1610 com_loadchannelregs(sc); 1611 } 1612 1613 if (!ISSET(t->c_cflag, CHWFLOW)) { 1614 /* Disable the high water mark. */ 1615 sc->sc_r_hiwat = 0; 1616 sc->sc_r_lowat = 0; 1617 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1618 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1619 com_schedrx(sc); 1620 } 1621 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1622 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1623 com_hwiflow(sc); 1624 } 1625 } else { 1626 sc->sc_r_hiwat = com_rbuf_hiwat; 1627 sc->sc_r_lowat = com_rbuf_lowat; 1628 } 1629 1630 mutex_spin_exit(&sc->sc_lock); 1631 1632 /* 1633 * Update the tty layer's idea of the carrier bit, in case we changed 1634 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1635 * explicit request. 1636 */ 1637 if (sc->sc_type == COM_TYPE_INGENIC) { 1638 /* no DCD here */ 1639 (void) (*tp->t_linesw->l_modem)(tp, 1); 1640 } else 1641 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1642 1643 #ifdef COM_DEBUG 1644 if (com_debug) 1645 comstatus(sc, "comparam "); 1646 #endif 1647 1648 if (!ISSET(t->c_cflag, CHWFLOW)) { 1649 if (sc->sc_tx_stopped) { 1650 sc->sc_tx_stopped = 0; 1651 comstart(tp); 1652 } 1653 } 1654 1655 return (0); 1656 } 1657 1658 void 1659 com_iflush(struct com_softc *sc) 1660 { 1661 struct com_regs *regsp = &sc->sc_regs; 1662 uint8_t fifo; 1663 #ifdef DIAGNOSTIC 1664 int reg; 1665 #endif 1666 int timo; 1667 1668 #ifdef DIAGNOSTIC 1669 reg = 0xffff; 1670 #endif 1671 timo = 50000; 1672 /* flush any pending I/O */ 1673 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1674 && --timo) 1675 #ifdef DIAGNOSTIC 1676 reg = 1677 #else 1678 (void) 1679 #endif 1680 CSR_READ_1(regsp, COM_REG_RXDATA); 1681 #ifdef DIAGNOSTIC 1682 if (!timo) 1683 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1684 #endif 1685 1686 switch (sc->sc_type) { 1687 case COM_TYPE_16750: 1688 case COM_TYPE_DW_APB: 1689 /* 1690 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1691 * This should prevent triggering busy interrupt while 1692 * manipulating divisors. 1693 */ 1694 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1695 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1696 CSR_WRITE_1(regsp, COM_REG_FIFO, 1697 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1698 delay(100); 1699 break; 1700 } 1701 } 1702 1703 void 1704 com_loadchannelregs(struct com_softc *sc) 1705 { 1706 struct com_regs *regsp = &sc->sc_regs; 1707 1708 /* XXXXX necessary? */ 1709 com_iflush(sc); 1710 1711 if (sc->sc_type == COM_TYPE_PXA2x0) 1712 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1713 else 1714 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1715 1716 if (sc->sc_type == COM_TYPE_OMAP) { 1717 /* disable before changing settings */ 1718 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1719 } 1720 1721 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1722 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1723 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1724 /* no EFR on alchemy */ 1725 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1726 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1727 } 1728 if (sc->sc_type == COM_TYPE_AU1x00) { 1729 /* alchemy has single separate 16-bit clock divisor register */ 1730 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1731 (sc->sc_dlbh << 8)); 1732 } else { 1733 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1734 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1735 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1736 } 1737 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1738 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1739 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1740 if (sc->sc_type == COM_TYPE_HAYESP) { 1741 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1742 HAYESP_SETPRESCALER); 1743 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1744 sc->sc_prescaler); 1745 } 1746 if (sc->sc_type == COM_TYPE_OMAP) { 1747 /* setup the fifos. the FCR value is not used as long 1748 as SCR[6] and SCR[7] are 0, which they are at reset 1749 and we never touch the SCR register */ 1750 uint8_t rx_fifo_trig = 40; 1751 uint8_t tx_fifo_trig = 60; 1752 uint8_t rx_start = 8; 1753 uint8_t rx_halt = 60; 1754 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1755 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1756 1757 /* enable access to TCR & TLR */ 1758 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1759 1760 /* write tcr and tlr values */ 1761 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1762 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1763 1764 /* disable access to TCR & TLR */ 1765 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1766 1767 /* enable again, but mode is based on speed */ 1768 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1769 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1770 } else { 1771 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1772 } 1773 } 1774 1775 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1776 } 1777 1778 int 1779 comhwiflow(struct tty *tp, int block) 1780 { 1781 struct com_softc *sc = 1782 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1783 1784 if (COM_ISALIVE(sc) == 0) 1785 return (0); 1786 1787 if (sc->sc_mcr_rts == 0) 1788 return (0); 1789 1790 mutex_spin_enter(&sc->sc_lock); 1791 1792 if (block) { 1793 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1794 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1795 com_hwiflow(sc); 1796 } 1797 } else { 1798 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1799 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1800 com_schedrx(sc); 1801 } 1802 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1803 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1804 com_hwiflow(sc); 1805 } 1806 } 1807 1808 mutex_spin_exit(&sc->sc_lock); 1809 return (1); 1810 } 1811 1812 /* 1813 * (un)block input via hw flowcontrol 1814 */ 1815 void 1816 com_hwiflow(struct com_softc *sc) 1817 { 1818 struct com_regs *regsp= &sc->sc_regs; 1819 1820 if (sc->sc_mcr_rts == 0) 1821 return; 1822 1823 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1824 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1825 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1826 } else { 1827 SET(sc->sc_mcr, sc->sc_mcr_rts); 1828 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1829 } 1830 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1831 } 1832 1833 1834 void 1835 comstart(struct tty *tp) 1836 { 1837 struct com_softc *sc = 1838 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1839 struct com_regs *regsp = &sc->sc_regs; 1840 int s; 1841 1842 if (COM_ISALIVE(sc) == 0) 1843 return; 1844 1845 s = spltty(); 1846 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1847 goto out; 1848 if (sc->sc_tx_stopped) 1849 goto out; 1850 if (!ttypull(tp)) 1851 goto out; 1852 1853 /* Grab the first contiguous region of buffer space. */ 1854 { 1855 u_char *tba; 1856 int tbc; 1857 1858 tba = tp->t_outq.c_cf; 1859 tbc = ndqb(&tp->t_outq, 0); 1860 1861 mutex_spin_enter(&sc->sc_lock); 1862 1863 sc->sc_tba = tba; 1864 sc->sc_tbc = tbc; 1865 } 1866 1867 SET(tp->t_state, TS_BUSY); 1868 sc->sc_tx_busy = 1; 1869 1870 /* Enable transmit completion interrupts if necessary. */ 1871 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1872 SET(sc->sc_ier, IER_ETXRDY); 1873 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1874 } 1875 1876 /* Output the first chunk of the contiguous buffer. */ 1877 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1878 u_int n; 1879 1880 n = sc->sc_tbc; 1881 if (n > sc->sc_fifolen) 1882 n = sc->sc_fifolen; 1883 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1884 sc->sc_tbc -= n; 1885 sc->sc_tba += n; 1886 } 1887 1888 mutex_spin_exit(&sc->sc_lock); 1889 out: 1890 splx(s); 1891 return; 1892 } 1893 1894 /* 1895 * Stop output on a line. 1896 */ 1897 void 1898 comstop(struct tty *tp, int flag) 1899 { 1900 struct com_softc *sc = 1901 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1902 1903 mutex_spin_enter(&sc->sc_lock); 1904 if (ISSET(tp->t_state, TS_BUSY)) { 1905 /* Stop transmitting at the next chunk. */ 1906 sc->sc_tbc = 0; 1907 sc->sc_heldtbc = 0; 1908 if (!ISSET(tp->t_state, TS_TTSTOP)) 1909 SET(tp->t_state, TS_FLUSH); 1910 } 1911 mutex_spin_exit(&sc->sc_lock); 1912 } 1913 1914 void 1915 comdiag(void *arg) 1916 { 1917 struct com_softc *sc = arg; 1918 int overflows, floods; 1919 1920 mutex_spin_enter(&sc->sc_lock); 1921 overflows = sc->sc_overflows; 1922 sc->sc_overflows = 0; 1923 floods = sc->sc_floods; 1924 sc->sc_floods = 0; 1925 sc->sc_errors = 0; 1926 mutex_spin_exit(&sc->sc_lock); 1927 1928 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1929 device_xname(sc->sc_dev), 1930 overflows, overflows == 1 ? "" : "s", 1931 floods, floods == 1 ? "" : "s"); 1932 } 1933 1934 integrate void 1935 com_rxsoft(struct com_softc *sc, struct tty *tp) 1936 { 1937 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1938 u_char *get, *end; 1939 u_int cc, scc; 1940 u_char lsr; 1941 int code; 1942 1943 end = sc->sc_ebuf; 1944 get = sc->sc_rbget; 1945 scc = cc = com_rbuf_size - sc->sc_rbavail; 1946 1947 if (cc == com_rbuf_size) { 1948 sc->sc_floods++; 1949 if (sc->sc_errors++ == 0) 1950 callout_reset(&sc->sc_diag_callout, 60 * hz, 1951 comdiag, sc); 1952 } 1953 1954 /* If not yet open, drop the entire buffer content here */ 1955 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1956 get += cc << 1; 1957 if (get >= end) 1958 get -= com_rbuf_size << 1; 1959 cc = 0; 1960 } 1961 while (cc) { 1962 code = get[0]; 1963 lsr = get[1]; 1964 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1965 if (ISSET(lsr, LSR_OE)) { 1966 sc->sc_overflows++; 1967 if (sc->sc_errors++ == 0) 1968 callout_reset(&sc->sc_diag_callout, 1969 60 * hz, comdiag, sc); 1970 } 1971 if (ISSET(lsr, LSR_BI | LSR_FE)) 1972 SET(code, TTY_FE); 1973 if (ISSET(lsr, LSR_PE)) 1974 SET(code, TTY_PE); 1975 } 1976 if ((*rint)(code, tp) == -1) { 1977 /* 1978 * The line discipline's buffer is out of space. 1979 */ 1980 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1981 /* 1982 * We're either not using flow control, or the 1983 * line discipline didn't tell us to block for 1984 * some reason. Either way, we have no way to 1985 * know when there's more space available, so 1986 * just drop the rest of the data. 1987 */ 1988 get += cc << 1; 1989 if (get >= end) 1990 get -= com_rbuf_size << 1; 1991 cc = 0; 1992 } else { 1993 /* 1994 * Don't schedule any more receive processing 1995 * until the line discipline tells us there's 1996 * space available (through comhwiflow()). 1997 * Leave the rest of the data in the input 1998 * buffer. 1999 */ 2000 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 2001 } 2002 break; 2003 } 2004 get += 2; 2005 if (get >= end) 2006 get = sc->sc_rbuf; 2007 cc--; 2008 } 2009 2010 if (cc != scc) { 2011 sc->sc_rbget = get; 2012 mutex_spin_enter(&sc->sc_lock); 2013 2014 cc = sc->sc_rbavail += scc - cc; 2015 /* Buffers should be ok again, release possible block. */ 2016 if (cc >= sc->sc_r_lowat) { 2017 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2018 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2019 SET(sc->sc_ier, IER_ERXRDY); 2020 if (sc->sc_type == COM_TYPE_PXA2x0) 2021 SET(sc->sc_ier, IER_ERXTOUT); 2022 if (sc->sc_type == COM_TYPE_INGENIC || 2023 sc->sc_type == COM_TYPE_TEGRA) 2024 SET(sc->sc_ier, IER_ERXTOUT); 2025 2026 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 2027 sc->sc_ier); 2028 } 2029 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 2030 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2031 com_hwiflow(sc); 2032 } 2033 } 2034 mutex_spin_exit(&sc->sc_lock); 2035 } 2036 } 2037 2038 integrate void 2039 com_txsoft(struct com_softc *sc, struct tty *tp) 2040 { 2041 2042 CLR(tp->t_state, TS_BUSY); 2043 if (ISSET(tp->t_state, TS_FLUSH)) 2044 CLR(tp->t_state, TS_FLUSH); 2045 else 2046 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2047 (*tp->t_linesw->l_start)(tp); 2048 } 2049 2050 integrate void 2051 com_stsoft(struct com_softc *sc, struct tty *tp) 2052 { 2053 u_char msr, delta; 2054 2055 mutex_spin_enter(&sc->sc_lock); 2056 msr = sc->sc_msr; 2057 delta = sc->sc_msr_delta; 2058 sc->sc_msr_delta = 0; 2059 mutex_spin_exit(&sc->sc_lock); 2060 2061 if (ISSET(delta, sc->sc_msr_dcd)) { 2062 /* 2063 * Inform the tty layer that carrier detect changed. 2064 */ 2065 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2066 } 2067 2068 if (ISSET(delta, sc->sc_msr_cts)) { 2069 /* Block or unblock output according to flow control. */ 2070 if (ISSET(msr, sc->sc_msr_cts)) { 2071 sc->sc_tx_stopped = 0; 2072 (*tp->t_linesw->l_start)(tp); 2073 } else { 2074 sc->sc_tx_stopped = 1; 2075 } 2076 } 2077 2078 #ifdef COM_DEBUG 2079 if (com_debug) 2080 comstatus(sc, "com_stsoft"); 2081 #endif 2082 } 2083 2084 void 2085 comsoft(void *arg) 2086 { 2087 struct com_softc *sc = arg; 2088 struct tty *tp; 2089 2090 if (COM_ISALIVE(sc) == 0) 2091 return; 2092 2093 tp = sc->sc_tty; 2094 2095 if (sc->sc_rx_ready) { 2096 sc->sc_rx_ready = 0; 2097 com_rxsoft(sc, tp); 2098 } 2099 2100 if (sc->sc_st_check) { 2101 sc->sc_st_check = 0; 2102 com_stsoft(sc, tp); 2103 } 2104 2105 if (sc->sc_tx_done) { 2106 sc->sc_tx_done = 0; 2107 com_txsoft(sc, tp); 2108 } 2109 } 2110 2111 int 2112 comintr(void *arg) 2113 { 2114 struct com_softc *sc = arg; 2115 struct com_regs *regsp = &sc->sc_regs; 2116 2117 u_char *put, *end; 2118 u_int cc; 2119 u_char lsr, iir; 2120 2121 if (COM_ISALIVE(sc) == 0) 2122 return (0); 2123 2124 KASSERT(regsp != NULL); 2125 2126 mutex_spin_enter(&sc->sc_lock); 2127 iir = CSR_READ_1(regsp, COM_REG_IIR); 2128 2129 /* Handle ns16750-specific busy interrupt. */ 2130 if (sc->sc_type == COM_TYPE_16750 && 2131 (iir & IIR_BUSY) == IIR_BUSY) { 2132 for (int timeout = 10000; 2133 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2134 if (timeout <= 0) { 2135 aprint_error_dev(sc->sc_dev, 2136 "timeout while waiting for BUSY interrupt " 2137 "acknowledge\n"); 2138 mutex_spin_exit(&sc->sc_lock); 2139 return (0); 2140 } 2141 2142 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2143 iir = CSR_READ_1(regsp, COM_REG_IIR); 2144 } 2145 2146 /* DesignWare APB UART BUSY interrupt */ 2147 if (sc->sc_type == COM_TYPE_DW_APB && 2148 (iir & IIR_BUSY) == IIR_BUSY) { 2149 if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2150 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2151 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2152 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2153 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2154 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2155 CSR_WRITE_1(regsp, COM_REG_HALT, 2156 HALT_CHCFG_EN | HALT_CHCFG_UD); 2157 for (int timeout = 10000000; 2158 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2159 timeout--) { 2160 if (timeout <= 0) { 2161 aprint_error_dev(sc->sc_dev, 2162 "timeout while waiting for HALT " 2163 "update acknowledge 0x%x 0x%x\n", 2164 CSR_READ_1(regsp, COM_REG_HALT), 2165 CSR_READ_1(regsp, COM_REG_USR)); 2166 break; 2167 } 2168 } 2169 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2170 (void)CSR_READ_1(regsp, COM_REG_USR); 2171 } else { 2172 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2173 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2174 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2175 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2176 } 2177 } 2178 2179 end = sc->sc_ebuf; 2180 put = sc->sc_rbput; 2181 cc = sc->sc_rbavail; 2182 2183 if (ISSET(iir, IIR_NOPEND)) { 2184 if (ISSET(sc->sc_hwflags, COM_HW_BROKEN_ETXRDY)) 2185 goto do_tx; 2186 mutex_spin_exit(&sc->sc_lock); 2187 return (0); 2188 } 2189 2190 again: do { 2191 u_char msr, delta; 2192 2193 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2194 if (ISSET(lsr, LSR_BI)) { 2195 int cn_trapped = 0; /* see above: cn_trap() */ 2196 2197 cn_check_magic(sc->sc_tty->t_dev, 2198 CNC_BREAK, com_cnm_state); 2199 if (cn_trapped) 2200 continue; 2201 #if defined(KGDB) && !defined(DDB) 2202 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2203 kgdb_connect(1); 2204 continue; 2205 } 2206 #endif 2207 } 2208 2209 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2210 lsr |= LSR_RXRDY; 2211 2212 if (ISSET(lsr, LSR_RCV_MASK) && 2213 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2214 while (cc > 0) { 2215 int cn_trapped = 0; 2216 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2217 put[1] = lsr; 2218 cn_check_magic(sc->sc_tty->t_dev, 2219 put[0], com_cnm_state); 2220 if (cn_trapped) 2221 goto next; 2222 put += 2; 2223 if (put >= end) 2224 put = sc->sc_rbuf; 2225 cc--; 2226 next: 2227 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2228 if (!ISSET(lsr, LSR_RCV_MASK)) 2229 break; 2230 } 2231 2232 /* 2233 * Current string of incoming characters ended because 2234 * no more data was available or we ran out of space. 2235 * Schedule a receive event if any data was received. 2236 * If we're out of space, turn off receive interrupts. 2237 */ 2238 sc->sc_rbput = put; 2239 sc->sc_rbavail = cc; 2240 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2241 sc->sc_rx_ready = 1; 2242 2243 /* 2244 * See if we are in danger of overflowing a buffer. If 2245 * so, use hardware flow control to ease the pressure. 2246 */ 2247 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2248 cc < sc->sc_r_hiwat) { 2249 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2250 com_hwiflow(sc); 2251 } 2252 2253 /* 2254 * If we're out of space, disable receive interrupts 2255 * until the queue has drained a bit. 2256 */ 2257 if (!cc) { 2258 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2259 switch (sc->sc_type) { 2260 case COM_TYPE_PXA2x0: 2261 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2262 break; 2263 case COM_TYPE_INGENIC: 2264 case COM_TYPE_TEGRA: 2265 CLR(sc->sc_ier, 2266 IER_ERXRDY | IER_ERXTOUT); 2267 break; 2268 default: 2269 CLR(sc->sc_ier, IER_ERXRDY); 2270 break; 2271 } 2272 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2273 } 2274 } else { 2275 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2276 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2277 continue; 2278 } 2279 } 2280 2281 msr = CSR_READ_1(regsp, COM_REG_MSR); 2282 delta = msr ^ sc->sc_msr; 2283 sc->sc_msr = msr; 2284 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2285 (delta & MSR_DCD)) { 2286 mutex_spin_enter(&timecounter_lock); 2287 pps_capture(&sc->sc_pps_state); 2288 pps_event(&sc->sc_pps_state, 2289 (msr & MSR_DCD) ? 2290 PPS_CAPTUREASSERT : 2291 PPS_CAPTURECLEAR); 2292 mutex_spin_exit(&timecounter_lock); 2293 } 2294 2295 /* 2296 * Process normal status changes 2297 */ 2298 if (ISSET(delta, sc->sc_msr_mask)) { 2299 SET(sc->sc_msr_delta, delta); 2300 2301 /* 2302 * Stop output immediately if we lose the output 2303 * flow control signal or carrier detect. 2304 */ 2305 if (ISSET(~msr, sc->sc_msr_mask)) { 2306 sc->sc_tbc = 0; 2307 sc->sc_heldtbc = 0; 2308 #ifdef COM_DEBUG 2309 if (com_debug) 2310 comstatus(sc, "comintr "); 2311 #endif 2312 } 2313 2314 sc->sc_st_check = 1; 2315 } 2316 } while (!ISSET((iir = 2317 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2318 /* 2319 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2320 * by IIR read, so we can't do this way: `process all interrupts, 2321 * then do TX if possible'. 2322 */ 2323 (iir & IIR_IMASK) != IIR_TXRDY); 2324 2325 do_tx: 2326 /* 2327 * Read LSR again, since there may be an interrupt between 2328 * the last LSR read and IIR read above. 2329 */ 2330 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2331 2332 /* 2333 * See if data can be transmitted as well. 2334 * Schedule tx done event if no data left 2335 * and tty was marked busy. 2336 */ 2337 if (ISSET(lsr, LSR_TXRDY)) { 2338 /* 2339 * If we've delayed a parameter change, do it now, and restart 2340 * output. 2341 */ 2342 if (sc->sc_heldchange) { 2343 com_loadchannelregs(sc); 2344 sc->sc_heldchange = 0; 2345 sc->sc_tbc = sc->sc_heldtbc; 2346 sc->sc_heldtbc = 0; 2347 } 2348 2349 /* Output the next chunk of the contiguous buffer, if any. */ 2350 if (sc->sc_tbc > 0) { 2351 u_int n; 2352 2353 n = sc->sc_tbc; 2354 if (n > sc->sc_fifolen) 2355 n = sc->sc_fifolen; 2356 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2357 sc->sc_tbc -= n; 2358 sc->sc_tba += n; 2359 } else { 2360 /* Disable transmit completion interrupts if necessary. */ 2361 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2362 CLR(sc->sc_ier, IER_ETXRDY); 2363 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2364 } 2365 if (sc->sc_tx_busy) { 2366 sc->sc_tx_busy = 0; 2367 sc->sc_tx_done = 1; 2368 } 2369 } 2370 } 2371 2372 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2373 goto again; 2374 2375 mutex_spin_exit(&sc->sc_lock); 2376 2377 /* Wake up the poller. */ 2378 if ((sc->sc_rx_ready | sc->sc_st_check | sc->sc_tx_done) != 0) 2379 softint_schedule(sc->sc_si); 2380 2381 #ifdef RND_COM 2382 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2383 #endif 2384 2385 return (1); 2386 } 2387 2388 /* 2389 * The following functions are polled getc and putc routines, shared 2390 * by the console and kgdb glue. 2391 * 2392 * The read-ahead code is so that you can detect pending in-band 2393 * cn_magic in polled mode while doing output rather than having to 2394 * wait until the kernel decides it needs input. 2395 */ 2396 2397 #define MAX_READAHEAD 20 2398 static int com_readahead[MAX_READAHEAD]; 2399 static int com_readaheadcount = 0; 2400 2401 int 2402 com_common_getc(dev_t dev, struct com_regs *regsp) 2403 { 2404 int s = splserial(); 2405 u_char stat, c; 2406 2407 /* got a character from reading things earlier */ 2408 if (com_readaheadcount > 0) { 2409 int i; 2410 2411 c = com_readahead[0]; 2412 for (i = 1; i < com_readaheadcount; i++) { 2413 com_readahead[i-1] = com_readahead[i]; 2414 } 2415 com_readaheadcount--; 2416 splx(s); 2417 return (c); 2418 } 2419 2420 /* don't block until a character becomes available */ 2421 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2422 splx(s); 2423 return -1; 2424 } 2425 2426 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2427 stat = CSR_READ_1(regsp, COM_REG_IIR); 2428 { 2429 int cn_trapped = 0; /* required by cn_trap, see above */ 2430 #ifdef DDB 2431 extern int db_active; 2432 if (!db_active) 2433 #endif 2434 cn_check_magic(dev, c, com_cnm_state); 2435 } 2436 splx(s); 2437 return (c); 2438 } 2439 2440 static void 2441 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead) 2442 { 2443 int s = splserial(); 2444 int cin, stat, timo; 2445 2446 if (with_readahead && com_readaheadcount < MAX_READAHEAD 2447 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2448 int cn_trapped = 0; 2449 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2450 stat = CSR_READ_1(regsp, COM_REG_IIR); 2451 cn_check_magic(dev, cin, com_cnm_state); 2452 com_readahead[com_readaheadcount++] = cin; 2453 } 2454 2455 /* wait for any pending transmission to finish */ 2456 timo = 150000; 2457 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2458 continue; 2459 2460 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2461 COM_BARRIER(regsp, BR | BW); 2462 2463 splx(s); 2464 } 2465 2466 /* 2467 * Initialize UART for use as console or KGDB line. 2468 */ 2469 int 2470 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2471 tcflag_t cflag) 2472 { 2473 2474 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2475 ®sp->cr_ioh)) 2476 return (ENOMEM); /* ??? */ 2477 2478 if (type == COM_TYPE_OMAP) { 2479 /* disable before changing settings */ 2480 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2481 } 2482 2483 rate = comspeed(rate, frequency, type); 2484 if (rate != -1) { 2485 if (type == COM_TYPE_AU1x00) { 2486 /* no EFR on alchemy */ 2487 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2488 } else { 2489 if ((type != COM_TYPE_16550_NOERS) && 2490 (type != COM_TYPE_INGENIC)) { 2491 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2492 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2493 } 2494 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2495 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2496 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2497 } 2498 } 2499 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2500 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2501 2502 if (type == COM_TYPE_INGENIC) { 2503 CSR_WRITE_1(regsp, COM_REG_FIFO, 2504 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2505 FIFO_TRIGGER_1 | FIFO_UART_ON); 2506 } else { 2507 CSR_WRITE_1(regsp, COM_REG_FIFO, 2508 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2509 FIFO_TRIGGER_1); 2510 } 2511 2512 if (type == COM_TYPE_OMAP) { 2513 /* setup the fifos. the FCR value is not used as long 2514 as SCR[6] and SCR[7] are 0, which they are at reset 2515 and we never touch the SCR register */ 2516 uint8_t rx_fifo_trig = 40; 2517 uint8_t tx_fifo_trig = 60; 2518 uint8_t rx_start = 8; 2519 uint8_t rx_halt = 60; 2520 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2521 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2522 2523 /* enable access to TCR & TLR */ 2524 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2525 2526 /* write tcr and tlr values */ 2527 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2528 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2529 2530 /* disable access to TCR & TLR */ 2531 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2532 2533 /* enable again, but mode is based on speed */ 2534 if (rate > 230400) { 2535 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2536 } else { 2537 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2538 } 2539 } 2540 2541 if (type == COM_TYPE_PXA2x0) 2542 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2543 else 2544 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2545 2546 return (0); 2547 } 2548 2549 int 2550 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2551 tcflag_t cflag) 2552 { 2553 int res; 2554 2555 comcons_info.regs = *regsp; 2556 2557 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2558 if (res) 2559 return (res); 2560 2561 cn_tab = &comcons; 2562 cn_init_magic(&com_cnm_state); 2563 cn_set_magic("\047\001"); /* default magic is BREAK */ 2564 2565 comcons_info.frequency = frequency; 2566 comcons_info.type = type; 2567 comcons_info.rate = rate; 2568 comcons_info.cflag = cflag; 2569 2570 return (0); 2571 } 2572 2573 int 2574 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2575 int type, tcflag_t cflag) 2576 { 2577 struct com_regs regs; 2578 2579 /*XXX*/ 2580 bus_space_handle_t dummy_bsh; 2581 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2582 2583 /* 2584 * dummy_bsh required because com_init_regs() wants it. A 2585 * real bus_space_handle will be filled in by cominit() later. 2586 * XXXJRT Detangle this mess eventually, plz. 2587 */ 2588 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2589 2590 return comcnattach1(®s, rate, frequency, type, cflag); 2591 } 2592 2593 static int 2594 comcnreattach(void) 2595 { 2596 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2597 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2598 } 2599 2600 int 2601 comcngetc(dev_t dev) 2602 { 2603 2604 return (com_common_getc(dev, &comcons_info.regs)); 2605 } 2606 2607 /* 2608 * Console kernel output character routine. 2609 */ 2610 void 2611 comcnputc(dev_t dev, int c) 2612 { 2613 2614 com_common_putc(dev, &comcons_info.regs, c, cold); 2615 } 2616 2617 void 2618 comcnpollc(dev_t dev, int on) 2619 { 2620 2621 com_readaheadcount = 0; 2622 } 2623 2624 #ifdef KGDB 2625 int 2626 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2627 tcflag_t cflag) 2628 { 2629 int res; 2630 2631 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2632 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2633 #if !defined(DDB) 2634 return (EBUSY); /* cannot share with console */ 2635 #else 2636 comkgdbregs = *regsp; 2637 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2638 #endif 2639 } else { 2640 comkgdbregs = *regsp; 2641 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2642 if (res) 2643 return (res); 2644 2645 /* 2646 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2647 * expects this to be initialized 2648 */ 2649 cn_init_magic(&com_cnm_state); 2650 cn_set_magic("\047\001"); 2651 } 2652 2653 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2654 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2655 2656 return (0); 2657 } 2658 2659 int 2660 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2661 int frequency, int type, tcflag_t cflag) 2662 { 2663 struct com_regs regs; 2664 2665 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2666 2667 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2668 } 2669 2670 /* ARGSUSED */ 2671 int 2672 com_kgdb_getc(void *arg) 2673 { 2674 2675 return (com_common_getc(NODEV, &comkgdbregs)); 2676 } 2677 2678 /* ARGSUSED */ 2679 void 2680 com_kgdb_putc(void *arg, int c) 2681 { 2682 2683 com_common_putc(NODEV, &comkgdbregs, c, 0); 2684 } 2685 #endif /* KGDB */ 2686 2687 /* helper function to identify the com ports used by 2688 console or KGDB (and not yet autoconf attached) */ 2689 int 2690 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2691 { 2692 bus_space_handle_t help; 2693 2694 if (!comconsattached && 2695 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2696 iobase == comcons_info.regs.cr_iobase) 2697 help = comcons_info.regs.cr_ioh; 2698 #ifdef KGDB 2699 else if (!com_kgdb_attached && 2700 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2701 iobase == comkgdbregs.cr_iobase) 2702 help = comkgdbregs.cr_ioh; 2703 #endif 2704 else 2705 return (0); 2706 2707 if (ioh) 2708 *ioh = help; 2709 return (1); 2710 } 2711 2712 /* 2713 * this routine exists to serve as a shutdown hook for systems that 2714 * have firmware which doesn't interact properly with a com device in 2715 * FIFO mode. 2716 */ 2717 bool 2718 com_cleanup(device_t self, int how) 2719 { 2720 struct com_softc *sc = device_private(self); 2721 2722 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2723 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2724 2725 return true; 2726 } 2727 2728 bool 2729 com_suspend(device_t self, const pmf_qual_t *qual) 2730 { 2731 struct com_softc *sc = device_private(self); 2732 2733 #if 0 2734 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2735 cn_tab = &comcons_suspend; 2736 #endif 2737 2738 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2739 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2740 2741 return true; 2742 } 2743 2744 bool 2745 com_resume(device_t self, const pmf_qual_t *qual) 2746 { 2747 struct com_softc *sc = device_private(self); 2748 2749 mutex_spin_enter(&sc->sc_lock); 2750 com_loadchannelregs(sc); 2751 mutex_spin_exit(&sc->sc_lock); 2752 2753 return true; 2754 } 2755
Indexes created Wed Sep 24 05:09:52 GMT 2025