com.c revision 1.372
1 /* $NetBSD: com.c,v 1.372 2021/10/30 11:43:17 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.372 2021/10/30 11:43:17 jmcneill Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #define CSR_WRITE_1(r, o, v) \ 132 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 133 #define CSR_READ_1(r, o) \ 134 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 135 #define CSR_WRITE_2(r, o, v) \ 136 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 137 #define CSR_READ_2(r, o) \ 138 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 139 #define CSR_WRITE_MULTI(r, o, p, n) \ 140 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n) 141 142 143 static void com_enable_debugport(struct com_softc *); 144 145 void com_config(struct com_softc *); 146 void com_shutdown(struct com_softc *); 147 int comspeed(long, long, int); 148 static u_char cflag2lcr(tcflag_t); 149 int comparam(struct tty *, struct termios *); 150 void comstart(struct tty *); 151 int comhwiflow(struct tty *, int); 152 153 void com_loadchannelregs(struct com_softc *); 154 void com_hwiflow(struct com_softc *); 155 void com_break(struct com_softc *, int); 156 void com_modem(struct com_softc *, int); 157 void tiocm_to_com(struct com_softc *, u_long, int); 158 int com_to_tiocm(struct com_softc *); 159 void com_iflush(struct com_softc *); 160 161 int com_common_getc(dev_t, struct com_regs *); 162 static void com_common_putc(dev_t, struct com_regs *, int, int); 163 164 int cominit(struct com_regs *, int, int, int, tcflag_t); 165 166 static int comcnreattach(void); 167 168 int comcngetc(dev_t); 169 void comcnputc(dev_t, int); 170 void comcnpollc(dev_t, int); 171 172 #define integrate static inline 173 void comsoft(void *); 174 integrate void com_rxsoft(struct com_softc *, struct tty *); 175 integrate void com_txsoft(struct com_softc *, struct tty *); 176 integrate void com_stsoft(struct com_softc *, struct tty *); 177 integrate void com_schedrx(struct com_softc *); 178 void comdiag(void *); 179 180 dev_type_open(comopen); 181 dev_type_close(comclose); 182 dev_type_read(comread); 183 dev_type_write(comwrite); 184 dev_type_ioctl(comioctl); 185 dev_type_stop(comstop); 186 dev_type_tty(comtty); 187 dev_type_poll(compoll); 188 189 static struct comcons_info comcons_info; 190 191 /* 192 * Following are all routines needed for COM to act as console 193 */ 194 static struct consdev comcons = { 195 .cn_getc = comcngetc, 196 .cn_putc = comcnputc, 197 .cn_pollc = comcnpollc, 198 .cn_dev = NODEV, 199 .cn_pri = CN_NORMAL 200 }; 201 202 203 const struct cdevsw com_cdevsw = { 204 .d_open = comopen, 205 .d_close = comclose, 206 .d_read = comread, 207 .d_write = comwrite, 208 .d_ioctl = comioctl, 209 .d_stop = comstop, 210 .d_tty = comtty, 211 .d_poll = compoll, 212 .d_mmap = nommap, 213 .d_kqfilter = ttykqfilter, 214 .d_discard = nodiscard, 215 .d_flag = D_TTY 216 }; 217 218 /* 219 * Make this an option variable one can patch. 220 * But be warned: this must be a power of 2! 221 */ 222 u_int com_rbuf_size = COM_RING_SIZE; 223 224 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 225 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 226 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 227 228 static int comconsattached; 229 static struct cnm_state com_cnm_state; 230 231 #ifdef KGDB 232 #include <sys/kgdb.h> 233 234 static struct com_regs comkgdbregs; 235 static int com_kgdb_attached; 236 237 int com_kgdb_getc(void *); 238 void com_kgdb_putc(void *, int); 239 #endif /* KGDB */ 240 241 /* initializer for typical 16550-ish hardware */ 242 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 243 [COM_REG_RXDATA] = com_data, 244 [COM_REG_TXDATA] = com_data, 245 [COM_REG_DLBL] = com_dlbl, 246 [COM_REG_DLBH] = com_dlbh, 247 [COM_REG_IER] = com_ier, 248 [COM_REG_IIR] = com_iir, 249 [COM_REG_FIFO] = com_fifo, 250 [COM_REG_TCR] = com_fifo, 251 [COM_REG_EFR] = com_efr, 252 [COM_REG_TLR] = com_efr, 253 [COM_REG_LCR] = com_lcr, 254 [COM_REG_MCR] = com_mcr, 255 [COM_REG_LSR] = com_lsr, 256 [COM_REG_MSR] = com_msr, 257 [COM_REG_USR] = com_usr, 258 [COM_REG_TFL] = com_tfl, 259 [COM_REG_RFL] = com_rfl, 260 [COM_REG_HALT] = com_halt, 261 [COM_REG_MDR1] = com_mdr1, 262 }; 263 264 #define COMDIALOUT_MASK TTDIALOUT_MASK 265 266 #define COMUNIT(x) TTUNIT(x) 267 #define COMDIALOUT(x) TTDIALOUT(x) 268 269 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 270 device_is_active((sc)->sc_dev)) 271 272 #define BR BUS_SPACE_BARRIER_READ 273 #define BW BUS_SPACE_BARRIER_WRITE 274 #define COM_BARRIER(r, f) \ 275 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 276 277 /* 278 * com_init_regs -- 279 * Driver front-ends use this to initialize our register map 280 * in the standard fashion. They may then tailor the map to 281 * their own particular requirements. 282 */ 283 void 284 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 285 bus_addr_t addr) 286 { 287 288 memset(regs, 0, sizeof(*regs)); 289 regs->cr_iot = st; 290 regs->cr_ioh = sh; 291 regs->cr_iobase = addr; 292 regs->cr_nports = COM_NPORTS; 293 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 294 } 295 296 /* 297 * com_init_regs_stride -- 298 * Convenience function for front-ends that have a stride between 299 * registers. 300 */ 301 void 302 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 303 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 304 { 305 306 com_init_regs(regs, st, sh, addr); 307 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 308 regs->cr_map[i] <<= regshift; 309 } 310 regs->cr_nports <<= regshift; 311 } 312 313 /*ARGSUSED*/ 314 int 315 comspeed(long speed, long frequency, int type) 316 { 317 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 318 319 int x, err; 320 int divisor = 16; 321 322 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 323 divisor = 13; 324 } 325 326 if (speed == 0) 327 return (0); 328 if (speed < 0) 329 return (-1); 330 x = divrnd(frequency / divisor, speed); 331 if (x <= 0) 332 return (-1); 333 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 334 if (err < 0) 335 err = -err; 336 if (err > COM_TOLERANCE) 337 return (-1); 338 return (x); 339 340 #undef divrnd 341 } 342 343 #ifdef COM_DEBUG 344 int com_debug = 0; 345 346 void comstatus(struct com_softc *, const char *); 347 void 348 comstatus(struct com_softc *sc, const char *str) 349 { 350 struct tty *tp = sc->sc_tty; 351 352 aprint_normal_dev(sc->sc_dev, 353 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 354 str, 355 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 356 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 357 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 358 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 359 sc->sc_tx_stopped ? '+' : '-'); 360 361 aprint_normal_dev(sc->sc_dev, 362 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 363 str, 364 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 365 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 366 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 367 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 368 sc->sc_rx_flags); 369 } 370 #endif 371 372 int 373 com_probe_subr(struct com_regs *regs) 374 { 375 376 /* force access to id reg */ 377 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 378 CSR_WRITE_1(regs, COM_REG_IIR, 0); 379 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 380 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 381 return (0); 382 383 return (1); 384 } 385 386 int 387 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 388 { 389 struct com_regs regs; 390 391 com_init_regs(®s, iot, ioh, 0/*XXX*/); 392 393 return com_probe_subr(®s); 394 } 395 396 /* 397 * No locking in this routine; it is only called during attach, 398 * or with the port already locked. 399 */ 400 static void 401 com_enable_debugport(struct com_softc *sc) 402 { 403 404 /* Turn on line break interrupt, set carrier. */ 405 sc->sc_ier = IER_ERLS; 406 if (sc->sc_type == COM_TYPE_PXA2x0) 407 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 408 if (sc->sc_type == COM_TYPE_INGENIC || 409 sc->sc_type == COM_TYPE_TEGRA) 410 sc->sc_ier |= IER_ERXTOUT; 411 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 412 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 413 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 414 } 415 416 static void 417 com_intr_poll(void *arg) 418 { 419 struct com_softc * const sc = arg; 420 421 comintr(sc); 422 423 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 424 } 425 426 void 427 com_attach_subr(struct com_softc *sc) 428 { 429 struct com_regs *regsp = &sc->sc_regs; 430 struct tty *tp; 431 uint32_t cpr; 432 uint8_t lcr; 433 const char *fifo_msg = NULL; 434 prop_dictionary_t dict; 435 bool is_console = true; 436 bool force_console = false; 437 438 aprint_naive("\n"); 439 440 dict = device_properties(sc->sc_dev); 441 prop_dictionary_get_bool(dict, "is_console", &is_console); 442 prop_dictionary_get_bool(dict, "force_console", &force_console); 443 callout_init(&sc->sc_diag_callout, 0); 444 callout_init(&sc->sc_poll_callout, 0); 445 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 446 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 447 448 #if defined(COM_16650) 449 sc->sc_type = COM_TYPE_16650; 450 #elif defined(COM_16750) 451 sc->sc_type = COM_TYPE_16750; 452 #elif defined(COM_HAYESP) 453 sc->sc_type = COM_TYPE_HAYESP; 454 #elif defined(COM_PXA2X0) 455 sc->sc_type = COM_TYPE_PXA2x0; 456 #endif 457 458 /* Disable interrupts before configuring the device. */ 459 if (sc->sc_type == COM_TYPE_PXA2x0) 460 sc->sc_ier = IER_EUART; 461 else 462 sc->sc_ier = 0; 463 464 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 465 466 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 467 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 468 comconsattached = 1; 469 470 if (force_console) 471 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 472 473 if (cn_tab == NULL && comcnreattach() != 0) { 474 printf("can't re-init serial console @%lx\n", 475 (u_long)comcons_info.regs.cr_iobase); 476 } 477 478 switch (sc->sc_type) { 479 case COM_TYPE_16750: 480 case COM_TYPE_DW_APB: 481 /* Use in comintr(). */ 482 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 483 break; 484 } 485 486 /* Make sure the console is always "hardwired". */ 487 delay(10000); /* wait for output to finish */ 488 if (is_console) { 489 SET(sc->sc_hwflags, COM_HW_CONSOLE); 490 } 491 492 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 493 } 494 495 /* Probe for FIFO */ 496 switch (sc->sc_type) { 497 case COM_TYPE_HAYESP: 498 goto fifodone; 499 500 case COM_TYPE_AU1x00: 501 sc->sc_fifolen = 16; 502 fifo_msg = "Au1X00 UART"; 503 SET(sc->sc_hwflags, COM_HW_FIFO); 504 goto fifodelay; 505 506 case COM_TYPE_16550_NOERS: 507 sc->sc_fifolen = 16; 508 fifo_msg = "ns16650, no ERS"; 509 SET(sc->sc_hwflags, COM_HW_FIFO); 510 goto fifodelay; 511 512 case COM_TYPE_OMAP: 513 sc->sc_fifolen = 64; 514 fifo_msg = "OMAP UART"; 515 SET(sc->sc_hwflags, COM_HW_FIFO); 516 goto fifodelay; 517 518 case COM_TYPE_INGENIC: 519 sc->sc_fifolen = 16; 520 fifo_msg = "Ingenic UART"; 521 SET(sc->sc_hwflags, COM_HW_FIFO); 522 SET(sc->sc_hwflags, COM_HW_NOIEN); 523 goto fifodelay; 524 525 case COM_TYPE_TEGRA: 526 sc->sc_fifolen = 8; 527 fifo_msg = "Tegra UART"; 528 SET(sc->sc_hwflags, COM_HW_FIFO); 529 CSR_WRITE_1(regsp, COM_REG_FIFO, 530 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 531 goto fifodelay; 532 533 case COM_TYPE_BCMAUXUART: 534 sc->sc_fifolen = 1; 535 fifo_msg = "BCM AUX UART"; 536 SET(sc->sc_hwflags, COM_HW_FIFO); 537 CSR_WRITE_1(regsp, COM_REG_FIFO, 538 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 539 goto fifodelay; 540 541 case COM_TYPE_DW_APB: 542 if (!prop_dictionary_get_uint(dict, "fifolen", &sc->sc_fifolen)) { 543 cpr = bus_space_read_4(sc->sc_regs.cr_iot, 544 sc->sc_regs.cr_ioh, DW_APB_UART_CPR); 545 sc->sc_fifolen = __SHIFTOUT(cpr, UART_CPR_FIFO_MODE) * 16; 546 } 547 if (sc->sc_fifolen == 0) { 548 sc->sc_fifolen = 1; 549 fifo_msg = "DesignWare APB UART, no fifo"; 550 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 551 } else { 552 fifo_msg = "DesignWare APB UART"; 553 SET(sc->sc_hwflags, COM_HW_FIFO); 554 CSR_WRITE_1(regsp, COM_REG_FIFO, 555 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 556 } 557 goto fifodelay; 558 } 559 560 sc->sc_fifolen = 1; 561 /* look for a NS 16550AF UART with FIFOs */ 562 if (sc->sc_type == COM_TYPE_INGENIC) { 563 CSR_WRITE_1(regsp, COM_REG_FIFO, 564 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 565 FIFO_TRIGGER_14 | FIFO_UART_ON); 566 } else 567 CSR_WRITE_1(regsp, COM_REG_FIFO, 568 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 569 delay(100); 570 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 571 == IIR_FIFO_MASK) 572 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 573 == FIFO_TRIGGER_14) { 574 SET(sc->sc_hwflags, COM_HW_FIFO); 575 576 fifo_msg = "ns16550a"; 577 sc->sc_fifolen = 16; 578 579 /* 580 * IIR changes into the EFR if LCR is set to LCR_EERS 581 * on 16650s. We also know IIR != 0 at this point. 582 * Write 0 into the EFR, and read it. If the result 583 * is 0, we have a 16650. 584 * 585 * Older 16650s were broken; the test to detect them 586 * is taken from the Linux driver. Apparently 587 * setting DLAB enable gives access to the EFR on 588 * these chips. 589 */ 590 if (sc->sc_type == COM_TYPE_16650) { 591 lcr = CSR_READ_1(regsp, COM_REG_LCR); 592 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 593 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 594 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 595 CSR_WRITE_1(regsp, COM_REG_LCR, 596 lcr | LCR_DLAB); 597 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 598 CLR(sc->sc_hwflags, COM_HW_FIFO); 599 sc->sc_fifolen = 0; 600 } else { 601 SET(sc->sc_hwflags, COM_HW_FLOW); 602 sc->sc_fifolen = 32; 603 } 604 } else 605 sc->sc_fifolen = 16; 606 607 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 608 if (sc->sc_fifolen == 0) 609 fifo_msg = "st16650, broken fifo"; 610 else if (sc->sc_fifolen == 32) 611 fifo_msg = "st16650a"; 612 else 613 fifo_msg = "ns16550a"; 614 } 615 616 /* 617 * TL16C750 can enable 64byte FIFO, only when DLAB 618 * is 1. However, some 16750 may always enable. For 619 * example, restrictions according to DLAB in a data 620 * sheet for SC16C750 were not described. 621 * Please enable 'options COM_16650', supposing you 622 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 623 * should become effective. 624 */ 625 if (sc->sc_type == COM_TYPE_16750) { 626 uint8_t iir1, iir2; 627 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 628 629 lcr = CSR_READ_1(regsp, COM_REG_LCR); 630 CSR_WRITE_1(regsp, COM_REG_LCR, 631 lcr & ~LCR_DLAB); 632 CSR_WRITE_1(regsp, COM_REG_FIFO, 633 fcr | FIFO_64B_ENABLE); 634 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 635 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 636 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 637 CSR_WRITE_1(regsp, COM_REG_FIFO, 638 fcr | FIFO_64B_ENABLE); 639 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 640 641 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 642 643 if (!ISSET(iir1, IIR_64B_FIFO) && 644 ISSET(iir2, IIR_64B_FIFO)) { 645 /* It is TL16C750. */ 646 sc->sc_fifolen = 64; 647 SET(sc->sc_hwflags, COM_HW_AFE); 648 } else 649 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 650 651 if (sc->sc_fifolen == 64) 652 fifo_msg = "tl16c750"; 653 else 654 fifo_msg = "ns16750"; 655 } 656 } else 657 fifo_msg = "ns16550, broken fifo"; 658 else 659 fifo_msg = "ns8250 or ns16450, no fifo"; 660 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 661 662 fifodelay: 663 /* 664 * Some chips will clear down both Tx and Rx FIFOs when zero is 665 * written to com_fifo. If this chip is the console, writing zero 666 * results in some of the chip/FIFO description being lost, so delay 667 * printing it until now. 668 */ 669 delay(10); 670 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 671 aprint_normal(": %s, %d-byte FIFO\n", fifo_msg, sc->sc_fifolen); 672 } else { 673 aprint_normal(": %s\n", fifo_msg); 674 } 675 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 676 sc->sc_fifolen = 1; 677 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 678 } 679 680 fifodone: 681 682 tp = tty_alloc(); 683 tp->t_oproc = comstart; 684 tp->t_param = comparam; 685 tp->t_hwiflow = comhwiflow; 686 tp->t_softc = sc; 687 688 sc->sc_tty = tp; 689 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK); 690 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 691 sc->sc_rbavail = com_rbuf_size; 692 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 693 694 tty_attach(tp); 695 696 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 697 SET(sc->sc_mcr, MCR_IENABLE); 698 699 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 700 int maj; 701 702 /* locate the major number */ 703 maj = cdevsw_lookup_major(&com_cdevsw); 704 705 tp->t_dev = cn_tab->cn_dev = makedev(maj, 706 device_unit(sc->sc_dev)); 707 708 aprint_normal_dev(sc->sc_dev, "console\n"); 709 } 710 711 #ifdef KGDB 712 /* 713 * Allow kgdb to "take over" this port. If this is 714 * not the console and is the kgdb device, it has 715 * exclusive use. If it's the console _and_ the 716 * kgdb device, it doesn't. 717 */ 718 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 719 regsp->cr_iobase == comkgdbregs.cr_iobase) { 720 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 721 com_kgdb_attached = 1; 722 723 SET(sc->sc_hwflags, COM_HW_KGDB); 724 } 725 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 726 } 727 #endif 728 729 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 730 731 #ifdef RND_COM 732 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 733 RND_TYPE_TTY, RND_FLAG_DEFAULT); 734 #endif 735 736 /* if there are no enable/disable functions, assume the device 737 is always enabled */ 738 if (!sc->enable) 739 sc->enabled = 1; 740 741 com_config(sc); 742 743 SET(sc->sc_hwflags, COM_HW_DEV_OK); 744 745 if (sc->sc_poll_ticks != 0) 746 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 747 } 748 749 void 750 com_config(struct com_softc *sc) 751 { 752 struct com_regs *regsp = &sc->sc_regs; 753 754 /* Disable interrupts before configuring the device. */ 755 if (sc->sc_type == COM_TYPE_PXA2x0) 756 sc->sc_ier = IER_EUART; 757 else 758 sc->sc_ier = 0; 759 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 760 (void) CSR_READ_1(regsp, COM_REG_IIR); 761 762 /* Look for a Hayes ESP board. */ 763 if (sc->sc_type == COM_TYPE_HAYESP) { 764 765 /* Set 16550 compatibility mode */ 766 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 767 HAYESP_SETMODE); 768 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 769 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 770 HAYESP_MODE_SCALE); 771 772 /* Set RTS/CTS flow control */ 773 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 774 HAYESP_SETFLOWTYPE); 775 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 776 HAYESP_FLOW_RTS); 777 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 778 HAYESP_FLOW_CTS); 779 780 /* Set flow control levels */ 781 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 782 HAYESP_SETRXFLOW); 783 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 784 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 785 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 786 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 787 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 788 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 789 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 790 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 791 } 792 793 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 794 com_enable_debugport(sc); 795 } 796 797 #if 0 798 static int 799 comcngetc_detached(dev_t dev) 800 { 801 return 0; 802 } 803 804 static void 805 comcnputc_detached(dev_t dev, int c) 806 { 807 } 808 #endif 809 810 int 811 com_detach(device_t self, int flags) 812 { 813 struct com_softc *sc = device_private(self); 814 int maj, mn; 815 816 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 817 return EBUSY; 818 819 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 820 (flags & DETACH_SHUTDOWN) != 0) 821 return EBUSY; 822 823 if (sc->disable != NULL && sc->enabled != 0) { 824 (*sc->disable)(sc); 825 sc->enabled = 0; 826 } 827 828 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 829 comconsattached = 0; 830 cn_tab = NULL; 831 } 832 833 /* locate the major number */ 834 maj = cdevsw_lookup_major(&com_cdevsw); 835 836 /* Nuke the vnodes for any open instances. */ 837 mn = device_unit(self); 838 vdevgone(maj, mn, mn, VCHR); 839 840 mn |= COMDIALOUT_MASK; 841 vdevgone(maj, mn, mn, VCHR); 842 843 if (sc->sc_rbuf == NULL) { 844 /* 845 * Ring buffer allocation failed in the com_attach_subr, 846 * only the tty is allocated, and nothing else. 847 */ 848 tty_free(sc->sc_tty); 849 return 0; 850 } 851 852 /* Free the receive buffer. */ 853 free(sc->sc_rbuf, M_DEVBUF); 854 855 /* Detach and free the tty. */ 856 tty_detach(sc->sc_tty); 857 tty_free(sc->sc_tty); 858 859 /* Unhook the soft interrupt handler. */ 860 softint_disestablish(sc->sc_si); 861 862 #ifdef RND_COM 863 /* Unhook the entropy source. */ 864 rnd_detach_source(&sc->rnd_source); 865 #endif 866 callout_destroy(&sc->sc_diag_callout); 867 868 /* Destroy the lock. */ 869 mutex_destroy(&sc->sc_lock); 870 871 return (0); 872 } 873 874 void 875 com_shutdown(struct com_softc *sc) 876 { 877 struct tty *tp = sc->sc_tty; 878 879 mutex_spin_enter(&sc->sc_lock); 880 881 /* If we were asserting flow control, then deassert it. */ 882 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 883 com_hwiflow(sc); 884 885 /* Clear any break condition set with TIOCSBRK. */ 886 com_break(sc, 0); 887 888 /* 889 * Hang up if necessary. Wait a bit, so the other side has time to 890 * notice even if we immediately open the port again. 891 * Avoid tsleeping above splhigh(). 892 */ 893 if (ISSET(tp->t_cflag, HUPCL)) { 894 com_modem(sc, 0); 895 microuptime(&sc->sc_hup_pending); 896 sc->sc_hup_pending.tv_sec++; 897 } 898 899 /* Turn off interrupts. */ 900 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 901 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 902 if ((sc->sc_type == COM_TYPE_PXA2x0) || 903 (sc->sc_type == COM_TYPE_INGENIC) || 904 (sc->sc_type == COM_TYPE_TEGRA)) 905 sc->sc_ier |= IER_ERXTOUT; 906 } else 907 sc->sc_ier = 0; 908 909 if (sc->sc_type == COM_TYPE_PXA2x0) 910 sc->sc_ier |= IER_EUART; 911 912 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 913 914 mutex_spin_exit(&sc->sc_lock); 915 916 if (sc->disable) { 917 #ifdef DIAGNOSTIC 918 if (!sc->enabled) 919 panic("com_shutdown: not enabled?"); 920 #endif 921 (*sc->disable)(sc); 922 sc->enabled = 0; 923 } 924 } 925 926 int 927 comopen(dev_t dev, int flag, int mode, struct lwp *l) 928 { 929 struct com_softc *sc; 930 struct tty *tp; 931 int s; 932 int error; 933 934 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 935 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 936 sc->sc_rbuf == NULL) 937 return (ENXIO); 938 939 if (!device_is_active(sc->sc_dev)) 940 return (ENXIO); 941 942 #ifdef KGDB 943 /* 944 * If this is the kgdb port, no other use is permitted. 945 */ 946 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 947 return (EBUSY); 948 #endif 949 950 tp = sc->sc_tty; 951 952 /* 953 * If the device is exclusively for kernel use, deny userland 954 * open. 955 */ 956 if (ISSET(tp->t_state, TS_KERN_ONLY)) 957 return (EBUSY); 958 959 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 960 return (EBUSY); 961 962 s = spltty(); 963 964 /* 965 * Do the following iff this is a first open. 966 */ 967 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 968 struct termios t; 969 struct timeval now, diff; 970 971 tp->t_dev = dev; 972 973 if (sc->enable) { 974 if ((*sc->enable)(sc)) { 975 splx(s); 976 aprint_error_dev(sc->sc_dev, 977 "device enable failed\n"); 978 return (EIO); 979 } 980 mutex_spin_enter(&sc->sc_lock); 981 sc->enabled = 1; 982 com_config(sc); 983 } else { 984 mutex_spin_enter(&sc->sc_lock); 985 } 986 987 if (timerisset(&sc->sc_hup_pending)) { 988 microuptime(&now); 989 while (timercmp(&now, &sc->sc_hup_pending, <)) { 990 timersub(&sc->sc_hup_pending, &now, &diff); 991 const int ms = diff.tv_sec * 1000 + 992 diff.tv_usec / 1000; 993 kpause(ttclos, false, uimax(mstohz(ms), 1), 994 &sc->sc_lock); 995 microuptime(&now); 996 } 997 timerclear(&sc->sc_hup_pending); 998 } 999 1000 /* Turn on interrupts. */ 1001 sc->sc_ier = IER_ERXRDY | IER_ERLS; 1002 if (!ISSET(tp->t_cflag, CLOCAL)) 1003 sc->sc_ier |= IER_EMSC; 1004 1005 if (sc->sc_type == COM_TYPE_PXA2x0) 1006 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 1007 else if (sc->sc_type == COM_TYPE_INGENIC || 1008 sc->sc_type == COM_TYPE_TEGRA) 1009 sc->sc_ier |= IER_ERXTOUT; 1010 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1011 1012 /* Fetch the current modem control status, needed later. */ 1013 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 1014 1015 /* Clear PPS capture state on first open. */ 1016 mutex_spin_enter(&timecounter_lock); 1017 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 1018 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1019 pps_init(&sc->sc_pps_state); 1020 mutex_spin_exit(&timecounter_lock); 1021 1022 mutex_spin_exit(&sc->sc_lock); 1023 1024 /* 1025 * Initialize the termios status to the defaults. Add in the 1026 * sticky bits from TIOCSFLAGS. 1027 */ 1028 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1029 t.c_ospeed = comcons_info.rate; 1030 t.c_cflag = comcons_info.cflag; 1031 } else { 1032 t.c_ospeed = TTYDEF_SPEED; 1033 t.c_cflag = TTYDEF_CFLAG; 1034 } 1035 t.c_ispeed = t.c_ospeed; 1036 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1037 SET(t.c_cflag, CLOCAL); 1038 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1039 SET(t.c_cflag, CRTSCTS); 1040 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1041 SET(t.c_cflag, MDMBUF); 1042 /* Make sure comparam() will do something. */ 1043 tp->t_ospeed = 0; 1044 (void) comparam(tp, &t); 1045 tp->t_iflag = TTYDEF_IFLAG; 1046 tp->t_oflag = TTYDEF_OFLAG; 1047 tp->t_lflag = TTYDEF_LFLAG; 1048 ttychars(tp); 1049 ttsetwater(tp); 1050 1051 mutex_spin_enter(&sc->sc_lock); 1052 1053 /* 1054 * Turn on DTR. We must always do this, even if carrier is not 1055 * present, because otherwise we'd have to use TIOCSDTR 1056 * immediately after setting CLOCAL, which applications do not 1057 * expect. We always assert DTR while the device is open 1058 * unless explicitly requested to deassert it. 1059 */ 1060 com_modem(sc, 1); 1061 1062 /* Clear the input ring, and unblock. */ 1063 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1064 sc->sc_rbavail = com_rbuf_size; 1065 com_iflush(sc); 1066 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1067 com_hwiflow(sc); 1068 1069 #ifdef COM_DEBUG 1070 if (com_debug) 1071 comstatus(sc, "comopen "); 1072 #endif 1073 1074 mutex_spin_exit(&sc->sc_lock); 1075 } 1076 1077 splx(s); 1078 1079 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1080 if (error) 1081 goto bad; 1082 1083 error = (*tp->t_linesw->l_open)(dev, tp); 1084 if (error) 1085 goto bad; 1086 1087 return (0); 1088 1089 bad: 1090 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1091 /* 1092 * We failed to open the device, and nobody else had it opened. 1093 * Clean up the state as appropriate. 1094 */ 1095 com_shutdown(sc); 1096 } 1097 1098 return (error); 1099 } 1100 1101 int 1102 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1103 { 1104 struct com_softc *sc = 1105 device_lookup_private(&com_cd, COMUNIT(dev)); 1106 struct tty *tp = sc->sc_tty; 1107 1108 /* XXX This is for cons.c. */ 1109 if (!ISSET(tp->t_state, TS_ISOPEN)) 1110 return (0); 1111 /* 1112 * If the device is exclusively for kernel use, deny userland 1113 * close. 1114 */ 1115 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1116 return (0); 1117 1118 (*tp->t_linesw->l_close)(tp, flag); 1119 ttyclose(tp); 1120 1121 if (COM_ISALIVE(sc) == 0) 1122 return (0); 1123 1124 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1125 /* 1126 * Although we got a last close, the device may still be in 1127 * use; e.g. if this was the dialout node, and there are still 1128 * processes waiting for carrier on the non-dialout node. 1129 */ 1130 com_shutdown(sc); 1131 } 1132 1133 return (0); 1134 } 1135 1136 int 1137 comread(dev_t dev, struct uio *uio, int flag) 1138 { 1139 struct com_softc *sc = 1140 device_lookup_private(&com_cd, COMUNIT(dev)); 1141 struct tty *tp = sc->sc_tty; 1142 1143 if (COM_ISALIVE(sc) == 0) 1144 return (EIO); 1145 1146 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1147 } 1148 1149 int 1150 comwrite(dev_t dev, struct uio *uio, int flag) 1151 { 1152 struct com_softc *sc = 1153 device_lookup_private(&com_cd, COMUNIT(dev)); 1154 struct tty *tp = sc->sc_tty; 1155 1156 if (COM_ISALIVE(sc) == 0) 1157 return (EIO); 1158 1159 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1160 } 1161 1162 int 1163 compoll(dev_t dev, int events, struct lwp *l) 1164 { 1165 struct com_softc *sc = 1166 device_lookup_private(&com_cd, COMUNIT(dev)); 1167 struct tty *tp = sc->sc_tty; 1168 1169 if (COM_ISALIVE(sc) == 0) 1170 return (POLLHUP); 1171 1172 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1173 } 1174 1175 struct tty * 1176 comtty(dev_t dev) 1177 { 1178 struct com_softc *sc = 1179 device_lookup_private(&com_cd, COMUNIT(dev)); 1180 struct tty *tp = sc->sc_tty; 1181 1182 return (tp); 1183 } 1184 1185 int 1186 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1187 { 1188 struct com_softc *sc; 1189 struct tty *tp; 1190 int error; 1191 1192 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1193 if (sc == NULL) 1194 return ENXIO; 1195 if (COM_ISALIVE(sc) == 0) 1196 return (EIO); 1197 1198 tp = sc->sc_tty; 1199 1200 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1201 if (error != EPASSTHROUGH) 1202 return (error); 1203 1204 error = ttioctl(tp, cmd, data, flag, l); 1205 if (error != EPASSTHROUGH) 1206 return (error); 1207 1208 error = 0; 1209 switch (cmd) { 1210 case TIOCSFLAGS: 1211 error = kauth_authorize_device_tty(l->l_cred, 1212 KAUTH_DEVICE_TTY_PRIVSET, tp); 1213 break; 1214 default: 1215 /* nothing */ 1216 break; 1217 } 1218 if (error) { 1219 return error; 1220 } 1221 1222 mutex_spin_enter(&sc->sc_lock); 1223 1224 switch (cmd) { 1225 case TIOCSBRK: 1226 com_break(sc, 1); 1227 break; 1228 1229 case TIOCCBRK: 1230 com_break(sc, 0); 1231 break; 1232 1233 case TIOCSDTR: 1234 com_modem(sc, 1); 1235 break; 1236 1237 case TIOCCDTR: 1238 com_modem(sc, 0); 1239 break; 1240 1241 case TIOCGFLAGS: 1242 *(int *)data = sc->sc_swflags; 1243 break; 1244 1245 case TIOCSFLAGS: 1246 sc->sc_swflags = *(int *)data; 1247 break; 1248 1249 case TIOCMSET: 1250 case TIOCMBIS: 1251 case TIOCMBIC: 1252 tiocm_to_com(sc, cmd, *(int *)data); 1253 break; 1254 1255 case TIOCMGET: 1256 *(int *)data = com_to_tiocm(sc); 1257 break; 1258 1259 case PPS_IOC_CREATE: 1260 case PPS_IOC_DESTROY: 1261 case PPS_IOC_GETPARAMS: 1262 case PPS_IOC_SETPARAMS: 1263 case PPS_IOC_GETCAP: 1264 case PPS_IOC_FETCH: 1265 #ifdef PPS_SYNC 1266 case PPS_IOC_KCBIND: 1267 #endif 1268 mutex_spin_enter(&timecounter_lock); 1269 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1270 mutex_spin_exit(&timecounter_lock); 1271 break; 1272 1273 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1274 mutex_spin_enter(&timecounter_lock); 1275 #ifndef PPS_TRAILING_EDGE 1276 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1277 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1278 #else 1279 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1280 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1281 #endif 1282 mutex_spin_exit(&timecounter_lock); 1283 break; 1284 1285 default: 1286 error = EPASSTHROUGH; 1287 break; 1288 } 1289 1290 mutex_spin_exit(&sc->sc_lock); 1291 1292 #ifdef COM_DEBUG 1293 if (com_debug) 1294 comstatus(sc, "comioctl "); 1295 #endif 1296 1297 return (error); 1298 } 1299 1300 integrate void 1301 com_schedrx(struct com_softc *sc) 1302 { 1303 1304 sc->sc_rx_ready = 1; 1305 1306 /* Wake up the poller. */ 1307 softint_schedule(sc->sc_si); 1308 } 1309 1310 void 1311 com_break(struct com_softc *sc, int onoff) 1312 { 1313 1314 if (onoff) 1315 SET(sc->sc_lcr, LCR_SBREAK); 1316 else 1317 CLR(sc->sc_lcr, LCR_SBREAK); 1318 1319 if (!sc->sc_heldchange) { 1320 if (sc->sc_tx_busy) { 1321 sc->sc_heldtbc = sc->sc_tbc; 1322 sc->sc_tbc = 0; 1323 sc->sc_heldchange = 1; 1324 } else 1325 com_loadchannelregs(sc); 1326 } 1327 } 1328 1329 void 1330 com_modem(struct com_softc *sc, int onoff) 1331 { 1332 1333 if (sc->sc_mcr_dtr == 0) 1334 return; 1335 1336 if (onoff) 1337 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1338 else 1339 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1340 1341 if (!sc->sc_heldchange) { 1342 if (sc->sc_tx_busy) { 1343 sc->sc_heldtbc = sc->sc_tbc; 1344 sc->sc_tbc = 0; 1345 sc->sc_heldchange = 1; 1346 } else 1347 com_loadchannelregs(sc); 1348 } 1349 } 1350 1351 void 1352 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1353 { 1354 u_char combits; 1355 1356 combits = 0; 1357 if (ISSET(ttybits, TIOCM_DTR)) 1358 SET(combits, MCR_DTR); 1359 if (ISSET(ttybits, TIOCM_RTS)) 1360 SET(combits, MCR_RTS); 1361 1362 switch (how) { 1363 case TIOCMBIC: 1364 CLR(sc->sc_mcr, combits); 1365 break; 1366 1367 case TIOCMBIS: 1368 SET(sc->sc_mcr, combits); 1369 break; 1370 1371 case TIOCMSET: 1372 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1373 SET(sc->sc_mcr, combits); 1374 break; 1375 } 1376 1377 if (!sc->sc_heldchange) { 1378 if (sc->sc_tx_busy) { 1379 sc->sc_heldtbc = sc->sc_tbc; 1380 sc->sc_tbc = 0; 1381 sc->sc_heldchange = 1; 1382 } else 1383 com_loadchannelregs(sc); 1384 } 1385 } 1386 1387 int 1388 com_to_tiocm(struct com_softc *sc) 1389 { 1390 u_char combits; 1391 int ttybits = 0; 1392 1393 combits = sc->sc_mcr; 1394 if (ISSET(combits, MCR_DTR)) 1395 SET(ttybits, TIOCM_DTR); 1396 if (ISSET(combits, MCR_RTS)) 1397 SET(ttybits, TIOCM_RTS); 1398 1399 combits = sc->sc_msr; 1400 if (sc->sc_type == COM_TYPE_INGENIC) { 1401 SET(ttybits, TIOCM_CD); 1402 } else { 1403 if (ISSET(combits, MSR_DCD)) 1404 SET(ttybits, TIOCM_CD); 1405 } 1406 if (ISSET(combits, MSR_CTS)) 1407 SET(ttybits, TIOCM_CTS); 1408 if (ISSET(combits, MSR_DSR)) 1409 SET(ttybits, TIOCM_DSR); 1410 if (ISSET(combits, MSR_RI | MSR_TERI)) 1411 SET(ttybits, TIOCM_RI); 1412 1413 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1414 SET(ttybits, TIOCM_LE); 1415 1416 return (ttybits); 1417 } 1418 1419 static u_char 1420 cflag2lcr(tcflag_t cflag) 1421 { 1422 u_char lcr = 0; 1423 1424 switch (ISSET(cflag, CSIZE)) { 1425 case CS5: 1426 SET(lcr, LCR_5BITS); 1427 break; 1428 case CS6: 1429 SET(lcr, LCR_6BITS); 1430 break; 1431 case CS7: 1432 SET(lcr, LCR_7BITS); 1433 break; 1434 case CS8: 1435 SET(lcr, LCR_8BITS); 1436 break; 1437 } 1438 if (ISSET(cflag, PARENB)) { 1439 SET(lcr, LCR_PENAB); 1440 if (!ISSET(cflag, PARODD)) 1441 SET(lcr, LCR_PEVEN); 1442 } 1443 if (ISSET(cflag, CSTOPB)) 1444 SET(lcr, LCR_STOPB); 1445 1446 return (lcr); 1447 } 1448 1449 int 1450 comparam(struct tty *tp, struct termios *t) 1451 { 1452 struct com_softc *sc = 1453 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1454 int ospeed; 1455 u_char lcr; 1456 1457 if (COM_ISALIVE(sc) == 0) 1458 return (EIO); 1459 1460 if (sc->sc_type == COM_TYPE_HAYESP) { 1461 int prescaler, speed; 1462 1463 /* 1464 * Calculate UART clock prescaler. It should be in 1465 * range of 0 .. 3. 1466 */ 1467 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1468 prescaler++, speed /= 2) 1469 if ((ospeed = comspeed(speed, sc->sc_frequency, 1470 sc->sc_type)) > 0) 1471 break; 1472 1473 if (prescaler == 4) 1474 return (EINVAL); 1475 sc->sc_prescaler = prescaler; 1476 } else 1477 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1478 1479 /* Check requested parameters. */ 1480 if (ospeed < 0) 1481 return (EINVAL); 1482 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1483 return (EINVAL); 1484 1485 /* 1486 * For the console, always force CLOCAL and !HUPCL, so that the port 1487 * is always active. 1488 */ 1489 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1490 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1491 SET(t->c_cflag, CLOCAL); 1492 CLR(t->c_cflag, HUPCL); 1493 } 1494 1495 /* 1496 * If there were no changes, don't do anything. This avoids dropping 1497 * input and improves performance when all we did was frob things like 1498 * VMIN and VTIME. 1499 */ 1500 if (tp->t_ospeed == t->c_ospeed && 1501 tp->t_cflag == t->c_cflag) 1502 return (0); 1503 1504 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1505 1506 mutex_spin_enter(&sc->sc_lock); 1507 1508 sc->sc_lcr = lcr; 1509 1510 /* 1511 * If we're not in a mode that assumes a connection is present, then 1512 * ignore carrier changes. 1513 */ 1514 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1515 sc->sc_msr_dcd = 0; 1516 else 1517 sc->sc_msr_dcd = MSR_DCD; 1518 /* 1519 * Set the flow control pins depending on the current flow control 1520 * mode. 1521 */ 1522 if (ISSET(t->c_cflag, CRTSCTS)) { 1523 sc->sc_mcr_dtr = MCR_DTR; 1524 sc->sc_mcr_rts = MCR_RTS; 1525 sc->sc_msr_cts = MSR_CTS; 1526 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1527 SET(sc->sc_mcr, MCR_AFE); 1528 } else { 1529 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1530 } 1531 } else if (ISSET(t->c_cflag, MDMBUF)) { 1532 /* 1533 * For DTR/DCD flow control, make sure we don't toggle DTR for 1534 * carrier detection. 1535 */ 1536 sc->sc_mcr_dtr = 0; 1537 sc->sc_mcr_rts = MCR_DTR; 1538 sc->sc_msr_cts = MSR_DCD; 1539 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1540 CLR(sc->sc_mcr, MCR_AFE); 1541 } else { 1542 sc->sc_efr = 0; 1543 } 1544 } else { 1545 /* 1546 * If no flow control, then always set RTS. This will make 1547 * the other side happy if it mistakenly thinks we're doing 1548 * RTS/CTS flow control. 1549 */ 1550 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1551 sc->sc_mcr_rts = 0; 1552 sc->sc_msr_cts = 0; 1553 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1554 CLR(sc->sc_mcr, MCR_AFE); 1555 } else { 1556 sc->sc_efr = 0; 1557 } 1558 if (ISSET(sc->sc_mcr, MCR_DTR)) 1559 SET(sc->sc_mcr, MCR_RTS); 1560 else 1561 CLR(sc->sc_mcr, MCR_RTS); 1562 } 1563 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1564 1565 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1566 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1567 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1568 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1569 1570 sc->sc_dlbl = ospeed; 1571 sc->sc_dlbh = ospeed >> 8; 1572 1573 /* 1574 * Set the FIFO threshold based on the receive speed. 1575 * 1576 * * If it's a low speed, it's probably a mouse or some other 1577 * interactive device, so set the threshold low. 1578 * * If it's a high speed, trim the trigger level down to prevent 1579 * overflows. 1580 * * Otherwise set it a bit higher. 1581 */ 1582 if (sc->sc_type == COM_TYPE_HAYESP) { 1583 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1584 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1585 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1586 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1587 if (t->c_ospeed <= 1200) 1588 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1589 else if (t->c_ospeed <= 38400) 1590 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1591 else 1592 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1593 } else { 1594 sc->sc_fifo = 0; 1595 } 1596 1597 if (sc->sc_type == COM_TYPE_INGENIC) 1598 sc->sc_fifo |= FIFO_UART_ON; 1599 1600 /* And copy to tty. */ 1601 tp->t_ispeed = t->c_ospeed; 1602 tp->t_ospeed = t->c_ospeed; 1603 tp->t_cflag = t->c_cflag; 1604 1605 if (!sc->sc_heldchange) { 1606 if (sc->sc_tx_busy) { 1607 sc->sc_heldtbc = sc->sc_tbc; 1608 sc->sc_tbc = 0; 1609 sc->sc_heldchange = 1; 1610 } else 1611 com_loadchannelregs(sc); 1612 } 1613 1614 if (!ISSET(t->c_cflag, CHWFLOW)) { 1615 /* Disable the high water mark. */ 1616 sc->sc_r_hiwat = 0; 1617 sc->sc_r_lowat = 0; 1618 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1619 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1620 com_schedrx(sc); 1621 } 1622 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1623 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1624 com_hwiflow(sc); 1625 } 1626 } else { 1627 sc->sc_r_hiwat = com_rbuf_hiwat; 1628 sc->sc_r_lowat = com_rbuf_lowat; 1629 } 1630 1631 mutex_spin_exit(&sc->sc_lock); 1632 1633 /* 1634 * Update the tty layer's idea of the carrier bit, in case we changed 1635 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1636 * explicit request. 1637 */ 1638 if (sc->sc_type == COM_TYPE_INGENIC) { 1639 /* no DCD here */ 1640 (void) (*tp->t_linesw->l_modem)(tp, 1); 1641 } else 1642 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1643 1644 #ifdef COM_DEBUG 1645 if (com_debug) 1646 comstatus(sc, "comparam "); 1647 #endif 1648 1649 if (!ISSET(t->c_cflag, CHWFLOW)) { 1650 if (sc->sc_tx_stopped) { 1651 sc->sc_tx_stopped = 0; 1652 comstart(tp); 1653 } 1654 } 1655 1656 return (0); 1657 } 1658 1659 void 1660 com_iflush(struct com_softc *sc) 1661 { 1662 struct com_regs *regsp = &sc->sc_regs; 1663 uint8_t fifo; 1664 #ifdef DIAGNOSTIC 1665 int reg; 1666 #endif 1667 int timo; 1668 1669 #ifdef DIAGNOSTIC 1670 reg = 0xffff; 1671 #endif 1672 timo = 50000; 1673 /* flush any pending I/O */ 1674 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1675 && --timo) 1676 #ifdef DIAGNOSTIC 1677 reg = 1678 #else 1679 (void) 1680 #endif 1681 CSR_READ_1(regsp, COM_REG_RXDATA); 1682 #ifdef DIAGNOSTIC 1683 if (!timo) 1684 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1685 #endif 1686 1687 switch (sc->sc_type) { 1688 case COM_TYPE_16750: 1689 case COM_TYPE_DW_APB: 1690 /* 1691 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1692 * This should prevent triggering busy interrupt while 1693 * manipulating divisors. 1694 */ 1695 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1696 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1697 CSR_WRITE_1(regsp, COM_REG_FIFO, 1698 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1699 delay(100); 1700 break; 1701 } 1702 } 1703 1704 void 1705 com_loadchannelregs(struct com_softc *sc) 1706 { 1707 struct com_regs *regsp = &sc->sc_regs; 1708 1709 /* XXXXX necessary? */ 1710 com_iflush(sc); 1711 1712 if (sc->sc_type == COM_TYPE_PXA2x0) 1713 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1714 else 1715 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1716 1717 if (sc->sc_type == COM_TYPE_OMAP) { 1718 /* disable before changing settings */ 1719 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1720 } 1721 1722 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1723 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1724 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1725 /* no EFR on alchemy */ 1726 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1727 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1728 } 1729 if (sc->sc_type == COM_TYPE_AU1x00) { 1730 /* alchemy has single separate 16-bit clock divisor register */ 1731 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1732 (sc->sc_dlbh << 8)); 1733 } else { 1734 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1735 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1736 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1737 } 1738 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1739 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1740 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1741 if (sc->sc_type == COM_TYPE_HAYESP) { 1742 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1743 HAYESP_SETPRESCALER); 1744 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1745 sc->sc_prescaler); 1746 } 1747 if (sc->sc_type == COM_TYPE_OMAP) { 1748 /* setup the fifos. the FCR value is not used as long 1749 as SCR[6] and SCR[7] are 0, which they are at reset 1750 and we never touch the SCR register */ 1751 uint8_t rx_fifo_trig = 40; 1752 uint8_t tx_fifo_trig = 60; 1753 uint8_t rx_start = 8; 1754 uint8_t rx_halt = 60; 1755 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1756 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1757 1758 /* enable access to TCR & TLR */ 1759 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1760 1761 /* write tcr and tlr values */ 1762 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1763 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1764 1765 /* disable access to TCR & TLR */ 1766 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1767 1768 /* enable again, but mode is based on speed */ 1769 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1770 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1771 } else { 1772 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1773 } 1774 } 1775 1776 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1777 } 1778 1779 int 1780 comhwiflow(struct tty *tp, int block) 1781 { 1782 struct com_softc *sc = 1783 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1784 1785 if (COM_ISALIVE(sc) == 0) 1786 return (0); 1787 1788 if (sc->sc_mcr_rts == 0) 1789 return (0); 1790 1791 mutex_spin_enter(&sc->sc_lock); 1792 1793 if (block) { 1794 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1795 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1796 com_hwiflow(sc); 1797 } 1798 } else { 1799 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1800 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1801 com_schedrx(sc); 1802 } 1803 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1804 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1805 com_hwiflow(sc); 1806 } 1807 } 1808 1809 mutex_spin_exit(&sc->sc_lock); 1810 return (1); 1811 } 1812 1813 /* 1814 * (un)block input via hw flowcontrol 1815 */ 1816 void 1817 com_hwiflow(struct com_softc *sc) 1818 { 1819 struct com_regs *regsp= &sc->sc_regs; 1820 1821 if (sc->sc_mcr_rts == 0) 1822 return; 1823 1824 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1825 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1826 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1827 } else { 1828 SET(sc->sc_mcr, sc->sc_mcr_rts); 1829 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1830 } 1831 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1832 } 1833 1834 1835 void 1836 comstart(struct tty *tp) 1837 { 1838 struct com_softc *sc = 1839 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1840 struct com_regs *regsp = &sc->sc_regs; 1841 int s; 1842 1843 if (COM_ISALIVE(sc) == 0) 1844 return; 1845 1846 s = spltty(); 1847 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1848 goto out; 1849 if (sc->sc_tx_stopped) 1850 goto out; 1851 if (!ttypull(tp)) 1852 goto out; 1853 1854 /* Grab the first contiguous region of buffer space. */ 1855 { 1856 u_char *tba; 1857 int tbc; 1858 1859 tba = tp->t_outq.c_cf; 1860 tbc = ndqb(&tp->t_outq, 0); 1861 1862 mutex_spin_enter(&sc->sc_lock); 1863 1864 sc->sc_tba = tba; 1865 sc->sc_tbc = tbc; 1866 } 1867 1868 SET(tp->t_state, TS_BUSY); 1869 sc->sc_tx_busy = 1; 1870 1871 /* Enable transmit completion interrupts if necessary. */ 1872 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1873 SET(sc->sc_ier, IER_ETXRDY); 1874 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1875 } 1876 1877 /* Output the first chunk of the contiguous buffer. */ 1878 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1879 u_int n; 1880 1881 n = sc->sc_tbc; 1882 if (n > sc->sc_fifolen) 1883 n = sc->sc_fifolen; 1884 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1885 sc->sc_tbc -= n; 1886 sc->sc_tba += n; 1887 } 1888 1889 mutex_spin_exit(&sc->sc_lock); 1890 out: 1891 splx(s); 1892 return; 1893 } 1894 1895 /* 1896 * Stop output on a line. 1897 */ 1898 void 1899 comstop(struct tty *tp, int flag) 1900 { 1901 struct com_softc *sc = 1902 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1903 1904 mutex_spin_enter(&sc->sc_lock); 1905 if (ISSET(tp->t_state, TS_BUSY)) { 1906 /* Stop transmitting at the next chunk. */ 1907 sc->sc_tbc = 0; 1908 sc->sc_heldtbc = 0; 1909 if (!ISSET(tp->t_state, TS_TTSTOP)) 1910 SET(tp->t_state, TS_FLUSH); 1911 } 1912 mutex_spin_exit(&sc->sc_lock); 1913 } 1914 1915 void 1916 comdiag(void *arg) 1917 { 1918 struct com_softc *sc = arg; 1919 int overflows, floods; 1920 1921 mutex_spin_enter(&sc->sc_lock); 1922 overflows = sc->sc_overflows; 1923 sc->sc_overflows = 0; 1924 floods = sc->sc_floods; 1925 sc->sc_floods = 0; 1926 sc->sc_errors = 0; 1927 mutex_spin_exit(&sc->sc_lock); 1928 1929 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1930 device_xname(sc->sc_dev), 1931 overflows, overflows == 1 ? "" : "s", 1932 floods, floods == 1 ? "" : "s"); 1933 } 1934 1935 integrate void 1936 com_rxsoft(struct com_softc *sc, struct tty *tp) 1937 { 1938 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1939 u_char *get, *end; 1940 u_int cc, scc; 1941 u_char lsr; 1942 int code; 1943 1944 end = sc->sc_ebuf; 1945 get = sc->sc_rbget; 1946 scc = cc = com_rbuf_size - sc->sc_rbavail; 1947 1948 if (cc == com_rbuf_size) { 1949 sc->sc_floods++; 1950 if (sc->sc_errors++ == 0) 1951 callout_reset(&sc->sc_diag_callout, 60 * hz, 1952 comdiag, sc); 1953 } 1954 1955 /* If not yet open, drop the entire buffer content here */ 1956 if (!ISSET(tp->t_state, TS_ISOPEN)) { 1957 get += cc << 1; 1958 if (get >= end) 1959 get -= com_rbuf_size << 1; 1960 cc = 0; 1961 } 1962 while (cc) { 1963 code = get[0]; 1964 lsr = get[1]; 1965 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 1966 if (ISSET(lsr, LSR_OE)) { 1967 sc->sc_overflows++; 1968 if (sc->sc_errors++ == 0) 1969 callout_reset(&sc->sc_diag_callout, 1970 60 * hz, comdiag, sc); 1971 } 1972 if (ISSET(lsr, LSR_BI | LSR_FE)) 1973 SET(code, TTY_FE); 1974 if (ISSET(lsr, LSR_PE)) 1975 SET(code, TTY_PE); 1976 } 1977 if ((*rint)(code, tp) == -1) { 1978 /* 1979 * The line discipline's buffer is out of space. 1980 */ 1981 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1982 /* 1983 * We're either not using flow control, or the 1984 * line discipline didn't tell us to block for 1985 * some reason. Either way, we have no way to 1986 * know when there's more space available, so 1987 * just drop the rest of the data. 1988 */ 1989 get += cc << 1; 1990 if (get >= end) 1991 get -= com_rbuf_size << 1; 1992 cc = 0; 1993 } else { 1994 /* 1995 * Don't schedule any more receive processing 1996 * until the line discipline tells us there's 1997 * space available (through comhwiflow()). 1998 * Leave the rest of the data in the input 1999 * buffer. 2000 */ 2001 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 2002 } 2003 break; 2004 } 2005 get += 2; 2006 if (get >= end) 2007 get = sc->sc_rbuf; 2008 cc--; 2009 } 2010 2011 if (cc != scc) { 2012 sc->sc_rbget = get; 2013 mutex_spin_enter(&sc->sc_lock); 2014 2015 cc = sc->sc_rbavail += scc - cc; 2016 /* Buffers should be ok again, release possible block. */ 2017 if (cc >= sc->sc_r_lowat) { 2018 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2019 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2020 SET(sc->sc_ier, IER_ERXRDY); 2021 if (sc->sc_type == COM_TYPE_PXA2x0) 2022 SET(sc->sc_ier, IER_ERXTOUT); 2023 if (sc->sc_type == COM_TYPE_INGENIC || 2024 sc->sc_type == COM_TYPE_TEGRA) 2025 SET(sc->sc_ier, IER_ERXTOUT); 2026 2027 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 2028 sc->sc_ier); 2029 } 2030 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 2031 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2032 com_hwiflow(sc); 2033 } 2034 } 2035 mutex_spin_exit(&sc->sc_lock); 2036 } 2037 } 2038 2039 integrate void 2040 com_txsoft(struct com_softc *sc, struct tty *tp) 2041 { 2042 2043 CLR(tp->t_state, TS_BUSY); 2044 if (ISSET(tp->t_state, TS_FLUSH)) 2045 CLR(tp->t_state, TS_FLUSH); 2046 else 2047 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2048 (*tp->t_linesw->l_start)(tp); 2049 } 2050 2051 integrate void 2052 com_stsoft(struct com_softc *sc, struct tty *tp) 2053 { 2054 u_char msr, delta; 2055 2056 mutex_spin_enter(&sc->sc_lock); 2057 msr = sc->sc_msr; 2058 delta = sc->sc_msr_delta; 2059 sc->sc_msr_delta = 0; 2060 mutex_spin_exit(&sc->sc_lock); 2061 2062 if (ISSET(delta, sc->sc_msr_dcd)) { 2063 /* 2064 * Inform the tty layer that carrier detect changed. 2065 */ 2066 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2067 } 2068 2069 if (ISSET(delta, sc->sc_msr_cts)) { 2070 /* Block or unblock output according to flow control. */ 2071 if (ISSET(msr, sc->sc_msr_cts)) { 2072 sc->sc_tx_stopped = 0; 2073 (*tp->t_linesw->l_start)(tp); 2074 } else { 2075 sc->sc_tx_stopped = 1; 2076 } 2077 } 2078 2079 #ifdef COM_DEBUG 2080 if (com_debug) 2081 comstatus(sc, "com_stsoft"); 2082 #endif 2083 } 2084 2085 void 2086 comsoft(void *arg) 2087 { 2088 struct com_softc *sc = arg; 2089 struct tty *tp; 2090 2091 if (COM_ISALIVE(sc) == 0) 2092 return; 2093 2094 tp = sc->sc_tty; 2095 2096 if (sc->sc_rx_ready) { 2097 sc->sc_rx_ready = 0; 2098 com_rxsoft(sc, tp); 2099 } 2100 2101 if (sc->sc_st_check) { 2102 sc->sc_st_check = 0; 2103 com_stsoft(sc, tp); 2104 } 2105 2106 if (sc->sc_tx_done) { 2107 sc->sc_tx_done = 0; 2108 com_txsoft(sc, tp); 2109 } 2110 } 2111 2112 int 2113 comintr(void *arg) 2114 { 2115 struct com_softc *sc = arg; 2116 struct com_regs *regsp = &sc->sc_regs; 2117 2118 u_char *put, *end; 2119 u_int cc; 2120 u_char lsr, iir; 2121 2122 if (COM_ISALIVE(sc) == 0) 2123 return (0); 2124 2125 KASSERT(regsp != NULL); 2126 2127 mutex_spin_enter(&sc->sc_lock); 2128 iir = CSR_READ_1(regsp, COM_REG_IIR); 2129 2130 /* Handle ns16750-specific busy interrupt. */ 2131 if (sc->sc_type == COM_TYPE_16750 && 2132 (iir & IIR_BUSY) == IIR_BUSY) { 2133 for (int timeout = 10000; 2134 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2135 if (timeout <= 0) { 2136 aprint_error_dev(sc->sc_dev, 2137 "timeout while waiting for BUSY interrupt " 2138 "acknowledge\n"); 2139 mutex_spin_exit(&sc->sc_lock); 2140 return (0); 2141 } 2142 2143 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2144 iir = CSR_READ_1(regsp, COM_REG_IIR); 2145 } 2146 2147 /* DesignWare APB UART BUSY interrupt */ 2148 if (sc->sc_type == COM_TYPE_DW_APB && 2149 (iir & IIR_BUSY) == IIR_BUSY) { 2150 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 2151 (void)CSR_READ_1(regsp, COM_REG_USR); 2152 } else if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2153 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2154 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2155 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2156 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2157 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2158 CSR_WRITE_1(regsp, COM_REG_HALT, 2159 HALT_CHCFG_EN | HALT_CHCFG_UD); 2160 for (int timeout = 10000000; 2161 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2162 timeout--) { 2163 if (timeout <= 0) { 2164 aprint_error_dev(sc->sc_dev, 2165 "timeout while waiting for HALT " 2166 "update acknowledge 0x%x 0x%x\n", 2167 CSR_READ_1(regsp, COM_REG_HALT), 2168 CSR_READ_1(regsp, COM_REG_USR)); 2169 break; 2170 } 2171 } 2172 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2173 (void)CSR_READ_1(regsp, COM_REG_USR); 2174 } else { 2175 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2176 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2177 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2178 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2179 } 2180 } 2181 2182 end = sc->sc_ebuf; 2183 put = sc->sc_rbput; 2184 cc = sc->sc_rbavail; 2185 2186 if (ISSET(iir, IIR_NOPEND)) { 2187 if (ISSET(sc->sc_hwflags, COM_HW_BROKEN_ETXRDY)) 2188 goto do_tx; 2189 mutex_spin_exit(&sc->sc_lock); 2190 return (0); 2191 } 2192 2193 again: do { 2194 u_char msr, delta; 2195 2196 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2197 if (ISSET(lsr, LSR_BI)) { 2198 int cn_trapped = 0; /* see above: cn_trap() */ 2199 2200 cn_check_magic(sc->sc_tty->t_dev, 2201 CNC_BREAK, com_cnm_state); 2202 if (cn_trapped) 2203 continue; 2204 #if defined(KGDB) && !defined(DDB) 2205 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2206 kgdb_connect(1); 2207 continue; 2208 } 2209 #endif 2210 } 2211 2212 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2213 lsr |= LSR_RXRDY; 2214 2215 if (ISSET(lsr, LSR_RCV_MASK) && 2216 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2217 while (cc > 0) { 2218 int cn_trapped = 0; 2219 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2220 put[1] = lsr; 2221 cn_check_magic(sc->sc_tty->t_dev, 2222 put[0], com_cnm_state); 2223 if (cn_trapped) 2224 goto next; 2225 put += 2; 2226 if (put >= end) 2227 put = sc->sc_rbuf; 2228 cc--; 2229 next: 2230 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2231 if (!ISSET(lsr, LSR_RCV_MASK)) 2232 break; 2233 } 2234 2235 /* 2236 * Current string of incoming characters ended because 2237 * no more data was available or we ran out of space. 2238 * Schedule a receive event if any data was received. 2239 * If we're out of space, turn off receive interrupts. 2240 */ 2241 sc->sc_rbput = put; 2242 sc->sc_rbavail = cc; 2243 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2244 sc->sc_rx_ready = 1; 2245 2246 /* 2247 * See if we are in danger of overflowing a buffer. If 2248 * so, use hardware flow control to ease the pressure. 2249 */ 2250 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2251 cc < sc->sc_r_hiwat) { 2252 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2253 com_hwiflow(sc); 2254 } 2255 2256 /* 2257 * If we're out of space, disable receive interrupts 2258 * until the queue has drained a bit. 2259 */ 2260 if (!cc) { 2261 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2262 switch (sc->sc_type) { 2263 case COM_TYPE_PXA2x0: 2264 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2265 break; 2266 case COM_TYPE_INGENIC: 2267 case COM_TYPE_TEGRA: 2268 CLR(sc->sc_ier, 2269 IER_ERXRDY | IER_ERXTOUT); 2270 break; 2271 default: 2272 CLR(sc->sc_ier, IER_ERXRDY); 2273 break; 2274 } 2275 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2276 } 2277 } else { 2278 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2279 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2280 continue; 2281 } 2282 } 2283 2284 msr = CSR_READ_1(regsp, COM_REG_MSR); 2285 delta = msr ^ sc->sc_msr; 2286 sc->sc_msr = msr; 2287 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2288 (delta & MSR_DCD)) { 2289 mutex_spin_enter(&timecounter_lock); 2290 pps_capture(&sc->sc_pps_state); 2291 pps_event(&sc->sc_pps_state, 2292 (msr & MSR_DCD) ? 2293 PPS_CAPTUREASSERT : 2294 PPS_CAPTURECLEAR); 2295 mutex_spin_exit(&timecounter_lock); 2296 } 2297 2298 /* 2299 * Process normal status changes 2300 */ 2301 if (ISSET(delta, sc->sc_msr_mask)) { 2302 SET(sc->sc_msr_delta, delta); 2303 2304 /* 2305 * Stop output immediately if we lose the output 2306 * flow control signal or carrier detect. 2307 */ 2308 if (ISSET(~msr, sc->sc_msr_mask)) { 2309 sc->sc_tbc = 0; 2310 sc->sc_heldtbc = 0; 2311 #ifdef COM_DEBUG 2312 if (com_debug) 2313 comstatus(sc, "comintr "); 2314 #endif 2315 } 2316 2317 sc->sc_st_check = 1; 2318 } 2319 } while (!ISSET((iir = 2320 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2321 /* 2322 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2323 * by IIR read, so we can't do this way: `process all interrupts, 2324 * then do TX if possible'. 2325 */ 2326 (iir & IIR_IMASK) != IIR_TXRDY); 2327 2328 do_tx: 2329 /* 2330 * Read LSR again, since there may be an interrupt between 2331 * the last LSR read and IIR read above. 2332 */ 2333 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2334 2335 /* 2336 * See if data can be transmitted as well. 2337 * Schedule tx done event if no data left 2338 * and tty was marked busy. 2339 */ 2340 if (ISSET(lsr, LSR_TXRDY)) { 2341 /* 2342 * If we've delayed a parameter change, do it now, and restart 2343 * output. 2344 */ 2345 if (sc->sc_heldchange) { 2346 com_loadchannelregs(sc); 2347 sc->sc_heldchange = 0; 2348 sc->sc_tbc = sc->sc_heldtbc; 2349 sc->sc_heldtbc = 0; 2350 } 2351 2352 /* Output the next chunk of the contiguous buffer, if any. */ 2353 if (sc->sc_tbc > 0) { 2354 u_int n; 2355 2356 n = sc->sc_tbc; 2357 if (n > sc->sc_fifolen) 2358 n = sc->sc_fifolen; 2359 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2360 sc->sc_tbc -= n; 2361 sc->sc_tba += n; 2362 } else { 2363 /* Disable transmit completion interrupts if necessary. */ 2364 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2365 CLR(sc->sc_ier, IER_ETXRDY); 2366 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2367 } 2368 if (sc->sc_tx_busy) { 2369 sc->sc_tx_busy = 0; 2370 sc->sc_tx_done = 1; 2371 } 2372 } 2373 } 2374 2375 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2376 goto again; 2377 2378 mutex_spin_exit(&sc->sc_lock); 2379 2380 /* Wake up the poller. */ 2381 if ((sc->sc_rx_ready | sc->sc_st_check | sc->sc_tx_done) != 0) 2382 softint_schedule(sc->sc_si); 2383 2384 #ifdef RND_COM 2385 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2386 #endif 2387 2388 return (1); 2389 } 2390 2391 /* 2392 * The following functions are polled getc and putc routines, shared 2393 * by the console and kgdb glue. 2394 * 2395 * The read-ahead code is so that you can detect pending in-band 2396 * cn_magic in polled mode while doing output rather than having to 2397 * wait until the kernel decides it needs input. 2398 */ 2399 2400 #define MAX_READAHEAD 20 2401 static int com_readahead[MAX_READAHEAD]; 2402 static int com_readaheadcount = 0; 2403 2404 int 2405 com_common_getc(dev_t dev, struct com_regs *regsp) 2406 { 2407 int s = splserial(); 2408 u_char stat, c; 2409 2410 /* got a character from reading things earlier */ 2411 if (com_readaheadcount > 0) { 2412 int i; 2413 2414 c = com_readahead[0]; 2415 for (i = 1; i < com_readaheadcount; i++) { 2416 com_readahead[i-1] = com_readahead[i]; 2417 } 2418 com_readaheadcount--; 2419 splx(s); 2420 return (c); 2421 } 2422 2423 /* don't block until a character becomes available */ 2424 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2425 splx(s); 2426 return -1; 2427 } 2428 2429 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2430 stat = CSR_READ_1(regsp, COM_REG_IIR); 2431 { 2432 int cn_trapped = 0; /* required by cn_trap, see above */ 2433 #ifdef DDB 2434 extern int db_active; 2435 if (!db_active) 2436 #endif 2437 cn_check_magic(dev, c, com_cnm_state); 2438 } 2439 splx(s); 2440 return (c); 2441 } 2442 2443 static void 2444 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead) 2445 { 2446 int s = splserial(); 2447 int cin, stat, timo; 2448 2449 if (with_readahead && com_readaheadcount < MAX_READAHEAD 2450 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2451 int cn_trapped = 0; 2452 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2453 stat = CSR_READ_1(regsp, COM_REG_IIR); 2454 cn_check_magic(dev, cin, com_cnm_state); 2455 com_readahead[com_readaheadcount++] = cin; 2456 } 2457 2458 /* wait for any pending transmission to finish */ 2459 timo = 150000; 2460 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2461 continue; 2462 2463 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2464 COM_BARRIER(regsp, BR | BW); 2465 2466 splx(s); 2467 } 2468 2469 /* 2470 * Initialize UART for use as console or KGDB line. 2471 */ 2472 int 2473 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2474 tcflag_t cflag) 2475 { 2476 2477 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2478 ®sp->cr_ioh)) 2479 return (ENOMEM); /* ??? */ 2480 2481 if (type == COM_TYPE_OMAP) { 2482 /* disable before changing settings */ 2483 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2484 } 2485 2486 rate = comspeed(rate, frequency, type); 2487 if (rate != -1) { 2488 if (type == COM_TYPE_AU1x00) { 2489 /* no EFR on alchemy */ 2490 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2491 } else { 2492 if ((type != COM_TYPE_16550_NOERS) && 2493 (type != COM_TYPE_INGENIC)) { 2494 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2495 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2496 } 2497 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2498 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2499 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2500 } 2501 } 2502 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2503 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2504 2505 if (type == COM_TYPE_INGENIC) { 2506 CSR_WRITE_1(regsp, COM_REG_FIFO, 2507 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2508 FIFO_TRIGGER_1 | FIFO_UART_ON); 2509 } else { 2510 CSR_WRITE_1(regsp, COM_REG_FIFO, 2511 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2512 FIFO_TRIGGER_1); 2513 } 2514 2515 if (type == COM_TYPE_OMAP) { 2516 /* setup the fifos. the FCR value is not used as long 2517 as SCR[6] and SCR[7] are 0, which they are at reset 2518 and we never touch the SCR register */ 2519 uint8_t rx_fifo_trig = 40; 2520 uint8_t tx_fifo_trig = 60; 2521 uint8_t rx_start = 8; 2522 uint8_t rx_halt = 60; 2523 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2524 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2525 2526 /* enable access to TCR & TLR */ 2527 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2528 2529 /* write tcr and tlr values */ 2530 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2531 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2532 2533 /* disable access to TCR & TLR */ 2534 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2535 2536 /* enable again, but mode is based on speed */ 2537 if (rate > 230400) { 2538 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2539 } else { 2540 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2541 } 2542 } 2543 2544 if (type == COM_TYPE_PXA2x0) 2545 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2546 else 2547 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2548 2549 return (0); 2550 } 2551 2552 int 2553 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2554 tcflag_t cflag) 2555 { 2556 int res; 2557 2558 comcons_info.regs = *regsp; 2559 2560 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2561 if (res) 2562 return (res); 2563 2564 cn_tab = &comcons; 2565 cn_init_magic(&com_cnm_state); 2566 cn_set_magic("\047\001"); /* default magic is BREAK */ 2567 2568 comcons_info.frequency = frequency; 2569 comcons_info.type = type; 2570 comcons_info.rate = rate; 2571 comcons_info.cflag = cflag; 2572 2573 return (0); 2574 } 2575 2576 int 2577 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2578 int type, tcflag_t cflag) 2579 { 2580 struct com_regs regs; 2581 2582 /*XXX*/ 2583 bus_space_handle_t dummy_bsh; 2584 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2585 2586 /* 2587 * dummy_bsh required because com_init_regs() wants it. A 2588 * real bus_space_handle will be filled in by cominit() later. 2589 * XXXJRT Detangle this mess eventually, plz. 2590 */ 2591 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2592 2593 return comcnattach1(®s, rate, frequency, type, cflag); 2594 } 2595 2596 static int 2597 comcnreattach(void) 2598 { 2599 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2600 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2601 } 2602 2603 int 2604 comcngetc(dev_t dev) 2605 { 2606 2607 return (com_common_getc(dev, &comcons_info.regs)); 2608 } 2609 2610 /* 2611 * Console kernel output character routine. 2612 */ 2613 void 2614 comcnputc(dev_t dev, int c) 2615 { 2616 2617 com_common_putc(dev, &comcons_info.regs, c, cold); 2618 } 2619 2620 void 2621 comcnpollc(dev_t dev, int on) 2622 { 2623 2624 com_readaheadcount = 0; 2625 } 2626 2627 #ifdef KGDB 2628 int 2629 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2630 tcflag_t cflag) 2631 { 2632 int res; 2633 2634 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2635 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2636 #if !defined(DDB) 2637 return (EBUSY); /* cannot share with console */ 2638 #else 2639 comkgdbregs = *regsp; 2640 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2641 #endif 2642 } else { 2643 comkgdbregs = *regsp; 2644 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2645 if (res) 2646 return (res); 2647 2648 /* 2649 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2650 * expects this to be initialized 2651 */ 2652 cn_init_magic(&com_cnm_state); 2653 cn_set_magic("\047\001"); 2654 } 2655 2656 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2657 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2658 2659 return (0); 2660 } 2661 2662 int 2663 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2664 int frequency, int type, tcflag_t cflag) 2665 { 2666 struct com_regs regs; 2667 2668 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2669 2670 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2671 } 2672 2673 /* ARGSUSED */ 2674 int 2675 com_kgdb_getc(void *arg) 2676 { 2677 2678 return (com_common_getc(NODEV, &comkgdbregs)); 2679 } 2680 2681 /* ARGSUSED */ 2682 void 2683 com_kgdb_putc(void *arg, int c) 2684 { 2685 2686 com_common_putc(NODEV, &comkgdbregs, c, 0); 2687 } 2688 #endif /* KGDB */ 2689 2690 /* helper function to identify the com ports used by 2691 console or KGDB (and not yet autoconf attached) */ 2692 int 2693 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2694 { 2695 bus_space_handle_t help; 2696 2697 if (!comconsattached && 2698 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2699 iobase == comcons_info.regs.cr_iobase) 2700 help = comcons_info.regs.cr_ioh; 2701 #ifdef KGDB 2702 else if (!com_kgdb_attached && 2703 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2704 iobase == comkgdbregs.cr_iobase) 2705 help = comkgdbregs.cr_ioh; 2706 #endif 2707 else 2708 return (0); 2709 2710 if (ioh) 2711 *ioh = help; 2712 return (1); 2713 } 2714 2715 /* 2716 * this routine exists to serve as a shutdown hook for systems that 2717 * have firmware which doesn't interact properly with a com device in 2718 * FIFO mode. 2719 */ 2720 bool 2721 com_cleanup(device_t self, int how) 2722 { 2723 struct com_softc *sc = device_private(self); 2724 2725 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2726 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2727 2728 return true; 2729 } 2730 2731 bool 2732 com_suspend(device_t self, const pmf_qual_t *qual) 2733 { 2734 struct com_softc *sc = device_private(self); 2735 2736 #if 0 2737 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2738 cn_tab = &comcons_suspend; 2739 #endif 2740 2741 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2742 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2743 2744 return true; 2745 } 2746 2747 bool 2748 com_resume(device_t self, const pmf_qual_t *qual) 2749 { 2750 struct com_softc *sc = device_private(self); 2751 2752 mutex_spin_enter(&sc->sc_lock); 2753 com_loadchannelregs(sc); 2754 mutex_spin_exit(&sc->sc_lock); 2755 2756 return true; 2757 } 2758
Indexes created Thu Sep 25 16:09:42 GMT 2025