com.c revision 1.374
1 /* $NetBSD: com.c,v 1.374 2022/10/03 19:26:35 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 */ 67 68 #include <sys/cdefs.h> 69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.374 2022/10/03 19:26:35 riastradh Exp $"); 70 71 #include "opt_com.h" 72 #include "opt_ddb.h" 73 #include "opt_kgdb.h" 74 #include "opt_lockdebug.h" 75 #include "opt_multiprocessor.h" 76 #include "opt_ntp.h" 77 78 /* The COM16650 option was renamed to COM_16650. */ 79 #ifdef COM16650 80 #error Obsolete COM16650 option; use COM_16650 instead. 81 #endif 82 83 /* 84 * Override cnmagic(9) macro before including <sys/systm.h>. 85 * We need to know if cn_check_magic triggered debugger, so set a flag. 86 * Callers of cn_check_magic must declare int cn_trapped = 0; 87 * XXX: this is *ugly*! 88 */ 89 #define cn_trap() \ 90 do { \ 91 console_debugger(); \ 92 cn_trapped = 1; \ 93 (void)cn_trapped; \ 94 } while (/* CONSTCOND */ 0) 95 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/ioctl.h> 99 #include <sys/select.h> 100 #include <sys/poll.h> 101 #include <sys/tty.h> 102 #include <sys/proc.h> 103 #include <sys/conf.h> 104 #include <sys/file.h> 105 #include <sys/uio.h> 106 #include <sys/kernel.h> 107 #include <sys/syslog.h> 108 #include <sys/device.h> 109 #include <sys/malloc.h> 110 #include <sys/timepps.h> 111 #include <sys/vnode.h> 112 #include <sys/kauth.h> 113 #include <sys/intr.h> 114 #ifdef RND_COM 115 #include <sys/rndsource.h> 116 #endif 117 118 119 #include <sys/bus.h> 120 121 #include <dev/ic/comreg.h> 122 #include <dev/ic/comvar.h> 123 #include <dev/ic/ns16550reg.h> 124 #include <dev/ic/st16650reg.h> 125 #include <dev/ic/hayespreg.h> 126 #define com_lcr com_cfcr 127 #include <dev/cons.h> 128 129 #include "ioconf.h" 130 131 #define CSR_READ_1(r, o) \ 132 (r)->cr_read((r), (r)->cr_map[o]) 133 #define CSR_WRITE_1(r, o, v) \ 134 (r)->cr_write((r), (r)->cr_map[o], (v)) 135 #define CSR_WRITE_MULTI(r, o, p, n) \ 136 (r)->cr_write_multi((r), (r)->cr_map[o], (p), (n)) 137 138 /* 139 * XXX COM_TYPE_AU1x00 specific 140 */ 141 #define CSR_WRITE_2(r, o, v) \ 142 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 143 #define CSR_READ_2(r, o) \ 144 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 145 146 static void com_enable_debugport(struct com_softc *); 147 148 void com_config(struct com_softc *); 149 void com_shutdown(struct com_softc *); 150 int comspeed(long, long, int); 151 static u_char cflag2lcr(tcflag_t); 152 int comparam(struct tty *, struct termios *); 153 void comstart(struct tty *); 154 int comhwiflow(struct tty *, int); 155 156 void com_loadchannelregs(struct com_softc *); 157 void com_hwiflow(struct com_softc *); 158 void com_break(struct com_softc *, int); 159 void com_modem(struct com_softc *, int); 160 void tiocm_to_com(struct com_softc *, u_long, int); 161 int com_to_tiocm(struct com_softc *); 162 void com_iflush(struct com_softc *); 163 164 int com_common_getc(dev_t, struct com_regs *); 165 static void com_common_putc(dev_t, struct com_regs *, int, int); 166 167 int cominit(struct com_regs *, int, int, int, tcflag_t); 168 169 static int comcnreattach(void); 170 171 int comcngetc(dev_t); 172 void comcnputc(dev_t, int); 173 void comcnpollc(dev_t, int); 174 175 #define integrate static inline 176 void comsoft(void *); 177 integrate void com_rxsoft(struct com_softc *, struct tty *); 178 integrate void com_txsoft(struct com_softc *, struct tty *); 179 integrate void com_stsoft(struct com_softc *, struct tty *); 180 integrate void com_schedrx(struct com_softc *); 181 void comdiag(void *); 182 183 dev_type_open(comopen); 184 dev_type_close(comclose); 185 dev_type_read(comread); 186 dev_type_write(comwrite); 187 dev_type_ioctl(comioctl); 188 dev_type_stop(comstop); 189 dev_type_tty(comtty); 190 dev_type_poll(compoll); 191 192 static struct comcons_info comcons_info; 193 194 /* 195 * Following are all routines needed for COM to act as console 196 */ 197 static struct consdev comcons = { 198 .cn_getc = comcngetc, 199 .cn_putc = comcnputc, 200 .cn_pollc = comcnpollc, 201 .cn_dev = NODEV, 202 .cn_pri = CN_NORMAL 203 }; 204 205 206 const struct cdevsw com_cdevsw = { 207 .d_open = comopen, 208 .d_close = comclose, 209 .d_read = comread, 210 .d_write = comwrite, 211 .d_ioctl = comioctl, 212 .d_stop = comstop, 213 .d_tty = comtty, 214 .d_poll = compoll, 215 .d_mmap = nommap, 216 .d_kqfilter = ttykqfilter, 217 .d_discard = nodiscard, 218 .d_flag = D_TTY 219 }; 220 221 /* 222 * Make this an option variable one can patch. 223 * But be warned: this must be a power of 2! 224 */ 225 u_int com_rbuf_size = COM_RING_SIZE; 226 227 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 228 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 229 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 230 231 static int comconsattached; 232 static struct cnm_state com_cnm_state; 233 234 #ifdef KGDB 235 #include <sys/kgdb.h> 236 237 static struct com_regs comkgdbregs; 238 static int com_kgdb_attached; 239 240 int com_kgdb_getc(void *); 241 void com_kgdb_putc(void *, int); 242 #endif /* KGDB */ 243 244 /* initializer for typical 16550-ish hardware */ 245 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 246 [COM_REG_RXDATA] = com_data, 247 [COM_REG_TXDATA] = com_data, 248 [COM_REG_DLBL] = com_dlbl, 249 [COM_REG_DLBH] = com_dlbh, 250 [COM_REG_IER] = com_ier, 251 [COM_REG_IIR] = com_iir, 252 [COM_REG_FIFO] = com_fifo, 253 [COM_REG_TCR] = com_fifo, 254 [COM_REG_EFR] = com_efr, 255 [COM_REG_TLR] = com_efr, 256 [COM_REG_LCR] = com_lcr, 257 [COM_REG_MCR] = com_mcr, 258 [COM_REG_LSR] = com_lsr, 259 [COM_REG_MSR] = com_msr, 260 [COM_REG_USR] = com_usr, 261 [COM_REG_TFL] = com_tfl, 262 [COM_REG_RFL] = com_rfl, 263 [COM_REG_HALT] = com_halt, 264 [COM_REG_MDR1] = com_mdr1, 265 }; 266 267 #define COMDIALOUT_MASK TTDIALOUT_MASK 268 269 #define COMUNIT(x) TTUNIT(x) 270 #define COMDIALOUT(x) TTDIALOUT(x) 271 272 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 273 device_is_active((sc)->sc_dev)) 274 275 #define BR BUS_SPACE_BARRIER_READ 276 #define BW BUS_SPACE_BARRIER_WRITE 277 #define COM_BARRIER(r, f) \ 278 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 279 280 /* 281 * com_read_1 -- 282 * Default register read callback using single byte accesses. 283 */ 284 static uint8_t 285 com_read_1(struct com_regs *regs, u_int reg) 286 { 287 return bus_space_read_1(regs->cr_iot, regs->cr_ioh, reg); 288 } 289 290 /* 291 * com_write_1 -- 292 * Default register write callback using single byte accesses. 293 */ 294 static void 295 com_write_1(struct com_regs *regs, u_int reg, uint8_t val) 296 { 297 bus_space_write_1(regs->cr_iot, regs->cr_ioh, reg, val); 298 } 299 300 /* 301 * com_write_multi_1 -- 302 * Default register multi write callback using single byte accesses. 303 */ 304 static void 305 com_write_multi_1(struct com_regs *regs, u_int reg, const uint8_t *datap, 306 bus_size_t count) 307 { 308 bus_space_write_multi_1(regs->cr_iot, regs->cr_ioh, reg, datap, count); 309 } 310 311 /* 312 * com_read_4 -- 313 * Default register read callback using dword accesses. 314 */ 315 static uint8_t 316 com_read_4(struct com_regs *regs, u_int reg) 317 { 318 return bus_space_read_4(regs->cr_iot, regs->cr_ioh, reg) & 0xff; 319 } 320 321 /* 322 * com_write_4 -- 323 * Default register write callback using dword accesses. 324 */ 325 static void 326 com_write_4(struct com_regs *regs, u_int reg, uint8_t val) 327 { 328 bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, val); 329 } 330 331 /* 332 * com_write_multi_4 -- 333 * Default register multi write callback using dword accesses. 334 */ 335 static void 336 com_write_multi_4(struct com_regs *regs, u_int reg, const uint8_t *datap, 337 bus_size_t count) 338 { 339 while (count-- > 0) { 340 bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, *datap++); 341 } 342 } 343 344 /* 345 * com_init_regs -- 346 * Driver front-ends use this to initialize our register map 347 * in the standard fashion. They may then tailor the map to 348 * their own particular requirements. 349 */ 350 void 351 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 352 bus_addr_t addr) 353 { 354 355 memset(regs, 0, sizeof(*regs)); 356 regs->cr_iot = st; 357 regs->cr_ioh = sh; 358 regs->cr_iobase = addr; 359 regs->cr_nports = COM_NPORTS; 360 regs->cr_read = com_read_1; 361 regs->cr_write = com_write_1; 362 regs->cr_write_multi = com_write_multi_1; 363 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 364 } 365 366 /* 367 * com_init_regs_stride -- 368 * Convenience function for front-ends that have a stride between 369 * registers. 370 */ 371 void 372 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 373 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 374 { 375 376 com_init_regs(regs, st, sh, addr); 377 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 378 regs->cr_map[i] <<= regshift; 379 } 380 regs->cr_nports <<= regshift; 381 } 382 383 /* 384 * com_init_regs_stride_width -- 385 * Convenience function for front-ends that have a stride between 386 * registers and specific I/O width requirements. 387 */ 388 void 389 com_init_regs_stride_width(struct com_regs *regs, bus_space_tag_t st, 390 bus_space_handle_t sh, bus_addr_t addr, 391 u_int regshift, u_int width) 392 { 393 394 com_init_regs(regs, st, sh, addr); 395 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 396 regs->cr_map[i] <<= regshift; 397 } 398 regs->cr_nports <<= regshift; 399 400 switch (width) { 401 case 1: 402 /* Already set by com_init_regs */ 403 break; 404 case 4: 405 regs->cr_read = com_read_4; 406 regs->cr_write = com_write_4; 407 regs->cr_write_multi = com_write_multi_4; 408 break; 409 default: 410 panic("com: unsupported I/O width %d", width); 411 } 412 } 413 414 /*ARGSUSED*/ 415 int 416 comspeed(long speed, long frequency, int type) 417 { 418 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 419 420 int x, err; 421 int divisor = 16; 422 423 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 424 divisor = 13; 425 } 426 427 if (speed == 0) 428 return (0); 429 if (speed < 0) 430 return (-1); 431 x = divrnd(frequency / divisor, speed); 432 if (x <= 0) 433 return (-1); 434 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 435 if (err < 0) 436 err = -err; 437 if (err > COM_TOLERANCE) 438 return (-1); 439 return (x); 440 441 #undef divrnd 442 } 443 444 #ifdef COM_DEBUG 445 int com_debug = 0; 446 447 void comstatus(struct com_softc *, const char *); 448 void 449 comstatus(struct com_softc *sc, const char *str) 450 { 451 struct tty *tp = sc->sc_tty; 452 453 aprint_normal_dev(sc->sc_dev, 454 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 455 str, 456 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 457 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 458 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 459 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 460 sc->sc_tx_stopped ? '+' : '-'); 461 462 aprint_normal_dev(sc->sc_dev, 463 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 464 str, 465 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 466 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 467 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 468 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 469 sc->sc_rx_flags); 470 } 471 #endif 472 473 int 474 com_probe_subr(struct com_regs *regs) 475 { 476 477 /* force access to id reg */ 478 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 479 CSR_WRITE_1(regs, COM_REG_IIR, 0); 480 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 481 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 482 return (0); 483 484 return (1); 485 } 486 487 int 488 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 489 { 490 struct com_regs regs; 491 492 com_init_regs(®s, iot, ioh, 0/*XXX*/); 493 494 return com_probe_subr(®s); 495 } 496 497 /* 498 * No locking in this routine; it is only called during attach, 499 * or with the port already locked. 500 */ 501 static void 502 com_enable_debugport(struct com_softc *sc) 503 { 504 505 /* Turn on line break interrupt, set carrier. */ 506 sc->sc_ier = IER_ERLS; 507 if (sc->sc_type == COM_TYPE_PXA2x0) 508 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 509 if (sc->sc_type == COM_TYPE_INGENIC || 510 sc->sc_type == COM_TYPE_TEGRA) 511 sc->sc_ier |= IER_ERXTOUT; 512 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 513 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 514 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 515 } 516 517 static void 518 com_intr_poll(void *arg) 519 { 520 struct com_softc * const sc = arg; 521 522 comintr(sc); 523 524 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 525 } 526 527 void 528 com_attach_subr(struct com_softc *sc) 529 { 530 struct com_regs *regsp = &sc->sc_regs; 531 struct tty *tp; 532 uint32_t cpr; 533 uint8_t lcr; 534 const char *fifo_msg = NULL; 535 prop_dictionary_t dict; 536 bool is_console = true; 537 bool force_console = false; 538 539 aprint_naive("\n"); 540 541 dict = device_properties(sc->sc_dev); 542 prop_dictionary_get_bool(dict, "is_console", &is_console); 543 prop_dictionary_get_bool(dict, "force_console", &force_console); 544 callout_init(&sc->sc_diag_callout, 0); 545 callout_init(&sc->sc_poll_callout, 0); 546 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 547 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 548 549 #if defined(COM_16650) 550 sc->sc_type = COM_TYPE_16650; 551 #elif defined(COM_16750) 552 sc->sc_type = COM_TYPE_16750; 553 #elif defined(COM_HAYESP) 554 sc->sc_type = COM_TYPE_HAYESP; 555 #elif defined(COM_PXA2X0) 556 sc->sc_type = COM_TYPE_PXA2x0; 557 #endif 558 559 /* Disable interrupts before configuring the device. */ 560 if (sc->sc_type == COM_TYPE_PXA2x0) 561 sc->sc_ier = IER_EUART; 562 else 563 sc->sc_ier = 0; 564 565 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 566 567 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 568 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 569 comconsattached = 1; 570 571 if (force_console) 572 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 573 574 if (cn_tab == NULL && comcnreattach() != 0) { 575 printf("can't re-init serial console @%lx\n", 576 (u_long)comcons_info.regs.cr_iobase); 577 } 578 579 switch (sc->sc_type) { 580 case COM_TYPE_16750: 581 case COM_TYPE_DW_APB: 582 /* Use in comintr(). */ 583 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 584 break; 585 } 586 587 /* Make sure the console is always "hardwired". */ 588 delay(10000); /* wait for output to finish */ 589 if (is_console) { 590 SET(sc->sc_hwflags, COM_HW_CONSOLE); 591 } 592 593 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 594 } 595 596 /* Probe for FIFO */ 597 switch (sc->sc_type) { 598 case COM_TYPE_HAYESP: 599 goto fifodone; 600 601 case COM_TYPE_AU1x00: 602 sc->sc_fifolen = 16; 603 fifo_msg = "Au1X00 UART"; 604 SET(sc->sc_hwflags, COM_HW_FIFO); 605 goto fifodelay; 606 607 case COM_TYPE_16550_NOERS: 608 sc->sc_fifolen = 16; 609 fifo_msg = "ns16650, no ERS"; 610 SET(sc->sc_hwflags, COM_HW_FIFO); 611 goto fifodelay; 612 613 case COM_TYPE_OMAP: 614 sc->sc_fifolen = 64; 615 fifo_msg = "OMAP UART"; 616 SET(sc->sc_hwflags, COM_HW_FIFO); 617 goto fifodelay; 618 619 case COM_TYPE_INGENIC: 620 sc->sc_fifolen = 16; 621 fifo_msg = "Ingenic UART"; 622 SET(sc->sc_hwflags, COM_HW_FIFO); 623 SET(sc->sc_hwflags, COM_HW_NOIEN); 624 goto fifodelay; 625 626 case COM_TYPE_TEGRA: 627 sc->sc_fifolen = 8; 628 fifo_msg = "Tegra UART"; 629 SET(sc->sc_hwflags, COM_HW_FIFO); 630 CSR_WRITE_1(regsp, COM_REG_FIFO, 631 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 632 goto fifodelay; 633 634 case COM_TYPE_BCMAUXUART: 635 sc->sc_fifolen = 1; 636 fifo_msg = "BCM AUX UART"; 637 SET(sc->sc_hwflags, COM_HW_FIFO); 638 CSR_WRITE_1(regsp, COM_REG_FIFO, 639 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 640 goto fifodelay; 641 642 case COM_TYPE_DW_APB: 643 if (!prop_dictionary_get_uint(dict, "fifolen", &sc->sc_fifolen)) { 644 cpr = bus_space_read_4(sc->sc_regs.cr_iot, 645 sc->sc_regs.cr_ioh, DW_APB_UART_CPR); 646 sc->sc_fifolen = __SHIFTOUT(cpr, UART_CPR_FIFO_MODE) * 16; 647 } 648 if (sc->sc_fifolen == 0) { 649 sc->sc_fifolen = 1; 650 fifo_msg = "DesignWare APB UART, no fifo"; 651 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 652 } else { 653 fifo_msg = "DesignWare APB UART"; 654 SET(sc->sc_hwflags, COM_HW_FIFO); 655 CSR_WRITE_1(regsp, COM_REG_FIFO, 656 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 657 } 658 goto fifodelay; 659 } 660 661 sc->sc_fifolen = 1; 662 /* look for a NS 16550AF UART with FIFOs */ 663 if (sc->sc_type == COM_TYPE_INGENIC) { 664 CSR_WRITE_1(regsp, COM_REG_FIFO, 665 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 666 FIFO_TRIGGER_14 | FIFO_UART_ON); 667 } else 668 CSR_WRITE_1(regsp, COM_REG_FIFO, 669 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 670 delay(100); 671 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 672 == IIR_FIFO_MASK) 673 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 674 == FIFO_TRIGGER_14) { 675 SET(sc->sc_hwflags, COM_HW_FIFO); 676 677 fifo_msg = "ns16550a"; 678 sc->sc_fifolen = 16; 679 680 /* 681 * IIR changes into the EFR if LCR is set to LCR_EERS 682 * on 16650s. We also know IIR != 0 at this point. 683 * Write 0 into the EFR, and read it. If the result 684 * is 0, we have a 16650. 685 * 686 * Older 16650s were broken; the test to detect them 687 * is taken from the Linux driver. Apparently 688 * setting DLAB enable gives access to the EFR on 689 * these chips. 690 */ 691 if (sc->sc_type == COM_TYPE_16650) { 692 lcr = CSR_READ_1(regsp, COM_REG_LCR); 693 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 694 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 695 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 696 CSR_WRITE_1(regsp, COM_REG_LCR, 697 lcr | LCR_DLAB); 698 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 699 CLR(sc->sc_hwflags, COM_HW_FIFO); 700 sc->sc_fifolen = 0; 701 } else { 702 SET(sc->sc_hwflags, COM_HW_FLOW); 703 sc->sc_fifolen = 32; 704 } 705 } else 706 sc->sc_fifolen = 16; 707 708 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 709 if (sc->sc_fifolen == 0) 710 fifo_msg = "st16650, broken fifo"; 711 else if (sc->sc_fifolen == 32) 712 fifo_msg = "st16650a"; 713 else 714 fifo_msg = "ns16550a"; 715 } 716 717 /* 718 * TL16C750 can enable 64byte FIFO, only when DLAB 719 * is 1. However, some 16750 may always enable. For 720 * example, restrictions according to DLAB in a data 721 * sheet for SC16C750 were not described. 722 * Please enable 'options COM_16650', supposing you 723 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 724 * should become effective. 725 */ 726 if (sc->sc_type == COM_TYPE_16750) { 727 uint8_t iir1, iir2; 728 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 729 730 lcr = CSR_READ_1(regsp, COM_REG_LCR); 731 CSR_WRITE_1(regsp, COM_REG_LCR, 732 lcr & ~LCR_DLAB); 733 CSR_WRITE_1(regsp, COM_REG_FIFO, 734 fcr | FIFO_64B_ENABLE); 735 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 736 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 737 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 738 CSR_WRITE_1(regsp, COM_REG_FIFO, 739 fcr | FIFO_64B_ENABLE); 740 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 741 742 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 743 744 if (!ISSET(iir1, IIR_64B_FIFO) && 745 ISSET(iir2, IIR_64B_FIFO)) { 746 /* It is TL16C750. */ 747 sc->sc_fifolen = 64; 748 SET(sc->sc_hwflags, COM_HW_AFE); 749 } else 750 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 751 752 if (sc->sc_fifolen == 64) 753 fifo_msg = "tl16c750"; 754 else 755 fifo_msg = "ns16750"; 756 } 757 } else 758 fifo_msg = "ns16550, broken fifo"; 759 else 760 fifo_msg = "ns8250 or ns16450, no fifo"; 761 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 762 763 fifodelay: 764 /* 765 * Some chips will clear down both Tx and Rx FIFOs when zero is 766 * written to com_fifo. If this chip is the console, writing zero 767 * results in some of the chip/FIFO description being lost, so delay 768 * printing it until now. 769 */ 770 delay(10); 771 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 772 aprint_normal(": %s, %d-byte FIFO\n", fifo_msg, sc->sc_fifolen); 773 } else { 774 aprint_normal(": %s\n", fifo_msg); 775 } 776 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 777 sc->sc_fifolen = 1; 778 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 779 } 780 781 fifodone: 782 783 tp = tty_alloc(); 784 tp->t_oproc = comstart; 785 tp->t_param = comparam; 786 tp->t_hwiflow = comhwiflow; 787 tp->t_softc = sc; 788 789 sc->sc_tty = tp; 790 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK); 791 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 792 sc->sc_rbavail = com_rbuf_size; 793 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 794 795 tty_attach(tp); 796 797 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 798 SET(sc->sc_mcr, MCR_IENABLE); 799 800 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 801 int maj; 802 803 /* locate the major number */ 804 maj = cdevsw_lookup_major(&com_cdevsw); 805 806 tp->t_dev = cn_tab->cn_dev = makedev(maj, 807 device_unit(sc->sc_dev)); 808 809 aprint_normal_dev(sc->sc_dev, "console\n"); 810 } 811 812 #ifdef KGDB 813 /* 814 * Allow kgdb to "take over" this port. If this is 815 * not the console and is the kgdb device, it has 816 * exclusive use. If it's the console _and_ the 817 * kgdb device, it doesn't. 818 */ 819 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 820 regsp->cr_iobase == comkgdbregs.cr_iobase) { 821 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 822 com_kgdb_attached = 1; 823 824 SET(sc->sc_hwflags, COM_HW_KGDB); 825 } 826 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 827 } 828 #endif 829 830 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 831 832 #ifdef RND_COM 833 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 834 RND_TYPE_TTY, RND_FLAG_DEFAULT); 835 #endif 836 837 /* if there are no enable/disable functions, assume the device 838 is always enabled */ 839 if (!sc->enable) 840 sc->enabled = 1; 841 842 com_config(sc); 843 844 SET(sc->sc_hwflags, COM_HW_DEV_OK); 845 846 if (sc->sc_poll_ticks != 0) 847 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 848 } 849 850 void 851 com_config(struct com_softc *sc) 852 { 853 struct com_regs *regsp = &sc->sc_regs; 854 855 /* Disable interrupts before configuring the device. */ 856 if (sc->sc_type == COM_TYPE_PXA2x0) 857 sc->sc_ier = IER_EUART; 858 else 859 sc->sc_ier = 0; 860 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 861 (void) CSR_READ_1(regsp, COM_REG_IIR); 862 863 /* Look for a Hayes ESP board. */ 864 if (sc->sc_type == COM_TYPE_HAYESP) { 865 866 /* Set 16550 compatibility mode */ 867 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 868 HAYESP_SETMODE); 869 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 870 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 871 HAYESP_MODE_SCALE); 872 873 /* Set RTS/CTS flow control */ 874 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 875 HAYESP_SETFLOWTYPE); 876 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 877 HAYESP_FLOW_RTS); 878 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 879 HAYESP_FLOW_CTS); 880 881 /* Set flow control levels */ 882 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 883 HAYESP_SETRXFLOW); 884 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 885 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 886 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 887 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 888 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 889 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 890 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 891 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 892 } 893 894 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 895 com_enable_debugport(sc); 896 } 897 898 #if 0 899 static int 900 comcngetc_detached(dev_t dev) 901 { 902 return 0; 903 } 904 905 static void 906 comcnputc_detached(dev_t dev, int c) 907 { 908 } 909 #endif 910 911 int 912 com_detach(device_t self, int flags) 913 { 914 struct com_softc *sc = device_private(self); 915 int maj, mn; 916 917 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 918 return EBUSY; 919 920 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 921 (flags & DETACH_SHUTDOWN) != 0) 922 return EBUSY; 923 924 if (sc->disable != NULL && sc->enabled != 0) { 925 (*sc->disable)(sc); 926 sc->enabled = 0; 927 } 928 929 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 930 comconsattached = 0; 931 cn_tab = NULL; 932 } 933 934 /* locate the major number */ 935 maj = cdevsw_lookup_major(&com_cdevsw); 936 937 /* Nuke the vnodes for any open instances. */ 938 mn = device_unit(self); 939 vdevgone(maj, mn, mn, VCHR); 940 941 mn |= COMDIALOUT_MASK; 942 vdevgone(maj, mn, mn, VCHR); 943 944 if (sc->sc_rbuf == NULL) { 945 /* 946 * Ring buffer allocation failed in the com_attach_subr, 947 * only the tty is allocated, and nothing else. 948 */ 949 tty_free(sc->sc_tty); 950 return 0; 951 } 952 953 /* Free the receive buffer. */ 954 free(sc->sc_rbuf, M_DEVBUF); 955 956 /* Detach and free the tty. */ 957 tty_detach(sc->sc_tty); 958 tty_free(sc->sc_tty); 959 960 /* Unhook the soft interrupt handler. */ 961 softint_disestablish(sc->sc_si); 962 963 #ifdef RND_COM 964 /* Unhook the entropy source. */ 965 rnd_detach_source(&sc->rnd_source); 966 #endif 967 callout_destroy(&sc->sc_diag_callout); 968 969 /* Destroy the lock. */ 970 mutex_destroy(&sc->sc_lock); 971 972 return (0); 973 } 974 975 void 976 com_shutdown(struct com_softc *sc) 977 { 978 struct tty *tp = sc->sc_tty; 979 980 mutex_spin_enter(&sc->sc_lock); 981 982 /* If we were asserting flow control, then deassert it. */ 983 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 984 com_hwiflow(sc); 985 986 /* Clear any break condition set with TIOCSBRK. */ 987 com_break(sc, 0); 988 989 /* 990 * Hang up if necessary. Record when we hung up, so if we 991 * immediately open the port again, we will wait a bit until 992 * the other side has had time to notice that we hung up. 993 */ 994 if (ISSET(tp->t_cflag, HUPCL)) { 995 com_modem(sc, 0); 996 microuptime(&sc->sc_hup_pending); 997 sc->sc_hup_pending.tv_sec++; 998 } 999 1000 /* Turn off interrupts. */ 1001 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1002 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 1003 if ((sc->sc_type == COM_TYPE_PXA2x0) || 1004 (sc->sc_type == COM_TYPE_INGENIC) || 1005 (sc->sc_type == COM_TYPE_TEGRA)) 1006 sc->sc_ier |= IER_ERXTOUT; 1007 } else 1008 sc->sc_ier = 0; 1009 1010 if (sc->sc_type == COM_TYPE_PXA2x0) 1011 sc->sc_ier |= IER_EUART; 1012 1013 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1014 1015 mutex_spin_exit(&sc->sc_lock); 1016 1017 if (sc->disable) { 1018 #ifdef DIAGNOSTIC 1019 if (!sc->enabled) 1020 panic("com_shutdown: not enabled?"); 1021 #endif 1022 (*sc->disable)(sc); 1023 sc->enabled = 0; 1024 } 1025 } 1026 1027 int 1028 comopen(dev_t dev, int flag, int mode, struct lwp *l) 1029 { 1030 struct com_softc *sc; 1031 struct tty *tp; 1032 int s; 1033 int error; 1034 1035 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1036 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 1037 sc->sc_rbuf == NULL) 1038 return (ENXIO); 1039 1040 if (!device_is_active(sc->sc_dev)) 1041 return (ENXIO); 1042 1043 #ifdef KGDB 1044 /* 1045 * If this is the kgdb port, no other use is permitted. 1046 */ 1047 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 1048 return (EBUSY); 1049 #endif 1050 1051 tp = sc->sc_tty; 1052 1053 /* 1054 * If the device is exclusively for kernel use, deny userland 1055 * open. 1056 */ 1057 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1058 return (EBUSY); 1059 1060 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 1061 return (EBUSY); 1062 1063 s = spltty(); 1064 1065 /* 1066 * Do the following iff this is a first open. 1067 */ 1068 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1069 struct termios t; 1070 struct timeval now, diff; 1071 1072 tp->t_dev = dev; 1073 1074 if (sc->enable) { 1075 if ((*sc->enable)(sc)) { 1076 splx(s); 1077 aprint_error_dev(sc->sc_dev, 1078 "device enable failed\n"); 1079 return (EIO); 1080 } 1081 mutex_spin_enter(&sc->sc_lock); 1082 sc->enabled = 1; 1083 com_config(sc); 1084 } else { 1085 mutex_spin_enter(&sc->sc_lock); 1086 } 1087 1088 if (timerisset(&sc->sc_hup_pending)) { 1089 microuptime(&now); 1090 while (timercmp(&now, &sc->sc_hup_pending, <)) { 1091 timersub(&sc->sc_hup_pending, &now, &diff); 1092 const int ms = diff.tv_sec * 1000 + 1093 diff.tv_usec / 1000; 1094 kpause(ttclos, false, uimax(mstohz(ms), 1), 1095 &sc->sc_lock); 1096 microuptime(&now); 1097 } 1098 timerclear(&sc->sc_hup_pending); 1099 } 1100 1101 /* Turn on interrupts. */ 1102 sc->sc_ier = IER_ERXRDY | IER_ERLS; 1103 if (!ISSET(tp->t_cflag, CLOCAL)) 1104 sc->sc_ier |= IER_EMSC; 1105 1106 if (sc->sc_type == COM_TYPE_PXA2x0) 1107 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 1108 else if (sc->sc_type == COM_TYPE_INGENIC || 1109 sc->sc_type == COM_TYPE_TEGRA) 1110 sc->sc_ier |= IER_ERXTOUT; 1111 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1112 1113 /* Fetch the current modem control status, needed later. */ 1114 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 1115 1116 /* Clear PPS capture state on first open. */ 1117 mutex_spin_enter(&timecounter_lock); 1118 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 1119 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1120 pps_init(&sc->sc_pps_state); 1121 mutex_spin_exit(&timecounter_lock); 1122 1123 mutex_spin_exit(&sc->sc_lock); 1124 1125 /* 1126 * Initialize the termios status to the defaults. Add in the 1127 * sticky bits from TIOCSFLAGS. 1128 */ 1129 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1130 t.c_ospeed = comcons_info.rate; 1131 t.c_cflag = comcons_info.cflag; 1132 } else { 1133 t.c_ospeed = TTYDEF_SPEED; 1134 t.c_cflag = TTYDEF_CFLAG; 1135 } 1136 t.c_ispeed = t.c_ospeed; 1137 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1138 SET(t.c_cflag, CLOCAL); 1139 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1140 SET(t.c_cflag, CRTSCTS); 1141 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1142 SET(t.c_cflag, MDMBUF); 1143 /* Make sure comparam() will do something. */ 1144 tp->t_ospeed = 0; 1145 (void) comparam(tp, &t); 1146 tp->t_iflag = TTYDEF_IFLAG; 1147 tp->t_oflag = TTYDEF_OFLAG; 1148 tp->t_lflag = TTYDEF_LFLAG; 1149 ttychars(tp); 1150 ttsetwater(tp); 1151 1152 mutex_spin_enter(&sc->sc_lock); 1153 1154 /* 1155 * Turn on DTR. We must always do this, even if carrier is not 1156 * present, because otherwise we'd have to use TIOCSDTR 1157 * immediately after setting CLOCAL, which applications do not 1158 * expect. We always assert DTR while the device is open 1159 * unless explicitly requested to deassert it. 1160 */ 1161 com_modem(sc, 1); 1162 1163 /* Clear the input ring, and unblock. */ 1164 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1165 sc->sc_rbavail = com_rbuf_size; 1166 com_iflush(sc); 1167 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1168 com_hwiflow(sc); 1169 1170 #ifdef COM_DEBUG 1171 if (com_debug) 1172 comstatus(sc, "comopen "); 1173 #endif 1174 1175 mutex_spin_exit(&sc->sc_lock); 1176 } 1177 1178 splx(s); 1179 1180 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1181 if (error) 1182 goto bad; 1183 1184 error = (*tp->t_linesw->l_open)(dev, tp); 1185 if (error) 1186 goto bad; 1187 1188 return (0); 1189 1190 bad: 1191 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1192 /* 1193 * We failed to open the device, and nobody else had it opened. 1194 * Clean up the state as appropriate. 1195 */ 1196 com_shutdown(sc); 1197 } 1198 1199 return (error); 1200 } 1201 1202 int 1203 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1204 { 1205 struct com_softc *sc = 1206 device_lookup_private(&com_cd, COMUNIT(dev)); 1207 struct tty *tp = sc->sc_tty; 1208 1209 /* XXX This is for cons.c. */ 1210 if (!ISSET(tp->t_state, TS_ISOPEN)) 1211 return (0); 1212 /* 1213 * If the device is exclusively for kernel use, deny userland 1214 * close. 1215 */ 1216 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1217 return (0); 1218 1219 (*tp->t_linesw->l_close)(tp, flag); 1220 ttyclose(tp); 1221 1222 if (COM_ISALIVE(sc) == 0) 1223 return (0); 1224 1225 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1226 /* 1227 * Although we got a last close, the device may still be in 1228 * use; e.g. if this was the dialout node, and there are still 1229 * processes waiting for carrier on the non-dialout node. 1230 */ 1231 com_shutdown(sc); 1232 } 1233 1234 return (0); 1235 } 1236 1237 int 1238 comread(dev_t dev, struct uio *uio, int flag) 1239 { 1240 struct com_softc *sc = 1241 device_lookup_private(&com_cd, COMUNIT(dev)); 1242 struct tty *tp = sc->sc_tty; 1243 1244 if (COM_ISALIVE(sc) == 0) 1245 return (EIO); 1246 1247 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1248 } 1249 1250 int 1251 comwrite(dev_t dev, struct uio *uio, int flag) 1252 { 1253 struct com_softc *sc = 1254 device_lookup_private(&com_cd, COMUNIT(dev)); 1255 struct tty *tp = sc->sc_tty; 1256 1257 if (COM_ISALIVE(sc) == 0) 1258 return (EIO); 1259 1260 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1261 } 1262 1263 int 1264 compoll(dev_t dev, int events, struct lwp *l) 1265 { 1266 struct com_softc *sc = 1267 device_lookup_private(&com_cd, COMUNIT(dev)); 1268 struct tty *tp = sc->sc_tty; 1269 1270 if (COM_ISALIVE(sc) == 0) 1271 return (POLLHUP); 1272 1273 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1274 } 1275 1276 struct tty * 1277 comtty(dev_t dev) 1278 { 1279 struct com_softc *sc = 1280 device_lookup_private(&com_cd, COMUNIT(dev)); 1281 struct tty *tp = sc->sc_tty; 1282 1283 return (tp); 1284 } 1285 1286 int 1287 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1288 { 1289 struct com_softc *sc; 1290 struct tty *tp; 1291 int error; 1292 1293 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1294 if (sc == NULL) 1295 return ENXIO; 1296 if (COM_ISALIVE(sc) == 0) 1297 return (EIO); 1298 1299 tp = sc->sc_tty; 1300 1301 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1302 if (error != EPASSTHROUGH) 1303 return (error); 1304 1305 error = ttioctl(tp, cmd, data, flag, l); 1306 if (error != EPASSTHROUGH) 1307 return (error); 1308 1309 error = 0; 1310 switch (cmd) { 1311 case TIOCSFLAGS: 1312 error = kauth_authorize_device_tty(l->l_cred, 1313 KAUTH_DEVICE_TTY_PRIVSET, tp); 1314 break; 1315 default: 1316 /* nothing */ 1317 break; 1318 } 1319 if (error) { 1320 return error; 1321 } 1322 1323 mutex_spin_enter(&sc->sc_lock); 1324 1325 switch (cmd) { 1326 case TIOCSBRK: 1327 com_break(sc, 1); 1328 break; 1329 1330 case TIOCCBRK: 1331 com_break(sc, 0); 1332 break; 1333 1334 case TIOCSDTR: 1335 com_modem(sc, 1); 1336 break; 1337 1338 case TIOCCDTR: 1339 com_modem(sc, 0); 1340 break; 1341 1342 case TIOCGFLAGS: 1343 *(int *)data = sc->sc_swflags; 1344 break; 1345 1346 case TIOCSFLAGS: 1347 sc->sc_swflags = *(int *)data; 1348 break; 1349 1350 case TIOCMSET: 1351 case TIOCMBIS: 1352 case TIOCMBIC: 1353 tiocm_to_com(sc, cmd, *(int *)data); 1354 break; 1355 1356 case TIOCMGET: 1357 *(int *)data = com_to_tiocm(sc); 1358 break; 1359 1360 case PPS_IOC_CREATE: 1361 case PPS_IOC_DESTROY: 1362 case PPS_IOC_GETPARAMS: 1363 case PPS_IOC_SETPARAMS: 1364 case PPS_IOC_GETCAP: 1365 case PPS_IOC_FETCH: 1366 #ifdef PPS_SYNC 1367 case PPS_IOC_KCBIND: 1368 #endif 1369 mutex_spin_enter(&timecounter_lock); 1370 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1371 mutex_spin_exit(&timecounter_lock); 1372 break; 1373 1374 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1375 mutex_spin_enter(&timecounter_lock); 1376 #ifndef PPS_TRAILING_EDGE 1377 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1378 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1379 #else 1380 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1381 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1382 #endif 1383 mutex_spin_exit(&timecounter_lock); 1384 break; 1385 1386 default: 1387 error = EPASSTHROUGH; 1388 break; 1389 } 1390 1391 mutex_spin_exit(&sc->sc_lock); 1392 1393 #ifdef COM_DEBUG 1394 if (com_debug) 1395 comstatus(sc, "comioctl "); 1396 #endif 1397 1398 return (error); 1399 } 1400 1401 integrate void 1402 com_schedrx(struct com_softc *sc) 1403 { 1404 1405 sc->sc_rx_ready = 1; 1406 1407 /* Wake up the poller. */ 1408 softint_schedule(sc->sc_si); 1409 } 1410 1411 void 1412 com_break(struct com_softc *sc, int onoff) 1413 { 1414 1415 if (onoff) 1416 SET(sc->sc_lcr, LCR_SBREAK); 1417 else 1418 CLR(sc->sc_lcr, LCR_SBREAK); 1419 1420 if (!sc->sc_heldchange) { 1421 if (sc->sc_tx_busy) { 1422 sc->sc_heldtbc = sc->sc_tbc; 1423 sc->sc_tbc = 0; 1424 sc->sc_heldchange = 1; 1425 } else 1426 com_loadchannelregs(sc); 1427 } 1428 } 1429 1430 void 1431 com_modem(struct com_softc *sc, int onoff) 1432 { 1433 1434 if (sc->sc_mcr_dtr == 0) 1435 return; 1436 1437 if (onoff) 1438 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1439 else 1440 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1441 1442 if (!sc->sc_heldchange) { 1443 if (sc->sc_tx_busy) { 1444 sc->sc_heldtbc = sc->sc_tbc; 1445 sc->sc_tbc = 0; 1446 sc->sc_heldchange = 1; 1447 } else 1448 com_loadchannelregs(sc); 1449 } 1450 } 1451 1452 void 1453 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1454 { 1455 u_char combits; 1456 1457 combits = 0; 1458 if (ISSET(ttybits, TIOCM_DTR)) 1459 SET(combits, MCR_DTR); 1460 if (ISSET(ttybits, TIOCM_RTS)) 1461 SET(combits, MCR_RTS); 1462 1463 switch (how) { 1464 case TIOCMBIC: 1465 CLR(sc->sc_mcr, combits); 1466 break; 1467 1468 case TIOCMBIS: 1469 SET(sc->sc_mcr, combits); 1470 break; 1471 1472 case TIOCMSET: 1473 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1474 SET(sc->sc_mcr, combits); 1475 break; 1476 } 1477 1478 if (!sc->sc_heldchange) { 1479 if (sc->sc_tx_busy) { 1480 sc->sc_heldtbc = sc->sc_tbc; 1481 sc->sc_tbc = 0; 1482 sc->sc_heldchange = 1; 1483 } else 1484 com_loadchannelregs(sc); 1485 } 1486 } 1487 1488 int 1489 com_to_tiocm(struct com_softc *sc) 1490 { 1491 u_char combits; 1492 int ttybits = 0; 1493 1494 combits = sc->sc_mcr; 1495 if (ISSET(combits, MCR_DTR)) 1496 SET(ttybits, TIOCM_DTR); 1497 if (ISSET(combits, MCR_RTS)) 1498 SET(ttybits, TIOCM_RTS); 1499 1500 combits = sc->sc_msr; 1501 if (sc->sc_type == COM_TYPE_INGENIC) { 1502 SET(ttybits, TIOCM_CD); 1503 } else { 1504 if (ISSET(combits, MSR_DCD)) 1505 SET(ttybits, TIOCM_CD); 1506 } 1507 if (ISSET(combits, MSR_CTS)) 1508 SET(ttybits, TIOCM_CTS); 1509 if (ISSET(combits, MSR_DSR)) 1510 SET(ttybits, TIOCM_DSR); 1511 if (ISSET(combits, MSR_RI | MSR_TERI)) 1512 SET(ttybits, TIOCM_RI); 1513 1514 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1515 SET(ttybits, TIOCM_LE); 1516 1517 return (ttybits); 1518 } 1519 1520 static u_char 1521 cflag2lcr(tcflag_t cflag) 1522 { 1523 u_char lcr = 0; 1524 1525 switch (ISSET(cflag, CSIZE)) { 1526 case CS5: 1527 SET(lcr, LCR_5BITS); 1528 break; 1529 case CS6: 1530 SET(lcr, LCR_6BITS); 1531 break; 1532 case CS7: 1533 SET(lcr, LCR_7BITS); 1534 break; 1535 case CS8: 1536 SET(lcr, LCR_8BITS); 1537 break; 1538 } 1539 if (ISSET(cflag, PARENB)) { 1540 SET(lcr, LCR_PENAB); 1541 if (!ISSET(cflag, PARODD)) 1542 SET(lcr, LCR_PEVEN); 1543 } 1544 if (ISSET(cflag, CSTOPB)) 1545 SET(lcr, LCR_STOPB); 1546 1547 return (lcr); 1548 } 1549 1550 int 1551 comparam(struct tty *tp, struct termios *t) 1552 { 1553 struct com_softc *sc = 1554 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1555 int ospeed; 1556 u_char lcr; 1557 1558 if (COM_ISALIVE(sc) == 0) 1559 return (EIO); 1560 1561 if (sc->sc_type == COM_TYPE_HAYESP) { 1562 int prescaler, speed; 1563 1564 /* 1565 * Calculate UART clock prescaler. It should be in 1566 * range of 0 .. 3. 1567 */ 1568 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1569 prescaler++, speed /= 2) 1570 if ((ospeed = comspeed(speed, sc->sc_frequency, 1571 sc->sc_type)) > 0) 1572 break; 1573 1574 if (prescaler == 4) 1575 return (EINVAL); 1576 sc->sc_prescaler = prescaler; 1577 } else 1578 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1579 1580 /* Check requested parameters. */ 1581 if (ospeed < 0) 1582 return (EINVAL); 1583 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1584 return (EINVAL); 1585 1586 /* 1587 * For the console, always force CLOCAL and !HUPCL, so that the port 1588 * is always active. 1589 */ 1590 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1591 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1592 SET(t->c_cflag, CLOCAL); 1593 CLR(t->c_cflag, HUPCL); 1594 } 1595 1596 /* 1597 * If there were no changes, don't do anything. This avoids dropping 1598 * input and improves performance when all we did was frob things like 1599 * VMIN and VTIME. 1600 */ 1601 if (tp->t_ospeed == t->c_ospeed && 1602 tp->t_cflag == t->c_cflag) 1603 return (0); 1604 1605 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1606 1607 mutex_spin_enter(&sc->sc_lock); 1608 1609 sc->sc_lcr = lcr; 1610 1611 /* 1612 * If we're not in a mode that assumes a connection is present, then 1613 * ignore carrier changes. 1614 */ 1615 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1616 sc->sc_msr_dcd = 0; 1617 else 1618 sc->sc_msr_dcd = MSR_DCD; 1619 /* 1620 * Set the flow control pins depending on the current flow control 1621 * mode. 1622 */ 1623 if (ISSET(t->c_cflag, CRTSCTS)) { 1624 sc->sc_mcr_dtr = MCR_DTR; 1625 sc->sc_mcr_rts = MCR_RTS; 1626 sc->sc_msr_cts = MSR_CTS; 1627 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1628 SET(sc->sc_mcr, MCR_AFE); 1629 } else { 1630 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1631 } 1632 } else if (ISSET(t->c_cflag, MDMBUF)) { 1633 /* 1634 * For DTR/DCD flow control, make sure we don't toggle DTR for 1635 * carrier detection. 1636 */ 1637 sc->sc_mcr_dtr = 0; 1638 sc->sc_mcr_rts = MCR_DTR; 1639 sc->sc_msr_cts = MSR_DCD; 1640 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1641 CLR(sc->sc_mcr, MCR_AFE); 1642 } else { 1643 sc->sc_efr = 0; 1644 } 1645 } else { 1646 /* 1647 * If no flow control, then always set RTS. This will make 1648 * the other side happy if it mistakenly thinks we're doing 1649 * RTS/CTS flow control. 1650 */ 1651 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1652 sc->sc_mcr_rts = 0; 1653 sc->sc_msr_cts = 0; 1654 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1655 CLR(sc->sc_mcr, MCR_AFE); 1656 } else { 1657 sc->sc_efr = 0; 1658 } 1659 if (ISSET(sc->sc_mcr, MCR_DTR)) 1660 SET(sc->sc_mcr, MCR_RTS); 1661 else 1662 CLR(sc->sc_mcr, MCR_RTS); 1663 } 1664 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1665 1666 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1667 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1668 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1669 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1670 1671 sc->sc_dlbl = ospeed; 1672 sc->sc_dlbh = ospeed >> 8; 1673 1674 /* 1675 * Set the FIFO threshold based on the receive speed. 1676 * 1677 * * If it's a low speed, it's probably a mouse or some other 1678 * interactive device, so set the threshold low. 1679 * * If it's a high speed, trim the trigger level down to prevent 1680 * overflows. 1681 * * Otherwise set it a bit higher. 1682 */ 1683 if (sc->sc_type == COM_TYPE_HAYESP) { 1684 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1685 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1686 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1687 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1688 if (t->c_ospeed <= 1200) 1689 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1690 else if (t->c_ospeed <= 38400) 1691 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1692 else 1693 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1694 } else { 1695 sc->sc_fifo = 0; 1696 } 1697 1698 if (sc->sc_type == COM_TYPE_INGENIC) 1699 sc->sc_fifo |= FIFO_UART_ON; 1700 1701 /* And copy to tty. */ 1702 tp->t_ispeed = t->c_ospeed; 1703 tp->t_ospeed = t->c_ospeed; 1704 tp->t_cflag = t->c_cflag; 1705 1706 if (!sc->sc_heldchange) { 1707 if (sc->sc_tx_busy) { 1708 sc->sc_heldtbc = sc->sc_tbc; 1709 sc->sc_tbc = 0; 1710 sc->sc_heldchange = 1; 1711 } else 1712 com_loadchannelregs(sc); 1713 } 1714 1715 if (!ISSET(t->c_cflag, CHWFLOW)) { 1716 /* Disable the high water mark. */ 1717 sc->sc_r_hiwat = 0; 1718 sc->sc_r_lowat = 0; 1719 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1720 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1721 com_schedrx(sc); 1722 } 1723 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1724 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1725 com_hwiflow(sc); 1726 } 1727 } else { 1728 sc->sc_r_hiwat = com_rbuf_hiwat; 1729 sc->sc_r_lowat = com_rbuf_lowat; 1730 } 1731 1732 mutex_spin_exit(&sc->sc_lock); 1733 1734 /* 1735 * Update the tty layer's idea of the carrier bit, in case we changed 1736 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1737 * explicit request. 1738 */ 1739 if (sc->sc_type == COM_TYPE_INGENIC) { 1740 /* no DCD here */ 1741 (void) (*tp->t_linesw->l_modem)(tp, 1); 1742 } else 1743 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1744 1745 #ifdef COM_DEBUG 1746 if (com_debug) 1747 comstatus(sc, "comparam "); 1748 #endif 1749 1750 if (!ISSET(t->c_cflag, CHWFLOW)) { 1751 if (sc->sc_tx_stopped) { 1752 sc->sc_tx_stopped = 0; 1753 comstart(tp); 1754 } 1755 } 1756 1757 return (0); 1758 } 1759 1760 void 1761 com_iflush(struct com_softc *sc) 1762 { 1763 struct com_regs *regsp = &sc->sc_regs; 1764 uint8_t fifo; 1765 #ifdef DIAGNOSTIC 1766 int reg; 1767 #endif 1768 int timo; 1769 1770 #ifdef DIAGNOSTIC 1771 reg = 0xffff; 1772 #endif 1773 timo = 50000; 1774 /* flush any pending I/O */ 1775 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1776 && --timo) 1777 #ifdef DIAGNOSTIC 1778 reg = 1779 #else 1780 (void) 1781 #endif 1782 CSR_READ_1(regsp, COM_REG_RXDATA); 1783 #ifdef DIAGNOSTIC 1784 if (!timo) 1785 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1786 #endif 1787 1788 switch (sc->sc_type) { 1789 case COM_TYPE_16750: 1790 case COM_TYPE_DW_APB: 1791 /* 1792 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1793 * This should prevent triggering busy interrupt while 1794 * manipulating divisors. 1795 */ 1796 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1797 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1798 CSR_WRITE_1(regsp, COM_REG_FIFO, 1799 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1800 delay(100); 1801 break; 1802 } 1803 } 1804 1805 void 1806 com_loadchannelregs(struct com_softc *sc) 1807 { 1808 struct com_regs *regsp = &sc->sc_regs; 1809 1810 /* XXXXX necessary? */ 1811 com_iflush(sc); 1812 1813 if (sc->sc_type == COM_TYPE_PXA2x0) 1814 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1815 else 1816 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1817 1818 if (sc->sc_type == COM_TYPE_OMAP) { 1819 /* disable before changing settings */ 1820 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1821 } 1822 1823 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1824 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1825 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1826 /* no EFR on alchemy */ 1827 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1828 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1829 } 1830 if (sc->sc_type == COM_TYPE_AU1x00) { 1831 /* alchemy has single separate 16-bit clock divisor register */ 1832 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1833 (sc->sc_dlbh << 8)); 1834 } else { 1835 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1836 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1837 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1838 } 1839 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1840 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1841 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1842 if (sc->sc_type == COM_TYPE_HAYESP) { 1843 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1844 HAYESP_SETPRESCALER); 1845 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1846 sc->sc_prescaler); 1847 } 1848 if (sc->sc_type == COM_TYPE_OMAP) { 1849 /* setup the fifos. the FCR value is not used as long 1850 as SCR[6] and SCR[7] are 0, which they are at reset 1851 and we never touch the SCR register */ 1852 uint8_t rx_fifo_trig = 40; 1853 uint8_t tx_fifo_trig = 60; 1854 uint8_t rx_start = 8; 1855 uint8_t rx_halt = 60; 1856 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1857 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1858 1859 /* enable access to TCR & TLR */ 1860 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1861 1862 /* write tcr and tlr values */ 1863 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1864 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1865 1866 /* disable access to TCR & TLR */ 1867 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1868 1869 /* enable again, but mode is based on speed */ 1870 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1871 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1872 } else { 1873 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1874 } 1875 } 1876 1877 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1878 } 1879 1880 int 1881 comhwiflow(struct tty *tp, int block) 1882 { 1883 struct com_softc *sc = 1884 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1885 1886 if (COM_ISALIVE(sc) == 0) 1887 return (0); 1888 1889 if (sc->sc_mcr_rts == 0) 1890 return (0); 1891 1892 mutex_spin_enter(&sc->sc_lock); 1893 1894 if (block) { 1895 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1896 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1897 com_hwiflow(sc); 1898 } 1899 } else { 1900 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1901 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1902 com_schedrx(sc); 1903 } 1904 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1905 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1906 com_hwiflow(sc); 1907 } 1908 } 1909 1910 mutex_spin_exit(&sc->sc_lock); 1911 return (1); 1912 } 1913 1914 /* 1915 * (un)block input via hw flowcontrol 1916 */ 1917 void 1918 com_hwiflow(struct com_softc *sc) 1919 { 1920 struct com_regs *regsp= &sc->sc_regs; 1921 1922 if (sc->sc_mcr_rts == 0) 1923 return; 1924 1925 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1926 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1927 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1928 } else { 1929 SET(sc->sc_mcr, sc->sc_mcr_rts); 1930 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1931 } 1932 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1933 } 1934 1935 1936 void 1937 comstart(struct tty *tp) 1938 { 1939 struct com_softc *sc = 1940 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1941 struct com_regs *regsp = &sc->sc_regs; 1942 int s; 1943 1944 if (COM_ISALIVE(sc) == 0) 1945 return; 1946 1947 s = spltty(); 1948 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1949 goto out; 1950 if (sc->sc_tx_stopped) 1951 goto out; 1952 if (!ttypull(tp)) 1953 goto out; 1954 1955 /* Grab the first contiguous region of buffer space. */ 1956 { 1957 u_char *tba; 1958 int tbc; 1959 1960 tba = tp->t_outq.c_cf; 1961 tbc = ndqb(&tp->t_outq, 0); 1962 1963 mutex_spin_enter(&sc->sc_lock); 1964 1965 sc->sc_tba = tba; 1966 sc->sc_tbc = tbc; 1967 } 1968 1969 SET(tp->t_state, TS_BUSY); 1970 sc->sc_tx_busy = 1; 1971 1972 /* Enable transmit completion interrupts if necessary. */ 1973 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1974 SET(sc->sc_ier, IER_ETXRDY); 1975 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1976 } 1977 1978 /* Output the first chunk of the contiguous buffer. */ 1979 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1980 u_int n; 1981 1982 n = sc->sc_tbc; 1983 if (n > sc->sc_fifolen) 1984 n = sc->sc_fifolen; 1985 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1986 sc->sc_tbc -= n; 1987 sc->sc_tba += n; 1988 } 1989 1990 mutex_spin_exit(&sc->sc_lock); 1991 out: 1992 splx(s); 1993 return; 1994 } 1995 1996 /* 1997 * Stop output on a line. 1998 */ 1999 void 2000 comstop(struct tty *tp, int flag) 2001 { 2002 struct com_softc *sc = 2003 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 2004 2005 mutex_spin_enter(&sc->sc_lock); 2006 if (ISSET(tp->t_state, TS_BUSY)) { 2007 /* Stop transmitting at the next chunk. */ 2008 sc->sc_tbc = 0; 2009 sc->sc_heldtbc = 0; 2010 if (!ISSET(tp->t_state, TS_TTSTOP)) 2011 SET(tp->t_state, TS_FLUSH); 2012 } 2013 mutex_spin_exit(&sc->sc_lock); 2014 } 2015 2016 void 2017 comdiag(void *arg) 2018 { 2019 struct com_softc *sc = arg; 2020 int overflows, floods; 2021 2022 mutex_spin_enter(&sc->sc_lock); 2023 overflows = sc->sc_overflows; 2024 sc->sc_overflows = 0; 2025 floods = sc->sc_floods; 2026 sc->sc_floods = 0; 2027 sc->sc_errors = 0; 2028 mutex_spin_exit(&sc->sc_lock); 2029 2030 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 2031 device_xname(sc->sc_dev), 2032 overflows, overflows == 1 ? "" : "s", 2033 floods, floods == 1 ? "" : "s"); 2034 } 2035 2036 integrate void 2037 com_rxsoft(struct com_softc *sc, struct tty *tp) 2038 { 2039 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 2040 u_char *get, *end; 2041 u_int cc, scc; 2042 u_char lsr; 2043 int code; 2044 2045 end = sc->sc_ebuf; 2046 get = sc->sc_rbget; 2047 scc = cc = com_rbuf_size - sc->sc_rbavail; 2048 2049 if (cc == com_rbuf_size) { 2050 sc->sc_floods++; 2051 if (sc->sc_errors++ == 0) 2052 callout_reset(&sc->sc_diag_callout, 60 * hz, 2053 comdiag, sc); 2054 } 2055 2056 /* If not yet open, drop the entire buffer content here */ 2057 if (!ISSET(tp->t_state, TS_ISOPEN)) { 2058 get += cc << 1; 2059 if (get >= end) 2060 get -= com_rbuf_size << 1; 2061 cc = 0; 2062 } 2063 while (cc) { 2064 code = get[0]; 2065 lsr = get[1]; 2066 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 2067 if (ISSET(lsr, LSR_OE)) { 2068 sc->sc_overflows++; 2069 if (sc->sc_errors++ == 0) 2070 callout_reset(&sc->sc_diag_callout, 2071 60 * hz, comdiag, sc); 2072 } 2073 if (ISSET(lsr, LSR_BI | LSR_FE)) 2074 SET(code, TTY_FE); 2075 if (ISSET(lsr, LSR_PE)) 2076 SET(code, TTY_PE); 2077 } 2078 if ((*rint)(code, tp) == -1) { 2079 /* 2080 * The line discipline's buffer is out of space. 2081 */ 2082 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 2083 /* 2084 * We're either not using flow control, or the 2085 * line discipline didn't tell us to block for 2086 * some reason. Either way, we have no way to 2087 * know when there's more space available, so 2088 * just drop the rest of the data. 2089 */ 2090 get += cc << 1; 2091 if (get >= end) 2092 get -= com_rbuf_size << 1; 2093 cc = 0; 2094 } else { 2095 /* 2096 * Don't schedule any more receive processing 2097 * until the line discipline tells us there's 2098 * space available (through comhwiflow()). 2099 * Leave the rest of the data in the input 2100 * buffer. 2101 */ 2102 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 2103 } 2104 break; 2105 } 2106 get += 2; 2107 if (get >= end) 2108 get = sc->sc_rbuf; 2109 cc--; 2110 } 2111 2112 if (cc != scc) { 2113 sc->sc_rbget = get; 2114 mutex_spin_enter(&sc->sc_lock); 2115 2116 cc = sc->sc_rbavail += scc - cc; 2117 /* Buffers should be ok again, release possible block. */ 2118 if (cc >= sc->sc_r_lowat) { 2119 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2120 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2121 SET(sc->sc_ier, IER_ERXRDY); 2122 if (sc->sc_type == COM_TYPE_PXA2x0) 2123 SET(sc->sc_ier, IER_ERXTOUT); 2124 if (sc->sc_type == COM_TYPE_INGENIC || 2125 sc->sc_type == COM_TYPE_TEGRA) 2126 SET(sc->sc_ier, IER_ERXTOUT); 2127 2128 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 2129 sc->sc_ier); 2130 } 2131 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 2132 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2133 com_hwiflow(sc); 2134 } 2135 } 2136 mutex_spin_exit(&sc->sc_lock); 2137 } 2138 } 2139 2140 integrate void 2141 com_txsoft(struct com_softc *sc, struct tty *tp) 2142 { 2143 2144 CLR(tp->t_state, TS_BUSY); 2145 if (ISSET(tp->t_state, TS_FLUSH)) 2146 CLR(tp->t_state, TS_FLUSH); 2147 else 2148 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2149 (*tp->t_linesw->l_start)(tp); 2150 } 2151 2152 integrate void 2153 com_stsoft(struct com_softc *sc, struct tty *tp) 2154 { 2155 u_char msr, delta; 2156 2157 mutex_spin_enter(&sc->sc_lock); 2158 msr = sc->sc_msr; 2159 delta = sc->sc_msr_delta; 2160 sc->sc_msr_delta = 0; 2161 mutex_spin_exit(&sc->sc_lock); 2162 2163 if (ISSET(delta, sc->sc_msr_dcd)) { 2164 /* 2165 * Inform the tty layer that carrier detect changed. 2166 */ 2167 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2168 } 2169 2170 if (ISSET(delta, sc->sc_msr_cts)) { 2171 /* Block or unblock output according to flow control. */ 2172 if (ISSET(msr, sc->sc_msr_cts)) { 2173 sc->sc_tx_stopped = 0; 2174 (*tp->t_linesw->l_start)(tp); 2175 } else { 2176 sc->sc_tx_stopped = 1; 2177 } 2178 } 2179 2180 #ifdef COM_DEBUG 2181 if (com_debug) 2182 comstatus(sc, "com_stsoft"); 2183 #endif 2184 } 2185 2186 void 2187 comsoft(void *arg) 2188 { 2189 struct com_softc *sc = arg; 2190 struct tty *tp; 2191 2192 if (COM_ISALIVE(sc) == 0) 2193 return; 2194 2195 tp = sc->sc_tty; 2196 2197 if (sc->sc_rx_ready) { 2198 sc->sc_rx_ready = 0; 2199 com_rxsoft(sc, tp); 2200 } 2201 2202 if (sc->sc_st_check) { 2203 sc->sc_st_check = 0; 2204 com_stsoft(sc, tp); 2205 } 2206 2207 if (sc->sc_tx_done) { 2208 sc->sc_tx_done = 0; 2209 com_txsoft(sc, tp); 2210 } 2211 } 2212 2213 int 2214 comintr(void *arg) 2215 { 2216 struct com_softc *sc = arg; 2217 struct com_regs *regsp = &sc->sc_regs; 2218 2219 u_char *put, *end; 2220 u_int cc; 2221 u_char lsr, iir; 2222 2223 if (COM_ISALIVE(sc) == 0) 2224 return (0); 2225 2226 KASSERT(regsp != NULL); 2227 2228 mutex_spin_enter(&sc->sc_lock); 2229 iir = CSR_READ_1(regsp, COM_REG_IIR); 2230 2231 /* Handle ns16750-specific busy interrupt. */ 2232 if (sc->sc_type == COM_TYPE_16750 && 2233 (iir & IIR_BUSY) == IIR_BUSY) { 2234 for (int timeout = 10000; 2235 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2236 if (timeout <= 0) { 2237 aprint_error_dev(sc->sc_dev, 2238 "timeout while waiting for BUSY interrupt " 2239 "acknowledge\n"); 2240 mutex_spin_exit(&sc->sc_lock); 2241 return (0); 2242 } 2243 2244 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2245 iir = CSR_READ_1(regsp, COM_REG_IIR); 2246 } 2247 2248 /* DesignWare APB UART BUSY interrupt */ 2249 if (sc->sc_type == COM_TYPE_DW_APB && 2250 (iir & IIR_BUSY) == IIR_BUSY) { 2251 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 2252 (void)CSR_READ_1(regsp, COM_REG_USR); 2253 } else if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2254 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2255 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2256 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2257 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2258 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2259 CSR_WRITE_1(regsp, COM_REG_HALT, 2260 HALT_CHCFG_EN | HALT_CHCFG_UD); 2261 for (int timeout = 10000000; 2262 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2263 timeout--) { 2264 if (timeout <= 0) { 2265 aprint_error_dev(sc->sc_dev, 2266 "timeout while waiting for HALT " 2267 "update acknowledge 0x%x 0x%x\n", 2268 CSR_READ_1(regsp, COM_REG_HALT), 2269 CSR_READ_1(regsp, COM_REG_USR)); 2270 break; 2271 } 2272 } 2273 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2274 (void)CSR_READ_1(regsp, COM_REG_USR); 2275 } else { 2276 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2277 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2278 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2279 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2280 } 2281 } 2282 2283 end = sc->sc_ebuf; 2284 put = sc->sc_rbput; 2285 cc = sc->sc_rbavail; 2286 2287 if (ISSET(iir, IIR_NOPEND)) { 2288 if (ISSET(sc->sc_hwflags, COM_HW_BROKEN_ETXRDY)) 2289 goto do_tx; 2290 mutex_spin_exit(&sc->sc_lock); 2291 return (0); 2292 } 2293 2294 again: do { 2295 u_char msr, delta; 2296 2297 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2298 if (ISSET(lsr, LSR_BI)) { 2299 int cn_trapped = 0; /* see above: cn_trap() */ 2300 2301 cn_check_magic(sc->sc_tty->t_dev, 2302 CNC_BREAK, com_cnm_state); 2303 if (cn_trapped) 2304 continue; 2305 #if defined(KGDB) && !defined(DDB) 2306 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2307 kgdb_connect(1); 2308 continue; 2309 } 2310 #endif 2311 } 2312 2313 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2314 lsr |= LSR_RXRDY; 2315 2316 if (ISSET(lsr, LSR_RCV_MASK) && 2317 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2318 while (cc > 0) { 2319 int cn_trapped = 0; 2320 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2321 put[1] = lsr; 2322 cn_check_magic(sc->sc_tty->t_dev, 2323 put[0], com_cnm_state); 2324 if (cn_trapped) 2325 goto next; 2326 put += 2; 2327 if (put >= end) 2328 put = sc->sc_rbuf; 2329 cc--; 2330 next: 2331 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2332 if (!ISSET(lsr, LSR_RCV_MASK)) 2333 break; 2334 } 2335 2336 /* 2337 * Current string of incoming characters ended because 2338 * no more data was available or we ran out of space. 2339 * Schedule a receive event if any data was received. 2340 * If we're out of space, turn off receive interrupts. 2341 */ 2342 sc->sc_rbput = put; 2343 sc->sc_rbavail = cc; 2344 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2345 sc->sc_rx_ready = 1; 2346 2347 /* 2348 * See if we are in danger of overflowing a buffer. If 2349 * so, use hardware flow control to ease the pressure. 2350 */ 2351 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2352 cc < sc->sc_r_hiwat) { 2353 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2354 com_hwiflow(sc); 2355 } 2356 2357 /* 2358 * If we're out of space, disable receive interrupts 2359 * until the queue has drained a bit. 2360 */ 2361 if (!cc) { 2362 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2363 switch (sc->sc_type) { 2364 case COM_TYPE_PXA2x0: 2365 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2366 break; 2367 case COM_TYPE_INGENIC: 2368 case COM_TYPE_TEGRA: 2369 CLR(sc->sc_ier, 2370 IER_ERXRDY | IER_ERXTOUT); 2371 break; 2372 default: 2373 CLR(sc->sc_ier, IER_ERXRDY); 2374 break; 2375 } 2376 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2377 } 2378 } else { 2379 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2380 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2381 continue; 2382 } 2383 } 2384 2385 msr = CSR_READ_1(regsp, COM_REG_MSR); 2386 delta = msr ^ sc->sc_msr; 2387 sc->sc_msr = msr; 2388 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2389 (delta & MSR_DCD)) { 2390 mutex_spin_enter(&timecounter_lock); 2391 pps_capture(&sc->sc_pps_state); 2392 pps_event(&sc->sc_pps_state, 2393 (msr & MSR_DCD) ? 2394 PPS_CAPTUREASSERT : 2395 PPS_CAPTURECLEAR); 2396 mutex_spin_exit(&timecounter_lock); 2397 } 2398 2399 /* 2400 * Process normal status changes 2401 */ 2402 if (ISSET(delta, sc->sc_msr_mask)) { 2403 SET(sc->sc_msr_delta, delta); 2404 2405 /* 2406 * Stop output immediately if we lose the output 2407 * flow control signal or carrier detect. 2408 */ 2409 if (ISSET(~msr, sc->sc_msr_mask)) { 2410 sc->sc_tbc = 0; 2411 sc->sc_heldtbc = 0; 2412 #ifdef COM_DEBUG 2413 if (com_debug) 2414 comstatus(sc, "comintr "); 2415 #endif 2416 } 2417 2418 sc->sc_st_check = 1; 2419 } 2420 } while (!ISSET((iir = 2421 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2422 /* 2423 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2424 * by IIR read, so we can't do this way: `process all interrupts, 2425 * then do TX if possible'. 2426 */ 2427 (iir & IIR_IMASK) != IIR_TXRDY); 2428 2429 do_tx: 2430 /* 2431 * Read LSR again, since there may be an interrupt between 2432 * the last LSR read and IIR read above. 2433 */ 2434 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2435 2436 /* 2437 * See if data can be transmitted as well. 2438 * Schedule tx done event if no data left 2439 * and tty was marked busy. 2440 */ 2441 if (ISSET(lsr, LSR_TXRDY)) { 2442 /* 2443 * If we've delayed a parameter change, do it now, and restart 2444 * output. 2445 */ 2446 if (sc->sc_heldchange) { 2447 com_loadchannelregs(sc); 2448 sc->sc_heldchange = 0; 2449 sc->sc_tbc = sc->sc_heldtbc; 2450 sc->sc_heldtbc = 0; 2451 } 2452 2453 /* Output the next chunk of the contiguous buffer, if any. */ 2454 if (sc->sc_tbc > 0) { 2455 u_int n; 2456 2457 n = sc->sc_tbc; 2458 if (n > sc->sc_fifolen) 2459 n = sc->sc_fifolen; 2460 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2461 sc->sc_tbc -= n; 2462 sc->sc_tba += n; 2463 } else { 2464 /* Disable transmit completion interrupts if necessary. */ 2465 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2466 CLR(sc->sc_ier, IER_ETXRDY); 2467 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2468 } 2469 if (sc->sc_tx_busy) { 2470 sc->sc_tx_busy = 0; 2471 sc->sc_tx_done = 1; 2472 } 2473 } 2474 } 2475 2476 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2477 goto again; 2478 2479 mutex_spin_exit(&sc->sc_lock); 2480 2481 /* Wake up the poller. */ 2482 if ((sc->sc_rx_ready | sc->sc_st_check | sc->sc_tx_done) != 0) 2483 softint_schedule(sc->sc_si); 2484 2485 #ifdef RND_COM 2486 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2487 #endif 2488 2489 return (1); 2490 } 2491 2492 /* 2493 * The following functions are polled getc and putc routines, shared 2494 * by the console and kgdb glue. 2495 * 2496 * The read-ahead code is so that you can detect pending in-band 2497 * cn_magic in polled mode while doing output rather than having to 2498 * wait until the kernel decides it needs input. 2499 */ 2500 2501 #define MAX_READAHEAD 20 2502 static int com_readahead[MAX_READAHEAD]; 2503 static int com_readaheadcount = 0; 2504 2505 int 2506 com_common_getc(dev_t dev, struct com_regs *regsp) 2507 { 2508 int s = splserial(); 2509 u_char stat, c; 2510 2511 /* got a character from reading things earlier */ 2512 if (com_readaheadcount > 0) { 2513 int i; 2514 2515 c = com_readahead[0]; 2516 for (i = 1; i < com_readaheadcount; i++) { 2517 com_readahead[i-1] = com_readahead[i]; 2518 } 2519 com_readaheadcount--; 2520 splx(s); 2521 return (c); 2522 } 2523 2524 /* don't block until a character becomes available */ 2525 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2526 splx(s); 2527 return -1; 2528 } 2529 2530 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2531 stat = CSR_READ_1(regsp, COM_REG_IIR); 2532 { 2533 int cn_trapped = 0; /* required by cn_trap, see above */ 2534 #ifdef DDB 2535 extern int db_active; 2536 if (!db_active) 2537 #endif 2538 cn_check_magic(dev, c, com_cnm_state); 2539 } 2540 splx(s); 2541 return (c); 2542 } 2543 2544 static void 2545 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead) 2546 { 2547 int s = splserial(); 2548 int cin, stat, timo; 2549 2550 if (with_readahead && com_readaheadcount < MAX_READAHEAD 2551 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2552 int cn_trapped = 0; 2553 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2554 stat = CSR_READ_1(regsp, COM_REG_IIR); 2555 cn_check_magic(dev, cin, com_cnm_state); 2556 com_readahead[com_readaheadcount++] = cin; 2557 } 2558 2559 /* wait for any pending transmission to finish */ 2560 timo = 150000; 2561 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2562 continue; 2563 2564 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2565 COM_BARRIER(regsp, BR | BW); 2566 2567 splx(s); 2568 } 2569 2570 /* 2571 * Initialize UART for use as console or KGDB line. 2572 */ 2573 int 2574 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2575 tcflag_t cflag) 2576 { 2577 2578 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2579 ®sp->cr_ioh)) 2580 return (ENOMEM); /* ??? */ 2581 2582 if (type == COM_TYPE_OMAP) { 2583 /* disable before changing settings */ 2584 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2585 } 2586 2587 rate = comspeed(rate, frequency, type); 2588 if (rate != -1) { 2589 if (type == COM_TYPE_AU1x00) { 2590 /* no EFR on alchemy */ 2591 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2592 } else { 2593 if ((type != COM_TYPE_16550_NOERS) && 2594 (type != COM_TYPE_INGENIC)) { 2595 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2596 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2597 } 2598 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2599 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2600 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2601 } 2602 } 2603 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2604 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2605 2606 if (type == COM_TYPE_INGENIC) { 2607 CSR_WRITE_1(regsp, COM_REG_FIFO, 2608 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2609 FIFO_TRIGGER_1 | FIFO_UART_ON); 2610 } else { 2611 CSR_WRITE_1(regsp, COM_REG_FIFO, 2612 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2613 FIFO_TRIGGER_1); 2614 } 2615 2616 if (type == COM_TYPE_OMAP) { 2617 /* setup the fifos. the FCR value is not used as long 2618 as SCR[6] and SCR[7] are 0, which they are at reset 2619 and we never touch the SCR register */ 2620 uint8_t rx_fifo_trig = 40; 2621 uint8_t tx_fifo_trig = 60; 2622 uint8_t rx_start = 8; 2623 uint8_t rx_halt = 60; 2624 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2625 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2626 2627 /* enable access to TCR & TLR */ 2628 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2629 2630 /* write tcr and tlr values */ 2631 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2632 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2633 2634 /* disable access to TCR & TLR */ 2635 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2636 2637 /* enable again, but mode is based on speed */ 2638 if (rate > 230400) { 2639 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2640 } else { 2641 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2642 } 2643 } 2644 2645 if (type == COM_TYPE_PXA2x0) 2646 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2647 else 2648 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2649 2650 return (0); 2651 } 2652 2653 int 2654 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2655 tcflag_t cflag) 2656 { 2657 int res; 2658 2659 comcons_info.regs = *regsp; 2660 2661 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2662 if (res) 2663 return (res); 2664 2665 cn_tab = &comcons; 2666 cn_init_magic(&com_cnm_state); 2667 cn_set_magic("\047\001"); /* default magic is BREAK */ 2668 2669 comcons_info.frequency = frequency; 2670 comcons_info.type = type; 2671 comcons_info.rate = rate; 2672 comcons_info.cflag = cflag; 2673 2674 return (0); 2675 } 2676 2677 int 2678 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2679 int type, tcflag_t cflag) 2680 { 2681 struct com_regs regs; 2682 2683 /*XXX*/ 2684 bus_space_handle_t dummy_bsh; 2685 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2686 2687 /* 2688 * dummy_bsh required because com_init_regs() wants it. A 2689 * real bus_space_handle will be filled in by cominit() later. 2690 * XXXJRT Detangle this mess eventually, plz. 2691 */ 2692 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2693 2694 return comcnattach1(®s, rate, frequency, type, cflag); 2695 } 2696 2697 static int 2698 comcnreattach(void) 2699 { 2700 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2701 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2702 } 2703 2704 int 2705 comcngetc(dev_t dev) 2706 { 2707 2708 return (com_common_getc(dev, &comcons_info.regs)); 2709 } 2710 2711 /* 2712 * Console kernel output character routine. 2713 */ 2714 void 2715 comcnputc(dev_t dev, int c) 2716 { 2717 2718 com_common_putc(dev, &comcons_info.regs, c, cold); 2719 } 2720 2721 void 2722 comcnpollc(dev_t dev, int on) 2723 { 2724 2725 com_readaheadcount = 0; 2726 } 2727 2728 #ifdef KGDB 2729 int 2730 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2731 tcflag_t cflag) 2732 { 2733 int res; 2734 2735 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2736 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2737 #if !defined(DDB) 2738 return (EBUSY); /* cannot share with console */ 2739 #else 2740 comkgdbregs = *regsp; 2741 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2742 #endif 2743 } else { 2744 comkgdbregs = *regsp; 2745 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2746 if (res) 2747 return (res); 2748 2749 /* 2750 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2751 * expects this to be initialized 2752 */ 2753 cn_init_magic(&com_cnm_state); 2754 cn_set_magic("\047\001"); 2755 } 2756 2757 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2758 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2759 2760 return (0); 2761 } 2762 2763 int 2764 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2765 int frequency, int type, tcflag_t cflag) 2766 { 2767 struct com_regs regs; 2768 2769 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2770 2771 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2772 } 2773 2774 /* ARGSUSED */ 2775 int 2776 com_kgdb_getc(void *arg) 2777 { 2778 2779 return (com_common_getc(NODEV, &comkgdbregs)); 2780 } 2781 2782 /* ARGSUSED */ 2783 void 2784 com_kgdb_putc(void *arg, int c) 2785 { 2786 2787 com_common_putc(NODEV, &comkgdbregs, c, 0); 2788 } 2789 #endif /* KGDB */ 2790 2791 /* helper function to identify the com ports used by 2792 console or KGDB (and not yet autoconf attached) */ 2793 int 2794 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2795 { 2796 bus_space_handle_t help; 2797 2798 if (!comconsattached && 2799 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2800 iobase == comcons_info.regs.cr_iobase) 2801 help = comcons_info.regs.cr_ioh; 2802 #ifdef KGDB 2803 else if (!com_kgdb_attached && 2804 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2805 iobase == comkgdbregs.cr_iobase) 2806 help = comkgdbregs.cr_ioh; 2807 #endif 2808 else 2809 return (0); 2810 2811 if (ioh) 2812 *ioh = help; 2813 return (1); 2814 } 2815 2816 /* 2817 * this routine exists to serve as a shutdown hook for systems that 2818 * have firmware which doesn't interact properly with a com device in 2819 * FIFO mode. 2820 */ 2821 bool 2822 com_cleanup(device_t self, int how) 2823 { 2824 struct com_softc *sc = device_private(self); 2825 2826 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2827 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2828 2829 return true; 2830 } 2831 2832 bool 2833 com_suspend(device_t self, const pmf_qual_t *qual) 2834 { 2835 struct com_softc *sc = device_private(self); 2836 2837 #if 0 2838 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && cn_tab == &comcons) 2839 cn_tab = &comcons_suspend; 2840 #endif 2841 2842 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2843 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2844 2845 return true; 2846 } 2847 2848 bool 2849 com_resume(device_t self, const pmf_qual_t *qual) 2850 { 2851 struct com_softc *sc = device_private(self); 2852 2853 mutex_spin_enter(&sc->sc_lock); 2854 com_loadchannelregs(sc); 2855 mutex_spin_exit(&sc->sc_lock); 2856 2857 return true; 2858 } 2859
Indexes created Sat Sep 27 22:09:54 GMT 2025