com.c revision 1.381
1 /* $NetBSD: com.c,v 1.381 2022/12/08 09:08:49 knakahara Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 * 67 * Lock order: 68 * tty_lock (IPL_VM) 69 * -> sc->sc_lock (IPL_HIGH) 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.381 2022/12/08 09:08:49 knakahara Exp $"); 74 75 #include "opt_com.h" 76 #include "opt_ddb.h" 77 #include "opt_kgdb.h" 78 #include "opt_lockdebug.h" 79 #include "opt_multiprocessor.h" 80 #include "opt_ntp.h" 81 82 /* The COM16650 option was renamed to COM_16650. */ 83 #ifdef COM16650 84 #error Obsolete COM16650 option; use COM_16650 instead. 85 #endif 86 87 /* 88 * Override cnmagic(9) macro before including <sys/systm.h>. 89 * We need to know if cn_check_magic triggered debugger, so set a flag. 90 * Callers of cn_check_magic must declare int cn_trapped = 0; 91 * XXX: this is *ugly*! 92 */ 93 #define cn_trap() \ 94 do { \ 95 console_debugger(); \ 96 cn_trapped = 1; \ 97 (void)cn_trapped; \ 98 } while (/* CONSTCOND */ 0) 99 100 #include <sys/param.h> 101 #include <sys/systm.h> 102 #include <sys/ioctl.h> 103 #include <sys/select.h> 104 #include <sys/poll.h> 105 #include <sys/tty.h> 106 #include <sys/proc.h> 107 #include <sys/conf.h> 108 #include <sys/file.h> 109 #include <sys/uio.h> 110 #include <sys/kernel.h> 111 #include <sys/syslog.h> 112 #include <sys/device.h> 113 #include <sys/malloc.h> 114 #include <sys/timepps.h> 115 #include <sys/vnode.h> 116 #include <sys/kauth.h> 117 #include <sys/intr.h> 118 #ifdef RND_COM 119 #include <sys/rndsource.h> 120 #endif 121 122 #include <sys/bus.h> 123 124 #include <ddb/db_active.h> 125 126 #include <dev/ic/comreg.h> 127 #include <dev/ic/comvar.h> 128 #include <dev/ic/ns16550reg.h> 129 #include <dev/ic/st16650reg.h> 130 #include <dev/ic/hayespreg.h> 131 #define com_lcr com_cfcr 132 #include <dev/cons.h> 133 134 #include "ioconf.h" 135 136 #define CSR_READ_1(r, o) \ 137 (r)->cr_read((r), (r)->cr_map[o]) 138 #define CSR_WRITE_1(r, o, v) \ 139 (r)->cr_write((r), (r)->cr_map[o], (v)) 140 #define CSR_WRITE_MULTI(r, o, p, n) \ 141 (r)->cr_write_multi((r), (r)->cr_map[o], (p), (n)) 142 143 /* 144 * XXX COM_TYPE_AU1x00 specific 145 */ 146 #define CSR_WRITE_2(r, o, v) \ 147 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 148 #define CSR_READ_2(r, o) \ 149 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 150 151 static void com_enable_debugport(struct com_softc *); 152 153 void com_config(struct com_softc *); 154 void com_shutdown(struct com_softc *); 155 int comspeed(long, long, int); 156 static u_char cflag2lcr(tcflag_t); 157 int comparam(struct tty *, struct termios *); 158 void comstart(struct tty *); 159 int comhwiflow(struct tty *, int); 160 161 void com_loadchannelregs(struct com_softc *); 162 void com_hwiflow(struct com_softc *); 163 void com_break(struct com_softc *, int); 164 void com_modem(struct com_softc *, int); 165 void tiocm_to_com(struct com_softc *, u_long, int); 166 int com_to_tiocm(struct com_softc *); 167 void com_iflush(struct com_softc *); 168 169 int com_common_getc(dev_t, struct com_regs *); 170 static void com_common_putc(dev_t, struct com_regs *, int, int); 171 172 int cominit(struct com_regs *, int, int, int, tcflag_t); 173 174 static int comcnreattach(void); 175 176 int comcngetc(dev_t); 177 void comcnputc(dev_t, int); 178 void comcnpollc(dev_t, int); 179 180 void comsoft(void *); 181 static inline void com_rxsoft(struct com_softc *, struct tty *); 182 static inline void com_txsoft(struct com_softc *, struct tty *); 183 static inline void com_stsoft(struct com_softc *, struct tty *); 184 static inline void com_schedrx(struct com_softc *); 185 void comdiag(void *); 186 187 dev_type_open(comopen); 188 dev_type_close(comclose); 189 dev_type_read(comread); 190 dev_type_write(comwrite); 191 dev_type_ioctl(comioctl); 192 dev_type_stop(comstop); 193 dev_type_tty(comtty); 194 dev_type_poll(compoll); 195 196 static struct comcons_info comcons_info; 197 198 /* 199 * Following are all routines needed for COM to act as console 200 */ 201 static struct consdev comcons = { 202 .cn_getc = comcngetc, 203 .cn_putc = comcnputc, 204 .cn_pollc = comcnpollc, 205 .cn_dev = NODEV, 206 .cn_pri = CN_NORMAL 207 }; 208 209 #define CSR_WRITE_1_SYNC(r, o, v) do { \ 210 CSR_WRITE_1(r, o, v); \ 211 switch(o) { \ 212 case COM_REG_IER: \ 213 (void)CSR_READ_1(r, COM_REG_IIR); \ 214 break; \ 215 case COM_REG_TXDATA: \ 216 (void)CSR_READ_1(r, COM_REG_TLR); \ 217 break; \ 218 } \ 219 } while(0) 220 #define CSR_WRITE_MULTI_SYNC(r, o, p, n) do { \ 221 CSR_WRITE_MULTI(r, o, p, n); \ 222 switch(o) { \ 223 case COM_REG_IER: \ 224 (void)CSR_READ_1(r, COM_REG_IIR); \ 225 break; \ 226 case COM_REG_TXDATA: \ 227 (void)CSR_READ_1(r, COM_REG_TLR); \ 228 break; \ 229 } \ 230 } while(0) 231 232 const struct cdevsw com_cdevsw = { 233 .d_open = comopen, 234 .d_close = comclose, 235 .d_read = comread, 236 .d_write = comwrite, 237 .d_ioctl = comioctl, 238 .d_stop = comstop, 239 .d_tty = comtty, 240 .d_poll = compoll, 241 .d_mmap = nommap, 242 .d_kqfilter = ttykqfilter, 243 .d_discard = nodiscard, 244 .d_flag = D_TTY 245 }; 246 247 /* 248 * Make this an option variable one can patch. 249 * But be warned: this must be a power of 2! 250 */ 251 u_int com_rbuf_size = COM_RING_SIZE; 252 253 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 254 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 255 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 256 257 static int comconsattached; 258 static struct cnm_state com_cnm_state; 259 260 #ifdef KGDB 261 #include <sys/kgdb.h> 262 263 static struct com_regs comkgdbregs; 264 static int com_kgdb_attached; 265 266 int com_kgdb_getc(void *); 267 void com_kgdb_putc(void *, int); 268 #endif /* KGDB */ 269 270 /* initializer for typical 16550-ish hardware */ 271 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 272 [COM_REG_RXDATA] = com_data, 273 [COM_REG_TXDATA] = com_data, 274 [COM_REG_DLBL] = com_dlbl, 275 [COM_REG_DLBH] = com_dlbh, 276 [COM_REG_IER] = com_ier, 277 [COM_REG_IIR] = com_iir, 278 [COM_REG_FIFO] = com_fifo, 279 [COM_REG_TCR] = com_fifo, 280 [COM_REG_EFR] = com_efr, 281 [COM_REG_TLR] = com_efr, 282 [COM_REG_LCR] = com_lcr, 283 [COM_REG_MCR] = com_mcr, 284 [COM_REG_LSR] = com_lsr, 285 [COM_REG_MSR] = com_msr, 286 [COM_REG_USR] = com_usr, 287 [COM_REG_TFL] = com_tfl, 288 [COM_REG_RFL] = com_rfl, 289 [COM_REG_HALT] = com_halt, 290 [COM_REG_MDR1] = com_mdr1, 291 }; 292 293 #define COMDIALOUT_MASK TTDIALOUT_MASK 294 295 #define COMUNIT(x) TTUNIT(x) 296 #define COMDIALOUT(x) TTDIALOUT(x) 297 298 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 299 device_is_active((sc)->sc_dev)) 300 301 #define BR BUS_SPACE_BARRIER_READ 302 #define BW BUS_SPACE_BARRIER_WRITE 303 #define COM_BARRIER(r, f) \ 304 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 305 306 /* 307 * com_read_1 -- 308 * Default register read callback using single byte accesses. 309 */ 310 static uint8_t 311 com_read_1(struct com_regs *regs, u_int reg) 312 { 313 return bus_space_read_1(regs->cr_iot, regs->cr_ioh, reg); 314 } 315 316 /* 317 * com_write_1 -- 318 * Default register write callback using single byte accesses. 319 */ 320 static void 321 com_write_1(struct com_regs *regs, u_int reg, uint8_t val) 322 { 323 bus_space_write_1(regs->cr_iot, regs->cr_ioh, reg, val); 324 } 325 326 /* 327 * com_write_multi_1 -- 328 * Default register multi write callback using single byte accesses. 329 */ 330 static void 331 com_write_multi_1(struct com_regs *regs, u_int reg, const uint8_t *datap, 332 bus_size_t count) 333 { 334 bus_space_write_multi_1(regs->cr_iot, regs->cr_ioh, reg, datap, count); 335 } 336 337 /* 338 * com_read_4 -- 339 * Default register read callback using dword accesses. 340 */ 341 static uint8_t 342 com_read_4(struct com_regs *regs, u_int reg) 343 { 344 return bus_space_read_4(regs->cr_iot, regs->cr_ioh, reg) & 0xff; 345 } 346 347 /* 348 * com_write_4 -- 349 * Default register write callback using dword accesses. 350 */ 351 static void 352 com_write_4(struct com_regs *regs, u_int reg, uint8_t val) 353 { 354 bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, val); 355 } 356 357 /* 358 * com_write_multi_4 -- 359 * Default register multi write callback using dword accesses. 360 */ 361 static void 362 com_write_multi_4(struct com_regs *regs, u_int reg, const uint8_t *datap, 363 bus_size_t count) 364 { 365 while (count-- > 0) { 366 bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, *datap++); 367 } 368 } 369 370 /* 371 * com_init_regs -- 372 * Driver front-ends use this to initialize our register map 373 * in the standard fashion. They may then tailor the map to 374 * their own particular requirements. 375 */ 376 void 377 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 378 bus_addr_t addr) 379 { 380 381 memset(regs, 0, sizeof(*regs)); 382 regs->cr_iot = st; 383 regs->cr_ioh = sh; 384 regs->cr_iobase = addr; 385 regs->cr_nports = COM_NPORTS; 386 regs->cr_read = com_read_1; 387 regs->cr_write = com_write_1; 388 regs->cr_write_multi = com_write_multi_1; 389 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 390 } 391 392 /* 393 * com_init_regs_stride -- 394 * Convenience function for front-ends that have a stride between 395 * registers. 396 */ 397 void 398 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 399 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 400 { 401 402 com_init_regs(regs, st, sh, addr); 403 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 404 regs->cr_map[i] <<= regshift; 405 } 406 regs->cr_nports <<= regshift; 407 } 408 409 /* 410 * com_init_regs_stride_width -- 411 * Convenience function for front-ends that have a stride between 412 * registers and specific I/O width requirements. 413 */ 414 void 415 com_init_regs_stride_width(struct com_regs *regs, bus_space_tag_t st, 416 bus_space_handle_t sh, bus_addr_t addr, 417 u_int regshift, u_int width) 418 { 419 420 com_init_regs(regs, st, sh, addr); 421 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 422 regs->cr_map[i] <<= regshift; 423 } 424 regs->cr_nports <<= regshift; 425 426 switch (width) { 427 case 1: 428 /* Already set by com_init_regs */ 429 break; 430 case 4: 431 regs->cr_read = com_read_4; 432 regs->cr_write = com_write_4; 433 regs->cr_write_multi = com_write_multi_4; 434 break; 435 default: 436 panic("com: unsupported I/O width %d", width); 437 } 438 } 439 440 /*ARGSUSED*/ 441 int 442 comspeed(long speed, long frequency, int type) 443 { 444 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 445 446 int x, err; 447 int divisor = 16; 448 449 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 450 divisor = 13; 451 } 452 453 if (speed == 0) 454 return (0); 455 if (speed < 0) 456 return (-1); 457 x = divrnd(frequency / divisor, speed); 458 if (x <= 0) 459 return (-1); 460 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 461 if (err < 0) 462 err = -err; 463 if (err > COM_TOLERANCE) 464 return (-1); 465 return (x); 466 467 #undef divrnd 468 } 469 470 #ifdef COM_DEBUG 471 int com_debug = 0; 472 473 void comstatus(struct com_softc *, const char *); 474 void 475 comstatus(struct com_softc *sc, const char *str) 476 { 477 struct tty *tp = sc->sc_tty; 478 479 aprint_normal_dev(sc->sc_dev, 480 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 481 str, 482 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 483 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 484 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 485 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 486 sc->sc_tx_stopped ? '+' : '-'); 487 488 aprint_normal_dev(sc->sc_dev, 489 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 490 str, 491 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 492 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 493 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 494 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 495 sc->sc_rx_flags); 496 } 497 #endif 498 499 int 500 com_probe_subr(struct com_regs *regs) 501 { 502 503 /* force access to id reg */ 504 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 505 CSR_WRITE_1(regs, COM_REG_IIR, 0); 506 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 507 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 508 return (0); 509 510 return (1); 511 } 512 513 int 514 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 515 { 516 struct com_regs regs; 517 518 com_init_regs(®s, iot, ioh, 0/*XXX*/); 519 520 return com_probe_subr(®s); 521 } 522 523 /* 524 * No locking in this routine; it is only called during attach, 525 * or with the port already locked. 526 */ 527 static void 528 com_enable_debugport(struct com_softc *sc) 529 { 530 531 /* Turn on line break interrupt, set carrier. */ 532 sc->sc_ier = IER_ERLS; 533 if (sc->sc_type == COM_TYPE_PXA2x0) 534 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 535 if (sc->sc_type == COM_TYPE_INGENIC || 536 sc->sc_type == COM_TYPE_TEGRA) 537 sc->sc_ier |= IER_ERXTOUT; 538 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 539 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 540 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 541 } 542 543 static void 544 com_intr_poll(void *arg) 545 { 546 struct com_softc * const sc = arg; 547 548 comintr(sc); 549 550 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 551 } 552 553 void 554 com_attach_subr(struct com_softc *sc) 555 { 556 struct com_regs *regsp = &sc->sc_regs; 557 struct tty *tp; 558 uint32_t cpr; 559 uint8_t lcr; 560 const char *fifo_msg = NULL; 561 prop_dictionary_t dict; 562 bool is_console = true; 563 bool force_console = false; 564 565 aprint_naive("\n"); 566 567 dict = device_properties(sc->sc_dev); 568 prop_dictionary_get_bool(dict, "is_console", &is_console); 569 prop_dictionary_get_bool(dict, "force_console", &force_console); 570 callout_init(&sc->sc_diag_callout, 0); 571 callout_init(&sc->sc_poll_callout, 0); 572 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 573 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 574 575 #if defined(COM_16650) 576 sc->sc_type = COM_TYPE_16650; 577 #elif defined(COM_16750) 578 sc->sc_type = COM_TYPE_16750; 579 #elif defined(COM_HAYESP) 580 sc->sc_type = COM_TYPE_HAYESP; 581 #elif defined(COM_PXA2X0) 582 sc->sc_type = COM_TYPE_PXA2x0; 583 #endif 584 585 /* Disable interrupts before configuring the device. */ 586 if (sc->sc_type == COM_TYPE_PXA2x0) 587 sc->sc_ier = IER_EUART; 588 else 589 sc->sc_ier = 0; 590 591 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 592 593 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 594 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 595 comconsattached = 1; 596 597 if (force_console) 598 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 599 600 if (cn_tab == NULL && comcnreattach() != 0) { 601 printf("can't re-init serial console @%lx\n", 602 (u_long)comcons_info.regs.cr_iobase); 603 } 604 605 switch (sc->sc_type) { 606 case COM_TYPE_16750: 607 case COM_TYPE_DW_APB: 608 /* Use in comintr(). */ 609 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 610 break; 611 } 612 613 /* Make sure the console is always "hardwired". */ 614 delay(10000); /* wait for output to finish */ 615 if (is_console) { 616 SET(sc->sc_hwflags, COM_HW_CONSOLE); 617 } 618 619 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 620 } 621 622 /* Probe for FIFO */ 623 switch (sc->sc_type) { 624 case COM_TYPE_HAYESP: 625 goto fifodone; 626 627 case COM_TYPE_AU1x00: 628 sc->sc_fifolen = 16; 629 fifo_msg = "Au1X00 UART"; 630 SET(sc->sc_hwflags, COM_HW_FIFO); 631 goto fifodelay; 632 633 case COM_TYPE_16550_NOERS: 634 sc->sc_fifolen = 16; 635 fifo_msg = "ns16650, no ERS"; 636 SET(sc->sc_hwflags, COM_HW_FIFO); 637 goto fifodelay; 638 639 case COM_TYPE_OMAP: 640 sc->sc_fifolen = 64; 641 fifo_msg = "OMAP UART"; 642 SET(sc->sc_hwflags, COM_HW_FIFO); 643 goto fifodelay; 644 645 case COM_TYPE_INGENIC: 646 sc->sc_fifolen = 16; 647 fifo_msg = "Ingenic UART"; 648 SET(sc->sc_hwflags, COM_HW_FIFO); 649 SET(sc->sc_hwflags, COM_HW_NOIEN); 650 goto fifodelay; 651 652 case COM_TYPE_TEGRA: 653 sc->sc_fifolen = 8; 654 fifo_msg = "Tegra UART"; 655 SET(sc->sc_hwflags, COM_HW_FIFO); 656 CSR_WRITE_1(regsp, COM_REG_FIFO, 657 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 658 goto fifodelay; 659 660 case COM_TYPE_BCMAUXUART: 661 sc->sc_fifolen = 1; 662 fifo_msg = "BCM AUX UART"; 663 SET(sc->sc_hwflags, COM_HW_FIFO); 664 CSR_WRITE_1(regsp, COM_REG_FIFO, 665 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 666 goto fifodelay; 667 668 case COM_TYPE_DW_APB: 669 if (!prop_dictionary_get_uint(dict, "fifolen", &sc->sc_fifolen)) { 670 cpr = bus_space_read_4(sc->sc_regs.cr_iot, 671 sc->sc_regs.cr_ioh, DW_APB_UART_CPR); 672 sc->sc_fifolen = __SHIFTOUT(cpr, UART_CPR_FIFO_MODE) * 16; 673 } 674 if (sc->sc_fifolen == 0) { 675 sc->sc_fifolen = 1; 676 fifo_msg = "DesignWare APB UART, no fifo"; 677 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 678 } else { 679 fifo_msg = "DesignWare APB UART"; 680 SET(sc->sc_hwflags, COM_HW_FIFO); 681 CSR_WRITE_1(regsp, COM_REG_FIFO, 682 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 683 } 684 goto fifodelay; 685 } 686 687 sc->sc_fifolen = 1; 688 /* look for a NS 16550AF UART with FIFOs */ 689 if (sc->sc_type == COM_TYPE_INGENIC) { 690 CSR_WRITE_1(regsp, COM_REG_FIFO, 691 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 692 FIFO_TRIGGER_14 | FIFO_UART_ON); 693 } else 694 CSR_WRITE_1(regsp, COM_REG_FIFO, 695 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 696 delay(100); 697 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 698 == IIR_FIFO_MASK) 699 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 700 == FIFO_TRIGGER_14) { 701 SET(sc->sc_hwflags, COM_HW_FIFO); 702 703 fifo_msg = "ns16550a"; 704 sc->sc_fifolen = 16; 705 706 /* 707 * IIR changes into the EFR if LCR is set to LCR_EERS 708 * on 16650s. We also know IIR != 0 at this point. 709 * Write 0 into the EFR, and read it. If the result 710 * is 0, we have a 16650. 711 * 712 * Older 16650s were broken; the test to detect them 713 * is taken from the Linux driver. Apparently 714 * setting DLAB enable gives access to the EFR on 715 * these chips. 716 */ 717 if (sc->sc_type == COM_TYPE_16650) { 718 lcr = CSR_READ_1(regsp, COM_REG_LCR); 719 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 720 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 721 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 722 CSR_WRITE_1(regsp, COM_REG_LCR, 723 lcr | LCR_DLAB); 724 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 725 CLR(sc->sc_hwflags, COM_HW_FIFO); 726 sc->sc_fifolen = 0; 727 } else { 728 SET(sc->sc_hwflags, COM_HW_FLOW); 729 sc->sc_fifolen = 32; 730 } 731 } else 732 sc->sc_fifolen = 16; 733 734 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 735 if (sc->sc_fifolen == 0) 736 fifo_msg = "st16650, broken fifo"; 737 else if (sc->sc_fifolen == 32) 738 fifo_msg = "st16650a"; 739 else 740 fifo_msg = "ns16550a"; 741 } 742 743 /* 744 * TL16C750 can enable 64byte FIFO, only when DLAB 745 * is 1. However, some 16750 may always enable. For 746 * example, restrictions according to DLAB in a data 747 * sheet for SC16C750 were not described. 748 * Please enable 'options COM_16650', supposing you 749 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 750 * should become effective. 751 */ 752 if (sc->sc_type == COM_TYPE_16750) { 753 uint8_t iir1, iir2; 754 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 755 756 lcr = CSR_READ_1(regsp, COM_REG_LCR); 757 CSR_WRITE_1(regsp, COM_REG_LCR, 758 lcr & ~LCR_DLAB); 759 CSR_WRITE_1(regsp, COM_REG_FIFO, 760 fcr | FIFO_64B_ENABLE); 761 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 762 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 763 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 764 CSR_WRITE_1(regsp, COM_REG_FIFO, 765 fcr | FIFO_64B_ENABLE); 766 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 767 768 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 769 770 if (!ISSET(iir1, IIR_64B_FIFO) && 771 ISSET(iir2, IIR_64B_FIFO)) { 772 /* It is TL16C750. */ 773 sc->sc_fifolen = 64; 774 SET(sc->sc_hwflags, COM_HW_AFE); 775 } else 776 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 777 778 if (sc->sc_fifolen == 64) 779 fifo_msg = "tl16c750"; 780 else 781 fifo_msg = "ns16750"; 782 } 783 } else 784 fifo_msg = "ns16550, broken fifo"; 785 else 786 fifo_msg = "ns8250 or ns16450, no fifo"; 787 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 788 789 fifodelay: 790 /* 791 * Some chips will clear down both Tx and Rx FIFOs when zero is 792 * written to com_fifo. If this chip is the console, writing zero 793 * results in some of the chip/FIFO description being lost, so delay 794 * printing it until now. 795 */ 796 delay(10); 797 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 798 aprint_normal(": %s, %d-byte FIFO\n", fifo_msg, sc->sc_fifolen); 799 } else { 800 aprint_normal(": %s\n", fifo_msg); 801 } 802 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 803 sc->sc_fifolen = 1; 804 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 805 } 806 807 fifodone: 808 809 tp = tty_alloc(); 810 tp->t_oproc = comstart; 811 tp->t_param = comparam; 812 tp->t_hwiflow = comhwiflow; 813 tp->t_softc = sc; 814 815 sc->sc_tty = tp; 816 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK); 817 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 818 sc->sc_rbavail = com_rbuf_size; 819 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 820 821 tty_attach(tp); 822 823 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 824 SET(sc->sc_mcr, MCR_IENABLE); 825 826 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 827 int maj; 828 829 /* locate the major number */ 830 maj = cdevsw_lookup_major(&com_cdevsw); 831 832 tp->t_dev = cn_tab->cn_dev = makedev(maj, 833 device_unit(sc->sc_dev)); 834 835 aprint_normal_dev(sc->sc_dev, "console\n"); 836 } 837 838 #ifdef KGDB 839 /* 840 * Allow kgdb to "take over" this port. If this is 841 * not the console and is the kgdb device, it has 842 * exclusive use. If it's the console _and_ the 843 * kgdb device, it doesn't. 844 */ 845 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 846 regsp->cr_iobase == comkgdbregs.cr_iobase) { 847 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 848 com_kgdb_attached = 1; 849 850 SET(sc->sc_hwflags, COM_HW_KGDB); 851 } 852 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 853 } 854 #endif 855 856 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 857 858 #ifdef RND_COM 859 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 860 RND_TYPE_TTY, RND_FLAG_DEFAULT); 861 #endif 862 863 /* if there are no enable/disable functions, assume the device 864 is always enabled */ 865 if (!sc->enable) 866 sc->enabled = 1; 867 868 com_config(sc); 869 870 SET(sc->sc_hwflags, COM_HW_DEV_OK); 871 872 if (sc->sc_poll_ticks != 0) 873 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 874 } 875 876 void 877 com_config(struct com_softc *sc) 878 { 879 struct com_regs *regsp = &sc->sc_regs; 880 881 /* Disable interrupts before configuring the device. */ 882 if (sc->sc_type == COM_TYPE_PXA2x0) 883 sc->sc_ier = IER_EUART; 884 else 885 sc->sc_ier = 0; 886 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 887 (void) CSR_READ_1(regsp, COM_REG_IIR); 888 889 /* Look for a Hayes ESP board. */ 890 if (sc->sc_type == COM_TYPE_HAYESP) { 891 892 /* Set 16550 compatibility mode */ 893 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 894 HAYESP_SETMODE); 895 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 896 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 897 HAYESP_MODE_SCALE); 898 899 /* Set RTS/CTS flow control */ 900 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 901 HAYESP_SETFLOWTYPE); 902 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 903 HAYESP_FLOW_RTS); 904 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 905 HAYESP_FLOW_CTS); 906 907 /* Set flow control levels */ 908 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 909 HAYESP_SETRXFLOW); 910 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 911 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 912 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 913 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 914 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 915 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 916 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 917 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 918 } 919 920 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 921 com_enable_debugport(sc); 922 } 923 924 int 925 com_detach(device_t self, int flags) 926 { 927 struct com_softc *sc = device_private(self); 928 int maj, mn; 929 930 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 931 return EBUSY; 932 933 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 934 (flags & DETACH_SHUTDOWN) != 0) 935 return EBUSY; 936 937 if (sc->disable != NULL && sc->enabled != 0) { 938 (*sc->disable)(sc); 939 sc->enabled = 0; 940 } 941 942 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 943 comconsattached = 0; 944 cn_tab = NULL; 945 } 946 947 /* locate the major number */ 948 maj = cdevsw_lookup_major(&com_cdevsw); 949 950 /* Nuke the vnodes for any open instances. */ 951 mn = device_unit(self); 952 vdevgone(maj, mn, mn, VCHR); 953 954 mn |= COMDIALOUT_MASK; 955 vdevgone(maj, mn, mn, VCHR); 956 957 if (sc->sc_rbuf == NULL) { 958 /* 959 * Ring buffer allocation failed in the com_attach_subr, 960 * only the tty is allocated, and nothing else. 961 */ 962 tty_free(sc->sc_tty); 963 return 0; 964 } 965 966 /* Free the receive buffer. */ 967 free(sc->sc_rbuf, M_DEVBUF); 968 969 /* Detach and free the tty. */ 970 tty_detach(sc->sc_tty); 971 tty_free(sc->sc_tty); 972 973 /* Unhook the soft interrupt handler. */ 974 softint_disestablish(sc->sc_si); 975 976 #ifdef RND_COM 977 /* Unhook the entropy source. */ 978 rnd_detach_source(&sc->rnd_source); 979 #endif 980 callout_destroy(&sc->sc_diag_callout); 981 982 /* Destroy the lock. */ 983 mutex_destroy(&sc->sc_lock); 984 985 return (0); 986 } 987 988 void 989 com_shutdown(struct com_softc *sc) 990 { 991 struct tty *tp = sc->sc_tty; 992 993 mutex_spin_enter(&sc->sc_lock); 994 995 /* If we were asserting flow control, then deassert it. */ 996 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 997 com_hwiflow(sc); 998 999 /* Clear any break condition set with TIOCSBRK. */ 1000 com_break(sc, 0); 1001 1002 /* 1003 * Hang up if necessary. Record when we hung up, so if we 1004 * immediately open the port again, we will wait a bit until 1005 * the other side has had time to notice that we hung up. 1006 */ 1007 if (ISSET(tp->t_cflag, HUPCL)) { 1008 com_modem(sc, 0); 1009 microuptime(&sc->sc_hup_pending); 1010 sc->sc_hup_pending.tv_sec++; 1011 } 1012 1013 /* Turn off interrupts. */ 1014 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1015 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 1016 if ((sc->sc_type == COM_TYPE_PXA2x0) || 1017 (sc->sc_type == COM_TYPE_INGENIC) || 1018 (sc->sc_type == COM_TYPE_TEGRA)) 1019 sc->sc_ier |= IER_ERXTOUT; 1020 } else 1021 sc->sc_ier = 0; 1022 1023 if (sc->sc_type == COM_TYPE_PXA2x0) 1024 sc->sc_ier |= IER_EUART; 1025 1026 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1027 1028 mutex_spin_exit(&sc->sc_lock); 1029 1030 if (sc->disable) { 1031 #ifdef DIAGNOSTIC 1032 if (!sc->enabled) 1033 panic("com_shutdown: not enabled?"); 1034 #endif 1035 (*sc->disable)(sc); 1036 sc->enabled = 0; 1037 } 1038 } 1039 1040 int 1041 comopen(dev_t dev, int flag, int mode, struct lwp *l) 1042 { 1043 struct com_softc *sc; 1044 struct tty *tp; 1045 int s; 1046 int error; 1047 1048 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1049 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 1050 sc->sc_rbuf == NULL) 1051 return (ENXIO); 1052 1053 if (!device_is_active(sc->sc_dev)) 1054 return (ENXIO); 1055 1056 #ifdef KGDB 1057 /* 1058 * If this is the kgdb port, no other use is permitted. 1059 */ 1060 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 1061 return (EBUSY); 1062 #endif 1063 1064 tp = sc->sc_tty; 1065 1066 /* 1067 * If the device is exclusively for kernel use, deny userland 1068 * open. 1069 */ 1070 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1071 return (EBUSY); 1072 1073 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 1074 return (EBUSY); 1075 1076 s = spltty(); 1077 1078 /* 1079 * Do the following iff this is a first open. 1080 */ 1081 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1082 struct termios t; 1083 struct timeval now, diff; 1084 1085 tp->t_dev = dev; 1086 1087 if (sc->enable) { 1088 if ((*sc->enable)(sc)) { 1089 splx(s); 1090 aprint_error_dev(sc->sc_dev, 1091 "device enable failed\n"); 1092 return (EIO); 1093 } 1094 mutex_spin_enter(&sc->sc_lock); 1095 sc->enabled = 1; 1096 com_config(sc); 1097 } else { 1098 mutex_spin_enter(&sc->sc_lock); 1099 } 1100 1101 if (timerisset(&sc->sc_hup_pending)) { 1102 microuptime(&now); 1103 while (timercmp(&now, &sc->sc_hup_pending, <)) { 1104 timersub(&sc->sc_hup_pending, &now, &diff); 1105 const int ms = diff.tv_sec * 1000 + 1106 diff.tv_usec / 1000; 1107 kpause(ttclos, false, uimax(mstohz(ms), 1), 1108 &sc->sc_lock); 1109 microuptime(&now); 1110 } 1111 timerclear(&sc->sc_hup_pending); 1112 } 1113 1114 /* Turn on interrupts. */ 1115 sc->sc_ier = IER_ERXRDY | IER_ERLS; 1116 if (!ISSET(tp->t_cflag, CLOCAL)) 1117 sc->sc_ier |= IER_EMSC; 1118 1119 if (sc->sc_type == COM_TYPE_PXA2x0) 1120 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 1121 else if (sc->sc_type == COM_TYPE_INGENIC || 1122 sc->sc_type == COM_TYPE_TEGRA) 1123 sc->sc_ier |= IER_ERXTOUT; 1124 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1125 1126 /* Fetch the current modem control status, needed later. */ 1127 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 1128 1129 /* Clear PPS capture state on first open. */ 1130 mutex_spin_enter(&timecounter_lock); 1131 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 1132 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1133 pps_init(&sc->sc_pps_state); 1134 mutex_spin_exit(&timecounter_lock); 1135 1136 mutex_spin_exit(&sc->sc_lock); 1137 1138 /* 1139 * Initialize the termios status to the defaults. Add in the 1140 * sticky bits from TIOCSFLAGS. 1141 */ 1142 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1143 t.c_ospeed = comcons_info.rate; 1144 t.c_cflag = comcons_info.cflag; 1145 } else { 1146 t.c_ospeed = TTYDEF_SPEED; 1147 t.c_cflag = TTYDEF_CFLAG; 1148 } 1149 t.c_ispeed = t.c_ospeed; 1150 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1151 SET(t.c_cflag, CLOCAL); 1152 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1153 SET(t.c_cflag, CRTSCTS); 1154 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1155 SET(t.c_cflag, MDMBUF); 1156 /* Make sure comparam() will do something. */ 1157 tp->t_ospeed = 0; 1158 (void) comparam(tp, &t); 1159 tp->t_iflag = TTYDEF_IFLAG; 1160 tp->t_oflag = TTYDEF_OFLAG; 1161 tp->t_lflag = TTYDEF_LFLAG; 1162 ttychars(tp); 1163 ttsetwater(tp); 1164 1165 mutex_spin_enter(&sc->sc_lock); 1166 1167 /* 1168 * Turn on DTR. We must always do this, even if carrier is not 1169 * present, because otherwise we'd have to use TIOCSDTR 1170 * immediately after setting CLOCAL, which applications do not 1171 * expect. We always assert DTR while the device is open 1172 * unless explicitly requested to deassert it. 1173 */ 1174 com_modem(sc, 1); 1175 1176 /* Clear the input ring, and unblock. */ 1177 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1178 sc->sc_rbavail = com_rbuf_size; 1179 com_iflush(sc); 1180 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1181 com_hwiflow(sc); 1182 1183 #ifdef COM_DEBUG 1184 if (com_debug) 1185 comstatus(sc, "comopen "); 1186 #endif 1187 1188 mutex_spin_exit(&sc->sc_lock); 1189 } 1190 1191 splx(s); 1192 1193 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1194 if (error) 1195 goto bad; 1196 1197 error = (*tp->t_linesw->l_open)(dev, tp); 1198 if (error) 1199 goto bad; 1200 1201 return (0); 1202 1203 bad: 1204 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1205 /* 1206 * We failed to open the device, and nobody else had it opened. 1207 * Clean up the state as appropriate. 1208 */ 1209 com_shutdown(sc); 1210 } 1211 1212 return (error); 1213 } 1214 1215 int 1216 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1217 { 1218 struct com_softc *sc = 1219 device_lookup_private(&com_cd, COMUNIT(dev)); 1220 struct tty *tp = sc->sc_tty; 1221 1222 /* XXX This is for cons.c. */ 1223 if (!ISSET(tp->t_state, TS_ISOPEN)) 1224 return (0); 1225 /* 1226 * If the device is exclusively for kernel use, deny userland 1227 * close. 1228 */ 1229 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1230 return (0); 1231 1232 (*tp->t_linesw->l_close)(tp, flag); 1233 ttyclose(tp); 1234 1235 if (COM_ISALIVE(sc) == 0) 1236 return (0); 1237 1238 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1239 /* 1240 * Although we got a last close, the device may still be in 1241 * use; e.g. if this was the dialout node, and there are still 1242 * processes waiting for carrier on the non-dialout node. 1243 */ 1244 com_shutdown(sc); 1245 } 1246 1247 return (0); 1248 } 1249 1250 int 1251 comread(dev_t dev, struct uio *uio, int flag) 1252 { 1253 struct com_softc *sc = 1254 device_lookup_private(&com_cd, COMUNIT(dev)); 1255 struct tty *tp = sc->sc_tty; 1256 1257 if (COM_ISALIVE(sc) == 0) 1258 return (EIO); 1259 1260 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1261 } 1262 1263 int 1264 comwrite(dev_t dev, struct uio *uio, int flag) 1265 { 1266 struct com_softc *sc = 1267 device_lookup_private(&com_cd, COMUNIT(dev)); 1268 struct tty *tp = sc->sc_tty; 1269 1270 if (COM_ISALIVE(sc) == 0) 1271 return (EIO); 1272 1273 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1274 } 1275 1276 int 1277 compoll(dev_t dev, int events, struct lwp *l) 1278 { 1279 struct com_softc *sc = 1280 device_lookup_private(&com_cd, COMUNIT(dev)); 1281 struct tty *tp = sc->sc_tty; 1282 1283 if (COM_ISALIVE(sc) == 0) 1284 return (POLLHUP); 1285 1286 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1287 } 1288 1289 struct tty * 1290 comtty(dev_t dev) 1291 { 1292 struct com_softc *sc = 1293 device_lookup_private(&com_cd, COMUNIT(dev)); 1294 struct tty *tp = sc->sc_tty; 1295 1296 return (tp); 1297 } 1298 1299 int 1300 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1301 { 1302 struct com_softc *sc; 1303 struct tty *tp; 1304 int error; 1305 1306 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1307 if (sc == NULL) 1308 return ENXIO; 1309 if (COM_ISALIVE(sc) == 0) 1310 return (EIO); 1311 1312 tp = sc->sc_tty; 1313 1314 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1315 if (error != EPASSTHROUGH) 1316 return (error); 1317 1318 error = ttioctl(tp, cmd, data, flag, l); 1319 if (error != EPASSTHROUGH) 1320 return (error); 1321 1322 error = 0; 1323 switch (cmd) { 1324 case TIOCSFLAGS: 1325 error = kauth_authorize_device_tty(l->l_cred, 1326 KAUTH_DEVICE_TTY_PRIVSET, tp); 1327 break; 1328 default: 1329 /* nothing */ 1330 break; 1331 } 1332 if (error) { 1333 return error; 1334 } 1335 1336 mutex_spin_enter(&sc->sc_lock); 1337 1338 switch (cmd) { 1339 case TIOCSBRK: 1340 com_break(sc, 1); 1341 break; 1342 1343 case TIOCCBRK: 1344 com_break(sc, 0); 1345 break; 1346 1347 case TIOCSDTR: 1348 com_modem(sc, 1); 1349 break; 1350 1351 case TIOCCDTR: 1352 com_modem(sc, 0); 1353 break; 1354 1355 case TIOCGFLAGS: 1356 *(int *)data = sc->sc_swflags; 1357 break; 1358 1359 case TIOCSFLAGS: 1360 sc->sc_swflags = *(int *)data; 1361 break; 1362 1363 case TIOCMSET: 1364 case TIOCMBIS: 1365 case TIOCMBIC: 1366 tiocm_to_com(sc, cmd, *(int *)data); 1367 break; 1368 1369 case TIOCMGET: 1370 *(int *)data = com_to_tiocm(sc); 1371 break; 1372 1373 case PPS_IOC_CREATE: 1374 case PPS_IOC_DESTROY: 1375 case PPS_IOC_GETPARAMS: 1376 case PPS_IOC_SETPARAMS: 1377 case PPS_IOC_GETCAP: 1378 case PPS_IOC_FETCH: 1379 #ifdef PPS_SYNC 1380 case PPS_IOC_KCBIND: 1381 #endif 1382 mutex_spin_enter(&timecounter_lock); 1383 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1384 mutex_spin_exit(&timecounter_lock); 1385 break; 1386 1387 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1388 mutex_spin_enter(&timecounter_lock); 1389 #ifndef PPS_TRAILING_EDGE 1390 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1391 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1392 #else 1393 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1394 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1395 #endif 1396 mutex_spin_exit(&timecounter_lock); 1397 break; 1398 1399 default: 1400 error = EPASSTHROUGH; 1401 break; 1402 } 1403 1404 mutex_spin_exit(&sc->sc_lock); 1405 1406 #ifdef COM_DEBUG 1407 if (com_debug) 1408 comstatus(sc, "comioctl "); 1409 #endif 1410 1411 return (error); 1412 } 1413 1414 static inline void 1415 com_schedrx(struct com_softc *sc) 1416 { 1417 1418 sc->sc_rx_ready = 1; 1419 1420 /* Wake up the poller. */ 1421 softint_schedule(sc->sc_si); 1422 } 1423 1424 void 1425 com_break(struct com_softc *sc, int onoff) 1426 { 1427 1428 if (onoff) 1429 SET(sc->sc_lcr, LCR_SBREAK); 1430 else 1431 CLR(sc->sc_lcr, LCR_SBREAK); 1432 1433 if (!sc->sc_heldchange) { 1434 if (sc->sc_tx_busy) { 1435 sc->sc_heldtbc = sc->sc_tbc; 1436 sc->sc_tbc = 0; 1437 sc->sc_heldchange = 1; 1438 } else 1439 com_loadchannelregs(sc); 1440 } 1441 } 1442 1443 void 1444 com_modem(struct com_softc *sc, int onoff) 1445 { 1446 1447 if (sc->sc_mcr_dtr == 0) 1448 return; 1449 1450 if (onoff) 1451 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1452 else 1453 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1454 1455 if (!sc->sc_heldchange) { 1456 if (sc->sc_tx_busy) { 1457 sc->sc_heldtbc = sc->sc_tbc; 1458 sc->sc_tbc = 0; 1459 sc->sc_heldchange = 1; 1460 } else 1461 com_loadchannelregs(sc); 1462 } 1463 } 1464 1465 void 1466 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1467 { 1468 u_char combits; 1469 1470 combits = 0; 1471 if (ISSET(ttybits, TIOCM_DTR)) 1472 SET(combits, MCR_DTR); 1473 if (ISSET(ttybits, TIOCM_RTS)) 1474 SET(combits, MCR_RTS); 1475 1476 switch (how) { 1477 case TIOCMBIC: 1478 CLR(sc->sc_mcr, combits); 1479 break; 1480 1481 case TIOCMBIS: 1482 SET(sc->sc_mcr, combits); 1483 break; 1484 1485 case TIOCMSET: 1486 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1487 SET(sc->sc_mcr, combits); 1488 break; 1489 } 1490 1491 if (!sc->sc_heldchange) { 1492 if (sc->sc_tx_busy) { 1493 sc->sc_heldtbc = sc->sc_tbc; 1494 sc->sc_tbc = 0; 1495 sc->sc_heldchange = 1; 1496 } else 1497 com_loadchannelregs(sc); 1498 } 1499 } 1500 1501 int 1502 com_to_tiocm(struct com_softc *sc) 1503 { 1504 u_char combits; 1505 int ttybits = 0; 1506 1507 combits = sc->sc_mcr; 1508 if (ISSET(combits, MCR_DTR)) 1509 SET(ttybits, TIOCM_DTR); 1510 if (ISSET(combits, MCR_RTS)) 1511 SET(ttybits, TIOCM_RTS); 1512 1513 combits = sc->sc_msr; 1514 if (sc->sc_type == COM_TYPE_INGENIC) { 1515 SET(ttybits, TIOCM_CD); 1516 } else { 1517 if (ISSET(combits, MSR_DCD)) 1518 SET(ttybits, TIOCM_CD); 1519 } 1520 if (ISSET(combits, MSR_CTS)) 1521 SET(ttybits, TIOCM_CTS); 1522 if (ISSET(combits, MSR_DSR)) 1523 SET(ttybits, TIOCM_DSR); 1524 if (ISSET(combits, MSR_RI | MSR_TERI)) 1525 SET(ttybits, TIOCM_RI); 1526 1527 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1528 SET(ttybits, TIOCM_LE); 1529 1530 return (ttybits); 1531 } 1532 1533 static u_char 1534 cflag2lcr(tcflag_t cflag) 1535 { 1536 u_char lcr = 0; 1537 1538 switch (ISSET(cflag, CSIZE)) { 1539 case CS5: 1540 SET(lcr, LCR_5BITS); 1541 break; 1542 case CS6: 1543 SET(lcr, LCR_6BITS); 1544 break; 1545 case CS7: 1546 SET(lcr, LCR_7BITS); 1547 break; 1548 case CS8: 1549 SET(lcr, LCR_8BITS); 1550 break; 1551 } 1552 if (ISSET(cflag, PARENB)) { 1553 SET(lcr, LCR_PENAB); 1554 if (!ISSET(cflag, PARODD)) 1555 SET(lcr, LCR_PEVEN); 1556 } 1557 if (ISSET(cflag, CSTOPB)) 1558 SET(lcr, LCR_STOPB); 1559 1560 return (lcr); 1561 } 1562 1563 int 1564 comparam(struct tty *tp, struct termios *t) 1565 { 1566 struct com_softc *sc = 1567 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1568 int ospeed; 1569 u_char lcr; 1570 1571 if (COM_ISALIVE(sc) == 0) 1572 return (EIO); 1573 1574 if (sc->sc_type == COM_TYPE_HAYESP) { 1575 int prescaler, speed; 1576 1577 /* 1578 * Calculate UART clock prescaler. It should be in 1579 * range of 0 .. 3. 1580 */ 1581 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1582 prescaler++, speed /= 2) 1583 if ((ospeed = comspeed(speed, sc->sc_frequency, 1584 sc->sc_type)) > 0) 1585 break; 1586 1587 if (prescaler == 4) 1588 return (EINVAL); 1589 sc->sc_prescaler = prescaler; 1590 } else 1591 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1592 1593 /* Check requested parameters. */ 1594 if (ospeed < 0) 1595 return (EINVAL); 1596 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1597 return (EINVAL); 1598 1599 /* 1600 * For the console, always force CLOCAL and !HUPCL, so that the port 1601 * is always active. 1602 */ 1603 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1604 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1605 SET(t->c_cflag, CLOCAL); 1606 CLR(t->c_cflag, HUPCL); 1607 } 1608 1609 /* 1610 * If there were no changes, don't do anything. This avoids dropping 1611 * input and improves performance when all we did was frob things like 1612 * VMIN and VTIME. 1613 */ 1614 if (tp->t_ospeed == t->c_ospeed && 1615 tp->t_cflag == t->c_cflag) 1616 return (0); 1617 1618 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1619 1620 mutex_spin_enter(&sc->sc_lock); 1621 1622 sc->sc_lcr = lcr; 1623 1624 /* 1625 * If we're not in a mode that assumes a connection is present, then 1626 * ignore carrier changes. 1627 */ 1628 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1629 sc->sc_msr_dcd = 0; 1630 else 1631 sc->sc_msr_dcd = MSR_DCD; 1632 /* 1633 * Set the flow control pins depending on the current flow control 1634 * mode. 1635 */ 1636 if (ISSET(t->c_cflag, CRTSCTS)) { 1637 sc->sc_mcr_dtr = MCR_DTR; 1638 sc->sc_mcr_rts = MCR_RTS; 1639 sc->sc_msr_cts = MSR_CTS; 1640 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1641 SET(sc->sc_mcr, MCR_AFE); 1642 } else { 1643 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1644 } 1645 } else if (ISSET(t->c_cflag, MDMBUF)) { 1646 /* 1647 * For DTR/DCD flow control, make sure we don't toggle DTR for 1648 * carrier detection. 1649 */ 1650 sc->sc_mcr_dtr = 0; 1651 sc->sc_mcr_rts = MCR_DTR; 1652 sc->sc_msr_cts = MSR_DCD; 1653 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1654 CLR(sc->sc_mcr, MCR_AFE); 1655 } else { 1656 sc->sc_efr = 0; 1657 } 1658 } else { 1659 /* 1660 * If no flow control, then always set RTS. This will make 1661 * the other side happy if it mistakenly thinks we're doing 1662 * RTS/CTS flow control. 1663 */ 1664 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1665 sc->sc_mcr_rts = 0; 1666 sc->sc_msr_cts = 0; 1667 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1668 CLR(sc->sc_mcr, MCR_AFE); 1669 } else { 1670 sc->sc_efr = 0; 1671 } 1672 if (ISSET(sc->sc_mcr, MCR_DTR)) 1673 SET(sc->sc_mcr, MCR_RTS); 1674 else 1675 CLR(sc->sc_mcr, MCR_RTS); 1676 } 1677 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1678 1679 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1680 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1681 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1682 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1683 1684 sc->sc_dlbl = ospeed; 1685 sc->sc_dlbh = ospeed >> 8; 1686 1687 /* 1688 * Set the FIFO threshold based on the receive speed. 1689 * 1690 * * If it's a low speed, it's probably a mouse or some other 1691 * interactive device, so set the threshold low. 1692 * * If it's a high speed, trim the trigger level down to prevent 1693 * overflows. 1694 * * Otherwise set it a bit higher. 1695 */ 1696 if (sc->sc_type == COM_TYPE_HAYESP) { 1697 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1698 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1699 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1700 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1701 if (t->c_ospeed <= 1200) 1702 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1703 else if (t->c_ospeed <= 38400) 1704 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1705 else 1706 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1707 } else { 1708 sc->sc_fifo = 0; 1709 } 1710 1711 if (sc->sc_type == COM_TYPE_INGENIC) 1712 sc->sc_fifo |= FIFO_UART_ON; 1713 1714 /* And copy to tty. */ 1715 tp->t_ispeed = t->c_ospeed; 1716 tp->t_ospeed = t->c_ospeed; 1717 tp->t_cflag = t->c_cflag; 1718 1719 if (!sc->sc_heldchange) { 1720 if (sc->sc_tx_busy) { 1721 sc->sc_heldtbc = sc->sc_tbc; 1722 sc->sc_tbc = 0; 1723 sc->sc_heldchange = 1; 1724 } else 1725 com_loadchannelregs(sc); 1726 } 1727 1728 if (!ISSET(t->c_cflag, CHWFLOW)) { 1729 /* Disable the high water mark. */ 1730 sc->sc_r_hiwat = 0; 1731 sc->sc_r_lowat = 0; 1732 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1733 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1734 com_schedrx(sc); 1735 } 1736 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1737 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1738 com_hwiflow(sc); 1739 } 1740 } else { 1741 sc->sc_r_hiwat = com_rbuf_hiwat; 1742 sc->sc_r_lowat = com_rbuf_lowat; 1743 } 1744 1745 mutex_spin_exit(&sc->sc_lock); 1746 1747 /* 1748 * Update the tty layer's idea of the carrier bit, in case we changed 1749 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1750 * explicit request. 1751 */ 1752 if (sc->sc_type == COM_TYPE_INGENIC) { 1753 /* no DCD here */ 1754 (void) (*tp->t_linesw->l_modem)(tp, 1); 1755 } else 1756 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1757 1758 #ifdef COM_DEBUG 1759 if (com_debug) 1760 comstatus(sc, "comparam "); 1761 #endif 1762 1763 if (!ISSET(t->c_cflag, CHWFLOW)) { 1764 if (sc->sc_tx_stopped) { 1765 sc->sc_tx_stopped = 0; 1766 comstart(tp); 1767 } 1768 } 1769 1770 return (0); 1771 } 1772 1773 void 1774 com_iflush(struct com_softc *sc) 1775 { 1776 struct com_regs *regsp = &sc->sc_regs; 1777 uint8_t fifo; 1778 #ifdef DIAGNOSTIC 1779 int reg; 1780 #endif 1781 int timo; 1782 1783 #ifdef DIAGNOSTIC 1784 reg = 0xffff; 1785 #endif 1786 timo = 50000; 1787 /* flush any pending I/O */ 1788 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1789 && --timo) 1790 #ifdef DIAGNOSTIC 1791 reg = 1792 #else 1793 (void) 1794 #endif 1795 CSR_READ_1(regsp, COM_REG_RXDATA); 1796 #ifdef DIAGNOSTIC 1797 if (!timo) 1798 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1799 #endif 1800 1801 switch (sc->sc_type) { 1802 case COM_TYPE_16750: 1803 case COM_TYPE_DW_APB: 1804 /* 1805 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1806 * This should prevent triggering busy interrupt while 1807 * manipulating divisors. 1808 */ 1809 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1810 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1811 CSR_WRITE_1(regsp, COM_REG_FIFO, 1812 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1813 delay(100); 1814 break; 1815 } 1816 } 1817 1818 void 1819 com_loadchannelregs(struct com_softc *sc) 1820 { 1821 struct com_regs *regsp = &sc->sc_regs; 1822 1823 /* XXXXX necessary? */ 1824 com_iflush(sc); 1825 1826 if (sc->sc_type == COM_TYPE_PXA2x0) 1827 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1828 else 1829 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1830 1831 if (sc->sc_type == COM_TYPE_OMAP) { 1832 /* disable before changing settings */ 1833 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1834 } 1835 1836 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1837 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1838 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1839 /* no EFR on alchemy */ 1840 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1841 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1842 } 1843 if (sc->sc_type == COM_TYPE_AU1x00) { 1844 /* alchemy has single separate 16-bit clock divisor register */ 1845 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1846 (sc->sc_dlbh << 8)); 1847 } else { 1848 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1849 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1850 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1851 } 1852 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1853 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1854 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1855 if (sc->sc_type == COM_TYPE_HAYESP) { 1856 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1857 HAYESP_SETPRESCALER); 1858 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1859 sc->sc_prescaler); 1860 } 1861 if (sc->sc_type == COM_TYPE_OMAP) { 1862 /* setup the fifos. the FCR value is not used as long 1863 as SCR[6] and SCR[7] are 0, which they are at reset 1864 and we never touch the SCR register */ 1865 uint8_t rx_fifo_trig = 40; 1866 uint8_t tx_fifo_trig = 60; 1867 uint8_t rx_start = 8; 1868 uint8_t rx_halt = 60; 1869 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1870 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1871 1872 /* enable access to TCR & TLR */ 1873 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1874 1875 /* write tcr and tlr values */ 1876 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1877 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1878 1879 /* disable access to TCR & TLR */ 1880 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1881 1882 /* enable again, but mode is based on speed */ 1883 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1884 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1885 } else { 1886 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1887 } 1888 } 1889 1890 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1891 } 1892 1893 int 1894 comhwiflow(struct tty *tp, int block) 1895 { 1896 struct com_softc *sc = 1897 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1898 1899 if (COM_ISALIVE(sc) == 0) 1900 return (0); 1901 1902 if (sc->sc_mcr_rts == 0) 1903 return (0); 1904 1905 mutex_spin_enter(&sc->sc_lock); 1906 1907 if (block) { 1908 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1909 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1910 com_hwiflow(sc); 1911 } 1912 } else { 1913 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1914 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1915 com_schedrx(sc); 1916 } 1917 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1918 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1919 com_hwiflow(sc); 1920 } 1921 } 1922 1923 mutex_spin_exit(&sc->sc_lock); 1924 return (1); 1925 } 1926 1927 /* 1928 * (un)block input via hw flowcontrol 1929 */ 1930 void 1931 com_hwiflow(struct com_softc *sc) 1932 { 1933 struct com_regs *regsp= &sc->sc_regs; 1934 1935 if (sc->sc_mcr_rts == 0) 1936 return; 1937 1938 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1939 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1940 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1941 } else { 1942 SET(sc->sc_mcr, sc->sc_mcr_rts); 1943 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1944 } 1945 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1946 } 1947 1948 1949 void 1950 comstart(struct tty *tp) 1951 { 1952 struct com_softc *sc = 1953 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1954 struct com_regs *regsp = &sc->sc_regs; 1955 1956 if (COM_ISALIVE(sc) == 0) 1957 return; 1958 1959 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1960 return; 1961 if (sc->sc_tx_stopped) 1962 return; 1963 if (!ttypull(tp)) 1964 return; 1965 1966 /* Grab the first contiguous region of buffer space. */ 1967 { 1968 u_char *tba; 1969 int tbc; 1970 1971 tba = tp->t_outq.c_cf; 1972 tbc = ndqb(&tp->t_outq, 0); 1973 1974 mutex_spin_enter(&sc->sc_lock); 1975 1976 sc->sc_tba = tba; 1977 sc->sc_tbc = tbc; 1978 } 1979 1980 SET(tp->t_state, TS_BUSY); 1981 sc->sc_tx_busy = 1; 1982 1983 /* Enable transmit completion interrupts if necessary. */ 1984 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1985 SET(sc->sc_ier, IER_ETXRDY); 1986 CSR_WRITE_1_SYNC(regsp, COM_REG_IER, sc->sc_ier); 1987 } 1988 1989 /* Output the first chunk of the contiguous buffer. */ 1990 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1991 u_int n; 1992 1993 n = sc->sc_tbc; 1994 if (n > sc->sc_fifolen) 1995 n = sc->sc_fifolen; 1996 CSR_WRITE_MULTI_SYNC(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1997 sc->sc_tbc -= n; 1998 sc->sc_tba += n; 1999 } 2000 2001 mutex_spin_exit(&sc->sc_lock); 2002 } 2003 2004 /* 2005 * Stop output on a line. 2006 */ 2007 void 2008 comstop(struct tty *tp, int flag) 2009 { 2010 struct com_softc *sc = 2011 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 2012 2013 mutex_spin_enter(&sc->sc_lock); 2014 if (ISSET(tp->t_state, TS_BUSY)) { 2015 /* Stop transmitting at the next chunk. */ 2016 sc->sc_tbc = 0; 2017 sc->sc_heldtbc = 0; 2018 if (!ISSET(tp->t_state, TS_TTSTOP)) 2019 SET(tp->t_state, TS_FLUSH); 2020 } 2021 mutex_spin_exit(&sc->sc_lock); 2022 } 2023 2024 void 2025 comdiag(void *arg) 2026 { 2027 struct com_softc *sc = arg; 2028 int overflows, floods; 2029 2030 mutex_spin_enter(&sc->sc_lock); 2031 overflows = sc->sc_overflows; 2032 sc->sc_overflows = 0; 2033 floods = sc->sc_floods; 2034 sc->sc_floods = 0; 2035 sc->sc_errors = 0; 2036 mutex_spin_exit(&sc->sc_lock); 2037 2038 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 2039 device_xname(sc->sc_dev), 2040 overflows, overflows == 1 ? "" : "s", 2041 floods, floods == 1 ? "" : "s"); 2042 } 2043 2044 static inline void 2045 com_rxsoft(struct com_softc *sc, struct tty *tp) 2046 { 2047 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 2048 u_char *get, *end; 2049 u_int cc, scc; 2050 u_char lsr; 2051 int code; 2052 2053 end = sc->sc_ebuf; 2054 get = sc->sc_rbget; 2055 scc = cc = com_rbuf_size - sc->sc_rbavail; 2056 2057 if (cc == com_rbuf_size) { 2058 sc->sc_floods++; 2059 if (sc->sc_errors++ == 0) 2060 callout_reset(&sc->sc_diag_callout, 60 * hz, 2061 comdiag, sc); 2062 } 2063 2064 /* If not yet open, drop the entire buffer content here */ 2065 if (!ISSET(tp->t_state, TS_ISOPEN)) { 2066 get += cc << 1; 2067 if (get >= end) 2068 get -= com_rbuf_size << 1; 2069 cc = 0; 2070 } 2071 while (cc) { 2072 code = get[0]; 2073 lsr = get[1]; 2074 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 2075 if (ISSET(lsr, LSR_OE)) { 2076 sc->sc_overflows++; 2077 if (sc->sc_errors++ == 0) 2078 callout_reset(&sc->sc_diag_callout, 2079 60 * hz, comdiag, sc); 2080 } 2081 if (ISSET(lsr, LSR_BI | LSR_FE)) 2082 SET(code, TTY_FE); 2083 if (ISSET(lsr, LSR_PE)) 2084 SET(code, TTY_PE); 2085 } 2086 if ((*rint)(code, tp) == -1) { 2087 /* 2088 * The line discipline's buffer is out of space. 2089 */ 2090 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 2091 /* 2092 * We're either not using flow control, or the 2093 * line discipline didn't tell us to block for 2094 * some reason. Either way, we have no way to 2095 * know when there's more space available, so 2096 * just drop the rest of the data. 2097 */ 2098 get += cc << 1; 2099 if (get >= end) 2100 get -= com_rbuf_size << 1; 2101 cc = 0; 2102 } else { 2103 /* 2104 * Don't schedule any more receive processing 2105 * until the line discipline tells us there's 2106 * space available (through comhwiflow()). 2107 * Leave the rest of the data in the input 2108 * buffer. 2109 */ 2110 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 2111 } 2112 break; 2113 } 2114 get += 2; 2115 if (get >= end) 2116 get = sc->sc_rbuf; 2117 cc--; 2118 } 2119 2120 if (cc != scc) { 2121 sc->sc_rbget = get; 2122 mutex_spin_enter(&sc->sc_lock); 2123 2124 cc = sc->sc_rbavail += scc - cc; 2125 /* Buffers should be ok again, release possible block. */ 2126 if (cc >= sc->sc_r_lowat) { 2127 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2128 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2129 SET(sc->sc_ier, IER_ERXRDY); 2130 if (sc->sc_type == COM_TYPE_PXA2x0) 2131 SET(sc->sc_ier, IER_ERXTOUT); 2132 if (sc->sc_type == COM_TYPE_INGENIC || 2133 sc->sc_type == COM_TYPE_TEGRA) 2134 SET(sc->sc_ier, IER_ERXTOUT); 2135 2136 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 2137 sc->sc_ier); 2138 } 2139 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 2140 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2141 com_hwiflow(sc); 2142 } 2143 } 2144 mutex_spin_exit(&sc->sc_lock); 2145 } 2146 } 2147 2148 static inline void 2149 com_txsoft(struct com_softc *sc, struct tty *tp) 2150 { 2151 2152 CLR(tp->t_state, TS_BUSY); 2153 if (ISSET(tp->t_state, TS_FLUSH)) 2154 CLR(tp->t_state, TS_FLUSH); 2155 else 2156 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2157 (*tp->t_linesw->l_start)(tp); 2158 } 2159 2160 static inline void 2161 com_stsoft(struct com_softc *sc, struct tty *tp) 2162 { 2163 u_char msr, delta; 2164 2165 mutex_spin_enter(&sc->sc_lock); 2166 msr = sc->sc_msr; 2167 delta = sc->sc_msr_delta; 2168 sc->sc_msr_delta = 0; 2169 mutex_spin_exit(&sc->sc_lock); 2170 2171 if (ISSET(delta, sc->sc_msr_dcd)) { 2172 /* 2173 * Inform the tty layer that carrier detect changed. 2174 */ 2175 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2176 } 2177 2178 if (ISSET(delta, sc->sc_msr_cts)) { 2179 /* Block or unblock output according to flow control. */ 2180 if (ISSET(msr, sc->sc_msr_cts)) { 2181 sc->sc_tx_stopped = 0; 2182 (*tp->t_linesw->l_start)(tp); 2183 } else { 2184 sc->sc_tx_stopped = 1; 2185 } 2186 } 2187 2188 #ifdef COM_DEBUG 2189 if (com_debug) 2190 comstatus(sc, "com_stsoft"); 2191 #endif 2192 } 2193 2194 void 2195 comsoft(void *arg) 2196 { 2197 struct com_softc *sc = arg; 2198 struct tty *tp; 2199 2200 if (COM_ISALIVE(sc) == 0) 2201 return; 2202 2203 tp = sc->sc_tty; 2204 2205 if (sc->sc_rx_ready) { 2206 sc->sc_rx_ready = 0; 2207 com_rxsoft(sc, tp); 2208 } 2209 2210 if (sc->sc_st_check) { 2211 sc->sc_st_check = 0; 2212 com_stsoft(sc, tp); 2213 } 2214 2215 if (sc->sc_tx_done) { 2216 sc->sc_tx_done = 0; 2217 com_txsoft(sc, tp); 2218 } 2219 } 2220 2221 int 2222 comintr(void *arg) 2223 { 2224 struct com_softc *sc = arg; 2225 struct com_regs *regsp = &sc->sc_regs; 2226 2227 u_char *put, *end; 2228 u_int cc; 2229 u_char lsr, iir; 2230 2231 if (COM_ISALIVE(sc) == 0) 2232 return (0); 2233 2234 KASSERT(regsp != NULL); 2235 2236 mutex_spin_enter(&sc->sc_lock); 2237 iir = CSR_READ_1(regsp, COM_REG_IIR); 2238 2239 /* Handle ns16750-specific busy interrupt. */ 2240 if (sc->sc_type == COM_TYPE_16750 && 2241 (iir & IIR_BUSY) == IIR_BUSY) { 2242 for (int timeout = 10000; 2243 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2244 if (timeout <= 0) { 2245 aprint_error_dev(sc->sc_dev, 2246 "timeout while waiting for BUSY interrupt " 2247 "acknowledge\n"); 2248 mutex_spin_exit(&sc->sc_lock); 2249 return (0); 2250 } 2251 2252 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2253 iir = CSR_READ_1(regsp, COM_REG_IIR); 2254 } 2255 2256 /* DesignWare APB UART BUSY interrupt */ 2257 if (sc->sc_type == COM_TYPE_DW_APB && 2258 (iir & IIR_BUSY) == IIR_BUSY) { 2259 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 2260 (void)CSR_READ_1(regsp, COM_REG_USR); 2261 } else if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2262 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2263 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2264 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2265 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2266 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2267 CSR_WRITE_1(regsp, COM_REG_HALT, 2268 HALT_CHCFG_EN | HALT_CHCFG_UD); 2269 for (int timeout = 10000000; 2270 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2271 timeout--) { 2272 if (timeout <= 0) { 2273 aprint_error_dev(sc->sc_dev, 2274 "timeout while waiting for HALT " 2275 "update acknowledge 0x%x 0x%x\n", 2276 CSR_READ_1(regsp, COM_REG_HALT), 2277 CSR_READ_1(regsp, COM_REG_USR)); 2278 break; 2279 } 2280 } 2281 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2282 (void)CSR_READ_1(regsp, COM_REG_USR); 2283 } else { 2284 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2285 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2286 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2287 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2288 } 2289 } 2290 2291 end = sc->sc_ebuf; 2292 put = sc->sc_rbput; 2293 cc = sc->sc_rbavail; 2294 2295 if (ISSET(iir, IIR_NOPEND)) { 2296 if (ISSET(sc->sc_hwflags, COM_HW_BROKEN_ETXRDY)) 2297 goto do_tx; 2298 mutex_spin_exit(&sc->sc_lock); 2299 return (0); 2300 } 2301 2302 again: do { 2303 u_char msr, delta; 2304 2305 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2306 if (ISSET(lsr, LSR_BI)) { 2307 int cn_trapped = 0; /* see above: cn_trap() */ 2308 2309 cn_check_magic(sc->sc_tty->t_dev, 2310 CNC_BREAK, com_cnm_state); 2311 if (cn_trapped) 2312 continue; 2313 #if defined(KGDB) && !defined(DDB) 2314 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2315 kgdb_connect(1); 2316 continue; 2317 } 2318 #endif 2319 } 2320 2321 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2322 lsr |= LSR_RXRDY; 2323 2324 if (ISSET(lsr, LSR_RCV_MASK) && 2325 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2326 while (cc > 0) { 2327 int cn_trapped = 0; 2328 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2329 put[1] = lsr; 2330 cn_check_magic(sc->sc_tty->t_dev, 2331 put[0], com_cnm_state); 2332 if (cn_trapped) 2333 goto next; 2334 put += 2; 2335 if (put >= end) 2336 put = sc->sc_rbuf; 2337 cc--; 2338 next: 2339 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2340 if (!ISSET(lsr, LSR_RCV_MASK)) 2341 break; 2342 } 2343 2344 /* 2345 * Current string of incoming characters ended because 2346 * no more data was available or we ran out of space. 2347 * Schedule a receive event if any data was received. 2348 * If we're out of space, turn off receive interrupts. 2349 */ 2350 sc->sc_rbput = put; 2351 sc->sc_rbavail = cc; 2352 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2353 sc->sc_rx_ready = 1; 2354 2355 /* 2356 * See if we are in danger of overflowing a buffer. If 2357 * so, use hardware flow control to ease the pressure. 2358 */ 2359 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2360 cc < sc->sc_r_hiwat) { 2361 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2362 com_hwiflow(sc); 2363 } 2364 2365 /* 2366 * If we're out of space, disable receive interrupts 2367 * until the queue has drained a bit. 2368 */ 2369 if (!cc) { 2370 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2371 switch (sc->sc_type) { 2372 case COM_TYPE_PXA2x0: 2373 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2374 break; 2375 case COM_TYPE_INGENIC: 2376 case COM_TYPE_TEGRA: 2377 CLR(sc->sc_ier, 2378 IER_ERXRDY | IER_ERXTOUT); 2379 break; 2380 default: 2381 CLR(sc->sc_ier, IER_ERXRDY); 2382 break; 2383 } 2384 CSR_WRITE_1_SYNC(regsp, COM_REG_IER, sc->sc_ier); 2385 } 2386 } else { 2387 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2388 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2389 continue; 2390 } 2391 } 2392 2393 msr = CSR_READ_1(regsp, COM_REG_MSR); 2394 delta = msr ^ sc->sc_msr; 2395 sc->sc_msr = msr; 2396 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2397 (delta & MSR_DCD)) { 2398 mutex_spin_enter(&timecounter_lock); 2399 pps_capture(&sc->sc_pps_state); 2400 pps_event(&sc->sc_pps_state, 2401 (msr & MSR_DCD) ? 2402 PPS_CAPTUREASSERT : 2403 PPS_CAPTURECLEAR); 2404 mutex_spin_exit(&timecounter_lock); 2405 } 2406 2407 /* 2408 * Process normal status changes 2409 */ 2410 if (ISSET(delta, sc->sc_msr_mask)) { 2411 SET(sc->sc_msr_delta, delta); 2412 2413 /* 2414 * Stop output immediately if we lose the output 2415 * flow control signal or carrier detect. 2416 */ 2417 if (ISSET(~msr, sc->sc_msr_mask)) { 2418 sc->sc_tbc = 0; 2419 sc->sc_heldtbc = 0; 2420 #ifdef COM_DEBUG 2421 if (com_debug) 2422 comstatus(sc, "comintr "); 2423 #endif 2424 } 2425 2426 sc->sc_st_check = 1; 2427 } 2428 } while (!ISSET((iir = 2429 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2430 /* 2431 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2432 * by IIR read, so we can't do this way: `process all interrupts, 2433 * then do TX if possible'. 2434 */ 2435 (iir & IIR_IMASK) != IIR_TXRDY); 2436 2437 do_tx: 2438 /* 2439 * Read LSR again, since there may be an interrupt between 2440 * the last LSR read and IIR read above. 2441 */ 2442 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2443 2444 /* 2445 * See if data can be transmitted as well. 2446 * Schedule tx done event if no data left 2447 * and tty was marked busy. 2448 */ 2449 if (ISSET(lsr, LSR_TXRDY)) { 2450 /* 2451 * If we've delayed a parameter change, do it now, and restart 2452 * output. 2453 */ 2454 if (sc->sc_heldchange) { 2455 com_loadchannelregs(sc); 2456 sc->sc_heldchange = 0; 2457 sc->sc_tbc = sc->sc_heldtbc; 2458 sc->sc_heldtbc = 0; 2459 } 2460 2461 /* Output the next chunk of the contiguous buffer, if any. */ 2462 if (sc->sc_tbc > 0) { 2463 u_int n; 2464 2465 n = sc->sc_tbc; 2466 if (n > sc->sc_fifolen) 2467 n = sc->sc_fifolen; 2468 CSR_WRITE_MULTI_SYNC(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2469 sc->sc_tbc -= n; 2470 sc->sc_tba += n; 2471 } else { 2472 /* Disable transmit completion interrupts if necessary. */ 2473 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2474 CLR(sc->sc_ier, IER_ETXRDY); 2475 CSR_WRITE_1_SYNC(regsp, COM_REG_IER, sc->sc_ier); 2476 } 2477 if (sc->sc_tx_busy) { 2478 sc->sc_tx_busy = 0; 2479 sc->sc_tx_done = 1; 2480 } 2481 } 2482 } 2483 2484 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2485 goto again; 2486 2487 mutex_spin_exit(&sc->sc_lock); 2488 2489 /* Wake up the poller. */ 2490 if ((sc->sc_rx_ready | sc->sc_st_check | sc->sc_tx_done) != 0) 2491 softint_schedule(sc->sc_si); 2492 2493 #ifdef RND_COM 2494 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2495 #endif 2496 2497 return (1); 2498 } 2499 2500 /* 2501 * The following functions are polled getc and putc routines, shared 2502 * by the console and kgdb glue. 2503 * 2504 * The read-ahead code is so that you can detect pending in-band 2505 * cn_magic in polled mode while doing output rather than having to 2506 * wait until the kernel decides it needs input. 2507 */ 2508 2509 #define MAX_READAHEAD 20 2510 static int com_readahead[MAX_READAHEAD]; 2511 static int com_readaheadcount = 0; 2512 2513 int 2514 com_common_getc(dev_t dev, struct com_regs *regsp) 2515 { 2516 int s = splserial(); 2517 u_char stat, c; 2518 2519 /* got a character from reading things earlier */ 2520 if (com_readaheadcount > 0) { 2521 int i; 2522 2523 c = com_readahead[0]; 2524 for (i = 1; i < com_readaheadcount; i++) { 2525 com_readahead[i-1] = com_readahead[i]; 2526 } 2527 com_readaheadcount--; 2528 splx(s); 2529 return (c); 2530 } 2531 2532 /* don't block until a character becomes available */ 2533 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2534 splx(s); 2535 return -1; 2536 } 2537 2538 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2539 stat = CSR_READ_1(regsp, COM_REG_IIR); 2540 { 2541 int cn_trapped = 0; /* required by cn_trap, see above */ 2542 if (!db_active) 2543 cn_check_magic(dev, c, com_cnm_state); 2544 } 2545 splx(s); 2546 return (c); 2547 } 2548 2549 static void 2550 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead) 2551 { 2552 int s = splserial(); 2553 int cin, stat, timo; 2554 2555 if (with_readahead && com_readaheadcount < MAX_READAHEAD 2556 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2557 int cn_trapped = 0; 2558 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2559 stat = CSR_READ_1(regsp, COM_REG_IIR); 2560 cn_check_magic(dev, cin, com_cnm_state); 2561 com_readahead[com_readaheadcount++] = cin; 2562 } 2563 2564 /* wait for any pending transmission to finish */ 2565 timo = 150000; 2566 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2567 continue; 2568 2569 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2570 COM_BARRIER(regsp, BR | BW); 2571 2572 splx(s); 2573 } 2574 2575 /* 2576 * Initialize UART for use as console or KGDB line. 2577 */ 2578 int 2579 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2580 tcflag_t cflag) 2581 { 2582 2583 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2584 ®sp->cr_ioh)) 2585 return (ENOMEM); /* ??? */ 2586 2587 if (type == COM_TYPE_OMAP) { 2588 /* disable before changing settings */ 2589 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2590 } 2591 2592 rate = comspeed(rate, frequency, type); 2593 if (rate != -1) { 2594 if (type == COM_TYPE_AU1x00) { 2595 /* no EFR on alchemy */ 2596 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2597 } else { 2598 if ((type != COM_TYPE_16550_NOERS) && 2599 (type != COM_TYPE_INGENIC)) { 2600 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2601 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2602 } 2603 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2604 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2605 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2606 } 2607 } 2608 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2609 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2610 2611 if (type == COM_TYPE_INGENIC) { 2612 CSR_WRITE_1(regsp, COM_REG_FIFO, 2613 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2614 FIFO_TRIGGER_1 | FIFO_UART_ON); 2615 } else { 2616 CSR_WRITE_1(regsp, COM_REG_FIFO, 2617 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2618 FIFO_TRIGGER_1); 2619 } 2620 2621 if (type == COM_TYPE_OMAP) { 2622 /* setup the fifos. the FCR value is not used as long 2623 as SCR[6] and SCR[7] are 0, which they are at reset 2624 and we never touch the SCR register */ 2625 uint8_t rx_fifo_trig = 40; 2626 uint8_t tx_fifo_trig = 60; 2627 uint8_t rx_start = 8; 2628 uint8_t rx_halt = 60; 2629 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2630 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2631 2632 /* enable access to TCR & TLR */ 2633 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2634 2635 /* write tcr and tlr values */ 2636 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2637 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2638 2639 /* disable access to TCR & TLR */ 2640 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2641 2642 /* enable again, but mode is based on speed */ 2643 if (rate > 230400) { 2644 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2645 } else { 2646 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2647 } 2648 } 2649 2650 if (type == COM_TYPE_PXA2x0) 2651 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2652 else 2653 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2654 2655 return (0); 2656 } 2657 2658 int 2659 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2660 tcflag_t cflag) 2661 { 2662 int res; 2663 2664 comcons_info.regs = *regsp; 2665 2666 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2667 if (res) 2668 return (res); 2669 2670 cn_tab = &comcons; 2671 cn_init_magic(&com_cnm_state); 2672 cn_set_magic("\047\001"); /* default magic is BREAK */ 2673 2674 comcons_info.frequency = frequency; 2675 comcons_info.type = type; 2676 comcons_info.rate = rate; 2677 comcons_info.cflag = cflag; 2678 2679 return (0); 2680 } 2681 2682 int 2683 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2684 int type, tcflag_t cflag) 2685 { 2686 struct com_regs regs; 2687 2688 /*XXX*/ 2689 bus_space_handle_t dummy_bsh; 2690 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2691 2692 /* 2693 * dummy_bsh required because com_init_regs() wants it. A 2694 * real bus_space_handle will be filled in by cominit() later. 2695 * XXXJRT Detangle this mess eventually, plz. 2696 */ 2697 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2698 2699 return comcnattach1(®s, rate, frequency, type, cflag); 2700 } 2701 2702 static int 2703 comcnreattach(void) 2704 { 2705 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2706 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2707 } 2708 2709 int 2710 comcngetc(dev_t dev) 2711 { 2712 2713 return (com_common_getc(dev, &comcons_info.regs)); 2714 } 2715 2716 /* 2717 * Console kernel output character routine. 2718 */ 2719 void 2720 comcnputc(dev_t dev, int c) 2721 { 2722 2723 com_common_putc(dev, &comcons_info.regs, c, cold); 2724 } 2725 2726 void 2727 comcnpollc(dev_t dev, int on) 2728 { 2729 2730 com_readaheadcount = 0; 2731 } 2732 2733 #ifdef KGDB 2734 int 2735 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2736 tcflag_t cflag) 2737 { 2738 int res; 2739 2740 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2741 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2742 #if !defined(DDB) 2743 return (EBUSY); /* cannot share with console */ 2744 #else 2745 comkgdbregs = *regsp; 2746 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2747 #endif 2748 } else { 2749 comkgdbregs = *regsp; 2750 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2751 if (res) 2752 return (res); 2753 2754 /* 2755 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2756 * expects this to be initialized 2757 */ 2758 cn_init_magic(&com_cnm_state); 2759 cn_set_magic("\047\001"); 2760 } 2761 2762 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2763 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2764 2765 return (0); 2766 } 2767 2768 int 2769 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2770 int frequency, int type, tcflag_t cflag) 2771 { 2772 struct com_regs regs; 2773 2774 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2775 2776 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2777 } 2778 2779 /* ARGSUSED */ 2780 int 2781 com_kgdb_getc(void *arg) 2782 { 2783 2784 return (com_common_getc(NODEV, &comkgdbregs)); 2785 } 2786 2787 /* ARGSUSED */ 2788 void 2789 com_kgdb_putc(void *arg, int c) 2790 { 2791 2792 com_common_putc(NODEV, &comkgdbregs, c, 0); 2793 } 2794 #endif /* KGDB */ 2795 2796 /* 2797 * helper function to identify the com ports used by 2798 * console or KGDB (and not yet autoconf attached) 2799 */ 2800 int 2801 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2802 { 2803 bus_space_handle_t help; 2804 2805 if (!comconsattached && 2806 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2807 iobase == comcons_info.regs.cr_iobase) 2808 help = comcons_info.regs.cr_ioh; 2809 #ifdef KGDB 2810 else if (!com_kgdb_attached && 2811 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2812 iobase == comkgdbregs.cr_iobase) 2813 help = comkgdbregs.cr_ioh; 2814 #endif 2815 else 2816 return (0); 2817 2818 if (ioh) 2819 *ioh = help; 2820 return (1); 2821 } 2822 2823 /* 2824 * this routine exists to serve as a shutdown hook for systems that 2825 * have firmware which doesn't interact properly with a com device in 2826 * FIFO mode. 2827 */ 2828 bool 2829 com_cleanup(device_t self, int how) 2830 { 2831 struct com_softc *sc = device_private(self); 2832 2833 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2834 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2835 2836 return true; 2837 } 2838 2839 bool 2840 com_suspend(device_t self, const pmf_qual_t *qual) 2841 { 2842 struct com_softc *sc = device_private(self); 2843 2844 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2845 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2846 2847 return true; 2848 } 2849 2850 bool 2851 com_resume(device_t self, const pmf_qual_t *qual) 2852 { 2853 struct com_softc *sc = device_private(self); 2854 2855 mutex_spin_enter(&sc->sc_lock); 2856 com_loadchannelregs(sc); 2857 mutex_spin_exit(&sc->sc_lock); 2858 2859 return true; 2860 } 2861
Indexes created Wed Oct 22 06:10:02 GMT 2025