com.c revision 1.387
1 /* $NetBSD: com.c,v 1.387 2025/02/09 10:27:29 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Copyright (c) 1991 The Regents of the University of California. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. Neither the name of the University nor the names of its contributors 45 * may be used to endorse or promote products derived from this software 46 * without specific prior written permission. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 58 * SUCH DAMAGE. 59 * 60 * @(#)com.c 7.5 (Berkeley) 5/16/91 61 */ 62 63 /* 64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART 65 * Supports automatic hardware flow control on StarTech ST16C650A UART 66 * 67 * Lock order: 68 * ttylock (IPL_VM) 69 * -> sc->sc_lock (IPL_HIGH) 70 * -> timecounter_lock (IPL_HIGH) 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.387 2025/02/09 10:27:29 skrll Exp $"); 75 76 #include "opt_com.h" 77 #include "opt_ddb.h" 78 #include "opt_kgdb.h" 79 #include "opt_lockdebug.h" 80 #include "opt_multiprocessor.h" 81 #include "opt_ntp.h" 82 83 /* The COM16650 option was renamed to COM_16650. */ 84 #ifdef COM16650 85 #error Obsolete COM16650 option; use COM_16650 instead. 86 #endif 87 88 /* 89 * Override cnmagic(9) macro before including <sys/systm.h>. 90 * We need to know if cn_check_magic triggered debugger, so set a flag. 91 * Callers of cn_check_magic must declare int cn_trapped = 0; 92 * XXX: this is *ugly*! 93 */ 94 #define cn_trap() \ 95 do { \ 96 console_debugger(); \ 97 cn_trapped = 1; \ 98 (void)cn_trapped; \ 99 } while (/* CONSTCOND */ 0) 100 101 #include <sys/param.h> 102 #include <sys/systm.h> 103 #include <sys/ioctl.h> 104 #include <sys/select.h> 105 #include <sys/poll.h> 106 #include <sys/tty.h> 107 #include <sys/proc.h> 108 #include <sys/conf.h> 109 #include <sys/file.h> 110 #include <sys/uio.h> 111 #include <sys/kernel.h> 112 #include <sys/syslog.h> 113 #include <sys/device.h> 114 #include <sys/malloc.h> 115 #include <sys/timepps.h> 116 #include <sys/vnode.h> 117 #include <sys/kauth.h> 118 #include <sys/intr.h> 119 #ifdef RND_COM 120 #include <sys/rndsource.h> 121 #endif 122 123 #include <sys/bus.h> 124 125 #include <ddb/db_active.h> 126 127 #include <dev/ic/comreg.h> 128 #include <dev/ic/comvar.h> 129 #include <dev/ic/ns16550reg.h> 130 #include <dev/ic/st16650reg.h> 131 #include <dev/ic/hayespreg.h> 132 #define com_lcr com_cfcr 133 #include <dev/cons.h> 134 135 #include "ioconf.h" 136 137 #define CSR_READ_1(r, o) \ 138 (r)->cr_read((r), (r)->cr_map[o]) 139 #define CSR_WRITE_1(r, o, v) \ 140 (r)->cr_write((r), (r)->cr_map[o], (v)) 141 #define CSR_WRITE_MULTI(r, o, p, n) \ 142 (r)->cr_write_multi((r), (r)->cr_map[o], (p), (n)) 143 144 /* 145 * XXX COM_TYPE_AU1x00 specific 146 */ 147 #define CSR_WRITE_2(r, o, v) \ 148 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v) 149 #define CSR_READ_2(r, o) \ 150 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o]) 151 152 static void com_enable_debugport(struct com_softc *); 153 154 void com_config(struct com_softc *); 155 void com_shutdown(struct com_softc *); 156 int comspeed(long, long, int); 157 static u_char cflag2lcr(tcflag_t); 158 int comparam(struct tty *, struct termios *); 159 void comstart(struct tty *); 160 int comhwiflow(struct tty *, int); 161 162 void com_loadchannelregs(struct com_softc *); 163 void com_hwiflow(struct com_softc *); 164 void com_break(struct com_softc *, int); 165 void com_modem(struct com_softc *, int); 166 void tiocm_to_com(struct com_softc *, u_long, int); 167 int com_to_tiocm(struct com_softc *); 168 void com_iflush(struct com_softc *); 169 170 int com_common_getc(dev_t, struct com_regs *); 171 static void com_common_putc(dev_t, struct com_regs *, int, int); 172 173 int cominit(struct com_regs *, int, int, int, tcflag_t); 174 175 static int comcnreattach(void); 176 177 int comcngetc(dev_t); 178 void comcnputc(dev_t, int); 179 void comcnpollc(dev_t, int); 180 181 void comsoft(void *); 182 static inline void com_rxsoft(struct com_softc *, struct tty *); 183 static inline void com_txsoft(struct com_softc *, struct tty *); 184 static inline void com_stsoft(struct com_softc *, struct tty *); 185 static inline void com_schedrx(struct com_softc *); 186 void comdiag(void *); 187 188 dev_type_open(comopen); 189 dev_type_close(comclose); 190 dev_type_read(comread); 191 dev_type_write(comwrite); 192 dev_type_ioctl(comioctl); 193 dev_type_stop(comstop); 194 dev_type_tty(comtty); 195 dev_type_poll(compoll); 196 197 static struct comcons_info comcons_info; 198 199 /* 200 * Following are all routines needed for COM to act as console 201 */ 202 static struct consdev comcons = { 203 .cn_getc = comcngetc, 204 .cn_putc = comcnputc, 205 .cn_pollc = comcnpollc, 206 .cn_dev = NODEV, 207 .cn_pri = CN_NORMAL 208 }; 209 210 211 const struct cdevsw com_cdevsw = { 212 .d_open = comopen, 213 .d_close = comclose, 214 .d_read = comread, 215 .d_write = comwrite, 216 .d_ioctl = comioctl, 217 .d_stop = comstop, 218 .d_tty = comtty, 219 .d_poll = compoll, 220 .d_mmap = nommap, 221 .d_kqfilter = ttykqfilter, 222 .d_discard = nodiscard, 223 .d_flag = D_TTY 224 }; 225 226 /* 227 * Make this an option variable one can patch. 228 * But be warned: this must be a power of 2! 229 */ 230 u_int com_rbuf_size = COM_RING_SIZE; 231 232 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 233 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4; 234 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4; 235 236 static int comconsattached; 237 static struct cnm_state com_cnm_state; 238 239 #ifdef KGDB 240 #include <sys/kgdb.h> 241 242 static struct com_regs comkgdbregs; 243 static int com_kgdb_attached; 244 245 int com_kgdb_getc(void *); 246 void com_kgdb_putc(void *, int); 247 #endif /* KGDB */ 248 249 /* initializer for typical 16550-ish hardware */ 250 static const bus_size_t com_std_map[COM_REGMAP_NENTRIES] = { 251 [COM_REG_RXDATA] = com_data, 252 [COM_REG_TXDATA] = com_data, 253 [COM_REG_DLBL] = com_dlbl, 254 [COM_REG_DLBH] = com_dlbh, 255 [COM_REG_IER] = com_ier, 256 [COM_REG_IIR] = com_iir, 257 [COM_REG_FIFO] = com_fifo, 258 [COM_REG_TCR] = com_fifo, 259 [COM_REG_EFR] = com_efr, 260 [COM_REG_TLR] = com_efr, 261 [COM_REG_LCR] = com_lcr, 262 [COM_REG_MCR] = com_mcr, 263 [COM_REG_LSR] = com_lsr, 264 [COM_REG_MSR] = com_msr, 265 [COM_REG_USR] = com_usr, 266 [COM_REG_TFL] = com_tfl, 267 [COM_REG_RFL] = com_rfl, 268 [COM_REG_HALT] = com_halt, 269 [COM_REG_MDR1] = com_mdr1, 270 }; 271 272 #define COMDIALOUT_MASK TTDIALOUT_MASK 273 274 #define COMUNIT(x) TTUNIT(x) 275 #define COMDIALOUT(x) TTDIALOUT(x) 276 277 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \ 278 device_is_active((sc)->sc_dev)) 279 280 #define BR BUS_SPACE_BARRIER_READ 281 #define BW BUS_SPACE_BARRIER_WRITE 282 #define COM_BARRIER(r, f) \ 283 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f)) 284 285 /* 286 * com_read_1 -- 287 * Default register read callback using single byte accesses. 288 */ 289 static uint8_t 290 com_read_1(struct com_regs *regs, u_int reg) 291 { 292 return bus_space_read_1(regs->cr_iot, regs->cr_ioh, reg); 293 } 294 295 /* 296 * com_write_1 -- 297 * Default register write callback using single byte accesses. 298 */ 299 static void 300 com_write_1(struct com_regs *regs, u_int reg, uint8_t val) 301 { 302 bus_space_write_1(regs->cr_iot, regs->cr_ioh, reg, val); 303 } 304 305 /* 306 * com_write_multi_1 -- 307 * Default register multi write callback using single byte accesses. 308 */ 309 static void 310 com_write_multi_1(struct com_regs *regs, u_int reg, const uint8_t *datap, 311 bus_size_t count) 312 { 313 bus_space_write_multi_1(regs->cr_iot, regs->cr_ioh, reg, datap, count); 314 } 315 316 /* 317 * com_read_4 -- 318 * Default register read callback using dword accesses. 319 */ 320 static uint8_t 321 com_read_4(struct com_regs *regs, u_int reg) 322 { 323 return bus_space_read_4(regs->cr_iot, regs->cr_ioh, reg) & 0xff; 324 } 325 326 /* 327 * com_write_4 -- 328 * Default register write callback using dword accesses. 329 */ 330 static void 331 com_write_4(struct com_regs *regs, u_int reg, uint8_t val) 332 { 333 bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, val); 334 } 335 336 /* 337 * com_write_multi_4 -- 338 * Default register multi write callback using dword accesses. 339 */ 340 static void 341 com_write_multi_4(struct com_regs *regs, u_int reg, const uint8_t *datap, 342 bus_size_t count) 343 { 344 while (count-- > 0) { 345 bus_space_write_4(regs->cr_iot, regs->cr_ioh, reg, *datap++); 346 } 347 } 348 349 /* 350 * com_init_regs -- 351 * Driver front-ends use this to initialize our register map 352 * in the standard fashion. They may then tailor the map to 353 * their own particular requirements. 354 */ 355 void 356 com_init_regs(struct com_regs *regs, bus_space_tag_t st, bus_space_handle_t sh, 357 bus_addr_t addr) 358 { 359 360 memset(regs, 0, sizeof(*regs)); 361 regs->cr_iot = st; 362 regs->cr_ioh = sh; 363 regs->cr_iobase = addr; 364 regs->cr_nports = COM_NPORTS; 365 regs->cr_read = com_read_1; 366 regs->cr_write = com_write_1; 367 regs->cr_write_multi = com_write_multi_1; 368 memcpy(regs->cr_map, com_std_map, sizeof(regs->cr_map)); 369 } 370 371 /* 372 * com_init_regs_stride -- 373 * Convenience function for front-ends that have a stride between 374 * registers. 375 */ 376 void 377 com_init_regs_stride(struct com_regs *regs, bus_space_tag_t st, 378 bus_space_handle_t sh, bus_addr_t addr, u_int regshift) 379 { 380 381 com_init_regs(regs, st, sh, addr); 382 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 383 regs->cr_map[i] <<= regshift; 384 } 385 regs->cr_nports <<= regshift; 386 } 387 388 /* 389 * com_init_regs_stride_width -- 390 * Convenience function for front-ends that have a stride between 391 * registers and specific I/O width requirements. 392 */ 393 void 394 com_init_regs_stride_width(struct com_regs *regs, bus_space_tag_t st, 395 bus_space_handle_t sh, bus_addr_t addr, 396 u_int regshift, u_int width) 397 { 398 399 com_init_regs(regs, st, sh, addr); 400 for (size_t i = 0; i < __arraycount(regs->cr_map); i++) { 401 regs->cr_map[i] <<= regshift; 402 } 403 regs->cr_nports <<= regshift; 404 405 switch (width) { 406 case 1: 407 /* Already set by com_init_regs */ 408 break; 409 case 4: 410 regs->cr_read = com_read_4; 411 regs->cr_write = com_write_4; 412 regs->cr_write_multi = com_write_multi_4; 413 break; 414 default: 415 panic("com: unsupported I/O width %d", width); 416 } 417 } 418 419 /*ARGSUSED*/ 420 int 421 comspeed(long speed, long frequency, int type) 422 { 423 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 424 425 int x, err; 426 int divisor = 16; 427 428 if ((type == COM_TYPE_OMAP) && (speed > 230400)) { 429 divisor = 13; 430 } 431 432 if (speed == 0) 433 return (0); 434 if (speed < 0) 435 return (-1); 436 x = divrnd(frequency / divisor, speed); 437 if (x <= 0) 438 return (-1); 439 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000; 440 if (err < 0) 441 err = -err; 442 if (err > COM_TOLERANCE) 443 return (-1); 444 return (x); 445 446 #undef divrnd 447 } 448 449 #ifdef COM_DEBUG 450 int com_debug = 0; 451 452 void comstatus(struct com_softc *, const char *); 453 void 454 comstatus(struct com_softc *sc, const char *str) 455 { 456 struct tty *tp = sc->sc_tty; 457 458 aprint_normal_dev(sc->sc_dev, 459 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n", 460 str, 461 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-', 462 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-', 463 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-', 464 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-', 465 sc->sc_tx_stopped ? '+' : '-'); 466 467 aprint_normal_dev(sc->sc_dev, 468 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n", 469 str, 470 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-', 471 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-', 472 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-', 473 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-', 474 sc->sc_rx_flags); 475 } 476 #endif 477 478 int 479 com_probe_subr(struct com_regs *regs) 480 { 481 482 /* force access to id reg */ 483 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS); 484 CSR_WRITE_1(regs, COM_REG_IIR, 0); 485 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) || 486 (CSR_READ_1(regs, COM_REG_IIR) & 0x38)) 487 return (0); 488 489 return (1); 490 } 491 492 int 493 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh) 494 { 495 struct com_regs regs; 496 497 com_init_regs(®s, iot, ioh, 0/*XXX*/); 498 499 return com_probe_subr(®s); 500 } 501 502 /* 503 * No locking in this routine; it is only called during attach, 504 * or with the port already locked. 505 */ 506 static void 507 com_enable_debugport(struct com_softc *sc) 508 { 509 510 /* Turn on line break interrupt, set carrier. */ 511 sc->sc_ier = IER_ERLS; 512 if (sc->sc_type == COM_TYPE_PXA2x0) 513 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 514 if (sc->sc_type == COM_TYPE_INGENIC || 515 sc->sc_type == COM_TYPE_TEGRA) 516 sc->sc_ier |= IER_ERXTOUT; 517 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 518 SET(sc->sc_mcr, MCR_DTR | MCR_RTS); 519 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr); 520 } 521 522 static void 523 com_intr_poll(void *arg) 524 { 525 struct com_softc * const sc = arg; 526 527 comintr(sc); 528 529 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 530 } 531 532 void 533 com_attach_subr(struct com_softc *sc) 534 { 535 struct com_regs *regsp = &sc->sc_regs; 536 struct tty *tp; 537 uint32_t cpr; 538 uint8_t lcr; 539 const char *fifo_msg = NULL; 540 prop_dictionary_t dict; 541 bool is_console = true; 542 bool force_console = false; 543 544 aprint_naive("\n"); 545 546 dict = device_properties(sc->sc_dev); 547 prop_dictionary_get_bool(dict, "is_console", &is_console); 548 prop_dictionary_get_bool(dict, "force_console", &force_console); 549 callout_init(&sc->sc_diag_callout, 0); 550 callout_init(&sc->sc_poll_callout, 0); 551 callout_setfunc(&sc->sc_poll_callout, com_intr_poll, sc); 552 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH); 553 554 #if defined(COM_16650) 555 sc->sc_type = COM_TYPE_16650; 556 #elif defined(COM_16750) 557 sc->sc_type = COM_TYPE_16750; 558 #elif defined(COM_HAYESP) 559 sc->sc_type = COM_TYPE_HAYESP; 560 #elif defined(COM_PXA2X0) 561 sc->sc_type = COM_TYPE_PXA2x0; 562 #endif 563 564 /* Disable interrupts before configuring the device. */ 565 if (sc->sc_type == COM_TYPE_PXA2x0) 566 sc->sc_ier = IER_EUART; 567 else 568 sc->sc_ier = 0; 569 570 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 571 572 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 573 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) { 574 comconsattached = 1; 575 576 if (force_console) 577 memcpy(regsp, &comcons_info.regs, sizeof(*regsp)); 578 579 if (cn_tab == NULL && comcnreattach() != 0) { 580 printf("can't re-init serial console @%lx\n", 581 (u_long)comcons_info.regs.cr_iobase); 582 } 583 584 switch (sc->sc_type) { 585 case COM_TYPE_16750: 586 case COM_TYPE_DW_APB: 587 /* Use in comintr(). */ 588 sc->sc_lcr = cflag2lcr(comcons_info.cflag); 589 break; 590 } 591 592 /* Make sure the console is always "hardwired". */ 593 delay(10000); /* wait for output to finish */ 594 if (is_console) { 595 SET(sc->sc_hwflags, COM_HW_CONSOLE); 596 } 597 598 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 599 } 600 601 /* Probe for FIFO */ 602 switch (sc->sc_type) { 603 case COM_TYPE_HAYESP: 604 goto fifodone; 605 606 case COM_TYPE_AU1x00: 607 sc->sc_fifolen = 16; 608 fifo_msg = "Au1X00 UART"; 609 SET(sc->sc_hwflags, COM_HW_FIFO); 610 goto fifodelay; 611 612 case COM_TYPE_16550_NOERS: 613 sc->sc_fifolen = 16; 614 fifo_msg = "ns16650, no ERS"; 615 SET(sc->sc_hwflags, COM_HW_FIFO); 616 goto fifodelay; 617 618 case COM_TYPE_OMAP: 619 sc->sc_fifolen = 64; 620 fifo_msg = "OMAP UART"; 621 SET(sc->sc_hwflags, COM_HW_FIFO); 622 goto fifodelay; 623 624 case COM_TYPE_INGENIC: 625 sc->sc_fifolen = 16; 626 fifo_msg = "Ingenic UART"; 627 SET(sc->sc_hwflags, COM_HW_FIFO); 628 SET(sc->sc_hwflags, COM_HW_NOIEN); 629 goto fifodelay; 630 631 case COM_TYPE_TEGRA: 632 sc->sc_fifolen = 8; 633 fifo_msg = "Tegra UART"; 634 SET(sc->sc_hwflags, COM_HW_FIFO); 635 CSR_WRITE_1(regsp, COM_REG_FIFO, 636 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 637 goto fifodelay; 638 639 case COM_TYPE_BCMAUXUART: 640 sc->sc_fifolen = 1; 641 fifo_msg = "BCM AUX UART"; 642 SET(sc->sc_hwflags, COM_HW_FIFO); 643 CSR_WRITE_1(regsp, COM_REG_FIFO, 644 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 645 goto fifodelay; 646 647 case COM_TYPE_DW_APB: 648 if (!prop_dictionary_get_uint(dict, "fifolen", &sc->sc_fifolen)) { 649 cpr = bus_space_read_4(sc->sc_regs.cr_iot, 650 sc->sc_regs.cr_ioh, DW_APB_UART_CPR); 651 sc->sc_fifolen = __SHIFTOUT(cpr, UART_CPR_FIFO_MODE) * 16; 652 } 653 if (sc->sc_fifolen == 0) { 654 sc->sc_fifolen = 1; 655 fifo_msg = "DesignWare APB UART, no fifo"; 656 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 657 } else { 658 fifo_msg = "DesignWare APB UART"; 659 SET(sc->sc_hwflags, COM_HW_FIFO); 660 CSR_WRITE_1(regsp, COM_REG_FIFO, 661 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 662 } 663 goto fifodelay; 664 } 665 666 sc->sc_fifolen = 1; 667 /* look for a NS 16550AF UART with FIFOs */ 668 if (sc->sc_type == COM_TYPE_INGENIC) { 669 CSR_WRITE_1(regsp, COM_REG_FIFO, 670 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 671 FIFO_TRIGGER_14 | FIFO_UART_ON); 672 } else 673 CSR_WRITE_1(regsp, COM_REG_FIFO, 674 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 675 delay(100); 676 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK) 677 == IIR_FIFO_MASK) 678 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14) 679 == FIFO_TRIGGER_14) { 680 SET(sc->sc_hwflags, COM_HW_FIFO); 681 682 fifo_msg = "ns16550a"; 683 sc->sc_fifolen = 16; 684 685 /* 686 * IIR changes into the EFR if LCR is set to LCR_EERS 687 * on 16650s. We also know IIR != 0 at this point. 688 * Write 0 into the EFR, and read it. If the result 689 * is 0, we have a 16650. 690 * 691 * Older 16650s were broken; the test to detect them 692 * is taken from the Linux driver. Apparently 693 * setting DLAB enable gives access to the EFR on 694 * these chips. 695 */ 696 if (sc->sc_type == COM_TYPE_16650) { 697 lcr = CSR_READ_1(regsp, COM_REG_LCR); 698 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 699 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 700 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 701 CSR_WRITE_1(regsp, COM_REG_LCR, 702 lcr | LCR_DLAB); 703 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) { 704 CLR(sc->sc_hwflags, COM_HW_FIFO); 705 sc->sc_fifolen = 0; 706 } else { 707 SET(sc->sc_hwflags, COM_HW_FLOW); 708 sc->sc_fifolen = 32; 709 } 710 } else 711 sc->sc_fifolen = 16; 712 713 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 714 if (sc->sc_fifolen == 0) 715 fifo_msg = "st16650, broken fifo"; 716 else if (sc->sc_fifolen == 32) 717 fifo_msg = "st16650a"; 718 else 719 fifo_msg = "ns16550a"; 720 } 721 722 /* 723 * TL16C750 can enable 64byte FIFO, only when DLAB 724 * is 1. However, some 16750 may always enable. For 725 * example, restrictions according to DLAB in a data 726 * sheet for SC16C750 were not described. 727 * Please enable 'options COM_16650', supposing you 728 * use SC16C750. Probably 32 bytes of FIFO and HW FLOW 729 * should become effective. 730 */ 731 if (sc->sc_type == COM_TYPE_16750) { 732 uint8_t iir1, iir2; 733 uint8_t fcr = FIFO_ENABLE | FIFO_TRIGGER_14; 734 735 lcr = CSR_READ_1(regsp, COM_REG_LCR); 736 CSR_WRITE_1(regsp, COM_REG_LCR, 737 lcr & ~LCR_DLAB); 738 CSR_WRITE_1(regsp, COM_REG_FIFO, 739 fcr | FIFO_64B_ENABLE); 740 iir1 = CSR_READ_1(regsp, COM_REG_IIR); 741 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 742 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB); 743 CSR_WRITE_1(regsp, COM_REG_FIFO, 744 fcr | FIFO_64B_ENABLE); 745 iir2 = CSR_READ_1(regsp, COM_REG_IIR); 746 747 CSR_WRITE_1(regsp, COM_REG_LCR, lcr); 748 749 if (!ISSET(iir1, IIR_64B_FIFO) && 750 ISSET(iir2, IIR_64B_FIFO)) { 751 /* It is TL16C750. */ 752 sc->sc_fifolen = 64; 753 SET(sc->sc_hwflags, COM_HW_AFE); 754 } else 755 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr); 756 757 if (sc->sc_fifolen == 64) 758 fifo_msg = "tl16c750"; 759 else 760 fifo_msg = "ns16750"; 761 } 762 } else 763 fifo_msg = "ns16550, broken fifo"; 764 else 765 fifo_msg = "ns8250 or ns16450, no fifo"; 766 CSR_WRITE_1(regsp, COM_REG_FIFO, 0); 767 768 fifodelay: 769 /* 770 * Some chips will clear down both Tx and Rx FIFOs when zero is 771 * written to com_fifo. If this chip is the console, writing zero 772 * results in some of the chip/FIFO description being lost, so delay 773 * printing it until now. 774 */ 775 delay(10); 776 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 777 aprint_normal(": %s, %d-byte FIFO\n", fifo_msg, sc->sc_fifolen); 778 } else { 779 aprint_normal(": %s\n", fifo_msg); 780 } 781 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) { 782 sc->sc_fifolen = 1; 783 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n"); 784 } 785 786 fifodone: 787 788 tp = tty_alloc(); 789 tp->t_oproc = comstart; 790 tp->t_param = comparam; 791 tp->t_hwiflow = comhwiflow; 792 tp->t_softc = sc; 793 794 sc->sc_tty = tp; 795 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_WAITOK); 796 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 797 sc->sc_rbavail = com_rbuf_size; 798 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1); 799 800 tty_attach(tp); 801 802 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 803 SET(sc->sc_mcr, MCR_IENABLE); 804 805 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 806 int maj; 807 808 /* locate the major number */ 809 maj = cdevsw_lookup_major(&com_cdevsw); 810 811 tp->t_dev = cn_tab->cn_dev = makedev(maj, 812 device_unit(sc->sc_dev)); 813 814 aprint_normal_dev(sc->sc_dev, "console\n"); 815 } 816 817 #ifdef KGDB 818 /* 819 * Allow kgdb to "take over" this port. If this is 820 * not the console and is the kgdb device, it has 821 * exclusive use. If it's the console _and_ the 822 * kgdb device, it doesn't. 823 */ 824 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) && 825 regsp->cr_iobase == comkgdbregs.cr_iobase) { 826 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 827 com_kgdb_attached = 1; 828 829 SET(sc->sc_hwflags, COM_HW_KGDB); 830 } 831 aprint_normal_dev(sc->sc_dev, "kgdb\n"); 832 } 833 #endif 834 835 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc); 836 837 #ifdef RND_COM 838 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 839 RND_TYPE_TTY, RND_FLAG_DEFAULT); 840 #endif 841 842 /* if there are no enable/disable functions, assume the device 843 is always enabled */ 844 if (!sc->enable) 845 sc->enabled = 1; 846 847 com_config(sc); 848 849 SET(sc->sc_hwflags, COM_HW_DEV_OK); 850 851 if (sc->sc_poll_ticks != 0) 852 callout_schedule(&sc->sc_poll_callout, sc->sc_poll_ticks); 853 } 854 855 void 856 com_config(struct com_softc *sc) 857 { 858 struct com_regs *regsp = &sc->sc_regs; 859 860 /* Disable interrupts before configuring the device. */ 861 if (sc->sc_type == COM_TYPE_PXA2x0) 862 sc->sc_ier = IER_EUART; 863 else 864 sc->sc_ier = 0; 865 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 866 (void) CSR_READ_1(regsp, COM_REG_IIR); 867 868 /* Look for a Hayes ESP board. */ 869 if (sc->sc_type == COM_TYPE_HAYESP) { 870 871 /* Set 16550 compatibility mode */ 872 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 873 HAYESP_SETMODE); 874 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 875 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 876 HAYESP_MODE_SCALE); 877 878 /* Set RTS/CTS flow control */ 879 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 880 HAYESP_SETFLOWTYPE); 881 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 882 HAYESP_FLOW_RTS); 883 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 884 HAYESP_FLOW_CTS); 885 886 /* Set flow control levels */ 887 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 888 HAYESP_SETRXFLOW); 889 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 890 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 891 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 892 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 893 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 894 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 895 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 896 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 897 } 898 899 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB)) 900 com_enable_debugport(sc); 901 } 902 903 int 904 com_detach(device_t self, int flags) 905 { 906 struct com_softc *sc = device_private(self); 907 int maj, mn; 908 909 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 910 return EBUSY; 911 912 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE) && 913 (flags & DETACH_SHUTDOWN) != 0) 914 return EBUSY; 915 916 if (sc->disable != NULL && sc->enabled != 0) { 917 (*sc->disable)(sc); 918 sc->enabled = 0; 919 } 920 921 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 922 comconsattached = 0; 923 cn_tab = NULL; 924 } 925 926 /* locate the major number */ 927 maj = cdevsw_lookup_major(&com_cdevsw); 928 929 /* Nuke the vnodes for any open instances. */ 930 mn = device_unit(self); 931 vdevgone(maj, mn, mn, VCHR); 932 933 mn |= COMDIALOUT_MASK; 934 vdevgone(maj, mn, mn, VCHR); 935 936 if (sc->sc_rbuf == NULL) { 937 /* 938 * Ring buffer allocation failed in the com_attach_subr, 939 * only the tty is allocated, and nothing else. 940 */ 941 tty_free(sc->sc_tty); 942 return 0; 943 } 944 945 /* Free the receive buffer. */ 946 free(sc->sc_rbuf, M_DEVBUF); 947 948 /* Detach and free the tty. */ 949 tty_detach(sc->sc_tty); 950 tty_free(sc->sc_tty); 951 952 /* Unhook the soft interrupt handler. */ 953 softint_disestablish(sc->sc_si); 954 955 #ifdef RND_COM 956 /* Unhook the entropy source. */ 957 rnd_detach_source(&sc->rnd_source); 958 #endif 959 callout_destroy(&sc->sc_diag_callout); 960 961 /* Destroy the lock. */ 962 mutex_destroy(&sc->sc_lock); 963 964 return (0); 965 } 966 967 void 968 com_shutdown(struct com_softc *sc) 969 { 970 struct tty *tp = sc->sc_tty; 971 972 mutex_spin_enter(&sc->sc_lock); 973 974 /* If we were asserting flow control, then deassert it. */ 975 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 976 com_hwiflow(sc); 977 978 /* Clear any break condition set with TIOCSBRK. */ 979 com_break(sc, 0); 980 981 /* 982 * Hang up if necessary. Record when we hung up, so if we 983 * immediately open the port again, we will wait a bit until 984 * the other side has had time to notice that we hung up. 985 */ 986 if (ISSET(tp->t_cflag, HUPCL)) { 987 com_modem(sc, 0); 988 microuptime(&sc->sc_hup_pending); 989 sc->sc_hup_pending.tv_sec++; 990 } 991 992 /* Turn off interrupts. */ 993 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 994 sc->sc_ier = IER_ERLS; /* interrupt on line break */ 995 if ((sc->sc_type == COM_TYPE_PXA2x0) || 996 (sc->sc_type == COM_TYPE_INGENIC) || 997 (sc->sc_type == COM_TYPE_TEGRA)) 998 sc->sc_ier |= IER_ERXTOUT; 999 } else 1000 sc->sc_ier = 0; 1001 1002 if (sc->sc_type == COM_TYPE_PXA2x0) 1003 sc->sc_ier |= IER_EUART; 1004 1005 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1006 1007 mutex_spin_exit(&sc->sc_lock); 1008 1009 if (sc->disable) { 1010 #ifdef DIAGNOSTIC 1011 if (!sc->enabled) 1012 panic("com_shutdown: not enabled?"); 1013 #endif 1014 (*sc->disable)(sc); 1015 sc->enabled = 0; 1016 } 1017 } 1018 1019 int 1020 comopen(dev_t dev, int flag, int mode, struct lwp *l) 1021 { 1022 struct com_softc *sc; 1023 struct tty *tp; 1024 int s; 1025 int error; 1026 1027 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1028 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) || 1029 sc->sc_rbuf == NULL) 1030 return (ENXIO); 1031 1032 if (!device_is_active(sc->sc_dev)) 1033 return (ENXIO); 1034 1035 #ifdef KGDB 1036 /* 1037 * If this is the kgdb port, no other use is permitted. 1038 */ 1039 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) 1040 return (EBUSY); 1041 #endif 1042 1043 tp = sc->sc_tty; 1044 1045 /* 1046 * If the device is exclusively for kernel use, deny userland 1047 * open. 1048 */ 1049 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1050 return (EBUSY); 1051 1052 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 1053 return (EBUSY); 1054 1055 s = spltty(); 1056 1057 /* 1058 * Do the following iff this is a first open. 1059 */ 1060 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1061 struct termios t; 1062 struct timeval now, diff; 1063 1064 tp->t_dev = dev; 1065 1066 if (sc->enable) { 1067 if ((*sc->enable)(sc)) { 1068 splx(s); 1069 aprint_error_dev(sc->sc_dev, 1070 "device enable failed\n"); 1071 return (EIO); 1072 } 1073 mutex_spin_enter(&sc->sc_lock); 1074 sc->enabled = 1; 1075 com_config(sc); 1076 } else { 1077 mutex_spin_enter(&sc->sc_lock); 1078 } 1079 1080 if (timerisset(&sc->sc_hup_pending)) { 1081 microuptime(&now); 1082 while (timercmp(&now, &sc->sc_hup_pending, <)) { 1083 timersub(&sc->sc_hup_pending, &now, &diff); 1084 const int ms = diff.tv_sec * 1000 + 1085 diff.tv_usec / 1000; 1086 kpause(ttclos, false, uimax(mstohz(ms), 1), 1087 &sc->sc_lock); 1088 microuptime(&now); 1089 } 1090 timerclear(&sc->sc_hup_pending); 1091 } 1092 1093 /* Turn on interrupts. */ 1094 sc->sc_ier = IER_ERXRDY | IER_ERLS; 1095 if (!ISSET(tp->t_cflag, CLOCAL)) 1096 sc->sc_ier |= IER_EMSC; 1097 1098 if (sc->sc_type == COM_TYPE_PXA2x0) 1099 sc->sc_ier |= IER_EUART | IER_ERXTOUT; 1100 else if (sc->sc_type == COM_TYPE_INGENIC || 1101 sc->sc_type == COM_TYPE_TEGRA) 1102 sc->sc_ier |= IER_ERXTOUT; 1103 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier); 1104 1105 /* Fetch the current modem control status, needed later. */ 1106 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR); 1107 1108 /* Clear PPS capture state on first open. */ 1109 mutex_spin_enter(&timecounter_lock); 1110 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state)); 1111 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR; 1112 pps_init(&sc->sc_pps_state); 1113 mutex_spin_exit(&timecounter_lock); 1114 1115 mutex_spin_exit(&sc->sc_lock); 1116 1117 /* 1118 * Initialize the termios status to the defaults. Add in the 1119 * sticky bits from TIOCSFLAGS. 1120 */ 1121 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1122 t.c_ospeed = comcons_info.rate; 1123 t.c_cflag = comcons_info.cflag; 1124 } else { 1125 t.c_ospeed = TTYDEF_SPEED; 1126 t.c_cflag = TTYDEF_CFLAG; 1127 } 1128 t.c_ispeed = t.c_ospeed; 1129 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 1130 SET(t.c_cflag, CLOCAL); 1131 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 1132 SET(t.c_cflag, CRTSCTS); 1133 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 1134 SET(t.c_cflag, MDMBUF); 1135 /* Make sure comparam() will do something. */ 1136 tp->t_ospeed = 0; 1137 (void) comparam(tp, &t); 1138 tp->t_iflag = TTYDEF_IFLAG; 1139 tp->t_oflag = TTYDEF_OFLAG; 1140 tp->t_lflag = TTYDEF_LFLAG; 1141 ttychars(tp); 1142 ttsetwater(tp); 1143 1144 mutex_spin_enter(&sc->sc_lock); 1145 1146 /* 1147 * Turn on DTR. We must always do this, even if carrier is not 1148 * present, because otherwise we'd have to use TIOCSDTR 1149 * immediately after setting CLOCAL, which applications do not 1150 * expect. We always assert DTR while the device is open 1151 * unless explicitly requested to deassert it. 1152 */ 1153 com_modem(sc, 1); 1154 1155 /* Clear the input ring, and unblock. */ 1156 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 1157 sc->sc_rbavail = com_rbuf_size; 1158 com_iflush(sc); 1159 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 1160 com_hwiflow(sc); 1161 1162 #ifdef COM_DEBUG 1163 if (com_debug) 1164 comstatus(sc, "comopen "); 1165 #endif 1166 1167 mutex_spin_exit(&sc->sc_lock); 1168 } 1169 1170 splx(s); 1171 1172 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 1173 if (error) 1174 goto bad; 1175 1176 error = (*tp->t_linesw->l_open)(dev, tp); 1177 if (error) 1178 goto bad; 1179 1180 return (0); 1181 1182 bad: 1183 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1184 /* 1185 * We failed to open the device, and nobody else had it opened. 1186 * Clean up the state as appropriate. 1187 */ 1188 com_shutdown(sc); 1189 } 1190 1191 return (error); 1192 } 1193 1194 int 1195 comclose(dev_t dev, int flag, int mode, struct lwp *l) 1196 { 1197 struct com_softc *sc = 1198 device_lookup_private(&com_cd, COMUNIT(dev)); 1199 struct tty *tp = sc->sc_tty; 1200 1201 /* XXX This is for cons.c. */ 1202 if (!ISSET(tp->t_state, TS_ISOPEN)) 1203 return (0); 1204 /* 1205 * If the device is exclusively for kernel use, deny userland 1206 * close. 1207 */ 1208 if (ISSET(tp->t_state, TS_KERN_ONLY)) 1209 return (0); 1210 1211 (*tp->t_linesw->l_close)(tp, flag); 1212 ttyclose(tp); 1213 1214 if (COM_ISALIVE(sc) == 0) 1215 return (0); 1216 1217 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 1218 /* 1219 * Although we got a last close, the device may still be in 1220 * use; e.g. if this was the dialout node, and there are still 1221 * processes waiting for carrier on the non-dialout node. 1222 */ 1223 com_shutdown(sc); 1224 } 1225 1226 return (0); 1227 } 1228 1229 int 1230 comread(dev_t dev, struct uio *uio, int flag) 1231 { 1232 struct com_softc *sc = 1233 device_lookup_private(&com_cd, COMUNIT(dev)); 1234 struct tty *tp = sc->sc_tty; 1235 1236 if (COM_ISALIVE(sc) == 0) 1237 return (EIO); 1238 1239 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 1240 } 1241 1242 int 1243 comwrite(dev_t dev, struct uio *uio, int flag) 1244 { 1245 struct com_softc *sc = 1246 device_lookup_private(&com_cd, COMUNIT(dev)); 1247 struct tty *tp = sc->sc_tty; 1248 1249 if (COM_ISALIVE(sc) == 0) 1250 return (EIO); 1251 1252 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 1253 } 1254 1255 int 1256 compoll(dev_t dev, int events, struct lwp *l) 1257 { 1258 struct com_softc *sc = 1259 device_lookup_private(&com_cd, COMUNIT(dev)); 1260 struct tty *tp = sc->sc_tty; 1261 1262 if (COM_ISALIVE(sc) == 0) 1263 return (POLLHUP); 1264 1265 return ((*tp->t_linesw->l_poll)(tp, events, l)); 1266 } 1267 1268 struct tty * 1269 comtty(dev_t dev) 1270 { 1271 struct com_softc *sc = 1272 device_lookup_private(&com_cd, COMUNIT(dev)); 1273 struct tty *tp = sc->sc_tty; 1274 1275 return (tp); 1276 } 1277 1278 int 1279 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 1280 { 1281 struct com_softc *sc; 1282 struct tty *tp; 1283 int error; 1284 1285 sc = device_lookup_private(&com_cd, COMUNIT(dev)); 1286 if (sc == NULL) 1287 return ENXIO; 1288 if (COM_ISALIVE(sc) == 0) 1289 return (EIO); 1290 1291 tp = sc->sc_tty; 1292 1293 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 1294 if (error != EPASSTHROUGH) 1295 return (error); 1296 1297 error = ttioctl(tp, cmd, data, flag, l); 1298 if (error != EPASSTHROUGH) 1299 return (error); 1300 1301 error = 0; 1302 switch (cmd) { 1303 case TIOCSFLAGS: 1304 error = kauth_authorize_device_tty(l->l_cred, 1305 KAUTH_DEVICE_TTY_PRIVSET, tp); 1306 break; 1307 default: 1308 /* nothing */ 1309 break; 1310 } 1311 if (error) { 1312 return error; 1313 } 1314 1315 mutex_spin_enter(&sc->sc_lock); 1316 1317 switch (cmd) { 1318 case TIOCSBRK: 1319 com_break(sc, 1); 1320 break; 1321 1322 case TIOCCBRK: 1323 com_break(sc, 0); 1324 break; 1325 1326 case TIOCSDTR: 1327 com_modem(sc, 1); 1328 break; 1329 1330 case TIOCCDTR: 1331 com_modem(sc, 0); 1332 break; 1333 1334 case TIOCGFLAGS: 1335 *(int *)data = sc->sc_swflags; 1336 break; 1337 1338 case TIOCSFLAGS: 1339 sc->sc_swflags = *(int *)data; 1340 break; 1341 1342 case TIOCMSET: 1343 case TIOCMBIS: 1344 case TIOCMBIC: 1345 tiocm_to_com(sc, cmd, *(int *)data); 1346 break; 1347 1348 case TIOCMGET: 1349 *(int *)data = com_to_tiocm(sc); 1350 break; 1351 1352 case PPS_IOC_CREATE: 1353 case PPS_IOC_DESTROY: 1354 case PPS_IOC_GETPARAMS: 1355 case PPS_IOC_SETPARAMS: 1356 case PPS_IOC_GETCAP: 1357 case PPS_IOC_FETCH: 1358 #ifdef PPS_SYNC 1359 case PPS_IOC_KCBIND: 1360 #endif 1361 mutex_spin_enter(&timecounter_lock); 1362 error = pps_ioctl(cmd, data, &sc->sc_pps_state); 1363 mutex_spin_exit(&timecounter_lock); 1364 break; 1365 1366 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */ 1367 mutex_spin_enter(&timecounter_lock); 1368 #ifndef PPS_TRAILING_EDGE 1369 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1370 &sc->sc_pps_state.ppsinfo.assert_timestamp); 1371 #else 1372 TIMESPEC_TO_TIMEVAL((struct timeval *)data, 1373 &sc->sc_pps_state.ppsinfo.clear_timestamp); 1374 #endif 1375 mutex_spin_exit(&timecounter_lock); 1376 break; 1377 1378 default: 1379 error = EPASSTHROUGH; 1380 break; 1381 } 1382 1383 mutex_spin_exit(&sc->sc_lock); 1384 1385 #ifdef COM_DEBUG 1386 if (com_debug) 1387 comstatus(sc, "comioctl "); 1388 #endif 1389 1390 return (error); 1391 } 1392 1393 static inline void 1394 com_schedrx(struct com_softc *sc) 1395 { 1396 1397 sc->sc_rx_ready = 1; 1398 1399 /* Wake up the poller. */ 1400 softint_schedule(sc->sc_si); 1401 } 1402 1403 void 1404 com_break(struct com_softc *sc, int onoff) 1405 { 1406 1407 if (onoff) 1408 SET(sc->sc_lcr, LCR_SBREAK); 1409 else 1410 CLR(sc->sc_lcr, LCR_SBREAK); 1411 1412 if (!sc->sc_heldchange) { 1413 if (sc->sc_tx_busy) { 1414 sc->sc_heldtbc = sc->sc_tbc; 1415 sc->sc_tbc = 0; 1416 sc->sc_heldchange = 1; 1417 } else 1418 com_loadchannelregs(sc); 1419 } 1420 } 1421 1422 void 1423 com_modem(struct com_softc *sc, int onoff) 1424 { 1425 1426 if (sc->sc_mcr_dtr == 0) 1427 return; 1428 1429 if (onoff) 1430 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1431 else 1432 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1433 1434 if (!sc->sc_heldchange) { 1435 if (sc->sc_tx_busy) { 1436 sc->sc_heldtbc = sc->sc_tbc; 1437 sc->sc_tbc = 0; 1438 sc->sc_heldchange = 1; 1439 } else 1440 com_loadchannelregs(sc); 1441 } 1442 } 1443 1444 void 1445 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits) 1446 { 1447 u_char combits; 1448 1449 combits = 0; 1450 if (ISSET(ttybits, TIOCM_DTR)) 1451 SET(combits, MCR_DTR); 1452 if (ISSET(ttybits, TIOCM_RTS)) 1453 SET(combits, MCR_RTS); 1454 1455 switch (how) { 1456 case TIOCMBIC: 1457 CLR(sc->sc_mcr, combits); 1458 break; 1459 1460 case TIOCMBIS: 1461 SET(sc->sc_mcr, combits); 1462 break; 1463 1464 case TIOCMSET: 1465 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 1466 SET(sc->sc_mcr, combits); 1467 break; 1468 } 1469 1470 if (!sc->sc_heldchange) { 1471 if (sc->sc_tx_busy) { 1472 sc->sc_heldtbc = sc->sc_tbc; 1473 sc->sc_tbc = 0; 1474 sc->sc_heldchange = 1; 1475 } else 1476 com_loadchannelregs(sc); 1477 } 1478 } 1479 1480 int 1481 com_to_tiocm(struct com_softc *sc) 1482 { 1483 u_char combits; 1484 int ttybits = 0; 1485 1486 combits = sc->sc_mcr; 1487 if (ISSET(combits, MCR_DTR)) 1488 SET(ttybits, TIOCM_DTR); 1489 if (ISSET(combits, MCR_RTS)) 1490 SET(ttybits, TIOCM_RTS); 1491 1492 combits = sc->sc_msr; 1493 if (sc->sc_type == COM_TYPE_INGENIC) { 1494 SET(ttybits, TIOCM_CD); 1495 } else { 1496 if (ISSET(combits, MSR_DCD)) 1497 SET(ttybits, TIOCM_CD); 1498 } 1499 if (ISSET(combits, MSR_CTS)) 1500 SET(ttybits, TIOCM_CTS); 1501 if (ISSET(combits, MSR_DSR)) 1502 SET(ttybits, TIOCM_DSR); 1503 if (ISSET(combits, MSR_RI | MSR_TERI)) 1504 SET(ttybits, TIOCM_RI); 1505 1506 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC)) 1507 SET(ttybits, TIOCM_LE); 1508 1509 return (ttybits); 1510 } 1511 1512 static u_char 1513 cflag2lcr(tcflag_t cflag) 1514 { 1515 u_char lcr = 0; 1516 1517 switch (ISSET(cflag, CSIZE)) { 1518 case CS5: 1519 SET(lcr, LCR_5BITS); 1520 break; 1521 case CS6: 1522 SET(lcr, LCR_6BITS); 1523 break; 1524 case CS7: 1525 SET(lcr, LCR_7BITS); 1526 break; 1527 case CS8: 1528 SET(lcr, LCR_8BITS); 1529 break; 1530 } 1531 if (ISSET(cflag, PARENB)) { 1532 SET(lcr, LCR_PENAB); 1533 if (!ISSET(cflag, PARODD)) 1534 SET(lcr, LCR_PEVEN); 1535 } 1536 if (ISSET(cflag, CSTOPB)) 1537 SET(lcr, LCR_STOPB); 1538 1539 return (lcr); 1540 } 1541 1542 int 1543 comparam(struct tty *tp, struct termios *t) 1544 { 1545 struct com_softc *sc = 1546 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1547 int ospeed; 1548 u_char lcr; 1549 1550 if (COM_ISALIVE(sc) == 0) 1551 return (EIO); 1552 1553 if (sc->sc_type == COM_TYPE_HAYESP) { 1554 int prescaler, speed; 1555 1556 /* 1557 * Calculate UART clock prescaler. It should be in 1558 * range of 0 .. 3. 1559 */ 1560 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4; 1561 prescaler++, speed /= 2) 1562 if ((ospeed = comspeed(speed, sc->sc_frequency, 1563 sc->sc_type)) > 0) 1564 break; 1565 1566 if (prescaler == 4) 1567 return (EINVAL); 1568 sc->sc_prescaler = prescaler; 1569 } else 1570 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type); 1571 1572 /* Check requested parameters. */ 1573 if (ospeed < 0) 1574 return (EINVAL); 1575 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 1576 return (EINVAL); 1577 1578 /* 1579 * For the console, always force CLOCAL and !HUPCL, so that the port 1580 * is always active. 1581 */ 1582 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 1583 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 1584 SET(t->c_cflag, CLOCAL); 1585 CLR(t->c_cflag, HUPCL); 1586 } 1587 1588 /* 1589 * If there were no changes, don't do anything. This avoids dropping 1590 * input and improves performance when all we did was frob things like 1591 * VMIN and VTIME. 1592 */ 1593 if (tp->t_ospeed == t->c_ospeed && 1594 tp->t_cflag == t->c_cflag) 1595 return (0); 1596 1597 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 1598 1599 mutex_spin_enter(&sc->sc_lock); 1600 1601 sc->sc_lcr = lcr; 1602 1603 /* 1604 * If we're not in a mode that assumes a connection is present, then 1605 * ignore carrier changes. 1606 */ 1607 if (ISSET(t->c_cflag, CLOCAL | MDMBUF)) 1608 sc->sc_msr_dcd = 0; 1609 else 1610 sc->sc_msr_dcd = MSR_DCD; 1611 /* 1612 * Set the flow control pins depending on the current flow control 1613 * mode. 1614 */ 1615 if (ISSET(t->c_cflag, CRTSCTS)) { 1616 sc->sc_mcr_dtr = MCR_DTR; 1617 sc->sc_mcr_rts = MCR_RTS; 1618 sc->sc_msr_cts = MSR_CTS; 1619 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1620 SET(sc->sc_mcr, MCR_AFE); 1621 } else { 1622 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS; 1623 } 1624 } else if (ISSET(t->c_cflag, MDMBUF)) { 1625 /* 1626 * For DTR/DCD flow control, make sure we don't toggle DTR for 1627 * carrier detection. 1628 */ 1629 sc->sc_mcr_dtr = 0; 1630 sc->sc_mcr_rts = MCR_DTR; 1631 sc->sc_msr_cts = MSR_DCD; 1632 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1633 CLR(sc->sc_mcr, MCR_AFE); 1634 } else { 1635 sc->sc_efr = 0; 1636 } 1637 } else { 1638 /* 1639 * If no flow control, then always set RTS. This will make 1640 * the other side happy if it mistakenly thinks we're doing 1641 * RTS/CTS flow control. 1642 */ 1643 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS; 1644 sc->sc_mcr_rts = 0; 1645 sc->sc_msr_cts = 0; 1646 if (ISSET(sc->sc_hwflags, COM_HW_AFE)) { 1647 CLR(sc->sc_mcr, MCR_AFE); 1648 } else { 1649 sc->sc_efr = 0; 1650 } 1651 if (ISSET(sc->sc_mcr, MCR_DTR)) 1652 SET(sc->sc_mcr, MCR_RTS); 1653 else 1654 CLR(sc->sc_mcr, MCR_RTS); 1655 } 1656 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd; 1657 1658 if (t->c_ospeed == 0 && tp->t_ospeed != 0) 1659 CLR(sc->sc_mcr, sc->sc_mcr_dtr); 1660 else if (t->c_ospeed != 0 && tp->t_ospeed == 0) 1661 SET(sc->sc_mcr, sc->sc_mcr_dtr); 1662 1663 sc->sc_dlbl = ospeed; 1664 sc->sc_dlbh = ospeed >> 8; 1665 1666 /* 1667 * Set the FIFO threshold based on the receive speed. 1668 * 1669 * * If it's a low speed, it's probably a mouse or some other 1670 * interactive device, so set the threshold low. 1671 * * If it's a high speed, trim the trigger level down to prevent 1672 * overflows. 1673 * * Otherwise set it a bit higher. 1674 */ 1675 if (sc->sc_type == COM_TYPE_HAYESP) { 1676 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 1677 } else if (sc->sc_type == COM_TYPE_TEGRA) { 1678 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1679 } else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1680 if (t->c_ospeed <= 1200) 1681 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1; 1682 else if (t->c_ospeed <= 38400) 1683 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8; 1684 else 1685 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4; 1686 } else { 1687 sc->sc_fifo = 0; 1688 } 1689 1690 if (sc->sc_type == COM_TYPE_INGENIC) 1691 sc->sc_fifo |= FIFO_UART_ON; 1692 1693 /* And copy to tty. */ 1694 tp->t_ispeed = t->c_ospeed; 1695 tp->t_ospeed = t->c_ospeed; 1696 tp->t_cflag = t->c_cflag; 1697 1698 if (!sc->sc_heldchange) { 1699 if (sc->sc_tx_busy) { 1700 sc->sc_heldtbc = sc->sc_tbc; 1701 sc->sc_tbc = 0; 1702 sc->sc_heldchange = 1; 1703 } else 1704 com_loadchannelregs(sc); 1705 } 1706 1707 if (!ISSET(t->c_cflag, CHWFLOW)) { 1708 /* Disable the high water mark. */ 1709 sc->sc_r_hiwat = 0; 1710 sc->sc_r_lowat = 0; 1711 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1712 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1713 com_schedrx(sc); 1714 } 1715 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) { 1716 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED); 1717 com_hwiflow(sc); 1718 } 1719 } else { 1720 sc->sc_r_hiwat = com_rbuf_hiwat; 1721 sc->sc_r_lowat = com_rbuf_lowat; 1722 } 1723 1724 mutex_spin_exit(&sc->sc_lock); 1725 1726 /* 1727 * Update the tty layer's idea of the carrier bit, in case we changed 1728 * CLOCAL or MDMBUF. We don't hang up here; we only do that by 1729 * explicit request. 1730 */ 1731 if (sc->sc_type == COM_TYPE_INGENIC) { 1732 /* no DCD here */ 1733 (void) (*tp->t_linesw->l_modem)(tp, 1); 1734 } else 1735 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD)); 1736 1737 #ifdef COM_DEBUG 1738 if (com_debug) 1739 comstatus(sc, "comparam "); 1740 #endif 1741 1742 if (!ISSET(t->c_cflag, CHWFLOW)) { 1743 if (sc->sc_tx_stopped) { 1744 sc->sc_tx_stopped = 0; 1745 comstart(tp); 1746 } 1747 } 1748 1749 return (0); 1750 } 1751 1752 void 1753 com_iflush(struct com_softc *sc) 1754 { 1755 struct com_regs *regsp = &sc->sc_regs; 1756 uint8_t fifo; 1757 #ifdef DIAGNOSTIC 1758 int reg; 1759 #endif 1760 int timo; 1761 1762 #ifdef DIAGNOSTIC 1763 reg = 0xffff; 1764 #endif 1765 timo = 50000; 1766 /* flush any pending I/O */ 1767 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY) 1768 && --timo) 1769 #ifdef DIAGNOSTIC 1770 reg = 1771 #else 1772 (void) 1773 #endif 1774 CSR_READ_1(regsp, COM_REG_RXDATA); 1775 #ifdef DIAGNOSTIC 1776 if (!timo) 1777 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg); 1778 #endif 1779 1780 switch (sc->sc_type) { 1781 case COM_TYPE_16750: 1782 case COM_TYPE_DW_APB: 1783 /* 1784 * Reset all Rx/Tx FIFO, preserve current FIFO length. 1785 * This should prevent triggering busy interrupt while 1786 * manipulating divisors. 1787 */ 1788 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 | 1789 FIFO_TRIGGER_4 | FIFO_TRIGGER_8 | FIFO_TRIGGER_14); 1790 CSR_WRITE_1(regsp, COM_REG_FIFO, 1791 fifo | FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST); 1792 delay(100); 1793 break; 1794 } 1795 } 1796 1797 void 1798 com_loadchannelregs(struct com_softc *sc) 1799 { 1800 struct com_regs *regsp = &sc->sc_regs; 1801 1802 /* XXXXX necessary? */ 1803 com_iflush(sc); 1804 1805 if (sc->sc_type == COM_TYPE_PXA2x0) 1806 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 1807 else 1808 CSR_WRITE_1(regsp, COM_REG_IER, 0); 1809 1810 if (sc->sc_type == COM_TYPE_OMAP) { 1811 /* disable before changing settings */ 1812 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 1813 } 1814 1815 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) { 1816 KASSERT(sc->sc_type != COM_TYPE_AU1x00); 1817 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS); 1818 /* no EFR on alchemy */ 1819 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 1820 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr); 1821 } 1822 if (sc->sc_type == COM_TYPE_AU1x00) { 1823 /* alchemy has single separate 16-bit clock divisor register */ 1824 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl + 1825 (sc->sc_dlbh << 8)); 1826 } else { 1827 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 1828 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 1829 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 1830 } 1831 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 1832 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr); 1833 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo); 1834 if (sc->sc_type == COM_TYPE_HAYESP) { 1835 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1, 1836 HAYESP_SETPRESCALER); 1837 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2, 1838 sc->sc_prescaler); 1839 } 1840 if (sc->sc_type == COM_TYPE_OMAP) { 1841 /* setup the fifos. the FCR value is not used as long 1842 as SCR[6] and SCR[7] are 0, which they are at reset 1843 and we never touch the SCR register */ 1844 uint8_t rx_fifo_trig = 40; 1845 uint8_t tx_fifo_trig = 60; 1846 uint8_t rx_start = 8; 1847 uint8_t rx_halt = 60; 1848 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 1849 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 1850 1851 /* enable access to TCR & TLR */ 1852 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR); 1853 1854 /* write tcr and tlr values */ 1855 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 1856 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 1857 1858 /* disable access to TCR & TLR */ 1859 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr); 1860 1861 /* enable again, but mode is based on speed */ 1862 if (sc->sc_tty->t_termios.c_ospeed > 230400) { 1863 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 1864 } else { 1865 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 1866 } 1867 } 1868 1869 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1870 } 1871 1872 int 1873 comhwiflow(struct tty *tp, int block) 1874 { 1875 struct com_softc *sc = 1876 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1877 1878 if (COM_ISALIVE(sc) == 0) 1879 return (0); 1880 1881 if (sc->sc_mcr_rts == 0) 1882 return (0); 1883 1884 mutex_spin_enter(&sc->sc_lock); 1885 1886 if (block) { 1887 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1888 SET(sc->sc_rx_flags, RX_TTY_BLOCKED); 1889 com_hwiflow(sc); 1890 } 1891 } else { 1892 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 1893 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1894 com_schedrx(sc); 1895 } 1896 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1897 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED); 1898 com_hwiflow(sc); 1899 } 1900 } 1901 1902 mutex_spin_exit(&sc->sc_lock); 1903 return (1); 1904 } 1905 1906 /* 1907 * (un)block input via hw flowcontrol 1908 */ 1909 void 1910 com_hwiflow(struct com_softc *sc) 1911 { 1912 struct com_regs *regsp= &sc->sc_regs; 1913 1914 if (sc->sc_mcr_rts == 0) 1915 return; 1916 1917 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) { 1918 CLR(sc->sc_mcr, sc->sc_mcr_rts); 1919 CLR(sc->sc_mcr_active, sc->sc_mcr_rts); 1920 } else { 1921 SET(sc->sc_mcr, sc->sc_mcr_rts); 1922 SET(sc->sc_mcr_active, sc->sc_mcr_rts); 1923 } 1924 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active); 1925 } 1926 1927 1928 void 1929 comstart(struct tty *tp) 1930 { 1931 struct com_softc *sc = 1932 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1933 struct com_regs *regsp = &sc->sc_regs; 1934 1935 if (COM_ISALIVE(sc) == 0) 1936 return; 1937 1938 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 1939 return; 1940 if (sc->sc_tx_stopped) 1941 return; 1942 if (!ttypull(tp)) 1943 return; 1944 1945 /* Grab the first contiguous region of buffer space. */ 1946 { 1947 u_char *tba; 1948 int tbc; 1949 1950 tba = tp->t_outq.c_cf; 1951 tbc = ndqb(&tp->t_outq, 0); 1952 1953 mutex_spin_enter(&sc->sc_lock); 1954 1955 sc->sc_tba = tba; 1956 sc->sc_tbc = tbc; 1957 } 1958 1959 SET(tp->t_state, TS_BUSY); 1960 sc->sc_tx_busy = 1; 1961 1962 /* Enable transmit completion interrupts if necessary. */ 1963 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1964 SET(sc->sc_ier, IER_ETXRDY); 1965 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 1966 } 1967 1968 /* Output the first chunk of the contiguous buffer. */ 1969 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) { 1970 u_int n; 1971 1972 n = sc->sc_tbc; 1973 if (n > sc->sc_fifolen) 1974 n = sc->sc_fifolen; 1975 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 1976 sc->sc_tbc -= n; 1977 sc->sc_tba += n; 1978 } 1979 1980 mutex_spin_exit(&sc->sc_lock); 1981 } 1982 1983 /* 1984 * Stop output on a line. 1985 */ 1986 void 1987 comstop(struct tty *tp, int flag) 1988 { 1989 struct com_softc *sc = 1990 device_lookup_private(&com_cd, COMUNIT(tp->t_dev)); 1991 1992 mutex_spin_enter(&sc->sc_lock); 1993 if (ISSET(tp->t_state, TS_BUSY)) { 1994 /* Stop transmitting at the next chunk. */ 1995 sc->sc_tbc = 0; 1996 sc->sc_heldtbc = 0; 1997 if (!ISSET(tp->t_state, TS_TTSTOP)) 1998 SET(tp->t_state, TS_FLUSH); 1999 } 2000 mutex_spin_exit(&sc->sc_lock); 2001 } 2002 2003 void 2004 comdiag(void *arg) 2005 { 2006 struct com_softc *sc = arg; 2007 int overflows, floods; 2008 2009 mutex_spin_enter(&sc->sc_lock); 2010 overflows = sc->sc_overflows; 2011 sc->sc_overflows = 0; 2012 floods = sc->sc_floods; 2013 sc->sc_floods = 0; 2014 sc->sc_errors = 0; 2015 mutex_spin_exit(&sc->sc_lock); 2016 2017 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 2018 device_xname(sc->sc_dev), 2019 overflows, overflows == 1 ? "" : "s", 2020 floods, floods == 1 ? "" : "s"); 2021 } 2022 2023 static inline void 2024 com_rxsoft(struct com_softc *sc, struct tty *tp) 2025 { 2026 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 2027 u_char *get, *end; 2028 u_int cc, scc; 2029 u_char lsr; 2030 int code; 2031 2032 end = sc->sc_ebuf; 2033 get = sc->sc_rbget; 2034 scc = cc = com_rbuf_size - sc->sc_rbavail; 2035 2036 if (cc == com_rbuf_size) { 2037 sc->sc_floods++; 2038 if (sc->sc_errors++ == 0) 2039 callout_reset(&sc->sc_diag_callout, 60 * hz, 2040 comdiag, sc); 2041 } 2042 2043 /* If not yet open, drop the entire buffer content here */ 2044 if (!ISSET(tp->t_state, TS_ISOPEN)) { 2045 get += cc << 1; 2046 if (get >= end) 2047 get -= com_rbuf_size << 1; 2048 cc = 0; 2049 } 2050 while (cc) { 2051 code = get[0]; 2052 lsr = get[1]; 2053 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) { 2054 if (ISSET(lsr, LSR_OE)) { 2055 sc->sc_overflows++; 2056 if (sc->sc_errors++ == 0) 2057 callout_reset(&sc->sc_diag_callout, 2058 60 * hz, comdiag, sc); 2059 } 2060 if (ISSET(lsr, LSR_BI | LSR_FE)) 2061 SET(code, TTY_FE); 2062 if (ISSET(lsr, LSR_PE)) 2063 SET(code, TTY_PE); 2064 } 2065 if ((*rint)(code, tp) == -1) { 2066 /* 2067 * The line discipline's buffer is out of space. 2068 */ 2069 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 2070 /* 2071 * We're either not using flow control, or the 2072 * line discipline didn't tell us to block for 2073 * some reason. Either way, we have no way to 2074 * know when there's more space available, so 2075 * just drop the rest of the data. 2076 */ 2077 get += cc << 1; 2078 if (get >= end) 2079 get -= com_rbuf_size << 1; 2080 cc = 0; 2081 } else { 2082 /* 2083 * Don't schedule any more receive processing 2084 * until the line discipline tells us there's 2085 * space available (through comhwiflow()). 2086 * Leave the rest of the data in the input 2087 * buffer. 2088 */ 2089 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 2090 } 2091 break; 2092 } 2093 get += 2; 2094 if (get >= end) 2095 get = sc->sc_rbuf; 2096 cc--; 2097 } 2098 2099 if (cc != scc) { 2100 sc->sc_rbget = get; 2101 mutex_spin_enter(&sc->sc_lock); 2102 2103 cc = sc->sc_rbavail += scc - cc; 2104 /* Buffers should be ok again, release possible block. */ 2105 if (cc >= sc->sc_r_lowat) { 2106 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2107 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2108 SET(sc->sc_ier, IER_ERXRDY); 2109 if (sc->sc_type == COM_TYPE_PXA2x0) 2110 SET(sc->sc_ier, IER_ERXTOUT); 2111 if (sc->sc_type == COM_TYPE_INGENIC || 2112 sc->sc_type == COM_TYPE_TEGRA) 2113 SET(sc->sc_ier, IER_ERXTOUT); 2114 2115 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 2116 sc->sc_ier); 2117 } 2118 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 2119 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2120 com_hwiflow(sc); 2121 } 2122 } 2123 mutex_spin_exit(&sc->sc_lock); 2124 } 2125 } 2126 2127 static inline void 2128 com_txsoft(struct com_softc *sc, struct tty *tp) 2129 { 2130 2131 CLR(tp->t_state, TS_BUSY); 2132 if (ISSET(tp->t_state, TS_FLUSH)) 2133 CLR(tp->t_state, TS_FLUSH); 2134 else 2135 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 2136 (*tp->t_linesw->l_start)(tp); 2137 } 2138 2139 static inline void 2140 com_stsoft(struct com_softc *sc, struct tty *tp) 2141 { 2142 u_char msr, delta; 2143 2144 mutex_spin_enter(&sc->sc_lock); 2145 msr = sc->sc_msr; 2146 delta = sc->sc_msr_delta; 2147 sc->sc_msr_delta = 0; 2148 mutex_spin_exit(&sc->sc_lock); 2149 2150 if (ISSET(delta, sc->sc_msr_dcd)) { 2151 /* 2152 * Inform the tty layer that carrier detect changed. 2153 */ 2154 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 2155 } 2156 2157 if (ISSET(delta, sc->sc_msr_cts)) { 2158 /* Block or unblock output according to flow control. */ 2159 if (ISSET(msr, sc->sc_msr_cts)) { 2160 sc->sc_tx_stopped = 0; 2161 (*tp->t_linesw->l_start)(tp); 2162 } else { 2163 sc->sc_tx_stopped = 1; 2164 } 2165 } 2166 2167 #ifdef COM_DEBUG 2168 if (com_debug) 2169 comstatus(sc, "com_stsoft"); 2170 #endif 2171 } 2172 2173 void 2174 comsoft(void *arg) 2175 { 2176 struct com_softc *sc = arg; 2177 struct tty *tp; 2178 2179 if (COM_ISALIVE(sc) == 0) 2180 return; 2181 2182 tp = sc->sc_tty; 2183 2184 if (sc->sc_rx_ready) { 2185 sc->sc_rx_ready = 0; 2186 com_rxsoft(sc, tp); 2187 } 2188 2189 if (sc->sc_st_check) { 2190 sc->sc_st_check = 0; 2191 com_stsoft(sc, tp); 2192 } 2193 2194 if (sc->sc_tx_done) { 2195 sc->sc_tx_done = 0; 2196 com_txsoft(sc, tp); 2197 } 2198 } 2199 2200 int 2201 comintr(void *arg) 2202 { 2203 struct com_softc *sc = arg; 2204 struct com_regs *regsp = &sc->sc_regs; 2205 2206 u_char *put, *end; 2207 u_int cc; 2208 u_char lsr, iir; 2209 2210 if (COM_ISALIVE(sc) == 0) 2211 return (0); 2212 2213 KASSERT(regsp != NULL); 2214 2215 mutex_spin_enter(&sc->sc_lock); 2216 iir = CSR_READ_1(regsp, COM_REG_IIR); 2217 2218 /* Handle ns16750-specific busy interrupt. */ 2219 if (sc->sc_type == COM_TYPE_16750 && 2220 (iir & IIR_BUSY) == IIR_BUSY) { 2221 for (int timeout = 10000; 2222 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--) 2223 if (timeout <= 0) { 2224 aprint_error_dev(sc->sc_dev, 2225 "timeout while waiting for BUSY interrupt " 2226 "acknowledge\n"); 2227 mutex_spin_exit(&sc->sc_lock); 2228 return (0); 2229 } 2230 2231 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2232 iir = CSR_READ_1(regsp, COM_REG_IIR); 2233 } 2234 2235 /* DesignWare APB UART BUSY interrupt */ 2236 if (sc->sc_type == COM_TYPE_DW_APB && 2237 (iir & IIR_BUSY) == IIR_BUSY) { 2238 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 2239 (void)CSR_READ_1(regsp, COM_REG_USR); 2240 } else if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) { 2241 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN); 2242 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2243 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2244 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2245 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2246 CSR_WRITE_1(regsp, COM_REG_HALT, 2247 HALT_CHCFG_EN | HALT_CHCFG_UD); 2248 for (int timeout = 10000000; 2249 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0; 2250 timeout--) { 2251 if (timeout <= 0) { 2252 aprint_error_dev(sc->sc_dev, 2253 "timeout while waiting for HALT " 2254 "update acknowledge 0x%x 0x%x\n", 2255 CSR_READ_1(regsp, COM_REG_HALT), 2256 CSR_READ_1(regsp, COM_REG_USR)); 2257 break; 2258 } 2259 } 2260 CSR_WRITE_1(regsp, COM_REG_HALT, 0); 2261 (void)CSR_READ_1(regsp, COM_REG_USR); 2262 } else { 2263 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB); 2264 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl); 2265 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh); 2266 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr); 2267 } 2268 } 2269 2270 end = sc->sc_ebuf; 2271 put = sc->sc_rbput; 2272 cc = sc->sc_rbavail; 2273 2274 if (ISSET(iir, IIR_NOPEND)) { 2275 if (ISSET(sc->sc_hwflags, COM_HW_BROKEN_ETXRDY)) 2276 goto do_tx; 2277 mutex_spin_exit(&sc->sc_lock); 2278 return (0); 2279 } 2280 2281 again: do { 2282 u_char msr, delta; 2283 2284 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2285 if (ISSET(lsr, LSR_BI)) { 2286 int cn_trapped = 0; /* see above: cn_trap() */ 2287 2288 cn_check_magic(sc->sc_tty->t_dev, 2289 CNC_BREAK, com_cnm_state); 2290 if (cn_trapped) 2291 continue; 2292 #if defined(KGDB) && !defined(DDB) 2293 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) { 2294 kgdb_connect(1); 2295 continue; 2296 } 2297 #endif 2298 } 2299 2300 if (sc->sc_type == COM_TYPE_BCMAUXUART && ISSET(iir, IIR_RXRDY)) 2301 lsr |= LSR_RXRDY; 2302 2303 if (ISSET(lsr, LSR_RCV_MASK) && 2304 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 2305 while (cc > 0) { 2306 int cn_trapped = 0; 2307 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA); 2308 put[1] = lsr; 2309 cn_check_magic(sc->sc_tty->t_dev, 2310 put[0], com_cnm_state); 2311 if (cn_trapped) 2312 goto next; 2313 put += 2; 2314 if (put >= end) 2315 put = sc->sc_rbuf; 2316 cc--; 2317 next: 2318 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2319 if (!ISSET(lsr, LSR_RCV_MASK)) 2320 break; 2321 } 2322 2323 /* 2324 * Current string of incoming characters ended because 2325 * no more data was available or we ran out of space. 2326 * Schedule a receive event if any data was received. 2327 * If we're out of space, turn off receive interrupts. 2328 */ 2329 sc->sc_rbput = put; 2330 sc->sc_rbavail = cc; 2331 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 2332 sc->sc_rx_ready = 1; 2333 2334 /* 2335 * See if we are in danger of overflowing a buffer. If 2336 * so, use hardware flow control to ease the pressure. 2337 */ 2338 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 2339 cc < sc->sc_r_hiwat) { 2340 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 2341 com_hwiflow(sc); 2342 } 2343 2344 /* 2345 * If we're out of space, disable receive interrupts 2346 * until the queue has drained a bit. 2347 */ 2348 if (!cc) { 2349 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 2350 switch (sc->sc_type) { 2351 case COM_TYPE_PXA2x0: 2352 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT); 2353 break; 2354 case COM_TYPE_INGENIC: 2355 case COM_TYPE_TEGRA: 2356 CLR(sc->sc_ier, 2357 IER_ERXRDY | IER_ERXTOUT); 2358 break; 2359 default: 2360 CLR(sc->sc_ier, IER_ERXRDY); 2361 break; 2362 } 2363 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2364 } 2365 } else { 2366 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) { 2367 (void) CSR_READ_1(regsp, COM_REG_RXDATA); 2368 continue; 2369 } 2370 } 2371 2372 msr = CSR_READ_1(regsp, COM_REG_MSR); 2373 delta = msr ^ sc->sc_msr; 2374 sc->sc_msr = msr; 2375 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) && 2376 (delta & MSR_DCD)) { 2377 mutex_spin_enter(&timecounter_lock); 2378 pps_capture(&sc->sc_pps_state); 2379 pps_event(&sc->sc_pps_state, 2380 (msr & MSR_DCD) ? 2381 PPS_CAPTUREASSERT : 2382 PPS_CAPTURECLEAR); 2383 mutex_spin_exit(&timecounter_lock); 2384 } 2385 2386 /* 2387 * Process normal status changes 2388 */ 2389 if (ISSET(delta, sc->sc_msr_mask)) { 2390 SET(sc->sc_msr_delta, delta); 2391 2392 /* 2393 * Stop output immediately if we lose the output 2394 * flow control signal or carrier detect. 2395 */ 2396 if (ISSET(~msr, sc->sc_msr_mask)) { 2397 sc->sc_tbc = 0; 2398 sc->sc_heldtbc = 0; 2399 #ifdef COM_DEBUG 2400 if (com_debug) 2401 comstatus(sc, "comintr "); 2402 #endif 2403 } 2404 2405 sc->sc_st_check = 1; 2406 } 2407 } while (!ISSET((iir = 2408 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) && 2409 /* 2410 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY 2411 * by IIR read, so we can't do this way: `process all interrupts, 2412 * then do TX if possible'. 2413 */ 2414 (iir & IIR_IMASK) != IIR_TXRDY); 2415 2416 do_tx: 2417 /* 2418 * Read LSR again, since there may be an interrupt between 2419 * the last LSR read and IIR read above. 2420 */ 2421 lsr = CSR_READ_1(regsp, COM_REG_LSR); 2422 2423 /* 2424 * See if data can be transmitted as well. 2425 * Schedule tx done event if no data left 2426 * and tty was marked busy. 2427 */ 2428 if (ISSET(lsr, LSR_TXRDY)) { 2429 /* 2430 * If we've delayed a parameter change, do it now, and restart 2431 * output. 2432 */ 2433 if (sc->sc_heldchange) { 2434 com_loadchannelregs(sc); 2435 sc->sc_heldchange = 0; 2436 sc->sc_tbc = sc->sc_heldtbc; 2437 sc->sc_heldtbc = 0; 2438 } 2439 2440 /* Output the next chunk of the contiguous buffer, if any. */ 2441 if (sc->sc_tbc > 0) { 2442 u_int n; 2443 2444 n = sc->sc_tbc; 2445 if (n > sc->sc_fifolen) 2446 n = sc->sc_fifolen; 2447 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n); 2448 sc->sc_tbc -= n; 2449 sc->sc_tba += n; 2450 } else { 2451 /* Disable transmit completion interrupts if necessary. */ 2452 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 2453 CLR(sc->sc_ier, IER_ETXRDY); 2454 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier); 2455 } 2456 if (sc->sc_tx_busy) { 2457 sc->sc_tx_busy = 0; 2458 sc->sc_tx_done = 1; 2459 } 2460 } 2461 } 2462 2463 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND)) 2464 goto again; 2465 2466 mutex_spin_exit(&sc->sc_lock); 2467 2468 /* Wake up the poller. */ 2469 if ((sc->sc_rx_ready | sc->sc_st_check | sc->sc_tx_done) != 0) 2470 softint_schedule(sc->sc_si); 2471 2472 #ifdef RND_COM 2473 rnd_add_uint32(&sc->rnd_source, iir | lsr); 2474 #endif 2475 2476 return (1); 2477 } 2478 2479 /* 2480 * The following functions are polled getc and putc routines, shared 2481 * by the console and kgdb glue. 2482 * 2483 * The read-ahead code is so that you can detect pending in-band 2484 * cn_magic in polled mode while doing output rather than having to 2485 * wait until the kernel decides it needs input. 2486 */ 2487 2488 #define MAX_READAHEAD 20 2489 static int com_readahead[MAX_READAHEAD]; 2490 static int com_readaheadcount = 0; 2491 2492 int 2493 com_common_getc(dev_t dev, struct com_regs *regsp) 2494 { 2495 int s = splserial(); 2496 u_char stat, c; 2497 2498 /* got a character from reading things earlier */ 2499 if (com_readaheadcount > 0) { 2500 int i; 2501 2502 c = com_readahead[0]; 2503 for (i = 1; i < com_readaheadcount; i++) { 2504 com_readahead[i-1] = com_readahead[i]; 2505 } 2506 com_readaheadcount--; 2507 splx(s); 2508 return (c); 2509 } 2510 2511 /* don't block until a character becomes available */ 2512 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2513 splx(s); 2514 return -1; 2515 } 2516 2517 c = CSR_READ_1(regsp, COM_REG_RXDATA); 2518 stat = CSR_READ_1(regsp, COM_REG_IIR); 2519 { 2520 int cn_trapped = 0; /* required by cn_trap, see above */ 2521 if (!db_active) 2522 cn_check_magic(dev, c, com_cnm_state); 2523 } 2524 splx(s); 2525 return (c); 2526 } 2527 2528 static void 2529 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead) 2530 { 2531 int s = splserial(); 2532 int cin, stat, timo; 2533 2534 if (with_readahead && com_readaheadcount < MAX_READAHEAD 2535 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) { 2536 int cn_trapped = 0; 2537 cin = CSR_READ_1(regsp, COM_REG_RXDATA); 2538 stat = CSR_READ_1(regsp, COM_REG_IIR); 2539 cn_check_magic(dev, cin, com_cnm_state); 2540 com_readahead[com_readaheadcount++] = cin; 2541 } 2542 2543 /* wait for any pending transmission to finish */ 2544 timo = 150000; 2545 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo) 2546 continue; 2547 2548 CSR_WRITE_1(regsp, COM_REG_TXDATA, c); 2549 COM_BARRIER(regsp, BR | BW); 2550 2551 splx(s); 2552 } 2553 2554 /* 2555 * Initialize UART for use as console or KGDB line. 2556 */ 2557 int 2558 cominit(struct com_regs *regsp, int rate, int frequency, int type, 2559 tcflag_t cflag) 2560 { 2561 2562 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0, 2563 ®sp->cr_ioh)) 2564 return (ENOMEM); /* ??? */ 2565 2566 if (type == COM_TYPE_OMAP) { 2567 /* disable before changing settings */ 2568 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE); 2569 } 2570 2571 rate = comspeed(rate, frequency, type); 2572 if (rate != -1) { 2573 if (type == COM_TYPE_AU1x00) { 2574 /* no EFR on alchemy */ 2575 CSR_WRITE_2(regsp, COM_REG_DLBL, rate); 2576 } else { 2577 if ((type != COM_TYPE_16550_NOERS) && 2578 (type != COM_TYPE_INGENIC)) { 2579 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS); 2580 CSR_WRITE_1(regsp, COM_REG_EFR, 0); 2581 } 2582 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB); 2583 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff); 2584 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8); 2585 } 2586 } 2587 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag)); 2588 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2589 2590 if (type == COM_TYPE_INGENIC) { 2591 CSR_WRITE_1(regsp, COM_REG_FIFO, 2592 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2593 FIFO_TRIGGER_1 | FIFO_UART_ON); 2594 } else { 2595 CSR_WRITE_1(regsp, COM_REG_FIFO, 2596 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 2597 FIFO_TRIGGER_1); 2598 } 2599 2600 if (type == COM_TYPE_OMAP) { 2601 /* setup the fifos. the FCR value is not used as long 2602 as SCR[6] and SCR[7] are 0, which they are at reset 2603 and we never touch the SCR register */ 2604 uint8_t rx_fifo_trig = 40; 2605 uint8_t tx_fifo_trig = 60; 2606 uint8_t rx_start = 8; 2607 uint8_t rx_halt = 60; 2608 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2); 2609 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2); 2610 2611 /* enable access to TCR & TLR */ 2612 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR); 2613 2614 /* write tcr and tlr values */ 2615 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value); 2616 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value); 2617 2618 /* disable access to TCR & TLR */ 2619 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS); 2620 2621 /* enable again, but mode is based on speed */ 2622 if (rate > 230400) { 2623 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X); 2624 } else { 2625 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X); 2626 } 2627 } 2628 2629 if (type == COM_TYPE_PXA2x0) 2630 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART); 2631 else 2632 CSR_WRITE_1(regsp, COM_REG_IER, 0); 2633 2634 return (0); 2635 } 2636 2637 int 2638 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type, 2639 tcflag_t cflag) 2640 { 2641 int res; 2642 2643 comcons_info.regs = *regsp; 2644 2645 res = cominit(&comcons_info.regs, rate, frequency, type, cflag); 2646 if (res) 2647 return (res); 2648 2649 cn_tab = &comcons; 2650 cn_init_magic(&com_cnm_state); 2651 cn_set_magic("\047\001"); /* default magic is BREAK */ 2652 2653 comcons_info.frequency = frequency; 2654 comcons_info.type = type; 2655 comcons_info.rate = rate; 2656 comcons_info.cflag = cflag; 2657 2658 return (0); 2659 } 2660 2661 int 2662 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency, 2663 int type, tcflag_t cflag) 2664 { 2665 struct com_regs regs; 2666 2667 /*XXX*/ 2668 bus_space_handle_t dummy_bsh; 2669 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 2670 2671 /* 2672 * dummy_bsh required because com_init_regs() wants it. A 2673 * real bus_space_handle will be filled in by cominit() later. 2674 * XXXJRT Detangle this mess eventually, plz. 2675 */ 2676 com_init_regs(®s, iot, dummy_bsh/*XXX*/, iobase); 2677 2678 return comcnattach1(®s, rate, frequency, type, cflag); 2679 } 2680 2681 static int 2682 comcnreattach(void) 2683 { 2684 return comcnattach1(&comcons_info.regs, comcons_info.rate, 2685 comcons_info.frequency, comcons_info.type, comcons_info.cflag); 2686 } 2687 2688 int 2689 comcngetc(dev_t dev) 2690 { 2691 2692 return (com_common_getc(dev, &comcons_info.regs)); 2693 } 2694 2695 /* 2696 * Console kernel output character routine. 2697 */ 2698 void 2699 comcnputc(dev_t dev, int c) 2700 { 2701 2702 com_common_putc(dev, &comcons_info.regs, c, cold); 2703 } 2704 2705 void 2706 comcnpollc(dev_t dev, int on) 2707 { 2708 2709 com_readaheadcount = 0; 2710 } 2711 2712 #ifdef KGDB 2713 int 2714 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type, 2715 tcflag_t cflag) 2716 { 2717 int res; 2718 2719 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) && 2720 regsp->cr_iobase == comcons_info.regs.cr_iobase) { 2721 #if !defined(DDB) 2722 return (EBUSY); /* cannot share with console */ 2723 #else 2724 comkgdbregs = *regsp; 2725 comkgdbregs.cr_ioh = comcons_info.regs.cr_ioh; 2726 #endif 2727 } else { 2728 comkgdbregs = *regsp; 2729 res = cominit(&comkgdbregs, rate, frequency, type, cflag); 2730 if (res) 2731 return (res); 2732 2733 /* 2734 * XXXfvdl this shouldn't be needed, but the cn_magic goo 2735 * expects this to be initialized 2736 */ 2737 cn_init_magic(&com_cnm_state); 2738 cn_set_magic("\047\001"); 2739 } 2740 2741 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL); 2742 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 2743 2744 return (0); 2745 } 2746 2747 int 2748 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate, 2749 int frequency, int type, tcflag_t cflag) 2750 { 2751 struct com_regs regs; 2752 2753 com_init_regs(®s, iot, (bus_space_handle_t)0/*XXX*/, iobase); 2754 2755 return com_kgdb_attach1(®s, rate, frequency, type, cflag); 2756 } 2757 2758 /* ARGSUSED */ 2759 int 2760 com_kgdb_getc(void *arg) 2761 { 2762 2763 return (com_common_getc(NODEV, &comkgdbregs)); 2764 } 2765 2766 /* ARGSUSED */ 2767 void 2768 com_kgdb_putc(void *arg, int c) 2769 { 2770 2771 com_common_putc(NODEV, &comkgdbregs, c, 0); 2772 } 2773 #endif /* KGDB */ 2774 2775 /* 2776 * helper function to identify the com ports used by 2777 * console or KGDB (and not yet autoconf attached) 2778 */ 2779 int 2780 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh) 2781 { 2782 bus_space_handle_t help; 2783 2784 if (!comconsattached && 2785 bus_space_is_equal(iot, comcons_info.regs.cr_iot) && 2786 iobase == comcons_info.regs.cr_iobase) 2787 help = comcons_info.regs.cr_ioh; 2788 #ifdef KGDB 2789 else if (!com_kgdb_attached && 2790 bus_space_is_equal(iot, comkgdbregs.cr_iot) && 2791 iobase == comkgdbregs.cr_iobase) 2792 help = comkgdbregs.cr_ioh; 2793 #endif 2794 else 2795 return (0); 2796 2797 if (ioh) 2798 *ioh = help; 2799 return (1); 2800 } 2801 2802 /* 2803 * this routine exists to serve as a shutdown hook for systems that 2804 * have firmware which doesn't interact properly with a com device in 2805 * FIFO mode. 2806 */ 2807 bool 2808 com_cleanup(device_t self, int how) 2809 { 2810 struct com_softc *sc = device_private(self); 2811 2812 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 2813 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0); 2814 2815 return true; 2816 } 2817 2818 bool 2819 com_suspend(device_t self, const pmf_qual_t *qual) 2820 { 2821 struct com_softc *sc = device_private(self); 2822 2823 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0); 2824 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR); 2825 2826 return true; 2827 } 2828 2829 bool 2830 com_resume(device_t self, const pmf_qual_t *qual) 2831 { 2832 struct com_softc *sc = device_private(self); 2833 2834 mutex_spin_enter(&sc->sc_lock); 2835 com_loadchannelregs(sc); 2836 mutex_spin_exit(&sc->sc_lock); 2837 2838 return true; 2839 } 2840
Indexes created Fri Sep 26 20:09:58 GMT 2025