com.c revision 1.76
1 /* $NetBSD: com.c,v 1.76 1996/03/17 00:53:10 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1993, 1994, 1995, 1996 5 * Charles M. Hannum. All rights reserved. 6 * Copyright (c) 1991 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)com.c 7.5 (Berkeley) 5/16/91 38 */ 39 40 /* 41 * COM driver, based on HP dca driver 42 * uses National Semiconductor NS16450/NS16550AF UART 43 */ 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/ioctl.h> 47 #include <sys/select.h> 48 #include <sys/tty.h> 49 #include <sys/proc.h> 50 #include <sys/user.h> 51 #include <sys/conf.h> 52 #include <sys/file.h> 53 #include <sys/uio.h> 54 #include <sys/kernel.h> 55 #include <sys/syslog.h> 56 #include <sys/types.h> 57 #include <sys/device.h> 58 59 #include <machine/cpu.h> 60 #include <machine/bus.h> 61 62 #include <dev/isa/isavar.h> 63 #include <dev/isa/comreg.h> 64 #include <dev/isa/comvar.h> 65 #include <dev/ic/ns16550reg.h> 66 #ifdef COM_HAYESP 67 #include <dev/ic/hayespreg.h> 68 #endif 69 #define com_lcr com_cfcr 70 71 #define COM_IBUFSIZE (2 * 512) 72 #define COM_IHIGHWATER ((3 * COM_IBUFSIZE) / 4) 73 74 struct com_softc { 75 struct device sc_dev; 76 void *sc_ih; 77 struct tty *sc_tty; 78 79 int sc_overflows; 80 int sc_floods; 81 int sc_errors; 82 83 int sc_halt; 84 85 int sc_iobase; 86 #ifdef COM_HAYESP 87 int sc_hayespbase; 88 #endif 89 90 bus_chipset_tag_t sc_bc; 91 bus_io_handle_t sc_ioh; 92 bus_io_handle_t sc_hayespioh; 93 94 u_char sc_hwflags; 95 #define COM_HW_NOIEN 0x01 96 #define COM_HW_FIFO 0x02 97 #define COM_HW_HAYESP 0x04 98 #define COM_HW_CONSOLE 0x40 99 u_char sc_swflags; 100 #define COM_SW_SOFTCAR 0x01 101 #define COM_SW_CLOCAL 0x02 102 #define COM_SW_CRTSCTS 0x04 103 #define COM_SW_MDMBUF 0x08 104 u_char sc_msr, sc_mcr, sc_lcr, sc_ier; 105 u_char sc_dtr; 106 107 u_char *sc_ibuf, *sc_ibufp, *sc_ibufhigh, *sc_ibufend; 108 u_char sc_ibufs[2][COM_IBUFSIZE]; 109 }; 110 111 int comprobe __P((struct device *, void *, void *)); 112 #ifdef COM_HAYESP 113 int comprobeHAYESP __P((bus_io_handle_t hayespioh, struct com_softc *sc)); 114 #endif 115 void comattach __P((struct device *, struct device *, void *)); 116 int comopen __P((dev_t, int, int, struct proc *)); 117 int comclose __P((dev_t, int, int, struct proc *)); 118 void comdiag __P((void *)); 119 int comintr __P((void *)); 120 void compoll __P((void *)); 121 int comparam __P((struct tty *, struct termios *)); 122 void comstart __P((struct tty *)); 123 124 /* 125 * XXX the following two cfattach structs should be different, and possibly 126 * XXX elsewhere. 127 */ 128 struct cfattach com_isa_ca = { 129 sizeof(struct com_softc), comprobe, comattach 130 }; 131 132 struct cfattach com_multi_ca = { 133 sizeof(struct com_softc), comprobe, comattach 134 }; 135 136 struct cfdriver com_cd = { 137 NULL, "com", DV_TTY 138 }; 139 140 int cominit __P((bus_chipset_tag_t, bus_io_handle_t, int)); 141 142 #ifdef COMCONSOLE 143 int comdefaultrate = CONSPEED; /* XXX why set default? */ 144 #else 145 int comdefaultrate = TTYDEF_SPEED; 146 #endif 147 int comconsaddr; 148 int comconsinit; 149 int comconsattached; 150 bus_chipset_tag_t comconsbc; 151 bus_io_handle_t comconsioh; 152 153 int commajor; 154 int comsopen = 0; 155 int comevents = 0; 156 157 #ifdef KGDB 158 #include <machine/remote-sl.h> 159 extern int kgdb_dev; 160 extern int kgdb_rate; 161 extern int kgdb_debug_init; 162 #endif 163 164 #define COMUNIT(x) (minor(x)) 165 166 /* Macros to clear/set/test flags. */ 167 #define SET(t, f) (t) |= (f) 168 #define CLR(t, f) (t) &= ~(f) 169 #define ISSET(t, f) ((t) & (f)) 170 171 int 172 comspeed(speed) 173 long speed; 174 { 175 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 176 177 int x, err; 178 179 if (speed == 0) 180 return 0; 181 if (speed < 0) 182 return -1; 183 x = divrnd((COM_FREQ / 16), speed); 184 if (x <= 0) 185 return -1; 186 err = divrnd((COM_FREQ / 16) * 1000, speed * x) - 1000; 187 if (err < 0) 188 err = -err; 189 if (err > COM_TOLERANCE) 190 return -1; 191 return x; 192 193 #undef divrnd(n, q) 194 } 195 196 int 197 comprobe1(bc, ioh, iobase) 198 bus_chipset_tag_t bc; 199 bus_io_handle_t ioh; 200 int iobase; 201 { 202 203 /* force access to id reg */ 204 bus_io_write_1(bc, ioh, com_lcr, 0); 205 bus_io_write_1(bc, ioh, com_iir, 0); 206 if (bus_io_read_1(bc, ioh, com_iir) & 0x38) 207 return 0; 208 209 return 1; 210 } 211 212 #ifdef COM_HAYESP 213 int 214 comprobeHAYESP(hayespioh, sc) 215 bus_io_handle_t hayespioh; 216 struct com_softc *sc; 217 { 218 char val, dips; 219 int combaselist[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; 220 bus_chipset_tag_t bc = sc->sc_bc; 221 222 /* 223 * Hayes ESP cards have two iobases. One is for compatibility with 224 * 16550 serial chips, and at the same ISA PC base addresses. The 225 * other is for ESP-specific enhanced features, and lies at a 226 * different addressing range entirely (0x140, 0x180, 0x280, or 0x300). 227 */ 228 229 /* Test for ESP signature */ 230 if ((bus_io_read_1(bc, hayespioh, 0) & 0xf3) == 0) 231 return 0; 232 233 /* 234 * ESP is present at ESP enhanced base address; unknown com port 235 */ 236 237 /* Get the dip-switch configurations */ 238 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETDIPS); 239 dips = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1); 240 241 /* Determine which com port this ESP card services: bits 0,1 of */ 242 /* dips is the port # (0-3); combaselist[val] is the com_iobase */ 243 if (sc->sc_iobase != combaselist[dips & 0x03]) 244 return 0; 245 246 printf(": ESP"); 247 248 /* Check ESP Self Test bits. */ 249 /* Check for ESP version 2.0: bits 4,5,6 == 010 */ 250 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETTEST); 251 val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1); /* Clear reg 1 */ 252 val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS2); 253 if ((val & 0x70) < 0x20) { 254 printf("-old (%o)", val & 0x70); 255 /* we do not support the necessary features */ 256 return 0; 257 } 258 259 /* Check for ability to emulate 16550: bit 8 == 1 */ 260 if ((dips & 0x80) == 0) { 261 printf(" slave"); 262 /* XXX Does slave really mean no 16550 support?? */ 263 return 0; 264 } 265 266 /* 267 * If we made it this far, we are a full-featured ESP v2.0 (or 268 * better), at the correct com port address. 269 */ 270 271 SET(sc->sc_hwflags, COM_HW_HAYESP); 272 printf(", 1024 byte fifo\n"); 273 return 1; 274 } 275 #endif 276 277 int 278 comprobe(parent, match, aux) 279 struct device *parent; 280 void *match, *aux; 281 { 282 struct cfdata *cf = match; 283 bus_chipset_tag_t bc; 284 bus_io_handle_t ioh; 285 int iobase, needioh; 286 int rv = 1; 287 288 /* 289 * XXX should be broken out into functions for isa probe and 290 * XXX for commulti probe, with a helper function that contains 291 * XXX most of the interesting stuff. 292 */ 293 if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) { 294 struct isa_attach_args *ia = aux; 295 296 bc = ia->ia_bc; 297 iobase = ia->ia_iobase; 298 needioh = 1; 299 } else { 300 struct commulti_attach_args *ca = aux; 301 302 if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != ca->ca_slave) 303 return (0); 304 305 bc = ca->ca_bc; 306 iobase = ca->ca_iobase; 307 ioh = ca->ca_ioh; 308 needioh = 0; 309 } 310 311 /* if it's in use as console, it's there. */ 312 if (iobase == comconsaddr && !comconsattached) 313 goto out; 314 315 if (needioh && bus_io_map(bc, iobase, COM_NPORTS, &ioh)) { 316 rv = 0; 317 goto out; 318 } 319 rv = comprobe1(bc, ioh, iobase); 320 if (needioh) 321 bus_io_unmap(bc, ioh, COM_NPORTS); 322 323 out: 324 if (rv && !strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) { 325 struct isa_attach_args *ia = aux; 326 327 ia->ia_iosize = COM_NPORTS; 328 ia->ia_msize = 0; 329 } 330 return (rv); 331 } 332 333 void 334 comattach(parent, self, aux) 335 struct device *parent, *self; 336 void *aux; 337 { 338 struct com_softc *sc = (void *)self; 339 struct cfdata *cf = sc->sc_dev.dv_cfdata; 340 int iobase, irq; 341 bus_chipset_tag_t bc; 342 bus_io_handle_t ioh; 343 struct tty *tp; 344 #ifdef COM_HAYESP 345 int hayesp_ports[] = { 0x140, 0x180, 0x280, 0x300, 0 }; 346 int *hayespp; 347 #endif 348 349 /* 350 * XXX should be broken out into functions for isa attach and 351 * XXX for commulti attach, with a helper function that contains 352 * XXX most of the interesting stuff. 353 */ 354 sc->sc_hwflags = 0; 355 sc->sc_swflags = 0; 356 if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) { 357 struct isa_attach_args *ia = aux; 358 359 /* 360 * We're living on an isa. 361 */ 362 iobase = ia->ia_iobase; 363 bc = ia->ia_bc; 364 if (iobase != comconsaddr) { 365 if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) 366 panic("comattach: io mapping failed"); 367 } else 368 ioh = comconsioh; 369 irq = ia->ia_irq; 370 } else { 371 struct commulti_attach_args *ca = aux; 372 373 /* 374 * We're living on a commulti. 375 */ 376 iobase = ca->ca_iobase; 377 bc = ca->ca_bc; 378 ioh = ca->ca_ioh; 379 irq = IRQUNK; 380 381 if (ca->ca_noien) 382 sc->sc_hwflags |= COM_HW_NOIEN; 383 } 384 385 sc->sc_bc = bc; 386 sc->sc_ioh = ioh; 387 sc->sc_iobase = iobase; 388 389 if (iobase == comconsaddr) { 390 comconsattached = 1; 391 392 /* 393 * Need to reset baud rate, etc. of next print so reset 394 * comconsinit. Also make sure console is always "hardwired". 395 */ 396 delay(1000); /* wait for output to finish */ 397 comconsinit = 0; 398 SET(sc->sc_hwflags, COM_HW_CONSOLE); 399 SET(sc->sc_swflags, COM_SW_SOFTCAR); 400 } 401 402 #ifdef COM_HAYESP 403 /* Look for a Hayes ESP board. */ 404 for (hayespp = hayesp_ports; *hayespp != 0; hayespp++) { 405 bus_io_handle_t hayespioh; 406 407 #define HAYESP_NPORTS 8 /* XXX XXX XXX ??? ??? ??? */ 408 if (bus_io_map(bc, *hayespp, HAYESP_NPORTS, &hayespioh)) 409 continue; 410 if (comprobeHAYESP(hayespioh, sc)) { 411 sc->sc_hayespbase = *hayespp; 412 sc->sc_hayespioh = hayespioh; 413 break; 414 } 415 bus_io_unmap(bc, hayespioh, HAYESP_NPORTS); 416 } 417 /* No ESP; look for other things. */ 418 if (*hayespp == 0) { 419 #endif 420 421 /* look for a NS 16550AF UART with FIFOs */ 422 bus_io_write_1(bc, ioh, com_fifo, 423 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 424 delay(100); 425 if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_FIFO_MASK) == IIR_FIFO_MASK) 426 if (ISSET(bus_io_read_1(bc, ioh, com_fifo), FIFO_TRIGGER_14) == FIFO_TRIGGER_14) { 427 SET(sc->sc_hwflags, COM_HW_FIFO); 428 printf(": ns16550a, working fifo\n"); 429 } else 430 printf(": ns16550, broken fifo\n"); 431 else 432 printf(": ns8250 or ns16450, no fifo\n"); 433 bus_io_write_1(bc, ioh, com_fifo, 0); 434 #ifdef COM_HAYESP 435 } 436 #endif 437 438 /* disable interrupts */ 439 bus_io_write_1(bc, ioh, com_ier, 0); 440 bus_io_write_1(bc, ioh, com_mcr, 0); 441 442 if (irq != IRQUNK) 443 sc->sc_ih = isa_intr_establish(irq, IST_EDGE, IPL_TTY, 444 comintr, sc); 445 446 #ifdef KGDB 447 if (kgdb_dev == makedev(commajor, unit)) { 448 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 449 kgdb_dev = -1; /* can't debug over console port */ 450 else { 451 (void) cominit(bc, ioh, kgdb_rate); 452 if (kgdb_debug_init) { 453 /* 454 * Print prefix of device name, 455 * let kgdb_connect print the rest. 456 */ 457 printf("%s: ", sc->sc_dev.dv_xname); 458 kgdb_connect(1); 459 } else 460 printf("%s: kgdb enabled\n", 461 sc->sc_dev.dv_xname); 462 } 463 } 464 #endif 465 466 /* XXX maybe move up some? */ 467 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 468 printf("%s: console\n", sc->sc_dev.dv_xname); 469 } 470 471 int 472 comopen(dev, flag, mode, p) 473 dev_t dev; 474 int flag, mode; 475 struct proc *p; 476 { 477 int unit = COMUNIT(dev); 478 struct com_softc *sc; 479 bus_chipset_tag_t bc; 480 bus_io_handle_t ioh; 481 struct tty *tp; 482 int s; 483 int error = 0; 484 485 if (unit >= com_cd.cd_ndevs) 486 return ENXIO; 487 sc = com_cd.cd_devs[unit]; 488 if (!sc) 489 return ENXIO; 490 491 if (!sc->sc_tty) 492 tp = sc->sc_tty = ttymalloc(); 493 else 494 tp = sc->sc_tty; 495 496 tp->t_oproc = comstart; 497 tp->t_param = comparam; 498 tp->t_dev = dev; 499 if (!ISSET(tp->t_state, TS_ISOPEN)) { 500 SET(tp->t_state, TS_WOPEN); 501 ttychars(tp); 502 tp->t_iflag = TTYDEF_IFLAG; 503 tp->t_oflag = TTYDEF_OFLAG; 504 tp->t_cflag = TTYDEF_CFLAG; 505 if (ISSET(sc->sc_swflags, COM_SW_CLOCAL)) 506 SET(tp->t_cflag, CLOCAL); 507 if (ISSET(sc->sc_swflags, COM_SW_CRTSCTS)) 508 SET(tp->t_cflag, CRTSCTS); 509 if (ISSET(sc->sc_swflags, COM_SW_MDMBUF)) 510 SET(tp->t_cflag, MDMBUF); 511 tp->t_lflag = TTYDEF_LFLAG; 512 tp->t_ispeed = tp->t_ospeed = comdefaultrate; 513 514 s = spltty(); 515 516 comparam(tp, &tp->t_termios); 517 ttsetwater(tp); 518 519 if (comsopen++ == 0) 520 timeout(compoll, NULL, 1); 521 522 sc->sc_ibufp = sc->sc_ibuf = sc->sc_ibufs[0]; 523 sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER; 524 sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE; 525 526 bc = sc->sc_bc; 527 ioh = sc->sc_ioh; 528 #ifdef COM_HAYESP 529 /* Setup the ESP board */ 530 if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) { 531 bus_io_handle_t hayespioh = sc->sc_hayespioh; 532 533 bus_io_write_1(bc, ioh, com_fifo, 534 FIFO_DMA_MODE|FIFO_ENABLE| 535 FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_8); 536 537 /* Set 16550 compatibility mode */ 538 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETMODE); 539 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 540 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 541 HAYESP_MODE_SCALE); 542 543 /* Set RTS/CTS flow control */ 544 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETFLOWTYPE); 545 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_RTS); 546 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_CTS); 547 548 /* Set flow control levels */ 549 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETRXFLOW); 550 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 551 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 552 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 553 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 554 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 555 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 556 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 557 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 558 } else 559 #endif 560 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 561 /* Set the FIFO threshold based on the receive speed. */ 562 bus_io_write_1(bc, ioh, com_fifo, 563 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 564 (tp->t_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8)); 565 /* flush any pending I/O */ 566 while (ISSET(bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY)) 567 (void) bus_io_read_1(bc, ioh, com_data); 568 /* you turn me on, baby */ 569 sc->sc_mcr = MCR_DTR | MCR_RTS; 570 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 571 SET(sc->sc_mcr, MCR_IENABLE); 572 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 573 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 574 bus_io_write_1(bc, ioh, com_ier, sc->sc_ier); 575 576 sc->sc_msr = bus_io_read_1(bc, ioh, com_msr); 577 if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR) || 578 ISSET(sc->sc_msr, MSR_DCD) || ISSET(tp->t_cflag, MDMBUF)) 579 SET(tp->t_state, TS_CARR_ON); 580 else 581 CLR(tp->t_state, TS_CARR_ON); 582 } else if (ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0) 583 return EBUSY; 584 else 585 s = spltty(); 586 587 /* wait for carrier if necessary */ 588 if (!ISSET(flag, O_NONBLOCK)) 589 while (!ISSET(tp->t_cflag, CLOCAL) && 590 !ISSET(tp->t_state, TS_CARR_ON)) { 591 SET(tp->t_state, TS_WOPEN); 592 error = ttysleep(tp, &tp->t_rawq, TTIPRI | PCATCH, 593 ttopen, 0); 594 if (error) { 595 /* XXX should turn off chip if we're the 596 only waiter */ 597 splx(s); 598 return error; 599 } 600 } 601 splx(s); 602 603 return (*linesw[tp->t_line].l_open)(dev, tp); 604 } 605 606 int 607 comclose(dev, flag, mode, p) 608 dev_t dev; 609 int flag, mode; 610 struct proc *p; 611 { 612 int unit = COMUNIT(dev); 613 struct com_softc *sc = com_cd.cd_devs[unit]; 614 struct tty *tp = sc->sc_tty; 615 bus_chipset_tag_t bc = sc->sc_bc; 616 bus_io_handle_t ioh = sc->sc_ioh; 617 int s; 618 619 /* XXX This is for cons.c. */ 620 if (!ISSET(tp->t_state, TS_ISOPEN)) 621 return 0; 622 623 (*linesw[tp->t_line].l_close)(tp, flag); 624 s = spltty(); 625 CLR(sc->sc_lcr, LCR_SBREAK); 626 bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr); 627 bus_io_write_1(bc, ioh, com_ier, 0); 628 if (ISSET(tp->t_cflag, HUPCL) && 629 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) { 630 /* XXX perhaps only clear DTR */ 631 bus_io_write_1(bc, ioh, com_mcr, 0); 632 } 633 CLR(tp->t_state, TS_BUSY | TS_FLUSH); 634 if (--comsopen == 0) 635 untimeout(compoll, NULL); 636 splx(s); 637 ttyclose(tp); 638 #ifdef notyet /* XXXX */ 639 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 640 ttyfree(tp); 641 sc->sc_tty = 0; 642 } 643 #endif 644 return 0; 645 } 646 647 int 648 comread(dev, uio, flag) 649 dev_t dev; 650 struct uio *uio; 651 int flag; 652 { 653 struct com_softc *sc = com_cd.cd_devs[COMUNIT(dev)]; 654 struct tty *tp = sc->sc_tty; 655 656 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 657 } 658 659 int 660 comwrite(dev, uio, flag) 661 dev_t dev; 662 struct uio *uio; 663 int flag; 664 { 665 struct com_softc *sc = com_cd.cd_devs[COMUNIT(dev)]; 666 struct tty *tp = sc->sc_tty; 667 668 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 669 } 670 671 struct tty * 672 comtty(dev) 673 dev_t dev; 674 { 675 struct com_softc *sc = com_cd.cd_devs[COMUNIT(dev)]; 676 struct tty *tp = sc->sc_tty; 677 678 return (tp); 679 } 680 681 static u_char 682 tiocm_xxx2mcr(data) 683 int data; 684 { 685 u_char m = 0; 686 687 if (ISSET(data, TIOCM_DTR)) 688 SET(m, MCR_DTR); 689 if (ISSET(data, TIOCM_RTS)) 690 SET(m, MCR_RTS); 691 return m; 692 } 693 694 int 695 comioctl(dev, cmd, data, flag, p) 696 dev_t dev; 697 u_long cmd; 698 caddr_t data; 699 int flag; 700 struct proc *p; 701 { 702 int unit = COMUNIT(dev); 703 struct com_softc *sc = com_cd.cd_devs[unit]; 704 struct tty *tp = sc->sc_tty; 705 bus_chipset_tag_t bc = sc->sc_bc; 706 bus_io_handle_t ioh = sc->sc_ioh; 707 int error; 708 709 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 710 if (error >= 0) 711 return error; 712 error = ttioctl(tp, cmd, data, flag, p); 713 if (error >= 0) 714 return error; 715 716 switch (cmd) { 717 case TIOCSBRK: 718 SET(sc->sc_lcr, LCR_SBREAK); 719 bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr); 720 break; 721 case TIOCCBRK: 722 CLR(sc->sc_lcr, LCR_SBREAK); 723 bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr); 724 break; 725 case TIOCSDTR: 726 SET(sc->sc_mcr, sc->sc_dtr); 727 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 728 break; 729 case TIOCCDTR: 730 CLR(sc->sc_mcr, sc->sc_dtr); 731 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 732 break; 733 case TIOCMSET: 734 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 735 case TIOCMBIS: 736 SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data)); 737 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 738 break; 739 case TIOCMBIC: 740 CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data)); 741 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 742 break; 743 case TIOCMGET: { 744 u_char m; 745 int bits = 0; 746 747 m = sc->sc_mcr; 748 if (ISSET(m, MCR_DTR)) 749 SET(bits, TIOCM_DTR); 750 if (ISSET(m, MCR_RTS)) 751 SET(bits, TIOCM_RTS); 752 m = sc->sc_msr; 753 if (ISSET(m, MSR_DCD)) 754 SET(bits, TIOCM_CD); 755 if (ISSET(m, MSR_CTS)) 756 SET(bits, TIOCM_CTS); 757 if (ISSET(m, MSR_DSR)) 758 SET(bits, TIOCM_DSR); 759 if (ISSET(m, MSR_RI | MSR_TERI)) 760 SET(bits, TIOCM_RI); 761 if (bus_io_read_1(bc, ioh, com_ier)) 762 SET(bits, TIOCM_LE); 763 *(int *)data = bits; 764 break; 765 } 766 case TIOCGFLAGS: { 767 int driverbits, userbits = 0; 768 769 driverbits = sc->sc_swflags; 770 if (ISSET(driverbits, COM_SW_SOFTCAR)) 771 SET(userbits, TIOCFLAG_SOFTCAR); 772 if (ISSET(driverbits, COM_SW_CLOCAL)) 773 SET(userbits, TIOCFLAG_CLOCAL); 774 if (ISSET(driverbits, COM_SW_CRTSCTS)) 775 SET(userbits, TIOCFLAG_CRTSCTS); 776 if (ISSET(driverbits, COM_SW_MDMBUF)) 777 SET(userbits, TIOCFLAG_MDMBUF); 778 779 *(int *)data = userbits; 780 break; 781 } 782 case TIOCSFLAGS: { 783 int userbits, driverbits = 0; 784 785 error = suser(p->p_ucred, &p->p_acflag); 786 if (error != 0) 787 return(EPERM); 788 789 userbits = *(int *)data; 790 if (ISSET(userbits, TIOCFLAG_SOFTCAR) || 791 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 792 SET(driverbits, COM_SW_SOFTCAR); 793 if (ISSET(userbits, TIOCFLAG_CLOCAL)) 794 SET(driverbits, COM_SW_CLOCAL); 795 if (ISSET(userbits, TIOCFLAG_CRTSCTS)) 796 SET(driverbits, COM_SW_CRTSCTS); 797 if (ISSET(userbits, TIOCFLAG_MDMBUF)) 798 SET(driverbits, COM_SW_MDMBUF); 799 800 sc->sc_swflags = driverbits; 801 break; 802 } 803 default: 804 return ENOTTY; 805 } 806 807 return 0; 808 } 809 810 int 811 comparam(tp, t) 812 struct tty *tp; 813 struct termios *t; 814 { 815 struct com_softc *sc = com_cd.cd_devs[COMUNIT(tp->t_dev)]; 816 bus_chipset_tag_t bc = sc->sc_bc; 817 bus_io_handle_t ioh = sc->sc_ioh; 818 int ospeed = comspeed(t->c_ospeed); 819 u_char lcr; 820 tcflag_t oldcflag; 821 int s; 822 823 /* check requested parameters */ 824 if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed)) 825 return EINVAL; 826 827 lcr = ISSET(sc->sc_lcr, LCR_SBREAK); 828 829 switch (ISSET(t->c_cflag, CSIZE)) { 830 case CS5: 831 SET(lcr, LCR_5BITS); 832 break; 833 case CS6: 834 SET(lcr, LCR_6BITS); 835 break; 836 case CS7: 837 SET(lcr, LCR_7BITS); 838 break; 839 case CS8: 840 SET(lcr, LCR_8BITS); 841 break; 842 } 843 if (ISSET(t->c_cflag, PARENB)) { 844 SET(lcr, LCR_PENAB); 845 if (!ISSET(t->c_cflag, PARODD)) 846 SET(lcr, LCR_PEVEN); 847 } 848 if (ISSET(t->c_cflag, CSTOPB)) 849 SET(lcr, LCR_STOPB); 850 851 sc->sc_lcr = lcr; 852 853 s = spltty(); 854 855 if (ospeed == 0) { 856 CLR(sc->sc_mcr, MCR_DTR); 857 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 858 } 859 860 /* 861 * Set the FIFO threshold based on the receive speed, if we are 862 * changing it. 863 */ 864 #if 1 865 if (tp->t_ispeed != t->c_ispeed) { 866 #else 867 if (1) { 868 #endif 869 if (ospeed != 0) { 870 /* 871 * Make sure the transmit FIFO is empty before 872 * proceeding. If we don't do this, some revisions 873 * of the UART will hang. Interestingly enough, 874 * even if we do this will the last character is 875 * still being pushed out, they don't hang. This 876 * seems good enough. 877 */ 878 while (ISSET(tp->t_state, TS_BUSY)) { 879 int error; 880 881 ++sc->sc_halt; 882 error = ttysleep(tp, &tp->t_outq, 883 TTOPRI | PCATCH, "comprm", 0); 884 --sc->sc_halt; 885 if (error) { 886 splx(s); 887 comstart(tp); 888 return (error); 889 } 890 } 891 892 bus_io_write_1(bc, ioh, com_lcr, lcr | LCR_DLAB); 893 bus_io_write_1(bc, ioh, com_dlbl, ospeed); 894 bus_io_write_1(bc, ioh, com_dlbh, ospeed >> 8); 895 bus_io_write_1(bc, ioh, com_lcr, lcr); 896 SET(sc->sc_mcr, MCR_DTR); 897 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 898 } else 899 bus_io_write_1(bc, ioh, com_lcr, lcr); 900 901 if (!ISSET(sc->sc_hwflags, COM_HW_HAYESP) && 902 ISSET(sc->sc_hwflags, COM_HW_FIFO)) 903 bus_io_write_1(bc, ioh, com_fifo, 904 FIFO_ENABLE | 905 (t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8)); 906 } else 907 bus_io_write_1(bc, ioh, com_lcr, lcr); 908 909 /* When not using CRTSCTS, RTS follows DTR. */ 910 if (!ISSET(t->c_cflag, CRTSCTS)) { 911 if (ISSET(sc->sc_mcr, MCR_DTR)) { 912 if (!ISSET(sc->sc_mcr, MCR_RTS)) { 913 SET(sc->sc_mcr, MCR_RTS); 914 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 915 } 916 } else { 917 if (ISSET(sc->sc_mcr, MCR_RTS)) { 918 CLR(sc->sc_mcr, MCR_RTS); 919 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 920 } 921 } 922 sc->sc_dtr = MCR_DTR | MCR_RTS; 923 } else 924 sc->sc_dtr = MCR_DTR; 925 926 /* and copy to tty */ 927 tp->t_ispeed = t->c_ispeed; 928 tp->t_ospeed = t->c_ospeed; 929 oldcflag = tp->t_cflag; 930 tp->t_cflag = t->c_cflag; 931 932 /* 933 * If DCD is off and MDMBUF is changed, ask the tty layer if we should 934 * stop the device. 935 */ 936 if (!ISSET(sc->sc_msr, MSR_DCD) && 937 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR) && 938 ISSET(oldcflag, MDMBUF) != ISSET(tp->t_cflag, MDMBUF) && 939 (*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 940 CLR(sc->sc_mcr, sc->sc_dtr); 941 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 942 } 943 944 /* Just to be sure... */ 945 splx(s); 946 comstart(tp); 947 return 0; 948 } 949 950 void 951 comstart(tp) 952 struct tty *tp; 953 { 954 struct com_softc *sc = com_cd.cd_devs[COMUNIT(tp->t_dev)]; 955 bus_chipset_tag_t bc = sc->sc_bc; 956 bus_io_handle_t ioh = sc->sc_ioh; 957 int s; 958 959 s = spltty(); 960 if (ISSET(tp->t_state, TS_BUSY)) 961 goto out; 962 if (ISSET(tp->t_state, TS_TIMEOUT | TS_TTSTOP) || 963 sc->sc_halt > 0) 964 goto stopped; 965 if (ISSET(tp->t_cflag, CRTSCTS) && !ISSET(sc->sc_msr, MSR_CTS)) 966 goto stopped; 967 if (tp->t_outq.c_cc <= tp->t_lowat) { 968 if (ISSET(tp->t_state, TS_ASLEEP)) { 969 CLR(tp->t_state, TS_ASLEEP); 970 wakeup(&tp->t_outq); 971 } 972 if (tp->t_outq.c_cc == 0) 973 goto stopped; 974 selwakeup(&tp->t_wsel); 975 } 976 SET(tp->t_state, TS_BUSY); 977 978 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 979 SET(sc->sc_ier, IER_ETXRDY); 980 bus_io_write_1(bc, ioh, com_ier, sc->sc_ier); 981 } 982 #ifdef COM_HAYESP 983 if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) { 984 u_char buffer[1024], *cp = buffer; 985 int n = q_to_b(&tp->t_outq, cp, sizeof buffer); 986 do 987 bus_io_write_1(bc, ioh, com_data, *cp++); 988 while (--n); 989 } 990 else 991 #endif 992 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 993 u_char buffer[16], *cp = buffer; 994 int n = q_to_b(&tp->t_outq, cp, sizeof buffer); 995 do { 996 bus_io_write_1(bc, ioh, com_data, *cp++); 997 } while (--n); 998 } else 999 bus_io_write_1(bc, ioh, com_data, getc(&tp->t_outq)); 1000 out: 1001 splx(s); 1002 return; 1003 stopped: 1004 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 1005 CLR(sc->sc_ier, IER_ETXRDY); 1006 bus_io_write_1(bc, ioh, com_ier, sc->sc_ier); 1007 } 1008 splx(s); 1009 } 1010 1011 /* 1012 * Stop output on a line. 1013 */ 1014 void 1015 comstop(tp, flag) 1016 struct tty *tp; 1017 { 1018 int s; 1019 1020 s = spltty(); 1021 if (ISSET(tp->t_state, TS_BUSY)) 1022 if (!ISSET(tp->t_state, TS_TTSTOP)) 1023 SET(tp->t_state, TS_FLUSH); 1024 splx(s); 1025 } 1026 1027 void 1028 comdiag(arg) 1029 void *arg; 1030 { 1031 struct com_softc *sc = arg; 1032 int overflows, floods; 1033 int s; 1034 1035 s = spltty(); 1036 sc->sc_errors = 0; 1037 overflows = sc->sc_overflows; 1038 sc->sc_overflows = 0; 1039 floods = sc->sc_floods; 1040 sc->sc_floods = 0; 1041 splx(s); 1042 1043 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf overflow%s\n", 1044 sc->sc_dev.dv_xname, 1045 overflows, overflows == 1 ? "" : "s", 1046 floods, floods == 1 ? "" : "s"); 1047 } 1048 1049 void 1050 compoll(arg) 1051 void *arg; 1052 { 1053 int unit; 1054 struct com_softc *sc; 1055 struct tty *tp; 1056 register u_char *ibufp; 1057 u_char *ibufend; 1058 register int c; 1059 int s; 1060 static int lsrmap[8] = { 1061 0, TTY_PE, 1062 TTY_FE, TTY_PE|TTY_FE, 1063 TTY_FE, TTY_PE|TTY_FE, 1064 TTY_FE, TTY_PE|TTY_FE 1065 }; 1066 1067 s = spltty(); 1068 if (comevents == 0) { 1069 splx(s); 1070 goto out; 1071 } 1072 comevents = 0; 1073 splx(s); 1074 1075 for (unit = 0; unit < com_cd.cd_ndevs; unit++) { 1076 sc = com_cd.cd_devs[unit]; 1077 if (sc == 0 || sc->sc_ibufp == sc->sc_ibuf) 1078 continue; 1079 1080 tp = sc->sc_tty; 1081 1082 s = spltty(); 1083 1084 ibufp = sc->sc_ibuf; 1085 ibufend = sc->sc_ibufp; 1086 1087 if (ibufp == ibufend) { 1088 splx(s); 1089 continue; 1090 } 1091 1092 sc->sc_ibufp = sc->sc_ibuf = (ibufp == sc->sc_ibufs[0]) ? 1093 sc->sc_ibufs[1] : sc->sc_ibufs[0]; 1094 sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER; 1095 sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE; 1096 1097 if (tp == 0 || !ISSET(tp->t_state, TS_ISOPEN)) { 1098 splx(s); 1099 continue; 1100 } 1101 1102 if (ISSET(tp->t_cflag, CRTSCTS) && 1103 !ISSET(sc->sc_mcr, MCR_RTS)) { 1104 /* XXX */ 1105 SET(sc->sc_mcr, MCR_RTS); 1106 bus_io_write_1(sc->sc_bc, sc->sc_ioh, com_mcr, 1107 sc->sc_mcr); 1108 } 1109 1110 splx(s); 1111 1112 while (ibufp < ibufend) { 1113 c = *ibufp++; 1114 if (*ibufp & LSR_OE) { 1115 sc->sc_overflows++; 1116 if (sc->sc_errors++ == 0) 1117 timeout(comdiag, sc, 60 * hz); 1118 } 1119 /* This is ugly, but fast. */ 1120 c |= lsrmap[(*ibufp++ & (LSR_BI|LSR_FE|LSR_PE)) >> 2]; 1121 (*linesw[tp->t_line].l_rint)(c, tp); 1122 } 1123 } 1124 1125 out: 1126 timeout(compoll, NULL, 1); 1127 } 1128 1129 int 1130 comintr(arg) 1131 void *arg; 1132 { 1133 struct com_softc *sc = arg; 1134 bus_chipset_tag_t bc = sc->sc_bc; 1135 bus_io_handle_t ioh = sc->sc_ioh; 1136 struct tty *tp; 1137 u_char lsr, data, msr, delta; 1138 #ifdef COM_DEBUG 1139 int n; 1140 struct { 1141 u_char iir, lsr, msr; 1142 } iter[32]; 1143 #endif 1144 1145 #ifdef COM_DEBUG 1146 n = 0; 1147 if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND)) 1148 return (0); 1149 #else 1150 if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND)) 1151 return (0); 1152 #endif 1153 1154 tp = sc->sc_tty; 1155 1156 for (;;) { 1157 #ifdef COM_DEBUG 1158 iter[n].lsr = 1159 #endif 1160 lsr = bus_io_read_1(bc, ioh, com_lsr); 1161 1162 if (ISSET(lsr, LSR_RXRDY)) { 1163 register u_char *p = sc->sc_ibufp; 1164 1165 comevents = 1; 1166 do { 1167 data = bus_io_read_1(bc, ioh, com_data); 1168 if (ISSET(lsr, LSR_BI)) { 1169 #ifdef notdef 1170 printf("break %02x %02x %02x %02x\n", 1171 sc->sc_msr, sc->sc_mcr, sc->sc_lcr, 1172 sc->sc_dtr); 1173 #endif 1174 #ifdef DDB 1175 if (ISSET(sc->sc_hwflags, 1176 COM_HW_CONSOLE)) { 1177 Debugger(); 1178 goto next; 1179 } 1180 #endif 1181 } 1182 if (p >= sc->sc_ibufend) { 1183 sc->sc_floods++; 1184 if (sc->sc_errors++ == 0) 1185 timeout(comdiag, sc, 60 * hz); 1186 } else { 1187 *p++ = data; 1188 *p++ = lsr; 1189 if (p == sc->sc_ibufhigh && 1190 ISSET(tp->t_cflag, CRTSCTS)) { 1191 /* XXX */ 1192 CLR(sc->sc_mcr, MCR_RTS); 1193 bus_io_write_1(bc, ioh, com_mcr, 1194 sc->sc_mcr); 1195 } 1196 } 1197 next: 1198 #ifdef COM_DEBUG 1199 if (++n >= 32) 1200 goto ohfudge; 1201 iter[n].lsr = 1202 #endif 1203 lsr = bus_io_read_1(bc, ioh, com_lsr); 1204 } while (ISSET(lsr, LSR_RXRDY)); 1205 1206 sc->sc_ibufp = p; 1207 } 1208 #ifdef COM_DEBUG 1209 else if (ISSET(lsr, LSR_BI|LSR_FE|LSR_PE|LSR_OE)) 1210 printf("weird lsr %02x\n", lsr); 1211 #endif 1212 1213 #ifdef COM_DEBUG 1214 iter[n].msr = 1215 #endif 1216 msr = bus_io_read_1(bc, ioh, com_msr); 1217 1218 if (msr != sc->sc_msr) { 1219 delta = msr ^ sc->sc_msr; 1220 sc->sc_msr = msr; 1221 if (ISSET(delta, MSR_DCD) && 1222 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR) && 1223 (*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)) == 0) { 1224 CLR(sc->sc_mcr, sc->sc_dtr); 1225 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 1226 } 1227 if (ISSET(delta & msr, MSR_CTS) && 1228 ISSET(tp->t_cflag, CRTSCTS)) { 1229 /* the line is up and we want to do rts/cts flow control */ 1230 (*linesw[tp->t_line].l_start)(tp); 1231 } 1232 } 1233 1234 if (ISSET(lsr, LSR_TXRDY) && ISSET(tp->t_state, TS_BUSY)) { 1235 CLR(tp->t_state, TS_BUSY | TS_FLUSH); 1236 if (sc->sc_halt > 0) 1237 wakeup(&tp->t_outq); 1238 (*linesw[tp->t_line].l_start)(tp); 1239 } 1240 1241 #ifdef COM_DEBUG 1242 if (++n >= 32) 1243 goto ohfudge; 1244 if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND)) 1245 return (1); 1246 #else 1247 if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND)) 1248 return (1); 1249 #endif 1250 } 1251 #ifdef COM_DEBUG 1252 ohfudge: 1253 printf("comintr: too many iterations"); 1254 for (n = 0; n < 32; n++) { 1255 if ((n % 4) == 0) 1256 printf("\ncomintr: iter[%02d]", n); 1257 printf(" %02x %02x %02x", iter[n].iir, iter[n].lsr, iter[n].msr); 1258 } 1259 printf("\n"); 1260 printf("comintr: msr %02x mcr %02x lcr %02x ier %02x\n", 1261 sc->sc_msr, sc->sc_mcr, sc->sc_lcr, sc->sc_ier); 1262 printf("comintr: state %08x cc %d\n", sc->sc_tty->t_state, 1263 sc->sc_tty->t_outq.c_cc); 1264 #endif 1265 } 1266 1267 /* 1268 * Following are all routines needed for COM to act as console 1269 */ 1270 #include <dev/cons.h> 1271 1272 void 1273 comcnprobe(cp) 1274 struct consdev *cp; 1275 { 1276 bus_chipset_tag_t bc; 1277 bus_io_handle_t ioh; 1278 int found; 1279 1280 #if 0 1281 XXX NEEDS TO BE FIXED XXX 1282 bc = ???; 1283 #endif 1284 if (bus_io_map(bc, CONADDR, COM_NPORTS, &ioh)) { 1285 cp->cn_pri = CN_DEAD; 1286 return; 1287 } 1288 found = comprobe1(bc, ioh, CONADDR); 1289 bus_io_unmap(bc, ioh, COM_NPORTS); 1290 if (!found) { 1291 cp->cn_pri = CN_DEAD; 1292 return; 1293 } 1294 1295 /* locate the major number */ 1296 for (commajor = 0; commajor < nchrdev; commajor++) 1297 if (cdevsw[commajor].d_open == comopen) 1298 break; 1299 1300 /* initialize required fields */ 1301 cp->cn_dev = makedev(commajor, CONUNIT); 1302 #ifdef COMCONSOLE 1303 cp->cn_pri = CN_REMOTE; /* Force a serial port console */ 1304 #else 1305 cp->cn_pri = CN_NORMAL; 1306 #endif 1307 } 1308 1309 void 1310 comcninit(cp) 1311 struct consdev *cp; 1312 { 1313 1314 #if 0 1315 XXX NEEDS TO BE FIXED XXX 1316 comconsbc = ???; 1317 #endif 1318 if (bus_io_map(comconsbc, CONADDR, COM_NPORTS, &comconsioh)) 1319 panic("comcninit: mapping failed"); 1320 1321 cominit(comconsbc, comconsioh, comdefaultrate); 1322 comconsaddr = CONADDR; 1323 comconsinit = 0; 1324 } 1325 1326 cominit(bc, ioh, rate) 1327 bus_chipset_tag_t bc; 1328 bus_io_handle_t ioh; 1329 int rate; 1330 { 1331 int s = splhigh(); 1332 u_char stat; 1333 1334 bus_io_write_1(bc, ioh, com_lcr, LCR_DLAB); 1335 rate = comspeed(comdefaultrate); 1336 bus_io_write_1(bc, ioh, com_dlbl, rate); 1337 bus_io_write_1(bc, ioh, com_dlbh, rate >> 8); 1338 bus_io_write_1(bc, ioh, com_lcr, LCR_8BITS); 1339 bus_io_write_1(bc, ioh, com_ier, IER_ERXRDY | IER_ETXRDY); 1340 bus_io_write_1(bc, ioh, com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_4); 1341 stat = bus_io_read_1(bc, ioh, com_iir); 1342 splx(s); 1343 } 1344 1345 comcngetc(dev) 1346 dev_t dev; 1347 { 1348 int s = splhigh(); 1349 bus_chipset_tag_t bc = comconsbc; 1350 bus_io_handle_t ioh = comconsioh; 1351 u_char stat, c; 1352 1353 while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY)) 1354 ; 1355 c = bus_io_read_1(bc, ioh, com_data); 1356 stat = bus_io_read_1(bc, ioh, com_iir); 1357 splx(s); 1358 return c; 1359 } 1360 1361 /* 1362 * Console kernel output character routine. 1363 */ 1364 void 1365 comcnputc(dev, c) 1366 dev_t dev; 1367 int c; 1368 { 1369 int s = splhigh(); 1370 bus_chipset_tag_t bc = comconsbc; 1371 bus_io_handle_t ioh = comconsioh; 1372 u_char stat; 1373 register int timo; 1374 1375 #ifdef KGDB 1376 if (dev != kgdb_dev) 1377 #endif 1378 if (comconsinit == 0) { 1379 (void) cominit(bc, ioh, comdefaultrate); 1380 comconsinit = 1; 1381 } 1382 /* wait for any pending transmission to finish */ 1383 timo = 50000; 1384 while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo) 1385 ; 1386 bus_io_write_1(bc, ioh, com_data, c); 1387 /* wait for this transmission to complete */ 1388 timo = 1500000; 1389 while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo) 1390 ; 1391 /* clear any interrupts generated by this transmission */ 1392 stat = bus_io_read_1(bc, ioh, com_iir); 1393 splx(s); 1394 } 1395 1396 void 1397 comcnpollc(dev, on) 1398 dev_t dev; 1399 int on; 1400 { 1401 1402 } 1403
Indexes created Thu Sep 25 16:09:42 GMT 2025