com.c revision 1.80
1 /* $NetBSD: com.c,v 1.80 1996/04/29 20:03:00 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1993, 1994, 1995, 1996 5 * Charles M. Hannum. All rights reserved. 6 * Copyright (c) 1991 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)com.c 7.5 (Berkeley) 5/16/91 38 */ 39 40 /* 41 * COM driver, based on HP dca driver 42 * uses National Semiconductor NS16450/NS16550AF UART 43 */ 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/ioctl.h> 47 #include <sys/select.h> 48 #include <sys/tty.h> 49 #include <sys/proc.h> 50 #include <sys/user.h> 51 #include <sys/conf.h> 52 #include <sys/file.h> 53 #include <sys/uio.h> 54 #include <sys/kernel.h> 55 #include <sys/syslog.h> 56 #include <sys/types.h> 57 #include <sys/device.h> 58 59 #ifdef i386 /* XXX */ 60 #include <machine/cpu.h> /* XXX */ 61 #else /* XXX */ 62 #include <machine/intr.h> 63 #endif /* XXX */ 64 #include <machine/bus.h> 65 66 #include <dev/isa/isavar.h> 67 #include <dev/isa/comreg.h> 68 #include <dev/isa/comvar.h> 69 #include <dev/ic/ns16550reg.h> 70 #ifdef COM_HAYESP 71 #include <dev/ic/hayespreg.h> 72 #endif 73 #define com_lcr com_cfcr 74 75 #include "com.h" 76 77 78 #define COM_IBUFSIZE (2 * 512) 79 #define COM_IHIGHWATER ((3 * COM_IBUFSIZE) / 4) 80 81 struct com_softc { 82 struct device sc_dev; 83 void *sc_ih; 84 struct tty *sc_tty; 85 86 int sc_overflows; 87 int sc_floods; 88 int sc_errors; 89 90 int sc_halt; 91 92 int sc_iobase; 93 #ifdef COM_HAYESP 94 int sc_hayespbase; 95 #endif 96 97 bus_chipset_tag_t sc_bc; 98 bus_io_handle_t sc_ioh; 99 bus_io_handle_t sc_hayespioh; 100 101 u_char sc_hwflags; 102 #define COM_HW_NOIEN 0x01 103 #define COM_HW_FIFO 0x02 104 #define COM_HW_HAYESP 0x04 105 #define COM_HW_CONSOLE 0x40 106 u_char sc_swflags; 107 #define COM_SW_SOFTCAR 0x01 108 #define COM_SW_CLOCAL 0x02 109 #define COM_SW_CRTSCTS 0x04 110 #define COM_SW_MDMBUF 0x08 111 u_char sc_msr, sc_mcr, sc_lcr, sc_ier; 112 u_char sc_dtr; 113 114 u_char *sc_ibuf, *sc_ibufp, *sc_ibufhigh, *sc_ibufend; 115 u_char sc_ibufs[2][COM_IBUFSIZE]; 116 }; 117 118 #ifdef COM_HAYESP 119 int comprobeHAYESP __P((bus_io_handle_t hayespioh, struct com_softc *sc)); 120 #endif 121 void comdiag __P((void *)); 122 int comspeed __P((long)); 123 int comparam __P((struct tty *, struct termios *)); 124 void comstart __P((struct tty *)); 125 int comintr __P((void *)); 126 void compoll __P((void *)); 127 128 /* XXX: These belong elsewhere */ 129 cdev_decl(com); 130 bdev_decl(com); 131 132 struct consdev; 133 void comcnprobe __P((struct consdev *)); 134 void comcninit __P((struct consdev *)); 135 int comcngetc __P((dev_t)); 136 void comcnputc __P((dev_t, int)); 137 void comcnpollc __P((dev_t, int)); 138 139 static u_char tiocm_xxx2mcr __P((int)); 140 141 /* 142 * XXX the following two cfattach structs should be different, and possibly 143 * XXX elsewhere. 144 */ 145 int comprobe __P((struct device *, void *, void *)); 146 void comattach __P((struct device *, struct device *, void *)); 147 148 #if NCOM_ISA 149 struct cfattach com_isa_ca = { 150 sizeof(struct com_softc), comprobe, comattach 151 }; 152 #endif 153 154 #if NCOM_COMMULTI 155 struct cfattach com_commulti_ca = { 156 sizeof(struct com_softc), comprobe, comattach 157 }; 158 #endif 159 160 struct cfdriver com_cd = { 161 NULL, "com", DV_TTY 162 }; 163 164 void cominit __P((bus_chipset_tag_t, bus_io_handle_t, int)); 165 166 #ifdef COMCONSOLE 167 int comdefaultrate = CONSPEED; /* XXX why set default? */ 168 #else 169 int comdefaultrate = TTYDEF_SPEED; 170 #endif 171 int comconsaddr; 172 int comconsinit; 173 int comconsattached; 174 bus_chipset_tag_t comconsbc; 175 bus_io_handle_t comconsioh; 176 tcflag_t comconscflag = TTYDEF_CFLAG; 177 178 int commajor; 179 int comsopen = 0; 180 int comevents = 0; 181 182 #ifdef KGDB 183 #include <machine/remote-sl.h> 184 extern int kgdb_dev; 185 extern int kgdb_rate; 186 extern int kgdb_debug_init; 187 #endif 188 189 #define COMUNIT(x) (minor(x)) 190 191 /* Macros to clear/set/test flags. */ 192 #define SET(t, f) (t) |= (f) 193 #define CLR(t, f) (t) &= ~(f) 194 #define ISSET(t, f) ((t) & (f)) 195 196 int 197 comspeed(speed) 198 long speed; 199 { 200 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 201 202 int x, err; 203 204 if (speed == 0) 205 return 0; 206 if (speed < 0) 207 return -1; 208 x = divrnd((COM_FREQ / 16), speed); 209 if (x <= 0) 210 return -1; 211 err = divrnd((COM_FREQ / 16) * 1000, speed * x) - 1000; 212 if (err < 0) 213 err = -err; 214 if (err > COM_TOLERANCE) 215 return -1; 216 return x; 217 218 #undef divrnd(n, q) 219 } 220 221 int 222 comprobe1(bc, ioh, iobase) 223 bus_chipset_tag_t bc; 224 bus_io_handle_t ioh; 225 int iobase; 226 { 227 228 /* force access to id reg */ 229 bus_io_write_1(bc, ioh, com_lcr, 0); 230 bus_io_write_1(bc, ioh, com_iir, 0); 231 if (bus_io_read_1(bc, ioh, com_iir) & 0x38) 232 return 0; 233 234 return 1; 235 } 236 237 #ifdef COM_HAYESP 238 int 239 comprobeHAYESP(hayespioh, sc) 240 bus_io_handle_t hayespioh; 241 struct com_softc *sc; 242 { 243 char val, dips; 244 int combaselist[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; 245 bus_chipset_tag_t bc = sc->sc_bc; 246 247 /* 248 * Hayes ESP cards have two iobases. One is for compatibility with 249 * 16550 serial chips, and at the same ISA PC base addresses. The 250 * other is for ESP-specific enhanced features, and lies at a 251 * different addressing range entirely (0x140, 0x180, 0x280, or 0x300). 252 */ 253 254 /* Test for ESP signature */ 255 if ((bus_io_read_1(bc, hayespioh, 0) & 0xf3) == 0) 256 return 0; 257 258 /* 259 * ESP is present at ESP enhanced base address; unknown com port 260 */ 261 262 /* Get the dip-switch configurations */ 263 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETDIPS); 264 dips = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1); 265 266 /* Determine which com port this ESP card services: bits 0,1 of */ 267 /* dips is the port # (0-3); combaselist[val] is the com_iobase */ 268 if (sc->sc_iobase != combaselist[dips & 0x03]) 269 return 0; 270 271 printf(": ESP"); 272 273 /* Check ESP Self Test bits. */ 274 /* Check for ESP version 2.0: bits 4,5,6 == 010 */ 275 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETTEST); 276 val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1); /* Clear reg 1 */ 277 val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS2); 278 if ((val & 0x70) < 0x20) { 279 printf("-old (%o)", val & 0x70); 280 /* we do not support the necessary features */ 281 return 0; 282 } 283 284 /* Check for ability to emulate 16550: bit 8 == 1 */ 285 if ((dips & 0x80) == 0) { 286 printf(" slave"); 287 /* XXX Does slave really mean no 16550 support?? */ 288 return 0; 289 } 290 291 /* 292 * If we made it this far, we are a full-featured ESP v2.0 (or 293 * better), at the correct com port address. 294 */ 295 296 SET(sc->sc_hwflags, COM_HW_HAYESP); 297 printf(", 1024 byte fifo\n"); 298 return 1; 299 } 300 #endif 301 302 int 303 comprobe(parent, match, aux) 304 struct device *parent; 305 void *match, *aux; 306 { 307 bus_chipset_tag_t bc; 308 bus_io_handle_t ioh; 309 int iobase, needioh; 310 int rv = 1; 311 312 /* 313 * XXX should be broken out into functions for isa probe and 314 * XXX for commulti probe, with a helper function that contains 315 * XXX most of the interesting stuff. 316 */ 317 #if NCOM_ISA 318 if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) { 319 struct isa_attach_args *ia = aux; 320 321 bc = ia->ia_bc; 322 iobase = ia->ia_iobase; 323 needioh = 1; 324 } else 325 #endif 326 #if NCOM_COMMULTI 327 if (1) { 328 struct cfdata *cf = match; 329 struct commulti_attach_args *ca = aux; 330 331 if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != ca->ca_slave) 332 return (0); 333 334 bc = ca->ca_bc; 335 iobase = ca->ca_iobase; 336 ioh = ca->ca_ioh; 337 needioh = 0; 338 } else 339 #endif 340 return(0); /* This cannot happen */ 341 342 /* if it's in use as console, it's there. */ 343 if (iobase == comconsaddr && !comconsattached) 344 goto out; 345 346 if (needioh && bus_io_map(bc, iobase, COM_NPORTS, &ioh)) { 347 rv = 0; 348 goto out; 349 } 350 rv = comprobe1(bc, ioh, iobase); 351 if (needioh) 352 bus_io_unmap(bc, ioh, COM_NPORTS); 353 354 out: 355 #if NCOM_ISA 356 if (rv && !strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) { 357 struct isa_attach_args *ia = aux; 358 359 ia->ia_iosize = COM_NPORTS; 360 ia->ia_msize = 0; 361 } 362 #endif 363 return (rv); 364 } 365 366 void 367 comattach(parent, self, aux) 368 struct device *parent, *self; 369 void *aux; 370 { 371 struct com_softc *sc = (void *)self; 372 int iobase, irq; 373 bus_chipset_tag_t bc; 374 bus_io_handle_t ioh; 375 #ifdef COM_HAYESP 376 int hayesp_ports[] = { 0x140, 0x180, 0x280, 0x300, 0 }; 377 int *hayespp; 378 #endif 379 380 /* 381 * XXX should be broken out into functions for isa attach and 382 * XXX for commulti attach, with a helper function that contains 383 * XXX most of the interesting stuff. 384 */ 385 sc->sc_hwflags = 0; 386 sc->sc_swflags = 0; 387 #if NCOM_ISA 388 if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) { 389 struct isa_attach_args *ia = aux; 390 391 /* 392 * We're living on an isa. 393 */ 394 iobase = ia->ia_iobase; 395 bc = ia->ia_bc; 396 if (iobase != comconsaddr) { 397 if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) 398 panic("comattach: io mapping failed"); 399 } else 400 ioh = comconsioh; 401 irq = ia->ia_irq; 402 } else 403 #endif 404 #if NCOM_COMMULTI 405 if (1) { 406 struct commulti_attach_args *ca = aux; 407 408 /* 409 * We're living on a commulti. 410 */ 411 iobase = ca->ca_iobase; 412 bc = ca->ca_bc; 413 ioh = ca->ca_ioh; 414 irq = IRQUNK; 415 416 if (ca->ca_noien) 417 sc->sc_hwflags |= COM_HW_NOIEN; 418 } else 419 #endif 420 panic("comattach: impossible"); 421 422 sc->sc_bc = bc; 423 sc->sc_ioh = ioh; 424 sc->sc_iobase = iobase; 425 426 if (iobase == comconsaddr) { 427 comconsattached = 1; 428 429 /* 430 * Need to reset baud rate, etc. of next print so reset 431 * comconsinit. Also make sure console is always "hardwired". 432 */ 433 delay(1000); /* wait for output to finish */ 434 comconsinit = 0; 435 SET(sc->sc_hwflags, COM_HW_CONSOLE); 436 SET(sc->sc_swflags, COM_SW_SOFTCAR); 437 } 438 439 #ifdef COM_HAYESP 440 /* Look for a Hayes ESP board. */ 441 for (hayespp = hayesp_ports; *hayespp != 0; hayespp++) { 442 bus_io_handle_t hayespioh; 443 444 #define HAYESP_NPORTS 8 /* XXX XXX XXX ??? ??? ??? */ 445 if (bus_io_map(bc, *hayespp, HAYESP_NPORTS, &hayespioh)) 446 continue; 447 if (comprobeHAYESP(hayespioh, sc)) { 448 sc->sc_hayespbase = *hayespp; 449 sc->sc_hayespioh = hayespioh; 450 break; 451 } 452 bus_io_unmap(bc, hayespioh, HAYESP_NPORTS); 453 } 454 /* No ESP; look for other things. */ 455 if (*hayespp == 0) { 456 #endif 457 458 /* look for a NS 16550AF UART with FIFOs */ 459 bus_io_write_1(bc, ioh, com_fifo, 460 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 461 delay(100); 462 if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_FIFO_MASK) == IIR_FIFO_MASK) 463 if (ISSET(bus_io_read_1(bc, ioh, com_fifo), FIFO_TRIGGER_14) == FIFO_TRIGGER_14) { 464 SET(sc->sc_hwflags, COM_HW_FIFO); 465 printf(": ns16550a, working fifo\n"); 466 } else 467 printf(": ns16550, broken fifo\n"); 468 else 469 printf(": ns8250 or ns16450, no fifo\n"); 470 bus_io_write_1(bc, ioh, com_fifo, 0); 471 #ifdef COM_HAYESP 472 } 473 #endif 474 475 /* disable interrupts */ 476 bus_io_write_1(bc, ioh, com_ier, 0); 477 bus_io_write_1(bc, ioh, com_mcr, 0); 478 479 if (irq != IRQUNK) { 480 #if NCOM_ISA 481 if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) { 482 struct isa_attach_args *ia = aux; 483 484 sc->sc_ih = isa_intr_establish(ia->ia_ic, irq, 485 IST_EDGE, IPL_TTY, comintr, sc); 486 } else 487 #endif 488 panic("comattach: IRQ but can't have one"); 489 } 490 491 #ifdef KGDB 492 if (kgdb_dev == makedev(commajor, unit)) { 493 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 494 kgdb_dev = -1; /* can't debug over console port */ 495 else { 496 cominit(bc, ioh, kgdb_rate); 497 if (kgdb_debug_init) { 498 /* 499 * Print prefix of device name, 500 * let kgdb_connect print the rest. 501 */ 502 printf("%s: ", sc->sc_dev.dv_xname); 503 kgdb_connect(1); 504 } else 505 printf("%s: kgdb enabled\n", 506 sc->sc_dev.dv_xname); 507 } 508 } 509 #endif 510 511 /* XXX maybe move up some? */ 512 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 513 printf("%s: console\n", sc->sc_dev.dv_xname); 514 } 515 516 int 517 comopen(dev, flag, mode, p) 518 dev_t dev; 519 int flag, mode; 520 struct proc *p; 521 { 522 int unit = COMUNIT(dev); 523 struct com_softc *sc; 524 bus_chipset_tag_t bc; 525 bus_io_handle_t ioh; 526 struct tty *tp; 527 int s; 528 int error = 0; 529 530 if (unit >= com_cd.cd_ndevs) 531 return ENXIO; 532 sc = com_cd.cd_devs[unit]; 533 if (!sc) 534 return ENXIO; 535 536 if (!sc->sc_tty) 537 tp = sc->sc_tty = ttymalloc(); 538 else 539 tp = sc->sc_tty; 540 541 tp->t_oproc = comstart; 542 tp->t_param = comparam; 543 tp->t_dev = dev; 544 if (!ISSET(tp->t_state, TS_ISOPEN)) { 545 SET(tp->t_state, TS_WOPEN); 546 ttychars(tp); 547 tp->t_iflag = TTYDEF_IFLAG; 548 tp->t_oflag = TTYDEF_OFLAG; 549 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 550 tp->t_cflag = comconscflag; 551 else 552 tp->t_cflag = TTYDEF_CFLAG; 553 if (ISSET(sc->sc_swflags, COM_SW_CLOCAL)) 554 SET(tp->t_cflag, CLOCAL); 555 if (ISSET(sc->sc_swflags, COM_SW_CRTSCTS)) 556 SET(tp->t_cflag, CRTSCTS); 557 if (ISSET(sc->sc_swflags, COM_SW_MDMBUF)) 558 SET(tp->t_cflag, MDMBUF); 559 tp->t_lflag = TTYDEF_LFLAG; 560 tp->t_ispeed = tp->t_ospeed = comdefaultrate; 561 562 s = spltty(); 563 564 comparam(tp, &tp->t_termios); 565 ttsetwater(tp); 566 567 if (comsopen++ == 0) 568 timeout(compoll, NULL, 1); 569 570 sc->sc_ibufp = sc->sc_ibuf = sc->sc_ibufs[0]; 571 sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER; 572 sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE; 573 574 bc = sc->sc_bc; 575 ioh = sc->sc_ioh; 576 #ifdef COM_HAYESP 577 /* Setup the ESP board */ 578 if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) { 579 bus_io_handle_t hayespioh = sc->sc_hayespioh; 580 581 bus_io_write_1(bc, ioh, com_fifo, 582 FIFO_DMA_MODE|FIFO_ENABLE| 583 FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_8); 584 585 /* Set 16550 compatibility mode */ 586 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETMODE); 587 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 588 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 589 HAYESP_MODE_SCALE); 590 591 /* Set RTS/CTS flow control */ 592 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETFLOWTYPE); 593 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_RTS); 594 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_CTS); 595 596 /* Set flow control levels */ 597 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETRXFLOW); 598 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 599 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 600 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 601 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 602 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 603 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 604 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 605 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 606 } else 607 #endif 608 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 609 /* Set the FIFO threshold based on the receive speed. */ 610 bus_io_write_1(bc, ioh, com_fifo, 611 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 612 (tp->t_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8)); 613 /* flush any pending I/O */ 614 while (ISSET(bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY)) 615 (void) bus_io_read_1(bc, ioh, com_data); 616 /* you turn me on, baby */ 617 sc->sc_mcr = MCR_DTR | MCR_RTS; 618 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 619 SET(sc->sc_mcr, MCR_IENABLE); 620 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 621 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 622 bus_io_write_1(bc, ioh, com_ier, sc->sc_ier); 623 624 sc->sc_msr = bus_io_read_1(bc, ioh, com_msr); 625 if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR) || 626 ISSET(sc->sc_msr, MSR_DCD) || ISSET(tp->t_cflag, MDMBUF)) 627 SET(tp->t_state, TS_CARR_ON); 628 else 629 CLR(tp->t_state, TS_CARR_ON); 630 } else if (ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0) 631 return EBUSY; 632 else 633 s = spltty(); 634 635 /* wait for carrier if necessary */ 636 if (!ISSET(flag, O_NONBLOCK)) 637 while (!ISSET(tp->t_cflag, CLOCAL) && 638 !ISSET(tp->t_state, TS_CARR_ON)) { 639 SET(tp->t_state, TS_WOPEN); 640 error = ttysleep(tp, &tp->t_rawq, TTIPRI | PCATCH, 641 ttopen, 0); 642 if (error) { 643 /* XXX should turn off chip if we're the 644 only waiter */ 645 splx(s); 646 return error; 647 } 648 } 649 splx(s); 650 651 return (*linesw[tp->t_line].l_open)(dev, tp); 652 } 653 654 int 655 comclose(dev, flag, mode, p) 656 dev_t dev; 657 int flag, mode; 658 struct proc *p; 659 { 660 int unit = COMUNIT(dev); 661 struct com_softc *sc = com_cd.cd_devs[unit]; 662 struct tty *tp = sc->sc_tty; 663 bus_chipset_tag_t bc = sc->sc_bc; 664 bus_io_handle_t ioh = sc->sc_ioh; 665 int s; 666 667 /* XXX This is for cons.c. */ 668 if (!ISSET(tp->t_state, TS_ISOPEN)) 669 return 0; 670 671 (*linesw[tp->t_line].l_close)(tp, flag); 672 s = spltty(); 673 CLR(sc->sc_lcr, LCR_SBREAK); 674 bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr); 675 bus_io_write_1(bc, ioh, com_ier, 0); 676 if (ISSET(tp->t_cflag, HUPCL) && 677 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) { 678 /* XXX perhaps only clear DTR */ 679 bus_io_write_1(bc, ioh, com_mcr, 0); 680 } 681 CLR(tp->t_state, TS_BUSY | TS_FLUSH); 682 if (--comsopen == 0) 683 untimeout(compoll, NULL); 684 splx(s); 685 ttyclose(tp); 686 #ifdef notyet /* XXXX */ 687 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 688 ttyfree(tp); 689 sc->sc_tty = 0; 690 } 691 #endif 692 return 0; 693 } 694 695 int 696 comread(dev, uio, flag) 697 dev_t dev; 698 struct uio *uio; 699 int flag; 700 { 701 struct com_softc *sc = com_cd.cd_devs[COMUNIT(dev)]; 702 struct tty *tp = sc->sc_tty; 703 704 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 705 } 706 707 int 708 comwrite(dev, uio, flag) 709 dev_t dev; 710 struct uio *uio; 711 int flag; 712 { 713 struct com_softc *sc = com_cd.cd_devs[COMUNIT(dev)]; 714 struct tty *tp = sc->sc_tty; 715 716 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 717 } 718 719 struct tty * 720 comtty(dev) 721 dev_t dev; 722 { 723 struct com_softc *sc = com_cd.cd_devs[COMUNIT(dev)]; 724 struct tty *tp = sc->sc_tty; 725 726 return (tp); 727 } 728 729 static u_char 730 tiocm_xxx2mcr(data) 731 int data; 732 { 733 u_char m = 0; 734 735 if (ISSET(data, TIOCM_DTR)) 736 SET(m, MCR_DTR); 737 if (ISSET(data, TIOCM_RTS)) 738 SET(m, MCR_RTS); 739 return m; 740 } 741 742 int 743 comioctl(dev, cmd, data, flag, p) 744 dev_t dev; 745 u_long cmd; 746 caddr_t data; 747 int flag; 748 struct proc *p; 749 { 750 int unit = COMUNIT(dev); 751 struct com_softc *sc = com_cd.cd_devs[unit]; 752 struct tty *tp = sc->sc_tty; 753 bus_chipset_tag_t bc = sc->sc_bc; 754 bus_io_handle_t ioh = sc->sc_ioh; 755 int error; 756 757 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 758 if (error >= 0) 759 return error; 760 error = ttioctl(tp, cmd, data, flag, p); 761 if (error >= 0) 762 return error; 763 764 switch (cmd) { 765 case TIOCSBRK: 766 SET(sc->sc_lcr, LCR_SBREAK); 767 bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr); 768 break; 769 case TIOCCBRK: 770 CLR(sc->sc_lcr, LCR_SBREAK); 771 bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr); 772 break; 773 case TIOCSDTR: 774 SET(sc->sc_mcr, sc->sc_dtr); 775 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 776 break; 777 case TIOCCDTR: 778 CLR(sc->sc_mcr, sc->sc_dtr); 779 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 780 break; 781 case TIOCMSET: 782 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 783 case TIOCMBIS: 784 SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data)); 785 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 786 break; 787 case TIOCMBIC: 788 CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data)); 789 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 790 break; 791 case TIOCMGET: { 792 u_char m; 793 int bits = 0; 794 795 m = sc->sc_mcr; 796 if (ISSET(m, MCR_DTR)) 797 SET(bits, TIOCM_DTR); 798 if (ISSET(m, MCR_RTS)) 799 SET(bits, TIOCM_RTS); 800 m = sc->sc_msr; 801 if (ISSET(m, MSR_DCD)) 802 SET(bits, TIOCM_CD); 803 if (ISSET(m, MSR_CTS)) 804 SET(bits, TIOCM_CTS); 805 if (ISSET(m, MSR_DSR)) 806 SET(bits, TIOCM_DSR); 807 if (ISSET(m, MSR_RI | MSR_TERI)) 808 SET(bits, TIOCM_RI); 809 if (bus_io_read_1(bc, ioh, com_ier)) 810 SET(bits, TIOCM_LE); 811 *(int *)data = bits; 812 break; 813 } 814 case TIOCGFLAGS: { 815 int driverbits, userbits = 0; 816 817 driverbits = sc->sc_swflags; 818 if (ISSET(driverbits, COM_SW_SOFTCAR)) 819 SET(userbits, TIOCFLAG_SOFTCAR); 820 if (ISSET(driverbits, COM_SW_CLOCAL)) 821 SET(userbits, TIOCFLAG_CLOCAL); 822 if (ISSET(driverbits, COM_SW_CRTSCTS)) 823 SET(userbits, TIOCFLAG_CRTSCTS); 824 if (ISSET(driverbits, COM_SW_MDMBUF)) 825 SET(userbits, TIOCFLAG_MDMBUF); 826 827 *(int *)data = userbits; 828 break; 829 } 830 case TIOCSFLAGS: { 831 int userbits, driverbits = 0; 832 833 error = suser(p->p_ucred, &p->p_acflag); 834 if (error != 0) 835 return(EPERM); 836 837 userbits = *(int *)data; 838 if (ISSET(userbits, TIOCFLAG_SOFTCAR) || 839 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 840 SET(driverbits, COM_SW_SOFTCAR); 841 if (ISSET(userbits, TIOCFLAG_CLOCAL)) 842 SET(driverbits, COM_SW_CLOCAL); 843 if (ISSET(userbits, TIOCFLAG_CRTSCTS)) 844 SET(driverbits, COM_SW_CRTSCTS); 845 if (ISSET(userbits, TIOCFLAG_MDMBUF)) 846 SET(driverbits, COM_SW_MDMBUF); 847 848 sc->sc_swflags = driverbits; 849 break; 850 } 851 default: 852 return ENOTTY; 853 } 854 855 return 0; 856 } 857 858 int 859 comparam(tp, t) 860 struct tty *tp; 861 struct termios *t; 862 { 863 struct com_softc *sc = com_cd.cd_devs[COMUNIT(tp->t_dev)]; 864 bus_chipset_tag_t bc = sc->sc_bc; 865 bus_io_handle_t ioh = sc->sc_ioh; 866 int ospeed = comspeed(t->c_ospeed); 867 u_char lcr; 868 tcflag_t oldcflag; 869 int s; 870 871 /* check requested parameters */ 872 if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed)) 873 return EINVAL; 874 875 lcr = ISSET(sc->sc_lcr, LCR_SBREAK); 876 877 switch (ISSET(t->c_cflag, CSIZE)) { 878 case CS5: 879 SET(lcr, LCR_5BITS); 880 break; 881 case CS6: 882 SET(lcr, LCR_6BITS); 883 break; 884 case CS7: 885 SET(lcr, LCR_7BITS); 886 break; 887 case CS8: 888 SET(lcr, LCR_8BITS); 889 break; 890 } 891 if (ISSET(t->c_cflag, PARENB)) { 892 SET(lcr, LCR_PENAB); 893 if (!ISSET(t->c_cflag, PARODD)) 894 SET(lcr, LCR_PEVEN); 895 } 896 if (ISSET(t->c_cflag, CSTOPB)) 897 SET(lcr, LCR_STOPB); 898 899 sc->sc_lcr = lcr; 900 901 s = spltty(); 902 903 if (ospeed == 0) { 904 CLR(sc->sc_mcr, MCR_DTR); 905 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 906 } 907 908 /* 909 * Set the FIFO threshold based on the receive speed, if we are 910 * changing it. 911 */ 912 #if 1 913 if (tp->t_ispeed != t->c_ispeed) { 914 #else 915 if (1) { 916 #endif 917 if (ospeed != 0) { 918 /* 919 * Make sure the transmit FIFO is empty before 920 * proceeding. If we don't do this, some revisions 921 * of the UART will hang. Interestingly enough, 922 * even if we do this will the last character is 923 * still being pushed out, they don't hang. This 924 * seems good enough. 925 */ 926 while (ISSET(tp->t_state, TS_BUSY)) { 927 int error; 928 929 ++sc->sc_halt; 930 error = ttysleep(tp, &tp->t_outq, 931 TTOPRI | PCATCH, "comprm", 0); 932 --sc->sc_halt; 933 if (error) { 934 splx(s); 935 comstart(tp); 936 return (error); 937 } 938 } 939 940 bus_io_write_1(bc, ioh, com_lcr, lcr | LCR_DLAB); 941 bus_io_write_1(bc, ioh, com_dlbl, ospeed); 942 bus_io_write_1(bc, ioh, com_dlbh, ospeed >> 8); 943 bus_io_write_1(bc, ioh, com_lcr, lcr); 944 SET(sc->sc_mcr, MCR_DTR); 945 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 946 } else 947 bus_io_write_1(bc, ioh, com_lcr, lcr); 948 949 if (!ISSET(sc->sc_hwflags, COM_HW_HAYESP) && 950 ISSET(sc->sc_hwflags, COM_HW_FIFO)) 951 bus_io_write_1(bc, ioh, com_fifo, 952 FIFO_ENABLE | 953 (t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8)); 954 } else 955 bus_io_write_1(bc, ioh, com_lcr, lcr); 956 957 /* When not using CRTSCTS, RTS follows DTR. */ 958 if (!ISSET(t->c_cflag, CRTSCTS)) { 959 if (ISSET(sc->sc_mcr, MCR_DTR)) { 960 if (!ISSET(sc->sc_mcr, MCR_RTS)) { 961 SET(sc->sc_mcr, MCR_RTS); 962 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 963 } 964 } else { 965 if (ISSET(sc->sc_mcr, MCR_RTS)) { 966 CLR(sc->sc_mcr, MCR_RTS); 967 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 968 } 969 } 970 sc->sc_dtr = MCR_DTR | MCR_RTS; 971 } else 972 sc->sc_dtr = MCR_DTR; 973 974 /* and copy to tty */ 975 tp->t_ispeed = t->c_ispeed; 976 tp->t_ospeed = t->c_ospeed; 977 oldcflag = tp->t_cflag; 978 tp->t_cflag = t->c_cflag; 979 980 /* 981 * If DCD is off and MDMBUF is changed, ask the tty layer if we should 982 * stop the device. 983 */ 984 if (!ISSET(sc->sc_msr, MSR_DCD) && 985 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR) && 986 ISSET(oldcflag, MDMBUF) != ISSET(tp->t_cflag, MDMBUF) && 987 (*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 988 CLR(sc->sc_mcr, sc->sc_dtr); 989 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 990 } 991 992 /* Just to be sure... */ 993 splx(s); 994 comstart(tp); 995 return 0; 996 } 997 998 void 999 comstart(tp) 1000 struct tty *tp; 1001 { 1002 struct com_softc *sc = com_cd.cd_devs[COMUNIT(tp->t_dev)]; 1003 bus_chipset_tag_t bc = sc->sc_bc; 1004 bus_io_handle_t ioh = sc->sc_ioh; 1005 int s; 1006 1007 s = spltty(); 1008 if (ISSET(tp->t_state, TS_BUSY)) 1009 goto out; 1010 if (ISSET(tp->t_state, TS_TIMEOUT | TS_TTSTOP) || 1011 sc->sc_halt > 0) 1012 goto stopped; 1013 if (ISSET(tp->t_cflag, CRTSCTS) && !ISSET(sc->sc_msr, MSR_CTS)) 1014 goto stopped; 1015 if (tp->t_outq.c_cc <= tp->t_lowat) { 1016 if (ISSET(tp->t_state, TS_ASLEEP)) { 1017 CLR(tp->t_state, TS_ASLEEP); 1018 wakeup(&tp->t_outq); 1019 } 1020 if (tp->t_outq.c_cc == 0) 1021 goto stopped; 1022 selwakeup(&tp->t_wsel); 1023 } 1024 SET(tp->t_state, TS_BUSY); 1025 1026 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1027 SET(sc->sc_ier, IER_ETXRDY); 1028 bus_io_write_1(bc, ioh, com_ier, sc->sc_ier); 1029 } 1030 #ifdef COM_HAYESP 1031 if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) { 1032 u_char buffer[1024], *cp = buffer; 1033 int n = q_to_b(&tp->t_outq, cp, sizeof buffer); 1034 do 1035 bus_io_write_1(bc, ioh, com_data, *cp++); 1036 while (--n); 1037 } 1038 else 1039 #endif 1040 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1041 u_char buffer[16], *cp = buffer; 1042 int n = q_to_b(&tp->t_outq, cp, sizeof buffer); 1043 do { 1044 bus_io_write_1(bc, ioh, com_data, *cp++); 1045 } while (--n); 1046 } else 1047 bus_io_write_1(bc, ioh, com_data, getc(&tp->t_outq)); 1048 out: 1049 splx(s); 1050 return; 1051 stopped: 1052 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 1053 CLR(sc->sc_ier, IER_ETXRDY); 1054 bus_io_write_1(bc, ioh, com_ier, sc->sc_ier); 1055 } 1056 splx(s); 1057 } 1058 1059 /* 1060 * Stop output on a line. 1061 */ 1062 int 1063 comstop(tp, flag) 1064 struct tty *tp; 1065 int flag; 1066 { 1067 int s; 1068 1069 s = spltty(); 1070 if (ISSET(tp->t_state, TS_BUSY)) 1071 if (!ISSET(tp->t_state, TS_TTSTOP)) 1072 SET(tp->t_state, TS_FLUSH); 1073 splx(s); 1074 return 0; 1075 } 1076 1077 void 1078 comdiag(arg) 1079 void *arg; 1080 { 1081 struct com_softc *sc = arg; 1082 int overflows, floods; 1083 int s; 1084 1085 s = spltty(); 1086 sc->sc_errors = 0; 1087 overflows = sc->sc_overflows; 1088 sc->sc_overflows = 0; 1089 floods = sc->sc_floods; 1090 sc->sc_floods = 0; 1091 splx(s); 1092 1093 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf overflow%s\n", 1094 sc->sc_dev.dv_xname, 1095 overflows, overflows == 1 ? "" : "s", 1096 floods, floods == 1 ? "" : "s"); 1097 } 1098 1099 void 1100 compoll(arg) 1101 void *arg; 1102 { 1103 int unit; 1104 struct com_softc *sc; 1105 struct tty *tp; 1106 register u_char *ibufp; 1107 u_char *ibufend; 1108 register int c; 1109 int s; 1110 static int lsrmap[8] = { 1111 0, TTY_PE, 1112 TTY_FE, TTY_PE|TTY_FE, 1113 TTY_FE, TTY_PE|TTY_FE, 1114 TTY_FE, TTY_PE|TTY_FE 1115 }; 1116 1117 s = spltty(); 1118 if (comevents == 0) { 1119 splx(s); 1120 goto out; 1121 } 1122 comevents = 0; 1123 splx(s); 1124 1125 for (unit = 0; unit < com_cd.cd_ndevs; unit++) { 1126 sc = com_cd.cd_devs[unit]; 1127 if (sc == 0 || sc->sc_ibufp == sc->sc_ibuf) 1128 continue; 1129 1130 tp = sc->sc_tty; 1131 1132 s = spltty(); 1133 1134 ibufp = sc->sc_ibuf; 1135 ibufend = sc->sc_ibufp; 1136 1137 if (ibufp == ibufend) { 1138 splx(s); 1139 continue; 1140 } 1141 1142 sc->sc_ibufp = sc->sc_ibuf = (ibufp == sc->sc_ibufs[0]) ? 1143 sc->sc_ibufs[1] : sc->sc_ibufs[0]; 1144 sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER; 1145 sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE; 1146 1147 if (tp == 0 || !ISSET(tp->t_state, TS_ISOPEN)) { 1148 splx(s); 1149 continue; 1150 } 1151 1152 if (ISSET(tp->t_cflag, CRTSCTS) && 1153 !ISSET(sc->sc_mcr, MCR_RTS)) { 1154 /* XXX */ 1155 SET(sc->sc_mcr, MCR_RTS); 1156 bus_io_write_1(sc->sc_bc, sc->sc_ioh, com_mcr, 1157 sc->sc_mcr); 1158 } 1159 1160 splx(s); 1161 1162 while (ibufp < ibufend) { 1163 c = *ibufp++; 1164 if (*ibufp & LSR_OE) { 1165 sc->sc_overflows++; 1166 if (sc->sc_errors++ == 0) 1167 timeout(comdiag, sc, 60 * hz); 1168 } 1169 /* This is ugly, but fast. */ 1170 c |= lsrmap[(*ibufp++ & (LSR_BI|LSR_FE|LSR_PE)) >> 2]; 1171 (*linesw[tp->t_line].l_rint)(c, tp); 1172 } 1173 } 1174 1175 out: 1176 timeout(compoll, NULL, 1); 1177 } 1178 1179 int 1180 comintr(arg) 1181 void *arg; 1182 { 1183 struct com_softc *sc = arg; 1184 bus_chipset_tag_t bc = sc->sc_bc; 1185 bus_io_handle_t ioh = sc->sc_ioh; 1186 struct tty *tp; 1187 u_char lsr, data, msr, delta; 1188 #ifdef COM_DEBUG 1189 int n; 1190 struct { 1191 u_char iir, lsr, msr; 1192 } iter[32]; 1193 #endif 1194 1195 #ifdef COM_DEBUG 1196 n = 0; 1197 if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND)) 1198 return (0); 1199 #else 1200 if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND)) 1201 return (0); 1202 #endif 1203 1204 tp = sc->sc_tty; 1205 1206 for (;;) { 1207 #ifdef COM_DEBUG 1208 iter[n].lsr = 1209 #endif 1210 lsr = bus_io_read_1(bc, ioh, com_lsr); 1211 1212 if (ISSET(lsr, LSR_RXRDY)) { 1213 register u_char *p = sc->sc_ibufp; 1214 1215 comevents = 1; 1216 do { 1217 data = bus_io_read_1(bc, ioh, com_data); 1218 if (ISSET(lsr, LSR_BI)) { 1219 #ifdef notdef 1220 printf("break %02x %02x %02x %02x\n", 1221 sc->sc_msr, sc->sc_mcr, sc->sc_lcr, 1222 sc->sc_dtr); 1223 #endif 1224 #ifdef DDB 1225 if (ISSET(sc->sc_hwflags, 1226 COM_HW_CONSOLE)) { 1227 Debugger(); 1228 goto next; 1229 } 1230 #endif 1231 } 1232 if (p >= sc->sc_ibufend) { 1233 sc->sc_floods++; 1234 if (sc->sc_errors++ == 0) 1235 timeout(comdiag, sc, 60 * hz); 1236 } else { 1237 *p++ = data; 1238 *p++ = lsr; 1239 if (p == sc->sc_ibufhigh && 1240 ISSET(tp->t_cflag, CRTSCTS)) { 1241 /* XXX */ 1242 CLR(sc->sc_mcr, MCR_RTS); 1243 bus_io_write_1(bc, ioh, com_mcr, 1244 sc->sc_mcr); 1245 } 1246 } 1247 next: 1248 #ifdef COM_DEBUG 1249 if (++n >= 32) 1250 goto ohfudge; 1251 iter[n].lsr = 1252 #endif 1253 lsr = bus_io_read_1(bc, ioh, com_lsr); 1254 } while (ISSET(lsr, LSR_RXRDY)); 1255 1256 sc->sc_ibufp = p; 1257 } 1258 #ifdef COM_DEBUG 1259 else if (ISSET(lsr, LSR_BI|LSR_FE|LSR_PE|LSR_OE)) 1260 printf("weird lsr %02x\n", lsr); 1261 #endif 1262 1263 #ifdef COM_DEBUG 1264 iter[n].msr = 1265 #endif 1266 msr = bus_io_read_1(bc, ioh, com_msr); 1267 1268 if (msr != sc->sc_msr) { 1269 delta = msr ^ sc->sc_msr; 1270 sc->sc_msr = msr; 1271 if (ISSET(delta, MSR_DCD) && 1272 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR) && 1273 (*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)) == 0) { 1274 CLR(sc->sc_mcr, sc->sc_dtr); 1275 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 1276 } 1277 if (ISSET(delta & msr, MSR_CTS) && 1278 ISSET(tp->t_cflag, CRTSCTS)) { 1279 /* the line is up and we want to do rts/cts flow control */ 1280 (*linesw[tp->t_line].l_start)(tp); 1281 } 1282 } 1283 1284 if (ISSET(lsr, LSR_TXRDY) && ISSET(tp->t_state, TS_BUSY)) { 1285 CLR(tp->t_state, TS_BUSY | TS_FLUSH); 1286 if (sc->sc_halt > 0) 1287 wakeup(&tp->t_outq); 1288 (*linesw[tp->t_line].l_start)(tp); 1289 } 1290 1291 #ifdef COM_DEBUG 1292 if (++n >= 32) 1293 goto ohfudge; 1294 if (ISSET(iter[n].iir = bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND)) 1295 return (1); 1296 #else 1297 if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_NOPEND)) 1298 return (1); 1299 #endif 1300 } 1301 #ifdef COM_DEBUG 1302 ohfudge: 1303 printf("comintr: too many iterations"); 1304 for (n = 0; n < 32; n++) { 1305 if ((n % 4) == 0) 1306 printf("\ncomintr: iter[%02d]", n); 1307 printf(" %02x %02x %02x", iter[n].iir, iter[n].lsr, iter[n].msr); 1308 } 1309 printf("\n"); 1310 printf("comintr: msr %02x mcr %02x lcr %02x ier %02x\n", 1311 sc->sc_msr, sc->sc_mcr, sc->sc_lcr, sc->sc_ier); 1312 printf("comintr: state %08x cc %d\n", sc->sc_tty->t_state, 1313 sc->sc_tty->t_outq.c_cc); 1314 #endif 1315 } 1316 1317 /* 1318 * Following are all routines needed for COM to act as console 1319 */ 1320 #include <dev/cons.h> 1321 1322 void 1323 comcnprobe(cp) 1324 struct consdev *cp; 1325 { 1326 /* XXX NEEDS TO BE FIXED XXX */ 1327 bus_chipset_tag_t bc = 0; 1328 bus_io_handle_t ioh; 1329 int found; 1330 1331 if (bus_io_map(bc, CONADDR, COM_NPORTS, &ioh)) { 1332 cp->cn_pri = CN_DEAD; 1333 return; 1334 } 1335 found = comprobe1(bc, ioh, CONADDR); 1336 bus_io_unmap(bc, ioh, COM_NPORTS); 1337 if (!found) { 1338 cp->cn_pri = CN_DEAD; 1339 return; 1340 } 1341 1342 /* locate the major number */ 1343 for (commajor = 0; commajor < nchrdev; commajor++) 1344 if (cdevsw[commajor].d_open == comopen) 1345 break; 1346 1347 /* initialize required fields */ 1348 cp->cn_dev = makedev(commajor, CONUNIT); 1349 #ifdef COMCONSOLE 1350 cp->cn_pri = CN_REMOTE; /* Force a serial port console */ 1351 #else 1352 cp->cn_pri = CN_NORMAL; 1353 #endif 1354 } 1355 1356 void 1357 comcninit(cp) 1358 struct consdev *cp; 1359 { 1360 1361 #if 0 1362 XXX NEEDS TO BE FIXED XXX 1363 comconsbc = ???; 1364 #endif 1365 if (bus_io_map(comconsbc, CONADDR, COM_NPORTS, &comconsioh)) 1366 panic("comcninit: mapping failed"); 1367 1368 cominit(comconsbc, comconsioh, comdefaultrate); 1369 comconsaddr = CONADDR; 1370 comconsinit = 0; 1371 } 1372 1373 void 1374 cominit(bc, ioh, rate) 1375 bus_chipset_tag_t bc; 1376 bus_io_handle_t ioh; 1377 int rate; 1378 { 1379 int s = splhigh(); 1380 u_char stat; 1381 1382 bus_io_write_1(bc, ioh, com_lcr, LCR_DLAB); 1383 rate = comspeed(comdefaultrate); 1384 bus_io_write_1(bc, ioh, com_dlbl, rate); 1385 bus_io_write_1(bc, ioh, com_dlbh, rate >> 8); 1386 bus_io_write_1(bc, ioh, com_lcr, LCR_8BITS); 1387 bus_io_write_1(bc, ioh, com_ier, IER_ERXRDY | IER_ETXRDY); 1388 bus_io_write_1(bc, ioh, com_fifo, FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_4); 1389 stat = bus_io_read_1(bc, ioh, com_iir); 1390 splx(s); 1391 } 1392 1393 int 1394 comcngetc(dev) 1395 dev_t dev; 1396 { 1397 int s = splhigh(); 1398 bus_chipset_tag_t bc = comconsbc; 1399 bus_io_handle_t ioh = comconsioh; 1400 u_char stat, c; 1401 1402 while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY)) 1403 ; 1404 c = bus_io_read_1(bc, ioh, com_data); 1405 stat = bus_io_read_1(bc, ioh, com_iir); 1406 splx(s); 1407 return c; 1408 } 1409 1410 /* 1411 * Console kernel output character routine. 1412 */ 1413 void 1414 comcnputc(dev, c) 1415 dev_t dev; 1416 int c; 1417 { 1418 int s = splhigh(); 1419 bus_chipset_tag_t bc = comconsbc; 1420 bus_io_handle_t ioh = comconsioh; 1421 u_char stat; 1422 register int timo; 1423 1424 #ifdef KGDB 1425 if (dev != kgdb_dev) 1426 #endif 1427 if (comconsinit == 0) { 1428 cominit(bc, ioh, comdefaultrate); 1429 comconsinit = 1; 1430 } 1431 /* wait for any pending transmission to finish */ 1432 timo = 50000; 1433 while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo) 1434 ; 1435 bus_io_write_1(bc, ioh, com_data, c); 1436 /* wait for this transmission to complete */ 1437 timo = 1500000; 1438 while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo) 1439 ; 1440 /* clear any interrupts generated by this transmission */ 1441 stat = bus_io_read_1(bc, ioh, com_iir); 1442 splx(s); 1443 } 1444 1445 void 1446 comcnpollc(dev, on) 1447 dev_t dev; 1448 int on; 1449 { 1450 1451 } 1452
Indexes created Mon Sep 22 13:09:51 GMT 2025