com.c revision 1.88
1 /* $NetBSD: com.c,v 1.88 1996/10/06 01:52:26 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1993, 1994, 1995, 1996 5 * Charles M. Hannum. All rights reserved. 6 * Copyright (c) 1991 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)com.c 7.5 (Berkeley) 5/16/91 38 */ 39 40 /* 41 * COM driver, based on HP dca driver 42 * uses National Semiconductor NS16450/NS16550AF UART 43 */ 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/ioctl.h> 47 #include <sys/select.h> 48 #include <sys/tty.h> 49 #include <sys/proc.h> 50 #include <sys/user.h> 51 #include <sys/conf.h> 52 #include <sys/file.h> 53 #include <sys/uio.h> 54 #include <sys/kernel.h> 55 #include <sys/syslog.h> 56 #include <sys/types.h> 57 #include <sys/device.h> 58 59 #include <machine/bus.h> 60 #include <machine/intr.h> 61 62 #include <dev/isa/isavar.h> 63 #include <dev/isa/comreg.h> 64 #include <dev/isa/comvar.h> 65 #include <dev/ic/ns16550reg.h> 66 #ifdef COM_HAYESP 67 #include <dev/ic/hayespreg.h> 68 #endif 69 #define com_lcr com_cfcr 70 71 #include "com.h" 72 73 74 #define COM_IBUFSIZE (2 * 512) 75 #define COM_IHIGHWATER ((3 * COM_IBUFSIZE) / 4) 76 77 struct com_softc { 78 struct device sc_dev; 79 void *sc_ih; 80 struct tty *sc_tty; 81 82 int sc_overflows; 83 int sc_floods; 84 int sc_failures; 85 int sc_errors; 86 87 int sc_halt; 88 89 int sc_iobase; 90 #ifdef COM_HAYESP 91 int sc_hayespbase; 92 #endif 93 94 bus_chipset_tag_t sc_bc; 95 bus_io_handle_t sc_ioh; 96 bus_io_handle_t sc_hayespioh; 97 98 u_char sc_hwflags; 99 #define COM_HW_NOIEN 0x01 100 #define COM_HW_FIFO 0x02 101 #define COM_HW_HAYESP 0x04 102 #define COM_HW_CONSOLE 0x40 103 u_char sc_swflags; 104 #define COM_SW_SOFTCAR 0x01 105 #define COM_SW_CLOCAL 0x02 106 #define COM_SW_CRTSCTS 0x04 107 #define COM_SW_MDMBUF 0x08 108 u_char sc_msr, sc_mcr, sc_lcr, sc_ier; 109 u_char sc_dtr; 110 111 u_char *sc_ibuf, *sc_ibufp, *sc_ibufhigh, *sc_ibufend; 112 u_char sc_ibufs[2][COM_IBUFSIZE]; 113 }; 114 115 #ifdef COM_HAYESP 116 int comprobeHAYESP __P((bus_io_handle_t hayespioh, struct com_softc *sc)); 117 #endif 118 void comdiag __P((void *)); 119 int comspeed __P((long)); 120 int comparam __P((struct tty *, struct termios *)); 121 void comstart __P((struct tty *)); 122 void comsoft __P((void *)); 123 124 /* XXX: These belong elsewhere */ 125 cdev_decl(com); 126 bdev_decl(com); 127 128 struct consdev; 129 void comcnprobe __P((struct consdev *)); 130 void comcninit __P((struct consdev *)); 131 int comcngetc __P((dev_t)); 132 void comcnputc __P((dev_t, int)); 133 void comcnpollc __P((dev_t, int)); 134 135 static u_char tiocm_xxx2mcr __P((int)); 136 137 /* 138 * XXX the following two cfattach structs should be different, and possibly 139 * XXX elsewhere. 140 */ 141 int comprobe __P((struct device *, void *, void *)); 142 void comattach __P((struct device *, struct device *, void *)); 143 144 #if NCOM_ISA 145 struct cfattach com_isa_ca = { 146 sizeof(struct com_softc), comprobe, comattach 147 }; 148 #endif 149 150 #if NCOM_COMMULTI 151 struct cfattach com_commulti_ca = { 152 sizeof(struct com_softc), comprobe, comattach 153 }; 154 #endif 155 156 struct cfdriver com_cd = { 157 NULL, "com", DV_TTY 158 }; 159 160 void cominit __P((bus_chipset_tag_t, bus_io_handle_t, int)); 161 162 #ifdef COMCONSOLE 163 int comdefaultrate = CONSPEED; /* XXX why set default? */ 164 #else 165 int comdefaultrate = TTYDEF_SPEED; 166 #endif 167 int comconsaddr; 168 int comconsinit; 169 int comconsattached; 170 bus_chipset_tag_t comconsbc; 171 bus_io_handle_t comconsioh; 172 tcflag_t comconscflag = TTYDEF_CFLAG; 173 174 int commajor; 175 int comsopen = 0; 176 int comevents = 0; 177 178 #ifdef KGDB 179 #include <machine/remote-sl.h> 180 extern int kgdb_dev; 181 extern int kgdb_rate; 182 extern int kgdb_debug_init; 183 #endif 184 185 #define COMUNIT(x) (minor(x)) 186 187 /* Macros to clear/set/test flags. */ 188 #define SET(t, f) (t) |= (f) 189 #define CLR(t, f) (t) &= ~(f) 190 #define ISSET(t, f) ((t) & (f)) 191 192 int 193 comspeed(speed) 194 long speed; 195 { 196 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 197 198 int x, err; 199 200 if (speed == 0) 201 return 0; 202 if (speed < 0) 203 return -1; 204 x = divrnd((COM_FREQ / 16), speed); 205 if (x <= 0) 206 return -1; 207 err = divrnd((COM_FREQ / 16) * 1000, speed * x) - 1000; 208 if (err < 0) 209 err = -err; 210 if (err > COM_TOLERANCE) 211 return -1; 212 return x; 213 214 #undef divrnd(n, q) 215 } 216 217 int 218 comprobe1(bc, ioh, iobase) 219 bus_chipset_tag_t bc; 220 bus_io_handle_t ioh; 221 int iobase; 222 { 223 224 /* force access to id reg */ 225 bus_io_write_1(bc, ioh, com_lcr, 0); 226 bus_io_write_1(bc, ioh, com_iir, 0); 227 if (bus_io_read_1(bc, ioh, com_iir) & 0x38) 228 return 0; 229 230 return 1; 231 } 232 233 #ifdef COM_HAYESP 234 int 235 comprobeHAYESP(hayespioh, sc) 236 bus_io_handle_t hayespioh; 237 struct com_softc *sc; 238 { 239 char val, dips; 240 int combaselist[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; 241 bus_chipset_tag_t bc = sc->sc_bc; 242 243 /* 244 * Hayes ESP cards have two iobases. One is for compatibility with 245 * 16550 serial chips, and at the same ISA PC base addresses. The 246 * other is for ESP-specific enhanced features, and lies at a 247 * different addressing range entirely (0x140, 0x180, 0x280, or 0x300). 248 */ 249 250 /* Test for ESP signature */ 251 if ((bus_io_read_1(bc, hayespioh, 0) & 0xf3) == 0) 252 return 0; 253 254 /* 255 * ESP is present at ESP enhanced base address; unknown com port 256 */ 257 258 /* Get the dip-switch configurations */ 259 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETDIPS); 260 dips = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1); 261 262 /* Determine which com port this ESP card services: bits 0,1 of */ 263 /* dips is the port # (0-3); combaselist[val] is the com_iobase */ 264 if (sc->sc_iobase != combaselist[dips & 0x03]) 265 return 0; 266 267 printf(": ESP"); 268 269 /* Check ESP Self Test bits. */ 270 /* Check for ESP version 2.0: bits 4,5,6 == 010 */ 271 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_GETTEST); 272 val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS1); /* Clear reg 1 */ 273 val = bus_io_read_1(bc, hayespioh, HAYESP_STATUS2); 274 if ((val & 0x70) < 0x20) { 275 printf("-old (%o)", val & 0x70); 276 /* we do not support the necessary features */ 277 return 0; 278 } 279 280 /* Check for ability to emulate 16550: bit 8 == 1 */ 281 if ((dips & 0x80) == 0) { 282 printf(" slave"); 283 /* XXX Does slave really mean no 16550 support?? */ 284 return 0; 285 } 286 287 /* 288 * If we made it this far, we are a full-featured ESP v2.0 (or 289 * better), at the correct com port address. 290 */ 291 292 SET(sc->sc_hwflags, COM_HW_HAYESP); 293 printf(", 1024 byte fifo\n"); 294 return 1; 295 } 296 #endif 297 298 int 299 comprobe(parent, match, aux) 300 struct device *parent; 301 void *match, *aux; 302 { 303 bus_chipset_tag_t bc; 304 bus_io_handle_t ioh; 305 int iobase, needioh; 306 int rv = 1; 307 308 /* 309 * XXX should be broken out into functions for isa probe and 310 * XXX for commulti probe, with a helper function that contains 311 * XXX most of the interesting stuff. 312 */ 313 #if NCOM_ISA 314 if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) { 315 struct isa_attach_args *ia = aux; 316 317 bc = ia->ia_bc; 318 iobase = ia->ia_iobase; 319 needioh = 1; 320 } else 321 #endif 322 #if NCOM_COMMULTI 323 if (1) { 324 struct cfdata *cf = match; 325 struct commulti_attach_args *ca = aux; 326 327 if (cf->cf_loc[0] != -1 && cf->cf_loc[0] != ca->ca_slave) 328 return (0); 329 330 bc = ca->ca_bc; 331 iobase = ca->ca_iobase; 332 ioh = ca->ca_ioh; 333 needioh = 0; 334 } else 335 #endif 336 return(0); /* This cannot happen */ 337 338 /* if it's in use as console, it's there. */ 339 if (iobase == comconsaddr && !comconsattached) 340 goto out; 341 342 if (needioh && bus_io_map(bc, iobase, COM_NPORTS, &ioh)) { 343 rv = 0; 344 goto out; 345 } 346 rv = comprobe1(bc, ioh, iobase); 347 if (needioh) 348 bus_io_unmap(bc, ioh, COM_NPORTS); 349 350 out: 351 #if NCOM_ISA 352 if (rv && !strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) { 353 struct isa_attach_args *ia = aux; 354 355 ia->ia_iosize = COM_NPORTS; 356 ia->ia_msize = 0; 357 } 358 #endif 359 return (rv); 360 } 361 362 void 363 comattach(parent, self, aux) 364 struct device *parent, *self; 365 void *aux; 366 { 367 struct com_softc *sc = (void *)self; 368 int iobase, irq; 369 bus_chipset_tag_t bc; 370 bus_io_handle_t ioh; 371 #ifdef COM_HAYESP 372 int hayesp_ports[] = { 0x140, 0x180, 0x280, 0x300, 0 }; 373 int *hayespp; 374 #endif 375 376 /* 377 * XXX should be broken out into functions for isa attach and 378 * XXX for commulti attach, with a helper function that contains 379 * XXX most of the interesting stuff. 380 */ 381 sc->sc_hwflags = 0; 382 sc->sc_swflags = 0; 383 #if NCOM_ISA 384 if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) { 385 struct isa_attach_args *ia = aux; 386 387 /* 388 * We're living on an isa. 389 */ 390 iobase = ia->ia_iobase; 391 bc = ia->ia_bc; 392 if (iobase != comconsaddr) { 393 if (bus_io_map(bc, iobase, COM_NPORTS, &ioh)) 394 panic("comattach: io mapping failed"); 395 } else 396 ioh = comconsioh; 397 irq = ia->ia_irq; 398 } else 399 #endif 400 #if NCOM_COMMULTI 401 if (1) { 402 struct commulti_attach_args *ca = aux; 403 404 /* 405 * We're living on a commulti. 406 */ 407 iobase = ca->ca_iobase; 408 bc = ca->ca_bc; 409 ioh = ca->ca_ioh; 410 irq = IRQUNK; 411 412 if (ca->ca_noien) 413 sc->sc_hwflags |= COM_HW_NOIEN; 414 } else 415 #endif 416 panic("comattach: impossible"); 417 418 sc->sc_bc = bc; 419 sc->sc_ioh = ioh; 420 sc->sc_iobase = iobase; 421 422 if (iobase == comconsaddr) { 423 comconsattached = 1; 424 425 /* 426 * Need to reset baud rate, etc. of next print so reset 427 * comconsinit. Also make sure console is always "hardwired". 428 */ 429 delay(1000); /* wait for output to finish */ 430 comconsinit = 0; 431 SET(sc->sc_hwflags, COM_HW_CONSOLE); 432 SET(sc->sc_swflags, COM_SW_SOFTCAR); 433 } 434 435 #ifdef COM_HAYESP 436 /* Look for a Hayes ESP board. */ 437 for (hayespp = hayesp_ports; *hayespp != 0; hayespp++) { 438 bus_io_handle_t hayespioh; 439 440 #define HAYESP_NPORTS 8 /* XXX XXX XXX ??? ??? ??? */ 441 if (bus_io_map(bc, *hayespp, HAYESP_NPORTS, &hayespioh)) 442 continue; 443 if (comprobeHAYESP(hayespioh, sc)) { 444 sc->sc_hayespbase = *hayespp; 445 sc->sc_hayespioh = hayespioh; 446 break; 447 } 448 bus_io_unmap(bc, hayespioh, HAYESP_NPORTS); 449 } 450 /* No ESP; look for other things. */ 451 if (*hayespp == 0) { 452 #endif 453 454 /* look for a NS 16550AF UART with FIFOs */ 455 bus_io_write_1(bc, ioh, com_fifo, 456 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14); 457 delay(100); 458 if (ISSET(bus_io_read_1(bc, ioh, com_iir), IIR_FIFO_MASK) == IIR_FIFO_MASK) 459 if (ISSET(bus_io_read_1(bc, ioh, com_fifo), FIFO_TRIGGER_14) == FIFO_TRIGGER_14) { 460 SET(sc->sc_hwflags, COM_HW_FIFO); 461 printf(": ns16550a, working fifo\n"); 462 } else 463 printf(": ns16550, broken fifo\n"); 464 else 465 printf(": ns8250 or ns16450, no fifo\n"); 466 bus_io_write_1(bc, ioh, com_fifo, 0); 467 #ifdef COM_HAYESP 468 } 469 #endif 470 471 /* disable interrupts */ 472 bus_io_write_1(bc, ioh, com_ier, 0); 473 bus_io_write_1(bc, ioh, com_mcr, 0); 474 475 if (irq != IRQUNK) { 476 #if NCOM_ISA 477 if (!strcmp(parent->dv_cfdata->cf_driver->cd_name, "isa")) { 478 struct isa_attach_args *ia = aux; 479 480 sc->sc_ih = isa_intr_establish(ia->ia_ic, irq, 481 IST_EDGE, IPL_TTY, comintr, sc); 482 } else 483 #endif 484 panic("comattach: IRQ but can't have one"); 485 } 486 487 #ifdef KGDB 488 if (kgdb_dev == makedev(commajor, unit)) { 489 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 490 kgdb_dev = -1; /* can't debug over console port */ 491 else { 492 cominit(bc, ioh, kgdb_rate); 493 if (kgdb_debug_init) { 494 /* 495 * Print prefix of device name, 496 * let kgdb_connect print the rest. 497 */ 498 printf("%s: ", sc->sc_dev.dv_xname); 499 kgdb_connect(1); 500 } else 501 printf("%s: kgdb enabled\n", 502 sc->sc_dev.dv_xname); 503 } 504 } 505 #endif 506 507 /* XXX maybe move up some? */ 508 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 509 printf("%s: console\n", sc->sc_dev.dv_xname); 510 } 511 512 int 513 comopen(dev, flag, mode, p) 514 dev_t dev; 515 int flag, mode; 516 struct proc *p; 517 { 518 int unit = COMUNIT(dev); 519 struct com_softc *sc; 520 bus_chipset_tag_t bc; 521 bus_io_handle_t ioh; 522 struct tty *tp; 523 int s; 524 int error = 0; 525 526 if (unit >= com_cd.cd_ndevs) 527 return ENXIO; 528 sc = com_cd.cd_devs[unit]; 529 if (!sc) 530 return ENXIO; 531 532 if (!sc->sc_tty) { 533 tp = sc->sc_tty = ttymalloc(); 534 tty_attach(tp); 535 } else 536 tp = sc->sc_tty; 537 538 tp->t_oproc = comstart; 539 tp->t_param = comparam; 540 tp->t_dev = dev; 541 if (!ISSET(tp->t_state, TS_ISOPEN)) { 542 SET(tp->t_state, TS_WOPEN); 543 ttychars(tp); 544 tp->t_iflag = TTYDEF_IFLAG; 545 tp->t_oflag = TTYDEF_OFLAG; 546 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 547 tp->t_cflag = comconscflag; 548 else 549 tp->t_cflag = TTYDEF_CFLAG; 550 if (ISSET(sc->sc_swflags, COM_SW_CLOCAL)) 551 SET(tp->t_cflag, CLOCAL); 552 if (ISSET(sc->sc_swflags, COM_SW_CRTSCTS)) 553 SET(tp->t_cflag, CRTSCTS); 554 if (ISSET(sc->sc_swflags, COM_SW_MDMBUF)) 555 SET(tp->t_cflag, MDMBUF); 556 tp->t_lflag = TTYDEF_LFLAG; 557 tp->t_ispeed = tp->t_ospeed = comdefaultrate; 558 559 s = spltty(); 560 561 comparam(tp, &tp->t_termios); 562 ttsetwater(tp); 563 564 if (comsopen++ == 0) 565 timeout(comsoft, NULL, 1); 566 567 sc->sc_ibufp = sc->sc_ibuf = sc->sc_ibufs[0]; 568 sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER; 569 sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE; 570 571 bc = sc->sc_bc; 572 ioh = sc->sc_ioh; 573 #ifdef COM_HAYESP 574 /* Setup the ESP board */ 575 if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) { 576 bus_io_handle_t hayespioh = sc->sc_hayespioh; 577 578 bus_io_write_1(bc, ioh, com_fifo, 579 FIFO_DMA_MODE|FIFO_ENABLE| 580 FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_8); 581 582 /* Set 16550 compatibility mode */ 583 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETMODE); 584 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 585 HAYESP_MODE_FIFO|HAYESP_MODE_RTS| 586 HAYESP_MODE_SCALE); 587 588 /* Set RTS/CTS flow control */ 589 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETFLOWTYPE); 590 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_RTS); 591 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, HAYESP_FLOW_CTS); 592 593 /* Set flow control levels */ 594 bus_io_write_1(bc, hayespioh, HAYESP_CMD1, HAYESP_SETRXFLOW); 595 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 596 HAYESP_HIBYTE(HAYESP_RXHIWMARK)); 597 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 598 HAYESP_LOBYTE(HAYESP_RXHIWMARK)); 599 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 600 HAYESP_HIBYTE(HAYESP_RXLOWMARK)); 601 bus_io_write_1(bc, hayespioh, HAYESP_CMD2, 602 HAYESP_LOBYTE(HAYESP_RXLOWMARK)); 603 } else 604 #endif 605 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) 606 /* Set the FIFO threshold based on the receive speed. */ 607 bus_io_write_1(bc, ioh, com_fifo, 608 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | 609 (tp->t_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8)); 610 /* flush any pending I/O */ 611 while (ISSET(bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY)) 612 (void) bus_io_read_1(bc, ioh, com_data); 613 /* you turn me on, baby */ 614 sc->sc_mcr = MCR_DTR | MCR_RTS; 615 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN)) 616 SET(sc->sc_mcr, MCR_IENABLE); 617 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 618 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC; 619 bus_io_write_1(bc, ioh, com_ier, sc->sc_ier); 620 621 sc->sc_msr = bus_io_read_1(bc, ioh, com_msr); 622 if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR) || 623 ISSET(sc->sc_msr, MSR_DCD) || ISSET(tp->t_cflag, MDMBUF)) 624 SET(tp->t_state, TS_CARR_ON); 625 else 626 CLR(tp->t_state, TS_CARR_ON); 627 } else if (ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0) 628 return EBUSY; 629 else 630 s = spltty(); 631 632 /* wait for carrier if necessary */ 633 if (!ISSET(flag, O_NONBLOCK)) 634 while (!ISSET(tp->t_cflag, CLOCAL) && 635 !ISSET(tp->t_state, TS_CARR_ON)) { 636 SET(tp->t_state, TS_WOPEN); 637 error = ttysleep(tp, &tp->t_rawq, TTIPRI | PCATCH, 638 ttopen, 0); 639 if (error) { 640 /* XXX should turn off chip if we're the 641 only waiter */ 642 splx(s); 643 return error; 644 } 645 } 646 splx(s); 647 648 return (*linesw[tp->t_line].l_open)(dev, tp); 649 } 650 651 int 652 comclose(dev, flag, mode, p) 653 dev_t dev; 654 int flag, mode; 655 struct proc *p; 656 { 657 int unit = COMUNIT(dev); 658 struct com_softc *sc = com_cd.cd_devs[unit]; 659 struct tty *tp = sc->sc_tty; 660 bus_chipset_tag_t bc = sc->sc_bc; 661 bus_io_handle_t ioh = sc->sc_ioh; 662 int s; 663 664 /* XXX This is for cons.c. */ 665 if (!ISSET(tp->t_state, TS_ISOPEN)) 666 return 0; 667 668 (*linesw[tp->t_line].l_close)(tp, flag); 669 s = spltty(); 670 CLR(sc->sc_lcr, LCR_SBREAK); 671 bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr); 672 bus_io_write_1(bc, ioh, com_ier, 0); 673 if (ISSET(tp->t_cflag, HUPCL) && 674 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR)) { 675 /* XXX perhaps only clear DTR */ 676 bus_io_write_1(bc, ioh, com_mcr, 0); 677 bus_io_write_1(bc, ioh, com_fifo, FIFO_RCV_RST | FIFO_XMT_RST); 678 } 679 CLR(tp->t_state, TS_BUSY | TS_FLUSH); 680 if (--comsopen == 0) 681 untimeout(comsoft, NULL); 682 splx(s); 683 ttyclose(tp); 684 #ifdef notyet /* XXXX */ 685 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) { 686 ttyfree(tp); 687 sc->sc_tty = 0; 688 } 689 #endif 690 return 0; 691 } 692 693 int 694 comread(dev, uio, flag) 695 dev_t dev; 696 struct uio *uio; 697 int flag; 698 { 699 struct com_softc *sc = com_cd.cd_devs[COMUNIT(dev)]; 700 struct tty *tp = sc->sc_tty; 701 702 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 703 } 704 705 int 706 comwrite(dev, uio, flag) 707 dev_t dev; 708 struct uio *uio; 709 int flag; 710 { 711 struct com_softc *sc = com_cd.cd_devs[COMUNIT(dev)]; 712 struct tty *tp = sc->sc_tty; 713 714 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 715 } 716 717 struct tty * 718 comtty(dev) 719 dev_t dev; 720 { 721 struct com_softc *sc = com_cd.cd_devs[COMUNIT(dev)]; 722 struct tty *tp = sc->sc_tty; 723 724 return (tp); 725 } 726 727 static u_char 728 tiocm_xxx2mcr(data) 729 int data; 730 { 731 u_char m = 0; 732 733 if (ISSET(data, TIOCM_DTR)) 734 SET(m, MCR_DTR); 735 if (ISSET(data, TIOCM_RTS)) 736 SET(m, MCR_RTS); 737 return m; 738 } 739 740 int 741 comioctl(dev, cmd, data, flag, p) 742 dev_t dev; 743 u_long cmd; 744 caddr_t data; 745 int flag; 746 struct proc *p; 747 { 748 int unit = COMUNIT(dev); 749 struct com_softc *sc = com_cd.cd_devs[unit]; 750 struct tty *tp = sc->sc_tty; 751 bus_chipset_tag_t bc = sc->sc_bc; 752 bus_io_handle_t ioh = sc->sc_ioh; 753 int error; 754 755 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 756 if (error >= 0) 757 return error; 758 error = ttioctl(tp, cmd, data, flag, p); 759 if (error >= 0) 760 return error; 761 762 switch (cmd) { 763 case TIOCSBRK: 764 SET(sc->sc_lcr, LCR_SBREAK); 765 bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr); 766 break; 767 case TIOCCBRK: 768 CLR(sc->sc_lcr, LCR_SBREAK); 769 bus_io_write_1(bc, ioh, com_lcr, sc->sc_lcr); 770 break; 771 case TIOCSDTR: 772 SET(sc->sc_mcr, sc->sc_dtr); 773 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 774 break; 775 case TIOCCDTR: 776 CLR(sc->sc_mcr, sc->sc_dtr); 777 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 778 break; 779 case TIOCMSET: 780 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS); 781 case TIOCMBIS: 782 SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data)); 783 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 784 break; 785 case TIOCMBIC: 786 CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data)); 787 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 788 break; 789 case TIOCMGET: { 790 u_char m; 791 int bits = 0; 792 793 m = sc->sc_mcr; 794 if (ISSET(m, MCR_DTR)) 795 SET(bits, TIOCM_DTR); 796 if (ISSET(m, MCR_RTS)) 797 SET(bits, TIOCM_RTS); 798 m = sc->sc_msr; 799 if (ISSET(m, MSR_DCD)) 800 SET(bits, TIOCM_CD); 801 if (ISSET(m, MSR_CTS)) 802 SET(bits, TIOCM_CTS); 803 if (ISSET(m, MSR_DSR)) 804 SET(bits, TIOCM_DSR); 805 if (ISSET(m, MSR_RI | MSR_TERI)) 806 SET(bits, TIOCM_RI); 807 if (bus_io_read_1(bc, ioh, com_ier)) 808 SET(bits, TIOCM_LE); 809 *(int *)data = bits; 810 break; 811 } 812 case TIOCGFLAGS: { 813 int driverbits, userbits = 0; 814 815 driverbits = sc->sc_swflags; 816 if (ISSET(driverbits, COM_SW_SOFTCAR)) 817 SET(userbits, TIOCFLAG_SOFTCAR); 818 if (ISSET(driverbits, COM_SW_CLOCAL)) 819 SET(userbits, TIOCFLAG_CLOCAL); 820 if (ISSET(driverbits, COM_SW_CRTSCTS)) 821 SET(userbits, TIOCFLAG_CRTSCTS); 822 if (ISSET(driverbits, COM_SW_MDMBUF)) 823 SET(userbits, TIOCFLAG_MDMBUF); 824 825 *(int *)data = userbits; 826 break; 827 } 828 case TIOCSFLAGS: { 829 int userbits, driverbits = 0; 830 831 error = suser(p->p_ucred, &p->p_acflag); 832 if (error != 0) 833 return(EPERM); 834 835 userbits = *(int *)data; 836 if (ISSET(userbits, TIOCFLAG_SOFTCAR) || 837 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) 838 SET(driverbits, COM_SW_SOFTCAR); 839 if (ISSET(userbits, TIOCFLAG_CLOCAL)) 840 SET(driverbits, COM_SW_CLOCAL); 841 if (ISSET(userbits, TIOCFLAG_CRTSCTS)) 842 SET(driverbits, COM_SW_CRTSCTS); 843 if (ISSET(userbits, TIOCFLAG_MDMBUF)) 844 SET(driverbits, COM_SW_MDMBUF); 845 846 sc->sc_swflags = driverbits; 847 break; 848 } 849 default: 850 return ENOTTY; 851 } 852 853 return 0; 854 } 855 856 int 857 comparam(tp, t) 858 struct tty *tp; 859 struct termios *t; 860 { 861 struct com_softc *sc = com_cd.cd_devs[COMUNIT(tp->t_dev)]; 862 bus_chipset_tag_t bc = sc->sc_bc; 863 bus_io_handle_t ioh = sc->sc_ioh; 864 int ospeed = comspeed(t->c_ospeed); 865 u_char lcr; 866 tcflag_t oldcflag; 867 int s; 868 869 /* check requested parameters */ 870 if (ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed)) 871 return EINVAL; 872 873 lcr = ISSET(sc->sc_lcr, LCR_SBREAK); 874 875 switch (ISSET(t->c_cflag, CSIZE)) { 876 case CS5: 877 SET(lcr, LCR_5BITS); 878 break; 879 case CS6: 880 SET(lcr, LCR_6BITS); 881 break; 882 case CS7: 883 SET(lcr, LCR_7BITS); 884 break; 885 case CS8: 886 SET(lcr, LCR_8BITS); 887 break; 888 } 889 if (ISSET(t->c_cflag, PARENB)) { 890 SET(lcr, LCR_PENAB); 891 if (!ISSET(t->c_cflag, PARODD)) 892 SET(lcr, LCR_PEVEN); 893 } 894 if (ISSET(t->c_cflag, CSTOPB)) 895 SET(lcr, LCR_STOPB); 896 897 sc->sc_lcr = lcr; 898 899 s = spltty(); 900 901 if (ospeed == 0) { 902 CLR(sc->sc_mcr, MCR_DTR); 903 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 904 } 905 906 /* 907 * Set the FIFO threshold based on the receive speed, if we are 908 * changing it. 909 */ 910 #if 1 911 if (tp->t_ispeed != t->c_ispeed) { 912 #else 913 if (1) { 914 #endif 915 if (ospeed != 0) { 916 /* 917 * Make sure the transmit FIFO is empty before 918 * proceeding. If we don't do this, some revisions 919 * of the UART will hang. Interestingly enough, 920 * even if we do this will the last character is 921 * still being pushed out, they don't hang. This 922 * seems good enough. 923 */ 924 while (ISSET(tp->t_state, TS_BUSY)) { 925 int error; 926 927 ++sc->sc_halt; 928 error = ttysleep(tp, &tp->t_outq, 929 TTOPRI | PCATCH, "comprm", 0); 930 --sc->sc_halt; 931 if (error) { 932 splx(s); 933 comstart(tp); 934 return (error); 935 } 936 } 937 938 bus_io_write_1(bc, ioh, com_lcr, lcr | LCR_DLAB); 939 bus_io_write_1(bc, ioh, com_dlbl, ospeed); 940 bus_io_write_1(bc, ioh, com_dlbh, ospeed >> 8); 941 bus_io_write_1(bc, ioh, com_lcr, lcr); 942 SET(sc->sc_mcr, MCR_DTR); 943 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 944 } else 945 bus_io_write_1(bc, ioh, com_lcr, lcr); 946 947 if (!ISSET(sc->sc_hwflags, COM_HW_HAYESP) && 948 ISSET(sc->sc_hwflags, COM_HW_FIFO)) 949 bus_io_write_1(bc, ioh, com_fifo, 950 FIFO_ENABLE | 951 (t->c_ispeed <= 1200 ? FIFO_TRIGGER_1 : FIFO_TRIGGER_8)); 952 } else 953 bus_io_write_1(bc, ioh, com_lcr, lcr); 954 955 /* When not using CRTSCTS, RTS follows DTR. */ 956 if (!ISSET(t->c_cflag, CRTSCTS)) { 957 if (ISSET(sc->sc_mcr, MCR_DTR)) { 958 if (!ISSET(sc->sc_mcr, MCR_RTS)) { 959 SET(sc->sc_mcr, MCR_RTS); 960 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 961 } 962 } else { 963 if (ISSET(sc->sc_mcr, MCR_RTS)) { 964 CLR(sc->sc_mcr, MCR_RTS); 965 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 966 } 967 } 968 sc->sc_dtr = MCR_DTR | MCR_RTS; 969 } else 970 sc->sc_dtr = MCR_DTR; 971 972 /* and copy to tty */ 973 tp->t_ispeed = t->c_ispeed; 974 tp->t_ospeed = t->c_ospeed; 975 oldcflag = tp->t_cflag; 976 tp->t_cflag = t->c_cflag; 977 978 /* 979 * If DCD is off and MDMBUF is changed, ask the tty layer if we should 980 * stop the device. 981 */ 982 if (!ISSET(sc->sc_msr, MSR_DCD) && 983 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR) && 984 ISSET(oldcflag, MDMBUF) != ISSET(tp->t_cflag, MDMBUF) && 985 (*linesw[tp->t_line].l_modem)(tp, 0) == 0) { 986 CLR(sc->sc_mcr, sc->sc_dtr); 987 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 988 } 989 990 /* Just to be sure... */ 991 splx(s); 992 comstart(tp); 993 return 0; 994 } 995 996 void 997 comstart(tp) 998 struct tty *tp; 999 { 1000 struct com_softc *sc = com_cd.cd_devs[COMUNIT(tp->t_dev)]; 1001 bus_chipset_tag_t bc = sc->sc_bc; 1002 bus_io_handle_t ioh = sc->sc_ioh; 1003 int s; 1004 1005 s = spltty(); 1006 if (ISSET(tp->t_state, TS_BUSY)) 1007 goto out; 1008 if (ISSET(tp->t_state, TS_TIMEOUT | TS_TTSTOP) || 1009 sc->sc_halt > 0) 1010 goto stopped; 1011 if (ISSET(tp->t_cflag, CRTSCTS) && !ISSET(sc->sc_msr, MSR_CTS)) 1012 goto stopped; 1013 if (tp->t_outq.c_cc <= tp->t_lowat) { 1014 if (ISSET(tp->t_state, TS_ASLEEP)) { 1015 CLR(tp->t_state, TS_ASLEEP); 1016 wakeup(&tp->t_outq); 1017 } 1018 if (tp->t_outq.c_cc == 0) 1019 goto stopped; 1020 selwakeup(&tp->t_wsel); 1021 } 1022 SET(tp->t_state, TS_BUSY); 1023 1024 if (!ISSET(sc->sc_ier, IER_ETXRDY)) { 1025 SET(sc->sc_ier, IER_ETXRDY); 1026 bus_io_write_1(bc, ioh, com_ier, sc->sc_ier); 1027 } 1028 #ifdef COM_HAYESP 1029 if (ISSET(sc->sc_hwflags, COM_HW_HAYESP)) { 1030 u_char buffer[1024], *cp = buffer; 1031 int n = q_to_b(&tp->t_outq, cp, sizeof buffer); 1032 do 1033 bus_io_write_1(bc, ioh, com_data, *cp++); 1034 while (--n); 1035 } 1036 else 1037 #endif 1038 if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) { 1039 u_char buffer[16], *cp = buffer; 1040 int n = q_to_b(&tp->t_outq, cp, sizeof buffer); 1041 do { 1042 bus_io_write_1(bc, ioh, com_data, *cp++); 1043 } while (--n); 1044 } else 1045 bus_io_write_1(bc, ioh, com_data, getc(&tp->t_outq)); 1046 out: 1047 splx(s); 1048 return; 1049 stopped: 1050 if (ISSET(sc->sc_ier, IER_ETXRDY)) { 1051 CLR(sc->sc_ier, IER_ETXRDY); 1052 bus_io_write_1(bc, ioh, com_ier, sc->sc_ier); 1053 } 1054 splx(s); 1055 } 1056 1057 /* 1058 * Stop output on a line. 1059 */ 1060 void 1061 comstop(tp, flag) 1062 struct tty *tp; 1063 int flag; 1064 { 1065 int s; 1066 1067 s = spltty(); 1068 if (ISSET(tp->t_state, TS_BUSY)) 1069 if (!ISSET(tp->t_state, TS_TTSTOP)) 1070 SET(tp->t_state, TS_FLUSH); 1071 splx(s); 1072 } 1073 1074 void 1075 comdiag(arg) 1076 void *arg; 1077 { 1078 struct com_softc *sc = arg; 1079 int overflows, floods, failures; 1080 int s; 1081 1082 s = spltty(); 1083 sc->sc_errors = 0; 1084 overflows = sc->sc_overflows; 1085 sc->sc_overflows = 0; 1086 floods = sc->sc_floods; 1087 sc->sc_floods = 0; 1088 failures = sc->sc_failures; 1089 sc->sc_failures = 0; 1090 splx(s); 1091 1092 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf overflow%s, %d uart failure%s\n", 1093 sc->sc_dev.dv_xname, 1094 overflows, overflows == 1 ? "" : "s", 1095 floods, floods == 1 ? "" : "s", 1096 failures, failures == 1 ? "" : "s"); 1097 } 1098 1099 void 1100 comsoft(arg) 1101 void *arg; 1102 { 1103 int unit; 1104 struct com_softc *sc; 1105 struct tty *tp; 1106 register u_char *ibufp; 1107 u_char *ibufend; 1108 register int c; 1109 int s; 1110 static int lsrmap[8] = { 1111 0, TTY_PE, 1112 TTY_FE, TTY_PE|TTY_FE, 1113 TTY_FE, TTY_PE|TTY_FE, 1114 TTY_FE, TTY_PE|TTY_FE 1115 }; 1116 1117 s = spltty(); 1118 if (comevents == 0) { 1119 splx(s); 1120 goto out; 1121 } 1122 comevents = 0; 1123 splx(s); 1124 1125 for (unit = 0; unit < com_cd.cd_ndevs; unit++) { 1126 sc = com_cd.cd_devs[unit]; 1127 if (sc == 0 || sc->sc_ibufp == sc->sc_ibuf) 1128 continue; 1129 1130 tp = sc->sc_tty; 1131 1132 s = spltty(); 1133 1134 ibufp = sc->sc_ibuf; 1135 ibufend = sc->sc_ibufp; 1136 1137 if (ibufp == ibufend) { 1138 splx(s); 1139 continue; 1140 } 1141 1142 sc->sc_ibufp = sc->sc_ibuf = (ibufp == sc->sc_ibufs[0]) ? 1143 sc->sc_ibufs[1] : sc->sc_ibufs[0]; 1144 sc->sc_ibufhigh = sc->sc_ibuf + COM_IHIGHWATER; 1145 sc->sc_ibufend = sc->sc_ibuf + COM_IBUFSIZE; 1146 1147 if (tp == 0 || !ISSET(tp->t_state, TS_ISOPEN)) { 1148 splx(s); 1149 continue; 1150 } 1151 1152 if (ISSET(tp->t_cflag, CRTSCTS) && 1153 !ISSET(sc->sc_mcr, MCR_RTS)) { 1154 /* XXX */ 1155 SET(sc->sc_mcr, MCR_RTS); 1156 bus_io_write_1(sc->sc_bc, sc->sc_ioh, com_mcr, 1157 sc->sc_mcr); 1158 } 1159 1160 splx(s); 1161 1162 while (ibufp < ibufend) { 1163 c = *ibufp++; 1164 if (*ibufp & LSR_OE) { 1165 sc->sc_overflows++; 1166 if (sc->sc_errors++ == 0) 1167 timeout(comdiag, sc, 60 * hz); 1168 } 1169 /* This is ugly, but fast. */ 1170 c |= lsrmap[(*ibufp++ & (LSR_BI|LSR_FE|LSR_PE)) >> 2]; 1171 (*linesw[tp->t_line].l_rint)(c, tp); 1172 } 1173 } 1174 1175 out: 1176 timeout(comsoft, NULL, 1); 1177 } 1178 1179 int 1180 comintr(arg) 1181 void *arg; 1182 { 1183 struct com_softc *sc = arg; 1184 bus_chipset_tag_t bc = sc->sc_bc; 1185 bus_io_handle_t ioh = sc->sc_ioh; 1186 struct tty *tp; 1187 u_char iir, lsr, data, msr, delta; 1188 #ifdef COM_DEBUG 1189 int n; 1190 struct { 1191 u_char iir, lsr, msr; 1192 } iter[32]; 1193 #endif 1194 1195 #ifdef COM_DEBUG 1196 n = 0; 1197 iter[n].iir = 1198 #endif 1199 iir = bus_io_read_1(bc, ioh, com_iir); 1200 if (ISSET(iir, IIR_NOPEND)) 1201 return (0); 1202 1203 tp = sc->sc_tty; 1204 1205 for (;;) { 1206 #ifdef COM_DEBUG 1207 iter[n].lsr = 1208 #endif 1209 lsr = bus_io_read_1(bc, ioh, com_lsr); 1210 1211 if (ISSET(lsr, LSR_RXRDY)) { 1212 register u_char *p = sc->sc_ibufp; 1213 1214 comevents = 1; 1215 do { 1216 data = bus_io_read_1(bc, ioh, com_data); 1217 if (ISSET(lsr, LSR_BI)) { 1218 #ifdef notdef 1219 printf("break %02x %02x %02x %02x\n", 1220 sc->sc_msr, sc->sc_mcr, sc->sc_lcr, 1221 sc->sc_dtr); 1222 #endif 1223 #ifdef DDB 1224 if (ISSET(sc->sc_hwflags, 1225 COM_HW_CONSOLE)) { 1226 Debugger(); 1227 goto next; 1228 } 1229 #endif 1230 } 1231 if (p >= sc->sc_ibufend) { 1232 sc->sc_floods++; 1233 if (sc->sc_errors++ == 0) 1234 timeout(comdiag, sc, 60 * hz); 1235 } else { 1236 *p++ = data; 1237 *p++ = lsr; 1238 if (p == sc->sc_ibufhigh && 1239 ISSET(tp->t_cflag, CRTSCTS)) { 1240 /* XXX */ 1241 CLR(sc->sc_mcr, MCR_RTS); 1242 bus_io_write_1(bc, ioh, 1243 com_mcr, sc->sc_mcr); 1244 } 1245 } 1246 #ifdef DDB 1247 next: 1248 #endif 1249 #ifdef COM_DEBUG 1250 if (++n >= 32) 1251 goto ohfudge; 1252 iter[n].lsr = 1253 #endif 1254 lsr = bus_io_read_1(bc, ioh, com_lsr); 1255 } while (ISSET(lsr, LSR_RXRDY)); 1256 1257 sc->sc_ibufp = p; 1258 } else { 1259 #ifdef COM_DEBUG 1260 if (ISSET(lsr, LSR_BI|LSR_FE|LSR_PE|LSR_OE)) 1261 printf("weird lsr %02x\n", lsr); 1262 #endif 1263 if ((iir & IIR_IMASK) == IIR_RXRDY) { 1264 sc->sc_failures++; 1265 if (sc->sc_errors++ == 0) 1266 timeout(comdiag, sc, 60 * hz); 1267 bus_io_write_1(bc, ioh, com_ier, 0); 1268 delay(10); 1269 bus_io_write_1(bc, ioh, com_ier, sc->sc_ier); 1270 iir = IIR_NOPEND; 1271 continue; 1272 } 1273 } 1274 1275 #ifdef COM_DEBUG 1276 iter[n].msr = 1277 #endif 1278 msr = bus_io_read_1(bc, ioh, com_msr); 1279 1280 if (msr != sc->sc_msr) { 1281 delta = msr ^ sc->sc_msr; 1282 sc->sc_msr = msr; 1283 if (ISSET(delta, MSR_DCD) && 1284 !ISSET(sc->sc_swflags, COM_SW_SOFTCAR) && 1285 (*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)) == 0) { 1286 CLR(sc->sc_mcr, sc->sc_dtr); 1287 bus_io_write_1(bc, ioh, com_mcr, sc->sc_mcr); 1288 } 1289 if (ISSET(delta & msr, MSR_CTS) && 1290 ISSET(tp->t_cflag, CRTSCTS)) { 1291 /* the line is up and we want to do rts/cts flow control */ 1292 (*linesw[tp->t_line].l_start)(tp); 1293 } 1294 } 1295 1296 if (ISSET(lsr, LSR_TXRDY) && ISSET(tp->t_state, TS_BUSY)) { 1297 CLR(tp->t_state, TS_BUSY | TS_FLUSH); 1298 if (sc->sc_halt > 0) 1299 wakeup(&tp->t_outq); 1300 (*linesw[tp->t_line].l_start)(tp); 1301 } 1302 1303 #ifdef COM_DEBUG 1304 if (++n >= 32) 1305 goto ohfudge; 1306 iter[n].iir = 1307 #endif 1308 iir = bus_io_read_1(bc, ioh, com_iir); 1309 if (ISSET(iir, IIR_NOPEND)) 1310 return (1); 1311 } 1312 1313 #ifdef COM_DEBUG 1314 ohfudge: 1315 printf("comintr: too many iterations"); 1316 for (n = 0; n < 32; n++) { 1317 if ((n % 4) == 0) 1318 printf("\ncomintr: iter[%02d]", n); 1319 printf(" %02x %02x %02x", iter[n].iir, iter[n].lsr, iter[n].msr); 1320 } 1321 printf("\n"); 1322 printf("comintr: msr %02x mcr %02x lcr %02x ier %02x\n", 1323 sc->sc_msr, sc->sc_mcr, sc->sc_lcr, sc->sc_ier); 1324 printf("comintr: state %08x cc %d\n", sc->sc_tty->t_state, 1325 sc->sc_tty->t_outq.c_cc); 1326 return (1); 1327 #endif 1328 } 1329 1330 /* 1331 * Following are all routines needed for COM to act as console 1332 */ 1333 #include <dev/cons.h> 1334 1335 void 1336 comcnprobe(cp) 1337 struct consdev *cp; 1338 { 1339 /* XXX NEEDS TO BE FIXED XXX */ 1340 bus_chipset_tag_t bc = 0; 1341 bus_io_handle_t ioh; 1342 int found; 1343 1344 if (bus_io_map(bc, CONADDR, COM_NPORTS, &ioh)) { 1345 cp->cn_pri = CN_DEAD; 1346 return; 1347 } 1348 found = comprobe1(bc, ioh, CONADDR); 1349 bus_io_unmap(bc, ioh, COM_NPORTS); 1350 if (!found) { 1351 cp->cn_pri = CN_DEAD; 1352 return; 1353 } 1354 1355 /* locate the major number */ 1356 for (commajor = 0; commajor < nchrdev; commajor++) 1357 if (cdevsw[commajor].d_open == comopen) 1358 break; 1359 1360 /* initialize required fields */ 1361 cp->cn_dev = makedev(commajor, CONUNIT); 1362 #ifdef COMCONSOLE 1363 cp->cn_pri = CN_REMOTE; /* Force a serial port console */ 1364 #else 1365 cp->cn_pri = CN_NORMAL; 1366 #endif 1367 } 1368 1369 void 1370 comcninit(cp) 1371 struct consdev *cp; 1372 { 1373 1374 #if 0 1375 XXX NEEDS TO BE FIXED XXX 1376 comconsbc = ???; 1377 #endif 1378 if (bus_io_map(comconsbc, CONADDR, COM_NPORTS, &comconsioh)) 1379 panic("comcninit: mapping failed"); 1380 1381 cominit(comconsbc, comconsioh, comdefaultrate); 1382 comconsaddr = CONADDR; 1383 comconsinit = 0; 1384 } 1385 1386 void 1387 cominit(bc, ioh, rate) 1388 bus_chipset_tag_t bc; 1389 bus_io_handle_t ioh; 1390 int rate; 1391 { 1392 int s = splhigh(); 1393 u_char stat; 1394 1395 bus_io_write_1(bc, ioh, com_lcr, LCR_DLAB); 1396 rate = comspeed(comdefaultrate); 1397 bus_io_write_1(bc, ioh, com_dlbl, rate); 1398 bus_io_write_1(bc, ioh, com_dlbh, rate >> 8); 1399 bus_io_write_1(bc, ioh, com_lcr, LCR_8BITS); 1400 bus_io_write_1(bc, ioh, com_ier, IER_ERXRDY | IER_ETXRDY); 1401 bus_io_write_1(bc, ioh, com_fifo, 1402 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1); 1403 bus_io_write_1(bc, ioh, com_mcr, MCR_DTR | MCR_RTS); 1404 DELAY(100); 1405 stat = bus_io_read_1(bc, ioh, com_iir); 1406 splx(s); 1407 } 1408 1409 int 1410 comcngetc(dev) 1411 dev_t dev; 1412 { 1413 int s = splhigh(); 1414 bus_chipset_tag_t bc = comconsbc; 1415 bus_io_handle_t ioh = comconsioh; 1416 u_char stat, c; 1417 1418 while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_RXRDY)) 1419 ; 1420 c = bus_io_read_1(bc, ioh, com_data); 1421 stat = bus_io_read_1(bc, ioh, com_iir); 1422 splx(s); 1423 return c; 1424 } 1425 1426 /* 1427 * Console kernel output character routine. 1428 */ 1429 void 1430 comcnputc(dev, c) 1431 dev_t dev; 1432 int c; 1433 { 1434 int s = splhigh(); 1435 bus_chipset_tag_t bc = comconsbc; 1436 bus_io_handle_t ioh = comconsioh; 1437 u_char stat; 1438 register int timo; 1439 1440 #ifdef KGDB 1441 if (dev != kgdb_dev) 1442 #endif 1443 if (comconsinit == 0) { 1444 cominit(bc, ioh, comdefaultrate); 1445 comconsinit = 1; 1446 } 1447 /* wait for any pending transmission to finish */ 1448 timo = 50000; 1449 while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo) 1450 ; 1451 bus_io_write_1(bc, ioh, com_data, c); 1452 /* wait for this transmission to complete */ 1453 timo = 1500000; 1454 while (!ISSET(stat = bus_io_read_1(bc, ioh, com_lsr), LSR_TXRDY) && --timo) 1455 ; 1456 /* clear any interrupts generated by this transmission */ 1457 stat = bus_io_read_1(bc, ioh, com_iir); 1458 splx(s); 1459 } 1460 1461 void 1462 comcnpollc(dev, on) 1463 dev_t dev; 1464 int on; 1465 { 1466 1467 } 1468
Indexes created Fri Sep 26 08:10:20 GMT 2025