cpc700reg.h revision 1.2
1 /* $NetBSD: cpc700reg.h,v 1.2 2003/01/23 21:17:15 augustss Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) at Sandburst Corp. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* PCI memory space */ 40 #define CPC_PCI_MEM_BASE 0x80000000 41 #define CPC_PCI_MEM_END 0xf7ffffff 42 43 /* PCI IO space */ 44 #define CPC_PCI_IO_BASE 0xf8000000 45 #define CPC_PCI_IO_START 0xf8800000 /* for allocation */ 46 #define CPC_PCI_IO_END 0xfbffffff 47 48 /* PCI config space */ 49 #define CPC_PCICFGADR 0xfec00000 50 #define CPC_PCI_CONFIG_ENABLE 0x80000000 51 #define CPC_PCICFGDATA 0xfec00004 52 53 /* Config space regs */ 54 #define CPC_PCI_BRDGERR 0x48 55 #define CPC_PCI_CLEARERR 0x0000ff00 56 57 /* PCI interrupt acknowledge & special cycle */ 58 #define CPC_INTR_ACK 0xfed00000 59 60 #define CPC_PMM0_LOCAL 0xff400000 61 #define CPC_PMM0_MASK_ATTR 0xff400004 62 #define CPC_PMM0_PCI_LOW 0xff400008 63 #define CPC_PMM0_PCI_HIGH 0xff40000c 64 #define CPC_PMM1_LOCAL 0xff400010 65 #define CPC_PMM1_MASK_ATTR 0xff400014 66 #define CPC_PMM1_PCI_LOW 0xff400018 67 #define CPC_PMM1_PCI_HIGH 0xff40001c 68 #define CPC_PMM2_LOCAL 0xff400020 69 #define CPC_PMM2_MASK_ATTR 0xff400024 70 #define CPC_PMM2_PCI_LOW 0xff400028 71 #define CPC_PMM2_PCI_HIGH 0xff40002c 72 #define CPC_PTM1_LOCAL 0xff400030 73 #define CPC_PTM1_MEMSIZE 0xff400034 74 #define CPC_PTM2_LOCAL 0xff400038 75 #define CPC_PTM2_MEMSIZE 0xff40003c 76 77 /* serial ports */ 78 #define CPC_COM0 0xff600300 79 #define CPC_COM1 0xff600400 80 #define CPC_COM_SPEED(bus) ((bus) / (2 * 4)) 81 82 /* processor interface registers */ 83 #define CPC_PIF_CFGADR 0xff500000 84 #define CPC_PIF_CFG_PRIFOPT1 0x00 85 #define CPC_PIF_CFG_ERRDET1 0x04 86 #define CPC_PIF_CFG_ERREN1 0x08 87 #define CPC_PIF_CFG_CPUERAD 0x0c 88 #define CPC_PIF_CFG_CPUERAT 0x10 89 #define CPC_PIF_CFG_PLBMIFOPT 0x18 90 #define CPC_PIF_CFG_PLBMTLSA1 0x20 91 #define CPC_PIF_CFG_PLBMTLEA1 0x24 92 #define CPC_PIF_CFG_PLBMTLSA2 0x28 93 #define CPC_PIF_CFG_PLBMTLEA2 0x2c 94 #define CPC_PIF_CFG_PLBMTLSA3 0x30 95 #define CPC_PIF_CFG_PLBMTLEA3 0x34 96 #define CPC_PIF_CFG_PLBSNSSA0 0x38 97 #define CPC_PIF_CFG_PLBSNSEA0 0x3c 98 #define CPC_PIF_CFG_BESR 0x40 99 #define CPC_PIF_CFG_BESRSET 0x44 100 #define CPC_PIF_CFG_BEAR 0x4c 101 #define CPC_PIF_CFG_PLBSWRINT 0x80 102 #define CPC_PIF_CFGDATA 0xff500004 103 104 /* interrupt controller */ 105 #define CPC_UIC_BASE 0xff500880 106 #define CPC_UIC_SIZE 0x00000024 107 #define CPC_UIC_SR 0x00000000 /* UIC status (read/clear) */ 108 #define CPC_UIC_SRS 0x00000004 /* UIC status (set) */ 109 #define CPC_UIC_ER 0x00000008 /* UIC enable */ 110 #define CPC_UIC_CR 0x0000000c /* UIC critical */ 111 #define CPC_UIC_PR 0x00000010 /* UIC polarity 0=low, 1=high*/ 112 #define CPC_UIC_TR 0x00000014 /* UIC trigger 0=level; 1=edge */ 113 #define CPC_UIC_MSR 0x00000018 /* UIC masked status */ 114 #define CPC_UIC_VR 0x0000001c /* UIC vector */ 115 #define CPC_UIC_VCR 0x00000020 /* UIC vector configuration */ 116 #define CPC_UIC_CVR_PRI 0x00000001 /* 0=intr31 high, 1=intr0 high */ 117 /* 118 * if intr0 high then interrupt vector at (vcr&~3) + N*512 119 * if intr31 high then interrupt vector at (vcr&~3) + (31-N)*512 120 */ 121 122 /* UIC interrupt bits. Note, MSB is bit 0 */ 123 /* Internal */ 124 #define CPC_IB_ECC 0 125 #define CPC_IB_PCI_WR_RANGE 1 126 #define CPC_IB_PCI_WR_CMD 2 127 #define CPC_IB_UART_0 3 128 #define CPC_IB_UART_1 4 129 #define CPC_IB_IIC_0 5 130 #define CPC_IB_IIC_1 6 131 /* 6-16 GPT compare&capture */ 132 /* 20-31 external */ 133 #define CPC_IB_EXT0 20 134 #define CPC_IB_EXT1 21 135 #define CPC_IB_EXT2 22 136 #define CPC_IB_EXT3 23 137 #define CPC_IB_EXT4 24 138 #define CPC_IB_EXT5 25 139 #define CPC_IB_EXT6 26 140 #define CPC_IB_EXT7 27 141 #define CPC_IB_EXT8 28 142 #define CPC_IB_EXT9 29 143 #define CPC_IB_EXT10 30 144 #define CPC_IB_EXT11 31 145 146 #define CPC_INTR_MASK(irq) (0x80000000 >> (irq)) 147 148 149 /* IIC */ 150 #define CPC_IIC0 0xff620000 151 #define CPC_IIC1 0xff630000 152 #define CPC_IIC_SIZE 0x00000014 153 /* offsets from base */ 154 #define CPC_IIC_MDBUF 0x00000000 155 #define CPC_IIC_SDBUF 0x00000002 156 #define CPC_IIC_LMADR 0x00000004 157 #define CPC_IIC_HNADR 0x00000005 158 #define CPC_IIC_CNTL 0x00000006 159 #define CPC_IIC_MDCNTL 0x00000007 160 #define CPC_IIC_STS 0x00000008 161 #define CPC_IIC_EXTSTS 0x00000009 162 #define CPC_IIC_LSADR 0x0000000a 163 #define CPC_IIC_HSADR 0x0000000b 164 #define CPC_IIC_CLKDIV 0x0000000c 165 #define CPC_IIC_INTRMSK 0x0000000d 166 #define CPC_IIC_FRCNT 0x0000000e 167 #define CPC_IIC_TCNTLSS 0x0000000f 168 #define CPC_IIC_DIRECTCNTL 0x00000010 169 170 /* timer */ 171 #define CPC_TIMER 0xff650000 172 #define CPC_GPTTBC 0x00000000 173
Indexes created Fri Sep 26 20:09:58 GMT 2025