cs4231reg.h revision 1.10.72.1
1 1.10.72.1 yamt /* $NetBSD: cs4231reg.h,v 1.10.72.1 2008/05/18 12:33:42 yamt Exp $ */ 2 1.2 jtc 3 1.2 jtc /*- 4 1.2 jtc * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 1.2 jtc * All rights reserved. 6 1.1 brezak * 7 1.2 jtc * This code is derived from software contributed to The NetBSD Foundation 8 1.2 jtc * by Ken Hornstein and John Kohl. 9 1.1 brezak * 10 1.2 jtc * Redistribution and use in source and binary forms, with or without 11 1.2 jtc * modification, are permitted provided that the following conditions 12 1.2 jtc * are met: 13 1.2 jtc * 1. Redistributions of source code must retain the above copyright 14 1.2 jtc * notice, this list of conditions and the following disclaimer. 15 1.2 jtc * 2. Redistributions in binary form must reproduce the above copyright 16 1.2 jtc * notice, this list of conditions and the following disclaimer in the 17 1.2 jtc * documentation and/or other materials provided with the distribution. 18 1.1 brezak * 19 1.3 jtc * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.3 jtc * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.3 jtc * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.5 jtc * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.5 jtc * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.3 jtc * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.3 jtc * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.3 jtc * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.3 jtc * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.3 jtc * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.3 jtc * POSSIBILITY OF SUCH DAMAGE. 30 1.1 brezak */ 31 1.1 brezak 32 1.1 brezak /* 33 1.1 brezak * Register defs for Crystal Semiconductor CS4231 Audio Codec/mixer 34 1.1 brezak * chip, used on Gravis UltraSound MAX cards. 35 1.1 brezak * 36 1.1 brezak * Block diagram: 37 1.1 brezak * +----------------------------------------------------+ 38 1.8 dbj * | | 39 1.1 brezak * | +----------------------------------------------+ | 40 1.8 dbj * | |mixed in +-+ | | 41 1.8 dbj * | +------------>--| | | | 42 1.8 dbj * | mic in | | | | 43 1.8 dbj * Mic --+-->| --------- GAIN ->-| | | | 44 1.8 dbj * | | AUX 1 in |M| | | 45 1.8 dbj * GF1 --)-->| -------------+-->-|U| | | 46 1.8 dbj * | | Line in | |X|---- GAIN ----------+ | | 47 1.8 dbj * Line --)-->| ---------+---)-->-| | | | | 48 1.8 dbj * | | | | | | | | | 49 1.8 dbj * | | | | +-+ ADC | | 50 1.8 dbj * | | | | | | | 51 1.8 dbj * | | | | | | | 52 1.8 dbj * | | | +--- L/M --\ | | | AMP--> 53 1.8 dbj * | | | \ | | | | 54 1.8 dbj * | | | \ | | | | 55 1.8 dbj * | | +---- L/M -------O-->--+--------)-------+-|--+-> line 56 1.8 dbj * | | mono in /| | | | 57 1.8 dbj * +---|-->------------ L/M -----/ | | | | 58 1.8 dbj * | AUX 2 in | | | | 59 1.8 dbj * CD --------|-->------------ L/M -------+ L/M | | 60 1.8 dbj * | | v | 61 1.8 dbj * | | | | 62 1.8 dbj * | DAC | | 63 1.8 dbj * | | | | 64 1.1 brezak * +----------------------------------------------------+ 65 1.8 dbj * | | 66 1.8 dbj * | | 67 1.8 dbj * v v 68 1.8 dbj * Pc BUS (DISK) ??? 69 1.1 brezak * 70 1.1 brezak */ 71 1.1 brezak 72 1.1 brezak /* CS4231/AD1845 mode2 registers; added to AD1848 registers */ 73 1.6 pk #define CS_ALT_FEATURE1 16 74 1.6 pk #define CS_ALT_FEATURE2 17 75 1.6 pk #define CS_LEFT_LINE_CONTROL 18 76 1.6 pk #define CS_RIGHT_LINE_CONTROL 19 77 1.6 pk #define CS_TIMER_LOW 20 78 1.6 pk #define CS_TIMER_HIGH 21 79 1.6 pk #define CS_UPPER_FREQUENCY_SEL 22 80 1.6 pk #define CS_LOWER_FREQUENCY_SEL 23 81 1.6 pk #define CS_IRQ_STATUS 24 82 1.6 pk #define CS_VERSION_ID 25 83 1.6 pk #define CS_MONO_IO_CONTROL 26 84 1.6 pk #define CS_POWERDOWN_CONTROL 27 85 1.10.72.1 yamt #define CS_LEFT_OUT 27 /* 4232 */ 86 1.6 pk #define CS_REC_FORMAT 28 87 1.10.72.1 yamt #define CS_RIGHT_OUT 29 /* 4232 */ 88 1.6 pk #define CS_XTAL_SELECT 29 89 1.6 pk #define CS_UPPER_REC_CNT 30 90 1.6 pk #define CS_LOWER_REC_CNT 31 91 1.1 brezak 92 1.6 pk /* ALT_FEATURE1 - register I16 */ 93 1.6 pk #define ALT_F1_DACZ 0x01 /* 1: hold sample during underrun */ 94 1.6 pk #define ALT_F1_SPE 0x02 /* 1: Serial port enable */ 95 1.6 pk #define ALT_F1_SFORMAT 0x06 /* Serial port format */ 96 1.6 pk #define ALT_F1_PMCE 0x10 /* Playback mode change enable */ 97 1.6 pk #define ALT_F1_CMCE 0x20 /* Capture mode change enable */ 98 1.6 pk #define ALT_F1_TE 0x40 /* Timer enable */ 99 1.6 pk #define ALT_F1_OLB 0x80 /* Output level bit */ 100 1.6 pk 101 1.6 pk /* ALT_FEATURE2 - register I17 */ 102 1.6 pk #define ALT_F2_HPF 0x01 /* High pass filter */ 103 1.6 pk #define ALT_F2_XTALE 0x02 /* Crytal enable */ 104 1.6 pk #define ALT_F2_APAR 0x04 /* ADPCM playback accumulator reset */ 105 1.6 pk #define ALT_F2_RES 0x08 /* reserved */ 106 1.6 pk #define ALT_F2_TEST 0xf0 /* Factory test bits */ 107 1.6 pk 108 1.6 pk /* LINE_CONTROL (LEFT & RIGHT) - register I18,I19 */ 109 1.6 pk #define LINE_INPUT_ATTEN_BITS 0x1f 110 1.6 pk #define LINE_INPUT_ATTEN_MASK 0xe0 111 1.6 pk #define LINE_INPUT_MUTE 0x80 112 1.6 pk #define LINE_INPUT_MUTE_MASK (~LINE_INPUT_MUTE & 0xff) 113 1.6 pk 114 1.6 pk /* ALT_FEATURE3 - register I23 */ 115 1.6 pk #define ALT_F3_ACF 0x01 /* ADPCM capture freeze */ 116 1.6 pk 117 1.6 pk /* ALT_FEATURE_STATUS (aka CS_IRQ_STATUS) - register I24 */ 118 1.6 pk #define CS_IRQ_PU 0x01 /* Playback Underrun */ 119 1.6 pk #define CS_IRQ_PO 0x02 /* Playback Overrun */ 120 1.6 pk #define CS_IRQ_CO 0x04 /* Capture Overrun */ 121 1.6 pk #define CS_IRQ_CU 0x08 /* Capture Underrun */ 122 1.6 pk #define CS_IRQ_PI 0x10 /* Playback Interrupt */ 123 1.6 pk #define CS_IRQ_CI 0x20 /* Capture Interrupt */ 124 1.6 pk #define CS_IRQ_TI 0x40 /* Timer Interrupt */ 125 1.6 pk #define CS_IRQ_RES 0x80 /* reserved */ 126 1.7 pk 127 1.7 pk #define CS_I24_BITS "\20\1PU\2PO\3CO\4CU\5PI\6CI\7TI" 128 1.6 pk 129 1.6 pk /* VERSION - register I25 */ 130 1.6 pk #define CS_VERSION_NUMBER 0xe0 /* Version number: 131 1.6 pk * 0x101 - 4231 rev. A 132 1.6 pk * 0x100 - 4231 previous revs 133 1.10.72.1 yamt * 0x100 - 4232 (unreleased?) 134 1.10.72.1 yamt * 0x101 - 4232 rev. C 135 1.6 pk */ 136 1.6 pk #define CS_VERSION_CHIPID 0x07 /* Chip Identification. 137 1.10.72.1 yamt * Currently know values: 138 1.10.72.1 yamt * 0x000 - CS4231 139 1.10.72.1 yamt * 0x010 - CS4232 140 1.6 pk */ 141 1.6 pk 142 1.6 pk /* MONO_IO_CONTROL - register I26 */ 143 1.1 brezak #define MONO_INPUT_ATTEN_BITS 0x0f 144 1.1 brezak #define MONO_INPUT_ATTEN_MASK 0xf0 145 1.6 pk #define MONO_BYPASS 0x20 146 1.6 pk #define MONO_OUTPUT_MUTE 0x40 147 1.6 pk #define MONO_OUTPUT_MUTE_MASK (~MONO_OUTPUT_MUTE & 0xff) 148 1.1 brezak #define MONO_INPUT_MUTE 0x80 149 1.6 pk #define MONO_INPUT_MUTE_MASK (~MONO_INPUT_MUTE & 0xff) 150 1.1 brezak 151 1.10.72.1 yamt /* CS_LEFT_OUT - register I27 */ 152 1.10.72.1 yamt #define LEFT_OUT_ATTEN_BITS 0x0f 153 1.10.72.1 yamt #define LEFT_OUT_ATTEN_MASK 0xf0 154 1.10.72.1 yamt #define LEFT_OUT_MUTE 0x80 155 1.10.72.1 yamt #define LEFT_OUT_MUTE_MASK (~LEFT_OUT_MUTE & 0xff) 156 1.10.72.1 yamt 157 1.6 pk /* CS_REC_FORMAT - register I28 */ 158 1.6 pk #define REC_FMT_reserved 0x0f /* reserved */ 159 1.6 pk #define REC_FMT_SM 0x10 /* 0: mono, 1: stereo */ 160 1.6 pk #define REC_FMT_CL 0x20 /* 0: linear, 1: companded */ 161 1.6 pk #define REC_FMT_FMT0 0x40 /* See register I8 for valid */ 162 1.6 pk #define REC_FMT_FMT1 0x80 /* combination of the FMT and CL bits */ 163 1.10.72.1 yamt 164 1.10.72.1 yamt /* CS_RIGHT_OUT - register I27 */ 165 1.10.72.1 yamt #define RIGHT_OUT_ATTEN_BITS 0x0f 166 1.10.72.1 yamt #define RIGHT_OUT_ATTEN_MASK 0xf0 167 1.10.72.1 yamt #define RIGHT_OUT_MUTE 0x80 168 1.10.72.1 yamt #define RIGHT_OUT_MUTE_MASK (~RIGHT_OUT_MUTE & 0xff) 169
Indexes created Wed Oct 22 13:09:56 GMT 2025