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cs4231reg.h revision 1.9
      1  1.9   perry /* $NetBSD: cs4231reg.h,v 1.9 2005/02/27 00:27:01 perry Exp $ */
      2  1.2     jtc 
      3  1.2     jtc /*-
      4  1.2     jtc  * Copyright (c) 1996 The NetBSD Foundation, Inc.
      5  1.2     jtc  * All rights reserved.
      6  1.1  brezak  *
      7  1.2     jtc  * This code is derived from software contributed to The NetBSD Foundation
      8  1.2     jtc  * by Ken Hornstein and John Kohl.
      9  1.1  brezak  *
     10  1.2     jtc  * Redistribution and use in source and binary forms, with or without
     11  1.2     jtc  * modification, are permitted provided that the following conditions
     12  1.2     jtc  * are met:
     13  1.2     jtc  * 1. Redistributions of source code must retain the above copyright
     14  1.2     jtc  *    notice, this list of conditions and the following disclaimer.
     15  1.2     jtc  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.2     jtc  *    notice, this list of conditions and the following disclaimer in the
     17  1.2     jtc  *    documentation and/or other materials provided with the distribution.
     18  1.2     jtc  * 3. All advertising materials mentioning features or use of this software
     19  1.2     jtc  *    must display the following acknowledgement:
     20  1.9   perry  *        This product includes software developed by the NetBSD
     21  1.2     jtc  *	  Foundation, Inc. and its contributors.
     22  1.9   perry  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  1.9   perry  *    contributors may be used to endorse or promote products derived
     24  1.2     jtc  *    from this software without specific prior written permission.
     25  1.1  brezak  *
     26  1.3     jtc  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  1.3     jtc  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  1.3     jtc  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  1.5     jtc  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  1.5     jtc  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  1.3     jtc  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  1.3     jtc  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  1.3     jtc  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  1.3     jtc  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  1.3     jtc  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  1.3     jtc  * POSSIBILITY OF SUCH DAMAGE.
     37  1.1  brezak  */
     38  1.1  brezak 
     39  1.1  brezak /*
     40  1.1  brezak  * Register defs for Crystal Semiconductor CS4231 Audio Codec/mixer
     41  1.1  brezak  * chip, used on Gravis UltraSound MAX cards.
     42  1.1  brezak  *
     43  1.1  brezak  * Block diagram:
     44  1.1  brezak  *             +----------------------------------------------------+
     45  1.8     dbj  *             |                                                    |
     46  1.1  brezak  *             |   +----------------------------------------------+ |
     47  1.8     dbj  *             |   |mixed in       +-+                            | |
     48  1.8     dbj  *             |   +------------>--| |                            | |
     49  1.8     dbj  *             | mic in            | |                            | |
     50  1.8     dbj  *   Mic --+-->| --------- GAIN ->-| |                            | |
     51  1.8     dbj  *         |   | AUX 1 in          |M|                            | |
     52  1.8     dbj  *   GF1 --)-->| -------------+-->-|U|                            | |
     53  1.8     dbj  *         |   | Line in      |    |X|---- GAIN ----------+       | |
     54  1.8     dbj  *  Line --)-->| ---------+---)-->-| |                    |       | |
     55  1.8     dbj  *         |   |          |   |    | |                    |       | |
     56  1.8     dbj  *         |   |          |   |    +-+                   ADC      | |
     57  1.8     dbj  *         |   |          |   |                           |       | |
     58  1.8     dbj  *         |   |          |   |                           |       | |
     59  1.8     dbj  *         |   |          |   +--- L/M --\                |       | | AMP-->
     60  1.8     dbj  *         |   |          |               \               |       | |  |
     61  1.8     dbj  *         |   |          |                \              |       | |  |
     62  1.8     dbj  *         |   |          +---- L/M -------O-->--+--------)-------+-|--+-> line
     63  1.8     dbj  *         |   |   mono in                /|     |        |         |
     64  1.8     dbj  *         +---|-->------------ L/M -----/ |     |        |         |
     65  1.8     dbj  *             |   AUX 2 in                |     |        |         |
     66  1.8     dbj  *  CD --------|-->------------ L/M -------+    L/M       |         |
     67  1.8     dbj  *             |                                 |        v         |
     68  1.8     dbj  *             |                                 |        |         |
     69  1.8     dbj  *             |                                DAC       |         |
     70  1.8     dbj  *             |                                 |        |         |
     71  1.1  brezak  *             +----------------------------------------------------+
     72  1.8     dbj  *                                               |        |
     73  1.8     dbj  *                                               |        |
     74  1.8     dbj  *                                               v        v
     75  1.8     dbj  *                                                Pc BUS (DISK) ???
     76  1.1  brezak  *
     77  1.1  brezak  */
     78  1.1  brezak 
     79  1.1  brezak /* CS4231/AD1845 mode2 registers; added to AD1848 registers */
     80  1.6      pk #define CS_ALT_FEATURE1		16
     81  1.6      pk #define CS_ALT_FEATURE2		17
     82  1.6      pk #define CS_LEFT_LINE_CONTROL	18
     83  1.6      pk #define CS_RIGHT_LINE_CONTROL	19
     84  1.6      pk #define CS_TIMER_LOW		20
     85  1.6      pk #define CS_TIMER_HIGH		21
     86  1.6      pk #define CS_UPPER_FREQUENCY_SEL	22
     87  1.6      pk #define CS_LOWER_FREQUENCY_SEL	23
     88  1.6      pk #define CS_IRQ_STATUS		24
     89  1.6      pk #define CS_VERSION_ID		25
     90  1.6      pk #define CS_MONO_IO_CONTROL	26
     91  1.6      pk #define CS_POWERDOWN_CONTROL	27
     92  1.6      pk #define CS_REC_FORMAT		28
     93  1.6      pk #define CS_XTAL_SELECT		29
     94  1.6      pk #define CS_UPPER_REC_CNT	30
     95  1.6      pk #define CS_LOWER_REC_CNT	31
     96  1.1  brezak 
     97  1.6      pk /* ALT_FEATURE1 - register I16 */
     98  1.6      pk #define ALT_F1_DACZ		0x01	/* 1: hold sample during underrun */
     99  1.6      pk #define ALT_F1_SPE		0x02	/* 1: Serial port enable */
    100  1.6      pk #define ALT_F1_SFORMAT		0x06	/* Serial port format */
    101  1.6      pk #define ALT_F1_PMCE		0x10	/* Playback mode change enable */
    102  1.6      pk #define ALT_F1_CMCE		0x20	/* Capture mode change enable */
    103  1.6      pk #define ALT_F1_TE		0x40	/* Timer enable */
    104  1.6      pk #define ALT_F1_OLB		0x80	/* Output level bit */
    105  1.6      pk 
    106  1.6      pk /* ALT_FEATURE2 - register I17 */
    107  1.6      pk #define ALT_F2_HPF		0x01	/* High pass filter */
    108  1.6      pk #define ALT_F2_XTALE		0x02	/* Crytal enable */
    109  1.6      pk #define ALT_F2_APAR		0x04	/* ADPCM playback accumulator reset */
    110  1.6      pk #define ALT_F2_RES		0x08	/* reserved */
    111  1.6      pk #define ALT_F2_TEST		0xf0	/* Factory test bits */
    112  1.6      pk 
    113  1.6      pk /* LINE_CONTROL (LEFT & RIGHT) - register I18,I19 */
    114  1.6      pk #define LINE_INPUT_ATTEN_BITS	0x1f
    115  1.6      pk #define LINE_INPUT_ATTEN_MASK	0xe0
    116  1.6      pk #define LINE_INPUT_MUTE		0x80
    117  1.6      pk #define LINE_INPUT_MUTE_MASK	(~LINE_INPUT_MUTE & 0xff)
    118  1.6      pk 
    119  1.6      pk /* ALT_FEATURE3 - register I23 */
    120  1.6      pk #define ALT_F3_ACF		0x01	/* ADPCM capture freeze */
    121  1.6      pk 
    122  1.6      pk /* ALT_FEATURE_STATUS (aka CS_IRQ_STATUS) - register I24 */
    123  1.6      pk #define CS_IRQ_PU		0x01	/* Playback Underrun */
    124  1.6      pk #define CS_IRQ_PO		0x02	/* Playback Overrun */
    125  1.6      pk #define CS_IRQ_CO		0x04	/* Capture Overrun */
    126  1.6      pk #define CS_IRQ_CU		0x08	/* Capture Underrun */
    127  1.6      pk #define CS_IRQ_PI		0x10	/* Playback Interrupt */
    128  1.6      pk #define CS_IRQ_CI		0x20	/* Capture Interrupt */
    129  1.6      pk #define CS_IRQ_TI		0x40	/* Timer Interrupt */
    130  1.6      pk #define CS_IRQ_RES		0x80	/* reserved */
    131  1.7      pk 
    132  1.7      pk #define CS_I24_BITS		"\20\1PU\2PO\3CO\4CU\5PI\6CI\7TI"
    133  1.6      pk 
    134  1.6      pk /* VERSION - register I25 */
    135  1.6      pk #define CS_VERSION_NUMBER	0xe0	/* Version number:
    136  1.6      pk 					 *	0x101 - 4231 rev. A
    137  1.6      pk 					 *	0x100 - 4231 previous revs
    138  1.6      pk 					 */
    139  1.6      pk #define CS_VERSION_CHIPID	0x07	/* Chip Identification.
    140  1.6      pk 					 * Currently know values: 0x000
    141  1.6      pk 					 */
    142  1.6      pk 
    143  1.6      pk /* MONO_IO_CONTROL - register I26 */
    144  1.1  brezak #define MONO_INPUT_ATTEN_BITS	0x0f
    145  1.1  brezak #define MONO_INPUT_ATTEN_MASK	0xf0
    146  1.6      pk #define MONO_BYPASS		0x20
    147  1.6      pk #define MONO_OUTPUT_MUTE	0x40
    148  1.6      pk #define MONO_OUTPUT_MUTE_MASK	(~MONO_OUTPUT_MUTE & 0xff)
    149  1.1  brezak #define MONO_INPUT_MUTE		0x80
    150  1.6      pk #define MONO_INPUT_MUTE_MASK	(~MONO_INPUT_MUTE & 0xff)
    151  1.1  brezak 
    152  1.6      pk /* CS_REC_FORMAT - register I28 */
    153  1.6      pk #define REC_FMT_reserved	0x0f	/* reserved */
    154  1.6      pk #define REC_FMT_SM		0x10	/* 0: mono, 1: stereo */
    155  1.6      pk #define REC_FMT_CL		0x20	/* 0: linear, 1: companded */
    156  1.6      pk #define REC_FMT_FMT0		0x40	/* See register I8 for valid */
    157  1.6      pk #define REC_FMT_FMT1		0x80	/* combination of the FMT and CL bits */
    158