cs89x0.c revision 1.2.2.2
1 1.2.2.2 nathanw /* $NetBSD: cs89x0.c,v 1.2.2.2 2002/01/08 00:29:39 nathanw Exp $ */ 2 1.2.2.2 nathanw 3 1.2.2.2 nathanw /* 4 1.2.2.2 nathanw * Copyright 1997 5 1.2.2.2 nathanw * Digital Equipment Corporation. All rights reserved. 6 1.2.2.2 nathanw * 7 1.2.2.2 nathanw * This software is furnished under license and may be used and 8 1.2.2.2 nathanw * copied only in accordance with the following terms and conditions. 9 1.2.2.2 nathanw * Subject to these conditions, you may download, copy, install, 10 1.2.2.2 nathanw * use, modify and distribute this software in source and/or binary 11 1.2.2.2 nathanw * form. No title or ownership is transferred hereby. 12 1.2.2.2 nathanw * 13 1.2.2.2 nathanw * 1) Any source code used, modified or distributed must reproduce 14 1.2.2.2 nathanw * and retain this copyright notice and list of conditions as 15 1.2.2.2 nathanw * they appear in the source file. 16 1.2.2.2 nathanw * 17 1.2.2.2 nathanw * 2) No right is granted to use any trade name, trademark, or logo of 18 1.2.2.2 nathanw * Digital Equipment Corporation. Neither the "Digital Equipment 19 1.2.2.2 nathanw * Corporation" name nor any trademark or logo of Digital Equipment 20 1.2.2.2 nathanw * Corporation may be used to endorse or promote products derived 21 1.2.2.2 nathanw * from this software without the prior written permission of 22 1.2.2.2 nathanw * Digital Equipment Corporation. 23 1.2.2.2 nathanw * 24 1.2.2.2 nathanw * 3) This software is provided "AS-IS" and any express or implied 25 1.2.2.2 nathanw * warranties, including but not limited to, any implied warranties 26 1.2.2.2 nathanw * of merchantability, fitness for a particular purpose, or 27 1.2.2.2 nathanw * non-infringement are disclaimed. In no event shall DIGITAL be 28 1.2.2.2 nathanw * liable for any damages whatsoever, and in particular, DIGITAL 29 1.2.2.2 nathanw * shall not be liable for special, indirect, consequential, or 30 1.2.2.2 nathanw * incidental damages or damages for lost profits, loss of 31 1.2.2.2 nathanw * revenue or loss of use, whether such damages arise in contract, 32 1.2.2.2 nathanw * negligence, tort, under statute, in equity, at law or otherwise, 33 1.2.2.2 nathanw * even if advised of the possibility of such damage. 34 1.2.2.2 nathanw */ 35 1.2.2.2 nathanw 36 1.2.2.2 nathanw /* 37 1.2.2.2 nathanw **++ 38 1.2.2.2 nathanw ** FACILITY 39 1.2.2.2 nathanw ** 40 1.2.2.2 nathanw ** Device Driver for the Crystal CS8900 ISA Ethernet Controller. 41 1.2.2.2 nathanw ** 42 1.2.2.2 nathanw ** ABSTRACT 43 1.2.2.2 nathanw ** 44 1.2.2.2 nathanw ** This module provides standard ethernet access for INET protocols 45 1.2.2.2 nathanw ** only. 46 1.2.2.2 nathanw ** 47 1.2.2.2 nathanw ** AUTHORS 48 1.2.2.2 nathanw ** 49 1.2.2.2 nathanw ** Peter Dettori SEA - Software Engineering. 50 1.2.2.2 nathanw ** 51 1.2.2.2 nathanw ** CREATION DATE: 52 1.2.2.2 nathanw ** 53 1.2.2.2 nathanw ** 13-Feb-1997. 54 1.2.2.2 nathanw ** 55 1.2.2.2 nathanw ** MODIFICATION HISTORY (Digital): 56 1.2.2.2 nathanw ** 57 1.2.2.2 nathanw ** Revision 1.27 1998/01/20 17:59:40 cgd 58 1.2.2.2 nathanw ** update for moved headers 59 1.2.2.2 nathanw ** 60 1.2.2.2 nathanw ** Revision 1.26 1998/01/12 19:29:36 cgd 61 1.2.2.2 nathanw ** use arm32/isa versions of isadma code. 62 1.2.2.2 nathanw ** 63 1.2.2.2 nathanw ** Revision 1.25 1997/12/12 01:35:27 cgd 64 1.2.2.2 nathanw ** convert to use new arp code (from Brini) 65 1.2.2.2 nathanw ** 66 1.2.2.2 nathanw ** Revision 1.24 1997/12/10 22:31:56 cgd 67 1.2.2.2 nathanw ** trim some fat (get rid of ability to explicitly supply enet addr, since 68 1.2.2.2 nathanw ** it was never used and added a bunch of code which really doesn't belong in 69 1.2.2.2 nathanw ** an enet driver), and clean up slightly. 70 1.2.2.2 nathanw ** 71 1.2.2.2 nathanw ** Revision 1.23 1997/10/06 16:42:12 cgd 72 1.2.2.2 nathanw ** copyright notices 73 1.2.2.2 nathanw ** 74 1.2.2.2 nathanw ** Revision 1.22 1997/06/20 19:38:01 chaiken 75 1.2.2.2 nathanw ** fixes some smartcard problems 76 1.2.2.2 nathanw ** 77 1.2.2.2 nathanw ** Revision 1.21 1997/06/10 02:56:20 grohn 78 1.2.2.2 nathanw ** Added call to ledNetActive 79 1.2.2.2 nathanw ** 80 1.2.2.2 nathanw ** Revision 1.20 1997/06/05 00:47:06 dettori 81 1.2.2.2 nathanw ** Changed cs_process_rx_dma to reset and re-initialise the 82 1.2.2.2 nathanw ** ethernet chip when DMA gets out of sync, or mbufs 83 1.2.2.2 nathanw ** can't be allocated. 84 1.2.2.2 nathanw ** 85 1.2.2.2 nathanw ** Revision 1.19 1997/06/03 03:09:58 dettori 86 1.2.2.2 nathanw ** Turn off sc_txbusy flag when a transmit underrun 87 1.2.2.2 nathanw ** occurs. 88 1.2.2.2 nathanw ** 89 1.2.2.2 nathanw ** Revision 1.18 1997/06/02 00:04:35 dettori 90 1.2.2.2 nathanw ** redefined the transmit table to get around the nfs_timer bug while we are 91 1.2.2.2 nathanw ** looking into it further. 92 1.2.2.2 nathanw ** 93 1.2.2.2 nathanw ** Also changed interrupts from EDGE to LEVEL. 94 1.2.2.2 nathanw ** 95 1.2.2.2 nathanw ** Revision 1.17 1997/05/27 23:31:01 dettori 96 1.2.2.2 nathanw ** Pulled out changes to DMAMODE defines. 97 1.2.2.2 nathanw ** 98 1.2.2.2 nathanw ** Revision 1.16 1997/05/23 04:25:16 cgd 99 1.2.2.2 nathanw ** reformat log so it fits in 80cols 100 1.2.2.2 nathanw ** 101 1.2.2.2 nathanw ** Revision 1.15 1997/05/23 04:22:18 cgd 102 1.2.2.2 nathanw ** remove the existing copyright notice (which Peter Dettori indicated 103 1.2.2.2 nathanw ** was incorrect, copied from an existing NetBSD file only so that the 104 1.2.2.2 nathanw ** file would have a copyright notice on it, and which he'd intended to 105 1.2.2.2 nathanw ** replace). Replace it with a Digital copyright notice, cloned from 106 1.2.2.2 nathanw ** ess.c. It's not really correct either (it indicates that the source 107 1.2.2.2 nathanw ** is Digital confidential!), but is better than nothing and more 108 1.2.2.2 nathanw ** correct than what was there before. 109 1.2.2.2 nathanw ** 110 1.2.2.2 nathanw ** Revision 1.14 1997/05/23 04:12:50 cgd 111 1.2.2.2 nathanw ** use an adaptive transmit start algorithm: start by telling the chip 112 1.2.2.2 nathanw ** to start transmitting after 381 bytes have been fed to it. if that 113 1.2.2.2 nathanw ** gets transmit underruns, ramp down to 1021 bytes then "whole 114 1.2.2.2 nathanw ** packet." If successful at a given level for a while, try the next 115 1.2.2.2 nathanw ** more agressive level. This code doesn't ever try to start 116 1.2.2.2 nathanw ** transmitting after 5 bytes have been sent to the NIC, because 117 1.2.2.2 nathanw ** that underruns rather regularly. The back-off and ramp-up mechanism 118 1.2.2.2 nathanw ** could probably be tuned a little bit, but this works well enough to 119 1.2.2.2 nathanw ** support > 1MB/s transmit rates on a clear ethernet (which is about 120 1.2.2.2 nathanw ** 20-25% better than the driver had previously been getting). 121 1.2.2.2 nathanw ** 122 1.2.2.2 nathanw ** Revision 1.13 1997/05/22 21:06:54 cgd 123 1.2.2.2 nathanw ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly 124 1.2.2.2 nathanw ** casting from u_int8_t * to u_int16_t * without worrying about alignment 125 1.2.2.2 nathanw ** issues. This would cause bogus data to be spit out for mbufs with 126 1.2.2.2 nathanw ** misaligned data. For instance, it caused the following bits to appear 127 1.2.2.2 nathanw ** on the wire: 128 1.2.2.2 nathanw ** ... etBND 1S2C .SHA(K) R ... 129 1.2.2.2 nathanw ** 11112222333344445555 130 1.2.2.2 nathanw ** which should have appeared as: 131 1.2.2.2 nathanw ** ... NetBSD 1.2C (SHARK) ... 132 1.2.2.2 nathanw ** 11112222333344445555 133 1.2.2.2 nathanw ** Note the apparent 'rotate' of the bytes in the word, which was due to 134 1.2.2.2 nathanw ** incorrect unaligned accesses. This data corruption was the cause of 135 1.2.2.2 nathanw ** incoming telnet/rlogin hangs. 136 1.2.2.2 nathanw ** 137 1.2.2.2 nathanw ** Revision 1.12 1997/05/22 01:55:32 cgd 138 1.2.2.2 nathanw ** reformat log so it fits in 80cols 139 1.2.2.2 nathanw ** 140 1.2.2.2 nathanw ** Revision 1.11 1997/05/22 01:50:27 cgd 141 1.2.2.2 nathanw ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case, 142 1.2.2.2 nathanw ** so packets aimed at other hosts don't get sent to ether_input(). 143 1.2.2.2 nathanw ** * Add a static const char *rcsid initialized with an RCS Id tag, so that 144 1.2.2.2 nathanw ** you can easily tell (`strings`) what version of the driver is in your 145 1.2.2.2 nathanw ** kernel binary. 146 1.2.2.2 nathanw ** * get rid of ether_cmp(). It was inconsistently used, not necessarily 147 1.2.2.2 nathanw ** safe, and not really a performance win anyway. (It was only used when 148 1.2.2.2 nathanw ** setting up the multicast logical address filter, which is an 149 1.2.2.2 nathanw ** infrequent event. It could have been used in the IFF_PROMISCUOUS 150 1.2.2.2 nathanw ** address check above, but the benefit of it vs. memcmp would be 151 1.2.2.2 nathanw ** inconsequential, there.) Use memcmp() instead. 152 1.2.2.2 nathanw ** * restructure csStartOuput to avoid the following bugs in the case where 153 1.2.2.2 nathanw ** txWait was being set: 154 1.2.2.2 nathanw ** * it would accidentally drop the outgoing packet if told to wait 155 1.2.2.2 nathanw ** but the outgoing packet queue was empty. 156 1.2.2.2 nathanw ** * it would bpf_mtap() the outgoing packet multiple times (once for 157 1.2.2.2 nathanw ** each time it was told to wait), and would also recalculate 158 1.2.2.2 nathanw ** the length of the outgoing packet each time it was told to 159 1.2.2.2 nathanw ** wait. 160 1.2.2.2 nathanw ** While there, rename txWait to txLoop, since with the new structure of 161 1.2.2.2 nathanw ** the code, the latter name makes more sense. 162 1.2.2.2 nathanw ** 163 1.2.2.2 nathanw ** Revision 1.10 1997/05/19 02:03:20 cgd 164 1.2.2.2 nathanw ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip() 165 1.2.2.2 nathanw ** is the only caller of cs_set_ladr_filt(), and always calls it, so this 166 1.2.2.2 nathanw ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC 167 1.2.2.2 nathanw ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave 168 1.2.2.2 nathanw ** as before. 169 1.2.2.2 nathanw ** 170 1.2.2.2 nathanw ** Revision 1.9 1997/05/19 01:45:37 cgd 171 1.2.2.2 nathanw ** create a new function, cs_ether_input(), which does received-packet 172 1.2.2.2 nathanw ** BPF and ether_input processing. This code used to be in three places, 173 1.2.2.2 nathanw ** and centralizing it will make adding IFF_PROMISC support much easier. 174 1.2.2.2 nathanw ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to 175 1.2.2.2 nathanw ** do copies with bus_space_write_region_2(). It's more correct, and 176 1.2.2.2 nathanw ** potentially more efficient. That function needs to be gutted (to 177 1.2.2.2 nathanw ** deal properly with alignment issues, which it currently does wrong), 178 1.2.2.2 nathanw ** however, and the change doesn't gain much, so there's no point in 179 1.2.2.2 nathanw ** enabling it now. 180 1.2.2.2 nathanw ** 181 1.2.2.2 nathanw ** Revision 1.8 1997/05/19 01:17:10 cgd 182 1.2.2.2 nathanw ** fix a comment re: the setting of the TxConfig register. Clean up 183 1.2.2.2 nathanw ** interface counter maintenance (make it use standard idiom). 184 1.2.2.2 nathanw ** 185 1.2.2.2 nathanw **-- 186 1.2.2.2 nathanw */ 187 1.2.2.2 nathanw 188 1.2.2.2 nathanw #include <sys/cdefs.h> 189 1.2.2.2 nathanw __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.2.2.2 2002/01/08 00:29:39 nathanw Exp $"); 190 1.2.2.2 nathanw 191 1.2.2.2 nathanw #include "opt_inet.h" 192 1.2.2.2 nathanw 193 1.2.2.2 nathanw #include <sys/param.h> 194 1.2.2.2 nathanw #include <sys/systm.h> 195 1.2.2.2 nathanw #include <sys/mbuf.h> 196 1.2.2.2 nathanw #include <sys/syslog.h> 197 1.2.2.2 nathanw #include <sys/socket.h> 198 1.2.2.2 nathanw #include <sys/device.h> 199 1.2.2.2 nathanw #include <sys/malloc.h> 200 1.2.2.2 nathanw #include <sys/ioctl.h> 201 1.2.2.2 nathanw #include <sys/errno.h> 202 1.2.2.2 nathanw 203 1.2.2.2 nathanw #include "rnd.h" 204 1.2.2.2 nathanw #if NRND > 0 205 1.2.2.2 nathanw #include <sys/rnd.h> 206 1.2.2.2 nathanw #endif 207 1.2.2.2 nathanw 208 1.2.2.2 nathanw #include <net/if.h> 209 1.2.2.2 nathanw #include <net/if_ether.h> 210 1.2.2.2 nathanw #include <net/if_media.h> 211 1.2.2.2 nathanw #ifdef INET 212 1.2.2.2 nathanw #include <netinet/in.h> 213 1.2.2.2 nathanw #include <netinet/if_inarp.h> 214 1.2.2.2 nathanw #endif 215 1.2.2.2 nathanw 216 1.2.2.2 nathanw #include "bpfilter.h" 217 1.2.2.2 nathanw #if NBPFILTER > 0 218 1.2.2.2 nathanw #include <net/bpf.h> 219 1.2.2.2 nathanw #include <net/bpfdesc.h> 220 1.2.2.2 nathanw #endif 221 1.2.2.2 nathanw 222 1.2.2.2 nathanw #include <uvm/uvm_extern.h> 223 1.2.2.2 nathanw 224 1.2.2.2 nathanw #include <machine/bus.h> 225 1.2.2.2 nathanw #include <machine/intr.h> 226 1.2.2.2 nathanw 227 1.2.2.2 nathanw #include <dev/ic/cs89x0reg.h> 228 1.2.2.2 nathanw #include <dev/ic/cs89x0var.h> 229 1.2.2.2 nathanw 230 1.2.2.2 nathanw #ifdef SHARK 231 1.2.2.2 nathanw #include <arm32/shark/sequoia.h> 232 1.2.2.2 nathanw #endif 233 1.2.2.2 nathanw 234 1.2.2.2 nathanw /* 235 1.2.2.2 nathanw * MACRO DEFINITIONS 236 1.2.2.2 nathanw */ 237 1.2.2.2 nathanw #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */ 238 1.2.2.2 nathanw 239 1.2.2.2 nathanw /* 240 1.2.2.2 nathanw * FUNCTION PROTOTYPES 241 1.2.2.2 nathanw */ 242 1.2.2.2 nathanw void cs_get_default_media __P((struct cs_softc *)); 243 1.2.2.2 nathanw int cs_get_params __P((struct cs_softc *)); 244 1.2.2.2 nathanw int cs_get_enaddr __P((struct cs_softc *)); 245 1.2.2.2 nathanw int cs_reset_chip __P((struct cs_softc *)); 246 1.2.2.2 nathanw void cs_reset __P((void *)); 247 1.2.2.2 nathanw int cs_ioctl __P((struct ifnet *, u_long, caddr_t)); 248 1.2.2.2 nathanw void cs_initChip __P((struct cs_softc *)); 249 1.2.2.2 nathanw void cs_buffer_event __P((struct cs_softc *, u_int16_t)); 250 1.2.2.2 nathanw void cs_transmit_event __P((struct cs_softc *, u_int16_t)); 251 1.2.2.2 nathanw void cs_receive_event __P((struct cs_softc *, u_int16_t)); 252 1.2.2.2 nathanw void cs_process_receive __P((struct cs_softc *)); 253 1.2.2.2 nathanw void cs_process_rx_early __P((struct cs_softc *)); 254 1.2.2.2 nathanw void cs_start_output __P((struct ifnet *)); 255 1.2.2.2 nathanw void cs_copy_tx_frame __P((struct cs_softc *, struct mbuf *)); 256 1.2.2.2 nathanw void cs_set_ladr_filt __P((struct cs_softc *, struct ethercom *)); 257 1.2.2.2 nathanw u_int16_t cs_hash_index __P((char *)); 258 1.2.2.2 nathanw void cs_counter_event __P((struct cs_softc *, u_int16_t)); 259 1.2.2.2 nathanw 260 1.2.2.2 nathanw int cs_mediachange __P((struct ifnet *)); 261 1.2.2.2 nathanw void cs_mediastatus __P((struct ifnet *, struct ifmediareq *)); 262 1.2.2.2 nathanw 263 1.2.2.2 nathanw static int cs_enable __P((struct cs_softc *)); 264 1.2.2.2 nathanw static void cs_disable __P((struct cs_softc *)); 265 1.2.2.2 nathanw static void cs_stop __P((struct ifnet *, int)); 266 1.2.2.2 nathanw static void cs_power __P((int, void *)); 267 1.2.2.2 nathanw 268 1.2.2.2 nathanw /* 269 1.2.2.2 nathanw * GLOBAL DECLARATIONS 270 1.2.2.2 nathanw */ 271 1.2.2.2 nathanw 272 1.2.2.2 nathanw /* 273 1.2.2.2 nathanw * Xmit-early table. 274 1.2.2.2 nathanw * 275 1.2.2.2 nathanw * To get better performance, we tell the chip to start packet 276 1.2.2.2 nathanw * transmission before the whole packet is copied to the chip. 277 1.2.2.2 nathanw * However, this can fail under load. When it fails, we back off 278 1.2.2.2 nathanw * to a safer setting for a little while. 279 1.2.2.2 nathanw * 280 1.2.2.2 nathanw * txcmd is the value of txcmd used to indicate when to start transmission. 281 1.2.2.2 nathanw * better is the next 'better' state in the table. 282 1.2.2.2 nathanw * better_count is the number of output packets before transition to the 283 1.2.2.2 nathanw * better state. 284 1.2.2.2 nathanw * worse is the next 'worse' state in the table. 285 1.2.2.2 nathanw * 286 1.2.2.2 nathanw * Transition to the next worse state happens automatically when a 287 1.2.2.2 nathanw * transmittion underrun occurs. 288 1.2.2.2 nathanw */ 289 1.2.2.2 nathanw struct cs_xmit_early { 290 1.2.2.2 nathanw u_int16_t txcmd; 291 1.2.2.2 nathanw int better; 292 1.2.2.2 nathanw int better_count; 293 1.2.2.2 nathanw int worse; 294 1.2.2.2 nathanw } cs_xmit_early_table[3] = { 295 1.2.2.2 nathanw { TX_CMD_START_381, 0, INT_MAX, 1, }, 296 1.2.2.2 nathanw { TX_CMD_START_1021, 0, 50000, 2, }, 297 1.2.2.2 nathanw { TX_CMD_START_ALL, 1, 5000, 2, }, 298 1.2.2.2 nathanw }; 299 1.2.2.2 nathanw 300 1.2.2.2 nathanw int cs_default_media[] = { 301 1.2.2.2 nathanw IFM_ETHER|IFM_10_2, 302 1.2.2.2 nathanw IFM_ETHER|IFM_10_5, 303 1.2.2.2 nathanw IFM_ETHER|IFM_10_T, 304 1.2.2.2 nathanw IFM_ETHER|IFM_10_T|IFM_FDX, 305 1.2.2.2 nathanw }; 306 1.2.2.2 nathanw int cs_default_nmedia = sizeof(cs_default_media) / sizeof(cs_default_media[0]); 307 1.2.2.2 nathanw 308 1.2.2.2 nathanw int 309 1.2.2.2 nathanw cs_attach(sc, enaddr, media, nmedia, defmedia) 310 1.2.2.2 nathanw struct cs_softc *sc; 311 1.2.2.2 nathanw u_int8_t *enaddr; 312 1.2.2.2 nathanw int *media, nmedia, defmedia; 313 1.2.2.2 nathanw { 314 1.2.2.2 nathanw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 315 1.2.2.2 nathanw const char *chipname, *medname; 316 1.2.2.2 nathanw u_int16_t reg; 317 1.2.2.2 nathanw int i; 318 1.2.2.2 nathanw 319 1.2.2.2 nathanw /* Start out in IO mode */ 320 1.2.2.2 nathanw sc->sc_memorymode = FALSE; 321 1.2.2.2 nathanw 322 1.2.2.2 nathanw /* make sure we're right */ 323 1.2.2.2 nathanw for (i = 0; i < 10000; i++) { 324 1.2.2.2 nathanw reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 325 1.2.2.2 nathanw if (reg == EISA_NUM_CRYSTAL) { 326 1.2.2.2 nathanw break; 327 1.2.2.2 nathanw } 328 1.2.2.2 nathanw } 329 1.2.2.2 nathanw if (i == 10000) { 330 1.2.2.2 nathanw printf("%s: wrong id(0x%x)\n", sc->sc_dev.dv_xname, reg); 331 1.2.2.2 nathanw return 1; /* XXX should panic? */ 332 1.2.2.2 nathanw } 333 1.2.2.2 nathanw 334 1.2.2.2 nathanw reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID); 335 1.2.2.2 nathanw sc->sc_prodid = reg & PROD_ID_MASK; 336 1.2.2.2 nathanw sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8; 337 1.2.2.2 nathanw 338 1.2.2.2 nathanw switch (sc->sc_prodid) { 339 1.2.2.2 nathanw case PROD_ID_CS8900: 340 1.2.2.2 nathanw chipname = "CS8900"; 341 1.2.2.2 nathanw break; 342 1.2.2.2 nathanw case PROD_ID_CS8920: 343 1.2.2.2 nathanw chipname = "CS8920"; 344 1.2.2.2 nathanw break; 345 1.2.2.2 nathanw case PROD_ID_CS8920M: 346 1.2.2.2 nathanw chipname = "CS8920M"; 347 1.2.2.2 nathanw break; 348 1.2.2.2 nathanw default: 349 1.2.2.2 nathanw panic("cs_attach: impossible"); 350 1.2.2.2 nathanw } 351 1.2.2.2 nathanw 352 1.2.2.2 nathanw /* 353 1.2.2.2 nathanw * the first thing to do is check that the mbuf cluster size is 354 1.2.2.2 nathanw * greater than the MTU for an ethernet frame. The code depends on 355 1.2.2.2 nathanw * this and to port this to a OS where this was not the case would 356 1.2.2.2 nathanw * not be straightforward. 357 1.2.2.2 nathanw * 358 1.2.2.2 nathanw * we need 1 byte spare because our 359 1.2.2.2 nathanw * packet read loop can overrun. 360 1.2.2.2 nathanw * and we may need pad bytes to align ip header. 361 1.2.2.2 nathanw */ 362 1.2.2.2 nathanw if (MCLBYTES < ETHER_MAX_LEN + 1 + 363 1.2.2.2 nathanw ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header)) { 364 1.2.2.2 nathanw printf("%s: MCLBYTES too small for Ethernet frame\n", 365 1.2.2.2 nathanw sc->sc_dev.dv_xname); 366 1.2.2.2 nathanw return 1; 367 1.2.2.2 nathanw } 368 1.2.2.2 nathanw 369 1.2.2.2 nathanw /* Start out not transmitting */ 370 1.2.2.2 nathanw sc->sc_txbusy = FALSE; 371 1.2.2.2 nathanw 372 1.2.2.2 nathanw /* Set up early transmit threshhold */ 373 1.2.2.2 nathanw sc->sc_xe_ent = 0; 374 1.2.2.2 nathanw sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count; 375 1.2.2.2 nathanw 376 1.2.2.2 nathanw /* Initialize ifnet structure. */ 377 1.2.2.2 nathanw strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 378 1.2.2.2 nathanw ifp->if_softc = sc; 379 1.2.2.2 nathanw ifp->if_start = cs_start_output; 380 1.2.2.2 nathanw ifp->if_init = cs_init; 381 1.2.2.2 nathanw ifp->if_ioctl = cs_ioctl; 382 1.2.2.2 nathanw ifp->if_stop = cs_stop; 383 1.2.2.2 nathanw ifp->if_watchdog = NULL; /* no watchdog at this stage */ 384 1.2.2.2 nathanw ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | 385 1.2.2.2 nathanw IFF_BROADCAST | IFF_MULTICAST; 386 1.2.2.2 nathanw IFQ_SET_READY(&ifp->if_snd); 387 1.2.2.2 nathanw 388 1.2.2.2 nathanw /* Initialize ifmedia structures. */ 389 1.2.2.2 nathanw ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus); 390 1.2.2.2 nathanw 391 1.2.2.2 nathanw if (media != NULL) { 392 1.2.2.2 nathanw for (i = 0; i < nmedia; i++) 393 1.2.2.2 nathanw ifmedia_add(&sc->sc_media, media[i], 0, NULL); 394 1.2.2.2 nathanw ifmedia_set(&sc->sc_media, defmedia); 395 1.2.2.2 nathanw } else { 396 1.2.2.2 nathanw for (i = 0; i < cs_default_nmedia; i++) 397 1.2.2.2 nathanw ifmedia_add(&sc->sc_media, cs_default_media[i], 398 1.2.2.2 nathanw 0, NULL); 399 1.2.2.2 nathanw cs_get_default_media(sc); 400 1.2.2.2 nathanw } 401 1.2.2.2 nathanw 402 1.2.2.2 nathanw if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 403 1.2.2.2 nathanw /* Get parameters from the EEPROM */ 404 1.2.2.2 nathanw if (cs_get_params(sc) == CS_ERROR) { 405 1.2.2.2 nathanw printf("%s: unable to get settings from EEPROM\n", 406 1.2.2.2 nathanw sc->sc_dev.dv_xname); 407 1.2.2.2 nathanw return 1; 408 1.2.2.2 nathanw } 409 1.2.2.2 nathanw } 410 1.2.2.2 nathanw 411 1.2.2.2 nathanw if (enaddr != NULL) 412 1.2.2.2 nathanw memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 413 1.2.2.2 nathanw else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 414 1.2.2.2 nathanw /* Get and store the Ethernet address */ 415 1.2.2.2 nathanw if (cs_get_enaddr(sc) == CS_ERROR) { 416 1.2.2.2 nathanw printf("%s: unable to read Ethernet address\n", 417 1.2.2.2 nathanw sc->sc_dev.dv_xname); 418 1.2.2.2 nathanw return 1; 419 1.2.2.2 nathanw } 420 1.2.2.2 nathanw } else { 421 1.2.2.2 nathanw printf("%s: no Ethernet address!\n", sc->sc_dev.dv_xname); 422 1.2.2.2 nathanw return 1; 423 1.2.2.2 nathanw } 424 1.2.2.2 nathanw 425 1.2.2.2 nathanw switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) { 426 1.2.2.2 nathanw case IFM_10_2: 427 1.2.2.2 nathanw medname = "BNC"; 428 1.2.2.2 nathanw break; 429 1.2.2.2 nathanw case IFM_10_5: 430 1.2.2.2 nathanw medname = "AUI"; 431 1.2.2.2 nathanw break; 432 1.2.2.2 nathanw case IFM_10_T: 433 1.2.2.2 nathanw if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 434 1.2.2.2 nathanw medname = "UTP <full-duplex>"; 435 1.2.2.2 nathanw else 436 1.2.2.2 nathanw medname = "UTP"; 437 1.2.2.2 nathanw break; 438 1.2.2.2 nathanw default: 439 1.2.2.2 nathanw panic("cs_attach: impossible"); 440 1.2.2.2 nathanw } 441 1.2.2.2 nathanw printf("%s: %s rev. %c, address %s, media %s\n", sc->sc_dev.dv_xname, 442 1.2.2.2 nathanw chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr), 443 1.2.2.2 nathanw medname); 444 1.2.2.2 nathanw 445 1.2.2.2 nathanw if (sc->sc_dma_attach) 446 1.2.2.2 nathanw (*sc->sc_dma_attach)(sc); 447 1.2.2.2 nathanw 448 1.2.2.2 nathanw sc->sc_sh = shutdownhook_establish(cs_reset, sc); 449 1.2.2.2 nathanw if (sc->sc_sh == NULL) { 450 1.2.2.2 nathanw printf("%s: unable to establish shutdownhook\n", 451 1.2.2.2 nathanw sc->sc_dev.dv_xname); 452 1.2.2.2 nathanw cs_detach(sc); 453 1.2.2.2 nathanw return 1; 454 1.2.2.2 nathanw } 455 1.2.2.2 nathanw 456 1.2.2.2 nathanw /* Attach the interface. */ 457 1.2.2.2 nathanw if_attach(ifp); 458 1.2.2.2 nathanw ether_ifattach(ifp, sc->sc_enaddr); 459 1.2.2.2 nathanw 460 1.2.2.2 nathanw #if NRND > 0 461 1.2.2.2 nathanw rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 462 1.2.2.2 nathanw RND_TYPE_NET, 0); 463 1.2.2.2 nathanw #endif 464 1.2.2.2 nathanw sc->sc_cfgflags |= CFGFLG_ATTACHED; 465 1.2.2.2 nathanw 466 1.2.2.2 nathanw /* Reset the chip */ 467 1.2.2.2 nathanw if (cs_reset_chip(sc) == CS_ERROR) { 468 1.2.2.2 nathanw printf("%s: reset failed\n", sc->sc_dev.dv_xname); 469 1.2.2.2 nathanw cs_detach(sc); 470 1.2.2.2 nathanw return 1; 471 1.2.2.2 nathanw } 472 1.2.2.2 nathanw 473 1.2.2.2 nathanw sc->sc_powerhook = powerhook_establish(cs_power, sc); 474 1.2.2.2 nathanw if (sc->sc_powerhook == 0) 475 1.2.2.2 nathanw printf("%s: warning: powerhook_establish failed\n", 476 1.2.2.2 nathanw sc->sc_dev.dv_xname); 477 1.2.2.2 nathanw 478 1.2.2.2 nathanw return 0; 479 1.2.2.2 nathanw } 480 1.2.2.2 nathanw 481 1.2.2.2 nathanw int 482 1.2.2.2 nathanw cs_detach(sc) 483 1.2.2.2 nathanw struct cs_softc *sc; 484 1.2.2.2 nathanw { 485 1.2.2.2 nathanw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 486 1.2.2.2 nathanw 487 1.2.2.2 nathanw if (sc->sc_powerhook) { 488 1.2.2.2 nathanw powerhook_disestablish(sc->sc_powerhook); 489 1.2.2.2 nathanw sc->sc_powerhook = 0; 490 1.2.2.2 nathanw } 491 1.2.2.2 nathanw 492 1.2.2.2 nathanw if (sc->sc_cfgflags & CFGFLG_ATTACHED) { 493 1.2.2.2 nathanw #if NRND > 0 494 1.2.2.2 nathanw rnd_detach_source(&sc->rnd_source); 495 1.2.2.2 nathanw #endif 496 1.2.2.2 nathanw ether_ifdetach(ifp); 497 1.2.2.2 nathanw if_detach(ifp); 498 1.2.2.2 nathanw sc->sc_cfgflags &= ~CFGFLG_ATTACHED; 499 1.2.2.2 nathanw } 500 1.2.2.2 nathanw 501 1.2.2.2 nathanw if (sc->sc_sh != NULL) 502 1.2.2.2 nathanw shutdownhook_disestablish(sc->sc_sh); 503 1.2.2.2 nathanw 504 1.2.2.2 nathanw #if 0 505 1.2.2.2 nathanw /* 506 1.2.2.2 nathanw * XXX not necessary 507 1.2.2.2 nathanw */ 508 1.2.2.2 nathanw if (sc->sc_cfgflags & CFGFLG_DMA_MODE) { 509 1.2.2.2 nathanw isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, sc->sc_dmasize); 510 1.2.2.2 nathanw isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, sc->sc_dmasize); 511 1.2.2.2 nathanw isa_dmamap_destroy(sc->sc_ic, sc->sc_drq); 512 1.2.2.2 nathanw sc->sc_cfgflags &= ~CFGFLG_DMA_MODE; 513 1.2.2.2 nathanw } 514 1.2.2.2 nathanw #endif 515 1.2.2.2 nathanw 516 1.2.2.2 nathanw return 0; 517 1.2.2.2 nathanw } 518 1.2.2.2 nathanw 519 1.2.2.2 nathanw void 520 1.2.2.2 nathanw cs_get_default_media(sc) 521 1.2.2.2 nathanw struct cs_softc *sc; 522 1.2.2.2 nathanw { 523 1.2.2.2 nathanw u_int16_t adp_cfg, xmit_ctl; 524 1.2.2.2 nathanw 525 1.2.2.2 nathanw if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 526 1.2.2.2 nathanw printf("%s: cs_get_default_media: EEPROM missing or bad\n", 527 1.2.2.2 nathanw sc->sc_dev.dv_xname); 528 1.2.2.2 nathanw goto fakeit; 529 1.2.2.2 nathanw } 530 1.2.2.2 nathanw 531 1.2.2.2 nathanw if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ADPTR_CFG, 532 1.2.2.2 nathanw &adp_cfg) == CS_ERROR) { 533 1.2.2.2 nathanw printf("%s: unable to read adapter config from EEPROM\n", 534 1.2.2.2 nathanw sc->sc_dev.dv_xname); 535 1.2.2.2 nathanw goto fakeit; 536 1.2.2.2 nathanw } 537 1.2.2.2 nathanw 538 1.2.2.2 nathanw if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_XMIT_CTL, 539 1.2.2.2 nathanw &xmit_ctl) == CS_ERROR) { 540 1.2.2.2 nathanw printf("%s: unable to read transmit control from EEPROM\n", 541 1.2.2.2 nathanw sc->sc_dev.dv_xname); 542 1.2.2.2 nathanw goto fakeit; 543 1.2.2.2 nathanw } 544 1.2.2.2 nathanw 545 1.2.2.2 nathanw switch (adp_cfg & ADPTR_CFG_MEDIA) { 546 1.2.2.2 nathanw case ADPTR_CFG_AUI: 547 1.2.2.2 nathanw ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5); 548 1.2.2.2 nathanw break; 549 1.2.2.2 nathanw case ADPTR_CFG_10BASE2: 550 1.2.2.2 nathanw ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2); 551 1.2.2.2 nathanw break; 552 1.2.2.2 nathanw case ADPTR_CFG_10BASET: 553 1.2.2.2 nathanw default: 554 1.2.2.2 nathanw if (xmit_ctl & XMIT_CTL_FDX) 555 1.2.2.2 nathanw ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX); 556 1.2.2.2 nathanw else 557 1.2.2.2 nathanw ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 558 1.2.2.2 nathanw break; 559 1.2.2.2 nathanw } 560 1.2.2.2 nathanw return; 561 1.2.2.2 nathanw 562 1.2.2.2 nathanw fakeit: 563 1.2.2.2 nathanw printf("%s: WARNING: default media setting may be inaccurate\n", 564 1.2.2.2 nathanw sc->sc_dev.dv_xname); 565 1.2.2.2 nathanw /* XXX Arbitrary... */ 566 1.2.2.2 nathanw ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 567 1.2.2.2 nathanw } 568 1.2.2.2 nathanw 569 1.2.2.2 nathanw int 570 1.2.2.2 nathanw cs_get_params(sc) 571 1.2.2.2 nathanw struct cs_softc *sc; 572 1.2.2.2 nathanw { 573 1.2.2.2 nathanw u_int16_t isaConfig; 574 1.2.2.2 nathanw u_int16_t adapterConfig; 575 1.2.2.2 nathanw 576 1.2.2.2 nathanw if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 577 1.2.2.2 nathanw printf("%s: cs_get_params: EEPROM missing or bad\n", 578 1.2.2.2 nathanw sc->sc_dev.dv_xname); 579 1.2.2.2 nathanw return (CS_ERROR); 580 1.2.2.2 nathanw } 581 1.2.2.2 nathanw 582 1.2.2.2 nathanw /* Get ISA configuration from the EEPROM */ 583 1.2.2.2 nathanw if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ISA_CFG, 584 1.2.2.2 nathanw &isaConfig) == CS_ERROR) 585 1.2.2.2 nathanw goto eeprom_bad; 586 1.2.2.2 nathanw 587 1.2.2.2 nathanw /* Get adapter configuration from the EEPROM */ 588 1.2.2.2 nathanw if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ADPTR_CFG, 589 1.2.2.2 nathanw &adapterConfig) == CS_ERROR) 590 1.2.2.2 nathanw goto eeprom_bad; 591 1.2.2.2 nathanw 592 1.2.2.2 nathanw /* Copy the USE_SA flag */ 593 1.2.2.2 nathanw if (isaConfig & ISA_CFG_USE_SA) 594 1.2.2.2 nathanw sc->sc_cfgflags |= CFGFLG_USE_SA; 595 1.2.2.2 nathanw 596 1.2.2.2 nathanw /* Copy the IO Channel Ready flag */ 597 1.2.2.2 nathanw if (isaConfig & ISA_CFG_IOCHRDY) 598 1.2.2.2 nathanw sc->sc_cfgflags |= CFGFLG_IOCHRDY; 599 1.2.2.2 nathanw 600 1.2.2.2 nathanw /* Copy the DC/DC Polarity flag */ 601 1.2.2.2 nathanw if (adapterConfig & ADPTR_CFG_DCDC_POL) 602 1.2.2.2 nathanw sc->sc_cfgflags |= CFGFLG_DCDC_POL; 603 1.2.2.2 nathanw 604 1.2.2.2 nathanw return (CS_OK); 605 1.2.2.2 nathanw 606 1.2.2.2 nathanw eeprom_bad: 607 1.2.2.2 nathanw printf("%s: cs_get_params: unable to read from EEPROM\n", 608 1.2.2.2 nathanw sc->sc_dev.dv_xname); 609 1.2.2.2 nathanw return (CS_ERROR); 610 1.2.2.2 nathanw } 611 1.2.2.2 nathanw 612 1.2.2.2 nathanw int 613 1.2.2.2 nathanw cs_get_enaddr(sc) 614 1.2.2.2 nathanw struct cs_softc *sc; 615 1.2.2.2 nathanw { 616 1.2.2.2 nathanw u_int16_t *myea; 617 1.2.2.2 nathanw 618 1.2.2.2 nathanw if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 619 1.2.2.2 nathanw printf("%s: cs_get_enaddr: EEPROM missing or bad\n", 620 1.2.2.2 nathanw sc->sc_dev.dv_xname); 621 1.2.2.2 nathanw return (CS_ERROR); 622 1.2.2.2 nathanw } 623 1.2.2.2 nathanw 624 1.2.2.2 nathanw myea = (u_int16_t *)sc->sc_enaddr; 625 1.2.2.2 nathanw 626 1.2.2.2 nathanw /* Get Ethernet address from the EEPROM */ 627 1.2.2.2 nathanw /* XXX this will likely lose on a big-endian machine. -- cgd */ 628 1.2.2.2 nathanw if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_H, 629 1.2.2.2 nathanw &myea[0]) == CS_ERROR) 630 1.2.2.2 nathanw goto eeprom_bad; 631 1.2.2.2 nathanw if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_M, 632 1.2.2.2 nathanw &myea[1]) == CS_ERROR) 633 1.2.2.2 nathanw goto eeprom_bad; 634 1.2.2.2 nathanw if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_L, 635 1.2.2.2 nathanw &myea[2]) == CS_ERROR) 636 1.2.2.2 nathanw goto eeprom_bad; 637 1.2.2.2 nathanw 638 1.2.2.2 nathanw return (CS_OK); 639 1.2.2.2 nathanw 640 1.2.2.2 nathanw eeprom_bad: 641 1.2.2.2 nathanw printf("%s: cs_get_enaddr: unable to read from EEPROM\n", 642 1.2.2.2 nathanw sc->sc_dev.dv_xname); 643 1.2.2.2 nathanw return (CS_ERROR); 644 1.2.2.2 nathanw } 645 1.2.2.2 nathanw 646 1.2.2.2 nathanw int 647 1.2.2.2 nathanw cs_reset_chip(sc) 648 1.2.2.2 nathanw struct cs_softc *sc; 649 1.2.2.2 nathanw { 650 1.2.2.2 nathanw int intState; 651 1.2.2.2 nathanw int x; 652 1.2.2.2 nathanw 653 1.2.2.2 nathanw /* Disable interrupts at the CPU so reset command is atomic */ 654 1.2.2.2 nathanw intState = splnet(); 655 1.2.2.2 nathanw 656 1.2.2.2 nathanw /* 657 1.2.2.2 nathanw * We are now resetting the chip 658 1.2.2.2 nathanw * 659 1.2.2.2 nathanw * A spurious interrupt is generated by the chip when it is reset. This 660 1.2.2.2 nathanw * variable informs the interrupt handler to ignore this interrupt. 661 1.2.2.2 nathanw */ 662 1.2.2.2 nathanw sc->sc_resetting = TRUE; 663 1.2.2.2 nathanw 664 1.2.2.2 nathanw /* Issue a reset command to the chip */ 665 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET); 666 1.2.2.2 nathanw 667 1.2.2.2 nathanw /* Re-enable interrupts at the CPU */ 668 1.2.2.2 nathanw splx(intState); 669 1.2.2.2 nathanw 670 1.2.2.2 nathanw /* The chip is always in IO mode after a reset */ 671 1.2.2.2 nathanw sc->sc_memorymode = FALSE; 672 1.2.2.2 nathanw 673 1.2.2.2 nathanw /* If transmission was in progress, it is not now */ 674 1.2.2.2 nathanw sc->sc_txbusy = FALSE; 675 1.2.2.2 nathanw 676 1.2.2.2 nathanw /* 677 1.2.2.2 nathanw * there was a delay(125); here, but it seems uneccesary 125 usec is 678 1.2.2.2 nathanw * 1/8000 of a second, not 1/8 of a second. the data sheet advises 679 1.2.2.2 nathanw * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below 680 1.2.2.2 nathanw * should be sufficient. 681 1.2.2.2 nathanw */ 682 1.2.2.2 nathanw 683 1.2.2.2 nathanw /* Transition SBHE to switch chip from 8-bit to 16-bit */ 684 1.2.2.2 nathanw bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 0); 685 1.2.2.2 nathanw bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 1); 686 1.2.2.2 nathanw bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 0); 687 1.2.2.2 nathanw bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 1); 688 1.2.2.2 nathanw 689 1.2.2.2 nathanw /* Wait until the EEPROM is not busy */ 690 1.2.2.2 nathanw for (x = 0; x < MAXLOOP; x++) { 691 1.2.2.2 nathanw if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY)) 692 1.2.2.2 nathanw break; 693 1.2.2.2 nathanw } 694 1.2.2.2 nathanw 695 1.2.2.2 nathanw if (x == MAXLOOP) 696 1.2.2.2 nathanw return CS_ERROR; 697 1.2.2.2 nathanw 698 1.2.2.2 nathanw /* Wait until initialization is done */ 699 1.2.2.2 nathanw for (x = 0; x < MAXLOOP; x++) { 700 1.2.2.2 nathanw if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE) 701 1.2.2.2 nathanw break; 702 1.2.2.2 nathanw } 703 1.2.2.2 nathanw 704 1.2.2.2 nathanw if (x == MAXLOOP) 705 1.2.2.2 nathanw return CS_ERROR; 706 1.2.2.2 nathanw 707 1.2.2.2 nathanw /* Reset is no longer in progress */ 708 1.2.2.2 nathanw sc->sc_resetting = FALSE; 709 1.2.2.2 nathanw 710 1.2.2.2 nathanw return CS_OK; 711 1.2.2.2 nathanw } 712 1.2.2.2 nathanw 713 1.2.2.2 nathanw int 714 1.2.2.2 nathanw cs_verify_eeprom(iot, ioh) 715 1.2.2.2 nathanw bus_space_tag_t iot; 716 1.2.2.2 nathanw bus_space_handle_t ioh; 717 1.2.2.2 nathanw { 718 1.2.2.2 nathanw u_int16_t self_status; 719 1.2.2.2 nathanw 720 1.2.2.2 nathanw /* Verify that the EEPROM is present and OK */ 721 1.2.2.2 nathanw self_status = CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST); 722 1.2.2.2 nathanw if (((self_status & SELF_ST_EEP_PRES) && 723 1.2.2.2 nathanw (self_status & SELF_ST_EEP_OK)) == 0) 724 1.2.2.2 nathanw return (CS_ERROR); 725 1.2.2.2 nathanw 726 1.2.2.2 nathanw return (CS_OK); 727 1.2.2.2 nathanw } 728 1.2.2.2 nathanw 729 1.2.2.2 nathanw int 730 1.2.2.2 nathanw cs_read_eeprom(iot, ioh, offset, pValue) 731 1.2.2.2 nathanw bus_space_tag_t iot; 732 1.2.2.2 nathanw bus_space_handle_t ioh; 733 1.2.2.2 nathanw int offset; 734 1.2.2.2 nathanw u_int16_t *pValue; 735 1.2.2.2 nathanw { 736 1.2.2.2 nathanw int x; 737 1.2.2.2 nathanw 738 1.2.2.2 nathanw /* Ensure that the EEPROM is not busy */ 739 1.2.2.2 nathanw for (x = 0; x < MAXLOOP; x++) { 740 1.2.2.2 nathanw if (!(CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST) & 741 1.2.2.2 nathanw SELF_ST_SI_BUSY)) 742 1.2.2.2 nathanw break; 743 1.2.2.2 nathanw } 744 1.2.2.2 nathanw 745 1.2.2.2 nathanw if (x == MAXLOOP) 746 1.2.2.2 nathanw return (CS_ERROR); 747 1.2.2.2 nathanw 748 1.2.2.2 nathanw /* Issue the command to read the offset within the EEPROM */ 749 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE_IO(iot, ioh, PKTPG_EEPROM_CMD, 750 1.2.2.2 nathanw offset | EEPROM_CMD_READ); 751 1.2.2.2 nathanw 752 1.2.2.2 nathanw /* Wait until the command is completed */ 753 1.2.2.2 nathanw for (x = 0; x < MAXLOOP; x++) { 754 1.2.2.2 nathanw if (!(CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST) & 755 1.2.2.2 nathanw SELF_ST_SI_BUSY)) 756 1.2.2.2 nathanw break; 757 1.2.2.2 nathanw } 758 1.2.2.2 nathanw 759 1.2.2.2 nathanw if (x == MAXLOOP) 760 1.2.2.2 nathanw return (CS_ERROR); 761 1.2.2.2 nathanw 762 1.2.2.2 nathanw /* Get the EEPROM data from the EEPROM Data register */ 763 1.2.2.2 nathanw *pValue = CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_EEPROM_DATA); 764 1.2.2.2 nathanw 765 1.2.2.2 nathanw return (CS_OK); 766 1.2.2.2 nathanw } 767 1.2.2.2 nathanw 768 1.2.2.2 nathanw void 769 1.2.2.2 nathanw cs_initChip(sc) 770 1.2.2.2 nathanw struct cs_softc *sc; 771 1.2.2.2 nathanw { 772 1.2.2.2 nathanw u_int16_t busCtl; 773 1.2.2.2 nathanw u_int16_t selfCtl; 774 1.2.2.2 nathanw u_int16_t *myea; 775 1.2.2.2 nathanw u_int16_t isaId; 776 1.2.2.2 nathanw int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media); 777 1.2.2.2 nathanw 778 1.2.2.2 nathanw /* Disable reception and transmission of frames */ 779 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 780 1.2.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) & 781 1.2.2.2 nathanw ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON); 782 1.2.2.2 nathanw 783 1.2.2.2 nathanw /* Disable interrupt at the chip */ 784 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 785 1.2.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL); 786 1.2.2.2 nathanw 787 1.2.2.2 nathanw /* If IOCHRDY is enabled then clear the bit in the busCtl register */ 788 1.2.2.2 nathanw busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL); 789 1.2.2.2 nathanw if (sc->sc_cfgflags & CFGFLG_IOCHRDY) { 790 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 791 1.2.2.2 nathanw busCtl & ~BUS_CTL_IOCHRDY); 792 1.2.2.2 nathanw } else { 793 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 794 1.2.2.2 nathanw busCtl | BUS_CTL_IOCHRDY); 795 1.2.2.2 nathanw } 796 1.2.2.2 nathanw 797 1.2.2.2 nathanw /* Set the Line Control register to match the media type */ 798 1.2.2.2 nathanw if (media == IFM_10_T) 799 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET); 800 1.2.2.2 nathanw else 801 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY); 802 1.2.2.2 nathanw 803 1.2.2.2 nathanw /* 804 1.2.2.2 nathanw * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to 805 1.2.2.2 nathanw * enable the DC/DC converter 806 1.2.2.2 nathanw */ 807 1.2.2.2 nathanw selfCtl = SELF_CTL_HC1E; 808 1.2.2.2 nathanw 809 1.2.2.2 nathanw /* If the media type is 10Base2 */ 810 1.2.2.2 nathanw if (media == IFM_10_2) { 811 1.2.2.2 nathanw /* 812 1.2.2.2 nathanw * Enable the DC/DC converter if it has a low enable. 813 1.2.2.2 nathanw */ 814 1.2.2.2 nathanw if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0) 815 1.2.2.2 nathanw /* 816 1.2.2.2 nathanw * Set the HCB1 bit, which causes the HC1 pin to go 817 1.2.2.2 nathanw * low. 818 1.2.2.2 nathanw */ 819 1.2.2.2 nathanw selfCtl |= SELF_CTL_HCB1; 820 1.2.2.2 nathanw } else { /* Media type is 10BaseT or AUI */ 821 1.2.2.2 nathanw /* 822 1.2.2.2 nathanw * Disable the DC/DC converter if it has a high enable. 823 1.2.2.2 nathanw */ 824 1.2.2.2 nathanw if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) { 825 1.2.2.2 nathanw /* 826 1.2.2.2 nathanw * Set the HCB1 bit, which causes the HC1 pin to go 827 1.2.2.2 nathanw * low. 828 1.2.2.2 nathanw */ 829 1.2.2.2 nathanw selfCtl |= SELF_CTL_HCB1; 830 1.2.2.2 nathanw } 831 1.2.2.2 nathanw } 832 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl); 833 1.2.2.2 nathanw 834 1.2.2.2 nathanw /* enable normal link pulse */ 835 1.2.2.2 nathanw if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M) 836 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE); 837 1.2.2.2 nathanw 838 1.2.2.2 nathanw /* Enable full-duplex, if appropriate */ 839 1.2.2.2 nathanw if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 840 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX); 841 1.2.2.2 nathanw 842 1.2.2.2 nathanw /* RX_CTL set in cs_set_ladr_filt(), below */ 843 1.2.2.2 nathanw 844 1.2.2.2 nathanw /* enable all transmission interrupts */ 845 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE); 846 1.2.2.2 nathanw 847 1.2.2.2 nathanw /* Accept all receive interrupts */ 848 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE); 849 1.2.2.2 nathanw 850 1.2.2.2 nathanw /* 851 1.2.2.2 nathanw * Configure Operational Modes 852 1.2.2.2 nathanw * 853 1.2.2.2 nathanw * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this is 854 1.2.2.2 nathanw * a better way to do it because the card has a counter which can be 855 1.2.2.2 nathanw * read to update the RX_MISS counter. This saves many interupts. 856 1.2.2.2 nathanw * 857 1.2.2.2 nathanw * I have turned on the tx and rx overflow interupts to counter using 858 1.2.2.2 nathanw * the receive miss interrupt. This is a better estimate of errors 859 1.2.2.2 nathanw * and requires lower system overhead. 860 1.2.2.2 nathanw */ 861 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE | 862 1.2.2.2 nathanw BUF_CFG_RX_DMA_IE); 863 1.2.2.2 nathanw 864 1.2.2.2 nathanw if (sc->sc_dma_chipinit) 865 1.2.2.2 nathanw (*sc->sc_dma_chipinit)(sc); 866 1.2.2.2 nathanw 867 1.2.2.2 nathanw /* If memory mode is enabled */ 868 1.2.2.2 nathanw if (sc->sc_cfgflags & CFGFLG_MEM_MODE) { 869 1.2.2.2 nathanw /* If external logic is present for address decoding */ 870 1.2.2.2 nathanw if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) { 871 1.2.2.2 nathanw /* 872 1.2.2.2 nathanw * Program the external logic to decode address bits 873 1.2.2.2 nathanw * SA20-SA23 874 1.2.2.2 nathanw */ 875 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD, 876 1.2.2.2 nathanw ((sc->sc_pktpgaddr & 0xffffff) >> 20) | 877 1.2.2.2 nathanw EEPROM_CMD_ELSEL); 878 1.2.2.2 nathanw } 879 1.2.2.2 nathanw 880 1.2.2.2 nathanw /* 881 1.2.2.2 nathanw * Write the packet page base physical address to the memory 882 1.2.2.2 nathanw * base register. 883 1.2.2.2 nathanw */ 884 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0, 885 1.2.2.2 nathanw sc->sc_pktpgaddr & 0xFFFF); 886 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2, 887 1.2.2.2 nathanw sc->sc_pktpgaddr >> 16); 888 1.2.2.2 nathanw busCtl = BUS_CTL_MEM_MODE; 889 1.2.2.2 nathanw 890 1.2.2.2 nathanw /* tell the chip to read the addresses off the SA pins */ 891 1.2.2.2 nathanw if (sc->sc_cfgflags & CFGFLG_USE_SA) { 892 1.2.2.2 nathanw busCtl |= BUS_CTL_USE_SA; 893 1.2.2.2 nathanw } 894 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 895 1.2.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl); 896 1.2.2.2 nathanw 897 1.2.2.2 nathanw /* We are in memory mode now! */ 898 1.2.2.2 nathanw sc->sc_memorymode = TRUE; 899 1.2.2.2 nathanw 900 1.2.2.2 nathanw /* 901 1.2.2.2 nathanw * wait here (10ms) for the chip to swap over. this is the 902 1.2.2.2 nathanw * maximum time that this could take. 903 1.2.2.2 nathanw */ 904 1.2.2.2 nathanw delay(10000); 905 1.2.2.2 nathanw 906 1.2.2.2 nathanw /* Verify that we can read from the chip */ 907 1.2.2.2 nathanw isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 908 1.2.2.2 nathanw 909 1.2.2.2 nathanw /* 910 1.2.2.2 nathanw * As a last minute sanity check before actually using mapped 911 1.2.2.2 nathanw * memory we verify that we can read the isa number from the 912 1.2.2.2 nathanw * chip in memory mode. 913 1.2.2.2 nathanw */ 914 1.2.2.2 nathanw if (isaId != EISA_NUM_CRYSTAL) { 915 1.2.2.2 nathanw printf("%s: failed to enable memory mode\n", 916 1.2.2.2 nathanw sc->sc_dev.dv_xname); 917 1.2.2.2 nathanw sc->sc_memorymode = FALSE; 918 1.2.2.2 nathanw } else { 919 1.2.2.2 nathanw /* 920 1.2.2.2 nathanw * we are in memory mode so if we aren't using DMA, 921 1.2.2.2 nathanw * then program the chip to interrupt early. 922 1.2.2.2 nathanw */ 923 1.2.2.2 nathanw if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) { 924 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 925 1.2.2.2 nathanw BUF_CFG_RX_DEST_IE | 926 1.2.2.2 nathanw BUF_CFG_RX_MISS_OVER_IE | 927 1.2.2.2 nathanw BUF_CFG_TX_COL_OVER_IE); 928 1.2.2.2 nathanw } 929 1.2.2.2 nathanw } 930 1.2.2.2 nathanw 931 1.2.2.2 nathanw } 932 1.2.2.2 nathanw 933 1.2.2.2 nathanw /* Put Ethernet address into the Individual Address register */ 934 1.2.2.2 nathanw myea = (u_int16_t *)sc->sc_enaddr; 935 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 0, myea[0]); 936 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 2, myea[1]); 937 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 4, myea[2]); 938 1.2.2.2 nathanw 939 1.2.2.2 nathanw if (sc->sc_irq != -1) { 940 1.2.2.2 nathanw /* Set the interrupt level in the chip */ 941 1.2.2.2 nathanw if (sc->sc_prodid == PROD_ID_CS8900) { 942 1.2.2.2 nathanw if (sc->sc_irq == 5) { 943 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3); 944 1.2.2.2 nathanw } else { 945 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, (sc->sc_irq) - 10); 946 1.2.2.2 nathanw } 947 1.2.2.2 nathanw } 948 1.2.2.2 nathanw else { /* CS8920 */ 949 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, sc->sc_irq); 950 1.2.2.2 nathanw } 951 1.2.2.2 nathanw } 952 1.2.2.2 nathanw 953 1.2.2.2 nathanw /* write the multicast mask to the address filter register */ 954 1.2.2.2 nathanw cs_set_ladr_filt(sc, &sc->sc_ethercom); 955 1.2.2.2 nathanw 956 1.2.2.2 nathanw /* Enable reception and transmission of frames */ 957 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 958 1.2.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) | 959 1.2.2.2 nathanw LINE_CTL_RX_ON | LINE_CTL_TX_ON); 960 1.2.2.2 nathanw 961 1.2.2.2 nathanw /* Enable interrupt at the chip */ 962 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 963 1.2.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL); 964 1.2.2.2 nathanw } 965 1.2.2.2 nathanw 966 1.2.2.2 nathanw int 967 1.2.2.2 nathanw cs_init(ifp) 968 1.2.2.2 nathanw struct ifnet *ifp; 969 1.2.2.2 nathanw { 970 1.2.2.2 nathanw int intState; 971 1.2.2.2 nathanw int error = CS_OK; 972 1.2.2.2 nathanw struct cs_softc *sc = ifp->if_softc; 973 1.2.2.2 nathanw 974 1.2.2.2 nathanw if (cs_enable(sc)) 975 1.2.2.2 nathanw goto out; 976 1.2.2.2 nathanw 977 1.2.2.2 nathanw cs_stop(ifp, 0); 978 1.2.2.2 nathanw 979 1.2.2.2 nathanw intState = splnet(); 980 1.2.2.2 nathanw 981 1.2.2.2 nathanw #if 0 982 1.2.2.2 nathanw /* Mark the interface as down */ 983 1.2.2.2 nathanw sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING); 984 1.2.2.2 nathanw #endif 985 1.2.2.2 nathanw 986 1.2.2.2 nathanw #ifdef CS_DEBUG 987 1.2.2.2 nathanw /* Enable debugging */ 988 1.2.2.2 nathanw sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG; 989 1.2.2.2 nathanw #endif 990 1.2.2.2 nathanw 991 1.2.2.2 nathanw /* Reset the chip */ 992 1.2.2.2 nathanw if ((error = cs_reset_chip(sc)) == CS_OK) { 993 1.2.2.2 nathanw /* Initialize the chip */ 994 1.2.2.2 nathanw cs_initChip(sc); 995 1.2.2.2 nathanw 996 1.2.2.2 nathanw /* Mark the interface as running */ 997 1.2.2.2 nathanw sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 998 1.2.2.2 nathanw sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 999 1.2.2.2 nathanw sc->sc_ethercom.ec_if.if_timer = 0; 1000 1.2.2.2 nathanw 1001 1.2.2.2 nathanw /* Assume we have carrier until we are told otherwise. */ 1002 1.2.2.2 nathanw sc->sc_carrier = 1; 1003 1.2.2.2 nathanw } else { 1004 1.2.2.2 nathanw printf("%s: unable to reset chip\n", sc->sc_dev.dv_xname); 1005 1.2.2.2 nathanw } 1006 1.2.2.2 nathanw 1007 1.2.2.2 nathanw splx(intState); 1008 1.2.2.2 nathanw out: 1009 1.2.2.2 nathanw if (error == CS_OK) 1010 1.2.2.2 nathanw return 0; 1011 1.2.2.2 nathanw return EIO; 1012 1.2.2.2 nathanw } 1013 1.2.2.2 nathanw 1014 1.2.2.2 nathanw void 1015 1.2.2.2 nathanw cs_set_ladr_filt(sc, ec) 1016 1.2.2.2 nathanw struct cs_softc *sc; 1017 1.2.2.2 nathanw struct ethercom *ec; 1018 1.2.2.2 nathanw { 1019 1.2.2.2 nathanw struct ifnet *ifp = &ec->ec_if; 1020 1.2.2.2 nathanw struct ether_multi *enm; 1021 1.2.2.2 nathanw struct ether_multistep step; 1022 1.2.2.2 nathanw u_int16_t af[4]; 1023 1.2.2.2 nathanw u_int16_t port, mask, index; 1024 1.2.2.2 nathanw 1025 1.2.2.2 nathanw /* 1026 1.2.2.2 nathanw * Set up multicast address filter by passing all multicast addresses 1027 1.2.2.2 nathanw * through a crc generator, and then using the high order 6 bits as an 1028 1.2.2.2 nathanw * index into the 64 bit logical address filter. The high order bit 1029 1.2.2.2 nathanw * selects the word, while the rest of the bits select the bit within 1030 1.2.2.2 nathanw * the word. 1031 1.2.2.2 nathanw */ 1032 1.2.2.2 nathanw if (ifp->if_flags & IFF_PROMISC) { 1033 1.2.2.2 nathanw /* accept all valid frames. */ 1034 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1035 1.2.2.2 nathanw RX_CTL_PROMISC_A | RX_CTL_RX_OK_A | 1036 1.2.2.2 nathanw RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1037 1.2.2.2 nathanw ifp->if_flags |= IFF_ALLMULTI; 1038 1.2.2.2 nathanw return; 1039 1.2.2.2 nathanw } 1040 1.2.2.2 nathanw 1041 1.2.2.2 nathanw /* 1042 1.2.2.2 nathanw * accept frames if a. crc valid, b. individual address match c. 1043 1.2.2.2 nathanw * broadcast address,and d. multicast addresses matched in the hash 1044 1.2.2.2 nathanw * filter 1045 1.2.2.2 nathanw */ 1046 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1047 1.2.2.2 nathanw RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1048 1.2.2.2 nathanw 1049 1.2.2.2 nathanw 1050 1.2.2.2 nathanw /* 1051 1.2.2.2 nathanw * start off with all multicast flag clear, set it if we need to 1052 1.2.2.2 nathanw * later, otherwise we will leave it. 1053 1.2.2.2 nathanw */ 1054 1.2.2.2 nathanw ifp->if_flags &= ~IFF_ALLMULTI; 1055 1.2.2.2 nathanw af[0] = af[1] = af[2] = af[3] = 0x0000; 1056 1.2.2.2 nathanw 1057 1.2.2.2 nathanw /* 1058 1.2.2.2 nathanw * Loop through all the multicast addresses unless we get a range of 1059 1.2.2.2 nathanw * addresses, in which case we will just accept all packets. 1060 1.2.2.2 nathanw * Justification for this is given in the next comment. 1061 1.2.2.2 nathanw */ 1062 1.2.2.2 nathanw ETHER_FIRST_MULTI(step, ec, enm); 1063 1.2.2.2 nathanw while (enm != NULL) { 1064 1.2.2.2 nathanw if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1065 1.2.2.2 nathanw sizeof enm->enm_addrlo)) { 1066 1.2.2.2 nathanw /* 1067 1.2.2.2 nathanw * We must listen to a range of multicast addresses. 1068 1.2.2.2 nathanw * For now, just accept all multicasts, rather than 1069 1.2.2.2 nathanw * trying to set only those filter bits needed to match 1070 1.2.2.2 nathanw * the range. (At this time, the only use of address 1071 1.2.2.2 nathanw * ranges is for IP multicast routing, for which the 1072 1.2.2.2 nathanw * range is big enough to require all bits set.) 1073 1.2.2.2 nathanw */ 1074 1.2.2.2 nathanw ifp->if_flags |= IFF_ALLMULTI; 1075 1.2.2.2 nathanw af[0] = af[1] = af[2] = af[3] = 0xffff; 1076 1.2.2.2 nathanw break; 1077 1.2.2.2 nathanw } else { 1078 1.2.2.2 nathanw /* 1079 1.2.2.2 nathanw * we have got an individual address so just set that 1080 1.2.2.2 nathanw * bit. 1081 1.2.2.2 nathanw */ 1082 1.2.2.2 nathanw index = cs_hash_index(enm->enm_addrlo); 1083 1.2.2.2 nathanw 1084 1.2.2.2 nathanw /* Set the bit the Logical address filter. */ 1085 1.2.2.2 nathanw port = (u_int16_t) (index >> 4); 1086 1.2.2.2 nathanw mask = (u_int16_t) (1 << (index & 0xf)); 1087 1.2.2.2 nathanw af[port] |= mask; 1088 1.2.2.2 nathanw 1089 1.2.2.2 nathanw ETHER_NEXT_MULTI(step, enm); 1090 1.2.2.2 nathanw } 1091 1.2.2.2 nathanw } 1092 1.2.2.2 nathanw 1093 1.2.2.2 nathanw /* now program the chip with the addresses */ 1094 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]); 1095 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]); 1096 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]); 1097 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]); 1098 1.2.2.2 nathanw return; 1099 1.2.2.2 nathanw } 1100 1.2.2.2 nathanw 1101 1.2.2.2 nathanw u_int16_t 1102 1.2.2.2 nathanw cs_hash_index(addr) 1103 1.2.2.2 nathanw char *addr; 1104 1.2.2.2 nathanw { 1105 1.2.2.2 nathanw u_int POLY = 0x04c11db6; 1106 1.2.2.2 nathanw u_int crc_value = 0xffffffff; 1107 1.2.2.2 nathanw u_int16_t hash_code = 0; 1108 1.2.2.2 nathanw int i; 1109 1.2.2.2 nathanw u_int current_bit; 1110 1.2.2.2 nathanw char current_byte = *addr; 1111 1.2.2.2 nathanw u_int cur_crc_high; 1112 1.2.2.2 nathanw 1113 1.2.2.2 nathanw for (i = 0; i < 6; i++) { 1114 1.2.2.2 nathanw current_byte = *addr; 1115 1.2.2.2 nathanw addr++; 1116 1.2.2.2 nathanw 1117 1.2.2.2 nathanw for (current_bit = 8; current_bit; current_bit--) { 1118 1.2.2.2 nathanw cur_crc_high = crc_value >> 31; 1119 1.2.2.2 nathanw crc_value <<= 1; 1120 1.2.2.2 nathanw if (cur_crc_high ^ (current_byte & 0x01)) { 1121 1.2.2.2 nathanw crc_value ^= POLY; 1122 1.2.2.2 nathanw crc_value |= 0x00000001; 1123 1.2.2.2 nathanw } 1124 1.2.2.2 nathanw current_byte >>= 1; 1125 1.2.2.2 nathanw } 1126 1.2.2.2 nathanw } 1127 1.2.2.2 nathanw 1128 1.2.2.2 nathanw /* 1129 1.2.2.2 nathanw * The hash code is the 6 least significant bits of the CRC 1130 1.2.2.2 nathanw * in the reverse order: CRC[0] = hash[5],CRC[1] = hash[4],etc. 1131 1.2.2.2 nathanw */ 1132 1.2.2.2 nathanw for (i = 0; i < 6; i++) { 1133 1.2.2.2 nathanw hash_code = (u_int16_t) ((hash_code << 1) | 1134 1.2.2.2 nathanw (u_int16_t) ((crc_value >> i) & 0x00000001)); 1135 1.2.2.2 nathanw } 1136 1.2.2.2 nathanw 1137 1.2.2.2 nathanw return hash_code; 1138 1.2.2.2 nathanw } 1139 1.2.2.2 nathanw 1140 1.2.2.2 nathanw void 1141 1.2.2.2 nathanw cs_reset(arg) 1142 1.2.2.2 nathanw void *arg; 1143 1.2.2.2 nathanw { 1144 1.2.2.2 nathanw struct cs_softc *sc = arg; 1145 1.2.2.2 nathanw 1146 1.2.2.2 nathanw /* Mark the interface as down */ 1147 1.2.2.2 nathanw sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1148 1.2.2.2 nathanw 1149 1.2.2.2 nathanw /* Reset the chip */ 1150 1.2.2.2 nathanw cs_reset_chip(sc); 1151 1.2.2.2 nathanw } 1152 1.2.2.2 nathanw 1153 1.2.2.2 nathanw int 1154 1.2.2.2 nathanw cs_ioctl(ifp, cmd, data) 1155 1.2.2.2 nathanw struct ifnet *ifp; 1156 1.2.2.2 nathanw u_long cmd; 1157 1.2.2.2 nathanw caddr_t data; 1158 1.2.2.2 nathanw { 1159 1.2.2.2 nathanw struct cs_softc *sc = ifp->if_softc; 1160 1.2.2.2 nathanw struct ifreq *ifr = (struct ifreq *) data; 1161 1.2.2.2 nathanw int state; 1162 1.2.2.2 nathanw int result; 1163 1.2.2.2 nathanw 1164 1.2.2.2 nathanw state = splnet(); 1165 1.2.2.2 nathanw 1166 1.2.2.2 nathanw result = 0; /* only set if something goes wrong */ 1167 1.2.2.2 nathanw 1168 1.2.2.2 nathanw switch (cmd) { 1169 1.2.2.2 nathanw case SIOCGIFMEDIA: 1170 1.2.2.2 nathanw case SIOCSIFMEDIA: 1171 1.2.2.2 nathanw result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1172 1.2.2.2 nathanw break; 1173 1.2.2.2 nathanw 1174 1.2.2.2 nathanw default: 1175 1.2.2.2 nathanw result = ether_ioctl(ifp, cmd, data); 1176 1.2.2.2 nathanw if (result == ENETRESET) { 1177 1.2.2.2 nathanw if (CS_IS_ENABLED(sc)) { 1178 1.2.2.2 nathanw /* 1179 1.2.2.2 nathanw * Multicast list has changed. Set the 1180 1.2.2.2 nathanw * hardware filter accordingly. 1181 1.2.2.2 nathanw */ 1182 1.2.2.2 nathanw cs_set_ladr_filt(sc, &sc->sc_ethercom); 1183 1.2.2.2 nathanw } 1184 1.2.2.2 nathanw result = 0; 1185 1.2.2.2 nathanw } 1186 1.2.2.2 nathanw break; 1187 1.2.2.2 nathanw } 1188 1.2.2.2 nathanw 1189 1.2.2.2 nathanw splx(state); 1190 1.2.2.2 nathanw 1191 1.2.2.2 nathanw return result; 1192 1.2.2.2 nathanw } 1193 1.2.2.2 nathanw 1194 1.2.2.2 nathanw int 1195 1.2.2.2 nathanw cs_mediachange(ifp) 1196 1.2.2.2 nathanw struct ifnet *ifp; 1197 1.2.2.2 nathanw { 1198 1.2.2.2 nathanw 1199 1.2.2.2 nathanw /* 1200 1.2.2.2 nathanw * Current media is already set up. Just reset the interface 1201 1.2.2.2 nathanw * to let the new value take hold. 1202 1.2.2.2 nathanw */ 1203 1.2.2.2 nathanw cs_init(ifp); 1204 1.2.2.2 nathanw return (0); 1205 1.2.2.2 nathanw } 1206 1.2.2.2 nathanw 1207 1.2.2.2 nathanw void 1208 1.2.2.2 nathanw cs_mediastatus(ifp, ifmr) 1209 1.2.2.2 nathanw struct ifnet *ifp; 1210 1.2.2.2 nathanw struct ifmediareq *ifmr; 1211 1.2.2.2 nathanw { 1212 1.2.2.2 nathanw struct cs_softc *sc = ifp->if_softc; 1213 1.2.2.2 nathanw 1214 1.2.2.2 nathanw /* 1215 1.2.2.2 nathanw * The currently selected media is always the active media. 1216 1.2.2.2 nathanw */ 1217 1.2.2.2 nathanw ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media; 1218 1.2.2.2 nathanw 1219 1.2.2.2 nathanw if (ifp->if_flags & IFF_UP) { 1220 1.2.2.2 nathanw /* Interface up, status is valid. */ 1221 1.2.2.2 nathanw ifmr->ifm_status = IFM_AVALID | 1222 1.2.2.2 nathanw (sc->sc_carrier ? IFM_ACTIVE : 0); 1223 1.2.2.2 nathanw } 1224 1.2.2.2 nathanw else ifmr->ifm_status = 0; 1225 1.2.2.2 nathanw } 1226 1.2.2.2 nathanw 1227 1.2.2.2 nathanw int 1228 1.2.2.2 nathanw cs_intr(arg) 1229 1.2.2.2 nathanw void *arg; 1230 1.2.2.2 nathanw { 1231 1.2.2.2 nathanw struct cs_softc *sc = arg; 1232 1.2.2.2 nathanw u_int16_t Event; 1233 1.2.2.2 nathanw #if NRND > 0 1234 1.2.2.2 nathanw u_int16_t rndEvent; 1235 1.2.2.2 nathanw #endif 1236 1.2.2.2 nathanw 1237 1.2.2.2 nathanw /* Ignore any interrupts that happen while the chip is being reset */ 1238 1.2.2.2 nathanw if (sc->sc_resetting) { 1239 1.2.2.2 nathanw printf("%s: cs_intr: reset in progress\n", 1240 1.2.2.2 nathanw sc->sc_dev.dv_xname); 1241 1.2.2.2 nathanw return 1; 1242 1.2.2.2 nathanw } 1243 1.2.2.2 nathanw 1244 1.2.2.2 nathanw /* Read an event from the Interrupt Status Queue */ 1245 1.2.2.2 nathanw if (sc->sc_memorymode) 1246 1.2.2.2 nathanw Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1247 1.2.2.2 nathanw else 1248 1.2.2.2 nathanw Event = CS_READ_PORT(sc, PORT_ISQ); 1249 1.2.2.2 nathanw 1250 1.2.2.2 nathanw if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff) 1251 1.2.2.2 nathanw return 0; /* not ours */ 1252 1.2.2.2 nathanw 1253 1.2.2.2 nathanw #if NRND > 0 1254 1.2.2.2 nathanw rndEvent = Event; 1255 1.2.2.2 nathanw #endif 1256 1.2.2.2 nathanw 1257 1.2.2.2 nathanw /* Process all the events in the Interrupt Status Queue */ 1258 1.2.2.2 nathanw while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) { 1259 1.2.2.2 nathanw /* Dispatch to an event handler based on the register number */ 1260 1.2.2.2 nathanw switch (Event & REG_NUM_MASK) { 1261 1.2.2.2 nathanw case REG_NUM_RX_EVENT: 1262 1.2.2.2 nathanw cs_receive_event(sc, Event); 1263 1.2.2.2 nathanw break; 1264 1.2.2.2 nathanw case REG_NUM_TX_EVENT: 1265 1.2.2.2 nathanw cs_transmit_event(sc, Event); 1266 1.2.2.2 nathanw break; 1267 1.2.2.2 nathanw case REG_NUM_BUF_EVENT: 1268 1.2.2.2 nathanw cs_buffer_event(sc, Event); 1269 1.2.2.2 nathanw break; 1270 1.2.2.2 nathanw case REG_NUM_TX_COL: 1271 1.2.2.2 nathanw case REG_NUM_RX_MISS: 1272 1.2.2.2 nathanw cs_counter_event(sc, Event); 1273 1.2.2.2 nathanw break; 1274 1.2.2.2 nathanw default: 1275 1.2.2.2 nathanw printf("%s: unknown interrupt event 0x%x\n", 1276 1.2.2.2 nathanw sc->sc_dev.dv_xname, Event); 1277 1.2.2.2 nathanw break; 1278 1.2.2.2 nathanw } 1279 1.2.2.2 nathanw 1280 1.2.2.2 nathanw /* Read another event from the Interrupt Status Queue */ 1281 1.2.2.2 nathanw if (sc->sc_memorymode) 1282 1.2.2.2 nathanw Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1283 1.2.2.2 nathanw else 1284 1.2.2.2 nathanw Event = CS_READ_PORT(sc, PORT_ISQ); 1285 1.2.2.2 nathanw } 1286 1.2.2.2 nathanw 1287 1.2.2.2 nathanw /* have handled the interupt */ 1288 1.2.2.2 nathanw #if NRND > 0 1289 1.2.2.2 nathanw rnd_add_uint32(&sc->rnd_source, rndEvent); 1290 1.2.2.2 nathanw #endif 1291 1.2.2.2 nathanw return 1; 1292 1.2.2.2 nathanw } 1293 1.2.2.2 nathanw 1294 1.2.2.2 nathanw void 1295 1.2.2.2 nathanw cs_counter_event(sc, cntEvent) 1296 1.2.2.2 nathanw struct cs_softc *sc; 1297 1.2.2.2 nathanw u_int16_t cntEvent; 1298 1.2.2.2 nathanw { 1299 1.2.2.2 nathanw struct ifnet *ifp; 1300 1.2.2.2 nathanw u_int16_t errorCount; 1301 1.2.2.2 nathanw 1302 1.2.2.2 nathanw ifp = &sc->sc_ethercom.ec_if; 1303 1.2.2.2 nathanw 1304 1.2.2.2 nathanw switch (cntEvent & REG_NUM_MASK) { 1305 1.2.2.2 nathanw case REG_NUM_TX_COL: 1306 1.2.2.2 nathanw /* 1307 1.2.2.2 nathanw * the count should be read before an overflow occurs. 1308 1.2.2.2 nathanw */ 1309 1.2.2.2 nathanw errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL); 1310 1.2.2.2 nathanw /* 1311 1.2.2.2 nathanw * the tramsit event routine always checks the number of 1312 1.2.2.2 nathanw * collisions for any packet so we don't increment any 1313 1.2.2.2 nathanw * counters here, as they should already have been 1314 1.2.2.2 nathanw * considered. 1315 1.2.2.2 nathanw */ 1316 1.2.2.2 nathanw break; 1317 1.2.2.2 nathanw case REG_NUM_RX_MISS: 1318 1.2.2.2 nathanw /* 1319 1.2.2.2 nathanw * the count should be read before an overflow occurs. 1320 1.2.2.2 nathanw */ 1321 1.2.2.2 nathanw errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS); 1322 1.2.2.2 nathanw /* 1323 1.2.2.2 nathanw * Increment the input error count, the first 6bits are the 1324 1.2.2.2 nathanw * register id. 1325 1.2.2.2 nathanw */ 1326 1.2.2.2 nathanw ifp->if_ierrors += ((errorCount & 0xffC0) >> 6); 1327 1.2.2.2 nathanw break; 1328 1.2.2.2 nathanw default: 1329 1.2.2.2 nathanw /* do nothing */ 1330 1.2.2.2 nathanw break; 1331 1.2.2.2 nathanw } 1332 1.2.2.2 nathanw } 1333 1.2.2.2 nathanw 1334 1.2.2.2 nathanw void 1335 1.2.2.2 nathanw cs_buffer_event(sc, bufEvent) 1336 1.2.2.2 nathanw struct cs_softc *sc; 1337 1.2.2.2 nathanw u_int16_t bufEvent; 1338 1.2.2.2 nathanw { 1339 1.2.2.2 nathanw struct ifnet *ifp; 1340 1.2.2.2 nathanw 1341 1.2.2.2 nathanw ifp = &sc->sc_ethercom.ec_if; 1342 1.2.2.2 nathanw 1343 1.2.2.2 nathanw /* 1344 1.2.2.2 nathanw * multiple events can be in the buffer event register at one time so 1345 1.2.2.2 nathanw * a standard switch statement will not suffice, here every event 1346 1.2.2.2 nathanw * must be checked. 1347 1.2.2.2 nathanw */ 1348 1.2.2.2 nathanw 1349 1.2.2.2 nathanw /* 1350 1.2.2.2 nathanw * if 128 bits have been rxed by the time we get here, the dest event 1351 1.2.2.2 nathanw * will be cleared and 128 event will be set. 1352 1.2.2.2 nathanw */ 1353 1.2.2.2 nathanw if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) { 1354 1.2.2.2 nathanw cs_process_rx_early(sc); 1355 1.2.2.2 nathanw } 1356 1.2.2.2 nathanw 1357 1.2.2.2 nathanw if (bufEvent & BUF_EVENT_RX_DMA) { 1358 1.2.2.2 nathanw /* process the receive data */ 1359 1.2.2.2 nathanw if (sc->sc_dma_process_rx) 1360 1.2.2.2 nathanw (*sc->sc_dma_process_rx)(sc); 1361 1.2.2.2 nathanw else 1362 1.2.2.2 nathanw /* should panic? */ 1363 1.2.2.2 nathanw printf("%s: unexpected dma event\n", sc->sc_dev.dv_xname); 1364 1.2.2.2 nathanw } 1365 1.2.2.2 nathanw 1366 1.2.2.2 nathanw if (bufEvent & BUF_EVENT_TX_UNDR) { 1367 1.2.2.2 nathanw #if 0 1368 1.2.2.2 nathanw /* 1369 1.2.2.2 nathanw * This can happen occasionally, and it's not worth worrying 1370 1.2.2.2 nathanw * about. 1371 1.2.2.2 nathanw */ 1372 1.2.2.2 nathanw printf("%s: transmit underrun (%d -> %d)\n", 1373 1.2.2.2 nathanw sc->sc_dev.dv_xname, sc->sc_xe_ent, 1374 1.2.2.2 nathanw cs_xmit_early_table[sc->sc_xe_ent].worse); 1375 1.2.2.2 nathanw #endif 1376 1.2.2.2 nathanw sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse; 1377 1.2.2.2 nathanw sc->sc_xe_togo = 1378 1.2.2.2 nathanw cs_xmit_early_table[sc->sc_xe_ent].better_count; 1379 1.2.2.2 nathanw 1380 1.2.2.2 nathanw /* had an underrun, transmit is finished */ 1381 1.2.2.2 nathanw sc->sc_txbusy = FALSE; 1382 1.2.2.2 nathanw } 1383 1.2.2.2 nathanw 1384 1.2.2.2 nathanw if (bufEvent & BUF_EVENT_SW_INT) { 1385 1.2.2.2 nathanw printf("%s: software initiated interrupt\n", 1386 1.2.2.2 nathanw sc->sc_dev.dv_xname); 1387 1.2.2.2 nathanw } 1388 1.2.2.2 nathanw } 1389 1.2.2.2 nathanw 1390 1.2.2.2 nathanw void 1391 1.2.2.2 nathanw cs_transmit_event(sc, txEvent) 1392 1.2.2.2 nathanw struct cs_softc *sc; 1393 1.2.2.2 nathanw u_int16_t txEvent; 1394 1.2.2.2 nathanw { 1395 1.2.2.2 nathanw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1396 1.2.2.2 nathanw 1397 1.2.2.2 nathanw /* If there were any errors transmitting this frame */ 1398 1.2.2.2 nathanw if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | TX_EVENT_OUT_WIN | 1399 1.2.2.2 nathanw TX_EVENT_JABBER | TX_EVENT_16_COLL)) { 1400 1.2.2.2 nathanw /* Increment the output error count */ 1401 1.2.2.2 nathanw ifp->if_oerrors++; 1402 1.2.2.2 nathanw 1403 1.2.2.2 nathanw /* Note carrier loss. */ 1404 1.2.2.2 nathanw if (txEvent & TX_EVENT_LOSS_CRS) 1405 1.2.2.2 nathanw sc->sc_carrier = 0; 1406 1.2.2.2 nathanw 1407 1.2.2.2 nathanw /* If debugging is enabled then log error messages */ 1408 1.2.2.2 nathanw if (ifp->if_flags & IFF_DEBUG) { 1409 1.2.2.2 nathanw if (txEvent & TX_EVENT_LOSS_CRS) { 1410 1.2.2.2 nathanw printf("%s: lost carrier\n", 1411 1.2.2.2 nathanw sc->sc_dev.dv_xname); 1412 1.2.2.2 nathanw } 1413 1.2.2.2 nathanw if (txEvent & TX_EVENT_SQE_ERR) { 1414 1.2.2.2 nathanw printf("%s: SQE error\n", 1415 1.2.2.2 nathanw sc->sc_dev.dv_xname); 1416 1.2.2.2 nathanw } 1417 1.2.2.2 nathanw if (txEvent & TX_EVENT_OUT_WIN) { 1418 1.2.2.2 nathanw printf("%s: out-of-window collision\n", 1419 1.2.2.2 nathanw sc->sc_dev.dv_xname); 1420 1.2.2.2 nathanw } 1421 1.2.2.2 nathanw if (txEvent & TX_EVENT_JABBER) { 1422 1.2.2.2 nathanw printf("%s: jabber\n", sc->sc_dev.dv_xname); 1423 1.2.2.2 nathanw } 1424 1.2.2.2 nathanw if (txEvent & TX_EVENT_16_COLL) { 1425 1.2.2.2 nathanw printf("%s: 16 collisions\n", 1426 1.2.2.2 nathanw sc->sc_dev.dv_xname); 1427 1.2.2.2 nathanw } 1428 1.2.2.2 nathanw } 1429 1.2.2.2 nathanw } 1430 1.2.2.2 nathanw else { 1431 1.2.2.2 nathanw /* Transmission successful, carrier is up. */ 1432 1.2.2.2 nathanw sc->sc_carrier = 1; 1433 1.2.2.2 nathanw #ifdef SHARK 1434 1.2.2.2 nathanw ledNetActive(); 1435 1.2.2.2 nathanw #endif 1436 1.2.2.2 nathanw } 1437 1.2.2.2 nathanw 1438 1.2.2.2 nathanw /* Add the number of collisions for this frame */ 1439 1.2.2.2 nathanw if (txEvent & TX_EVENT_16_COLL) { 1440 1.2.2.2 nathanw ifp->if_collisions += 16; 1441 1.2.2.2 nathanw } else { 1442 1.2.2.2 nathanw ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11); 1443 1.2.2.2 nathanw } 1444 1.2.2.2 nathanw 1445 1.2.2.2 nathanw ifp->if_opackets++; 1446 1.2.2.2 nathanw 1447 1.2.2.2 nathanw /* Transmission is no longer in progress */ 1448 1.2.2.2 nathanw sc->sc_txbusy = FALSE; 1449 1.2.2.2 nathanw 1450 1.2.2.2 nathanw /* If there is more to transmit */ 1451 1.2.2.2 nathanw if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 1452 1.2.2.2 nathanw /* Start the next transmission */ 1453 1.2.2.2 nathanw cs_start_output(ifp); 1454 1.2.2.2 nathanw } 1455 1.2.2.2 nathanw } 1456 1.2.2.2 nathanw 1457 1.2.2.2 nathanw void 1458 1.2.2.2 nathanw cs_print_rx_errors(sc, rxEvent) 1459 1.2.2.2 nathanw struct cs_softc *sc; 1460 1.2.2.2 nathanw u_int16_t rxEvent; 1461 1.2.2.2 nathanw { 1462 1.2.2.2 nathanw 1463 1.2.2.2 nathanw if (rxEvent & RX_EVENT_RUNT) 1464 1.2.2.2 nathanw printf("%s: runt\n", sc->sc_dev.dv_xname); 1465 1.2.2.2 nathanw 1466 1.2.2.2 nathanw if (rxEvent & RX_EVENT_X_DATA) 1467 1.2.2.2 nathanw printf("%s: extra data\n", sc->sc_dev.dv_xname); 1468 1.2.2.2 nathanw 1469 1.2.2.2 nathanw if (rxEvent & RX_EVENT_CRC_ERR) { 1470 1.2.2.2 nathanw if (rxEvent & RX_EVENT_DRIBBLE) 1471 1.2.2.2 nathanw printf("%s: alignment error\n", sc->sc_dev.dv_xname); 1472 1.2.2.2 nathanw else 1473 1.2.2.2 nathanw printf("%s: CRC error\n", sc->sc_dev.dv_xname); 1474 1.2.2.2 nathanw } else { 1475 1.2.2.2 nathanw if (rxEvent & RX_EVENT_DRIBBLE) 1476 1.2.2.2 nathanw printf("%s: dribble bits\n", sc->sc_dev.dv_xname); 1477 1.2.2.2 nathanw } 1478 1.2.2.2 nathanw } 1479 1.2.2.2 nathanw 1480 1.2.2.2 nathanw void 1481 1.2.2.2 nathanw cs_receive_event(sc, rxEvent) 1482 1.2.2.2 nathanw struct cs_softc *sc; 1483 1.2.2.2 nathanw u_int16_t rxEvent; 1484 1.2.2.2 nathanw { 1485 1.2.2.2 nathanw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1486 1.2.2.2 nathanw 1487 1.2.2.2 nathanw /* If the frame was not received OK */ 1488 1.2.2.2 nathanw if (!(rxEvent & RX_EVENT_RX_OK)) { 1489 1.2.2.2 nathanw /* Increment the input error count */ 1490 1.2.2.2 nathanw ifp->if_ierrors++; 1491 1.2.2.2 nathanw 1492 1.2.2.2 nathanw /* 1493 1.2.2.2 nathanw * If debugging is enabled then log error messages. 1494 1.2.2.2 nathanw */ 1495 1.2.2.2 nathanw if (ifp->if_flags & IFF_DEBUG) { 1496 1.2.2.2 nathanw if (rxEvent != REG_NUM_RX_EVENT) { 1497 1.2.2.2 nathanw cs_print_rx_errors(sc, rxEvent); 1498 1.2.2.2 nathanw 1499 1.2.2.2 nathanw /* 1500 1.2.2.2 nathanw * Must read the length of all received 1501 1.2.2.2 nathanw * frames 1502 1.2.2.2 nathanw */ 1503 1.2.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1504 1.2.2.2 nathanw 1505 1.2.2.2 nathanw /* Skip the received frame */ 1506 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1507 1.2.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | 1508 1.2.2.2 nathanw RX_CFG_SKIP); 1509 1.2.2.2 nathanw } else { 1510 1.2.2.2 nathanw printf("%s: implied skip\n", 1511 1.2.2.2 nathanw sc->sc_dev.dv_xname); 1512 1.2.2.2 nathanw } 1513 1.2.2.2 nathanw } 1514 1.2.2.2 nathanw } else { 1515 1.2.2.2 nathanw /* 1516 1.2.2.2 nathanw * process the received frame and pass it up to the upper 1517 1.2.2.2 nathanw * layers. 1518 1.2.2.2 nathanw */ 1519 1.2.2.2 nathanw cs_process_receive(sc); 1520 1.2.2.2 nathanw } 1521 1.2.2.2 nathanw } 1522 1.2.2.2 nathanw 1523 1.2.2.2 nathanw void 1524 1.2.2.2 nathanw cs_ether_input(sc, m) 1525 1.2.2.2 nathanw struct cs_softc *sc; 1526 1.2.2.2 nathanw struct mbuf *m; 1527 1.2.2.2 nathanw { 1528 1.2.2.2 nathanw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1529 1.2.2.2 nathanw 1530 1.2.2.2 nathanw ifp->if_ipackets++; 1531 1.2.2.2 nathanw 1532 1.2.2.2 nathanw #if NBPFILTER > 0 1533 1.2.2.2 nathanw /* 1534 1.2.2.2 nathanw * Check if there's a BPF listener on this interface. 1535 1.2.2.2 nathanw * If so, hand off the raw packet to BPF. 1536 1.2.2.2 nathanw */ 1537 1.2.2.2 nathanw if (ifp->if_bpf) 1538 1.2.2.2 nathanw bpf_mtap(ifp->if_bpf, m); 1539 1.2.2.2 nathanw #endif 1540 1.2.2.2 nathanw 1541 1.2.2.2 nathanw /* Pass the packet up. */ 1542 1.2.2.2 nathanw (*ifp->if_input)(ifp, m); 1543 1.2.2.2 nathanw } 1544 1.2.2.2 nathanw 1545 1.2.2.2 nathanw void 1546 1.2.2.2 nathanw cs_process_receive(sc) 1547 1.2.2.2 nathanw struct cs_softc *sc; 1548 1.2.2.2 nathanw { 1549 1.2.2.2 nathanw struct ifnet *ifp; 1550 1.2.2.2 nathanw struct mbuf *m; 1551 1.2.2.2 nathanw int totlen; 1552 1.2.2.2 nathanw u_int16_t *pBuff, *pBuffLimit; 1553 1.2.2.2 nathanw int pad; 1554 1.2.2.2 nathanw unsigned int frameOffset; 1555 1.2.2.2 nathanw 1556 1.2.2.2 nathanw #ifdef SHARK 1557 1.2.2.2 nathanw ledNetActive(); 1558 1.2.2.2 nathanw #endif 1559 1.2.2.2 nathanw 1560 1.2.2.2 nathanw ifp = &sc->sc_ethercom.ec_if; 1561 1.2.2.2 nathanw 1562 1.2.2.2 nathanw /* Received a packet; carrier is up. */ 1563 1.2.2.2 nathanw sc->sc_carrier = 1; 1564 1.2.2.2 nathanw 1565 1.2.2.2 nathanw if (sc->sc_memorymode) { 1566 1.2.2.2 nathanw /* Initialize the frame offset */ 1567 1.2.2.2 nathanw frameOffset = PKTPG_RX_LENGTH; 1568 1.2.2.2 nathanw 1569 1.2.2.2 nathanw /* Get the length of the received frame */ 1570 1.2.2.2 nathanw totlen = CS_READ_PACKET_PAGE(sc, frameOffset); 1571 1.2.2.2 nathanw frameOffset += 2; 1572 1.2.2.2 nathanw } 1573 1.2.2.2 nathanw else { 1574 1.2.2.2 nathanw /* drop status */ 1575 1.2.2.2 nathanw CS_READ_PORT(sc, PORT_RXTX_DATA); 1576 1.2.2.2 nathanw 1577 1.2.2.2 nathanw /* Get the length of the received frame */ 1578 1.2.2.2 nathanw totlen = CS_READ_PORT(sc, PORT_RXTX_DATA); 1579 1.2.2.2 nathanw } 1580 1.2.2.2 nathanw 1581 1.2.2.2 nathanw if (totlen > ETHER_MAX_LEN) { 1582 1.2.2.2 nathanw printf("%s: invalid packet length\n", sc->sc_dev.dv_xname); 1583 1.2.2.2 nathanw 1584 1.2.2.2 nathanw /* skip the received frame */ 1585 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1586 1.2.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1587 1.2.2.2 nathanw return; 1588 1.2.2.2 nathanw } 1589 1.2.2.2 nathanw 1590 1.2.2.2 nathanw MGETHDR(m, M_DONTWAIT, MT_DATA); 1591 1.2.2.2 nathanw if (m == 0) { 1592 1.2.2.2 nathanw printf("%s: cs_process_receive: unable to allocate mbuf\n", 1593 1.2.2.2 nathanw sc->sc_dev.dv_xname); 1594 1.2.2.2 nathanw ifp->if_ierrors++; 1595 1.2.2.2 nathanw /* 1596 1.2.2.2 nathanw * couldn't allocate an mbuf so things are not good, may as 1597 1.2.2.2 nathanw * well drop the packet I think. 1598 1.2.2.2 nathanw * 1599 1.2.2.2 nathanw * have already read the length so we should be right to skip 1600 1.2.2.2 nathanw * the packet. 1601 1.2.2.2 nathanw */ 1602 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1603 1.2.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1604 1.2.2.2 nathanw return; 1605 1.2.2.2 nathanw } 1606 1.2.2.2 nathanw m->m_pkthdr.rcvif = ifp; 1607 1.2.2.2 nathanw m->m_pkthdr.len = totlen; 1608 1.2.2.2 nathanw 1609 1.2.2.2 nathanw /* number of bytes to align ip header on word boundary for ipintr */ 1610 1.2.2.2 nathanw pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1611 1.2.2.2 nathanw 1612 1.2.2.2 nathanw /* 1613 1.2.2.2 nathanw * alloc mbuf cluster if we need. 1614 1.2.2.2 nathanw * we need 1 byte spare because following 1615 1.2.2.2 nathanw * packet read loop can overrun. 1616 1.2.2.2 nathanw */ 1617 1.2.2.2 nathanw if (totlen + pad + 1 > MHLEN) { 1618 1.2.2.2 nathanw MCLGET(m, M_DONTWAIT); 1619 1.2.2.2 nathanw if ((m->m_flags & M_EXT) == 0) { 1620 1.2.2.2 nathanw /* couldn't allocate an mbuf cluster */ 1621 1.2.2.2 nathanw printf("%s: cs_process_receive: unable to allocate a cluster\n", 1622 1.2.2.2 nathanw sc->sc_dev.dv_xname); 1623 1.2.2.2 nathanw m_freem(m); 1624 1.2.2.2 nathanw 1625 1.2.2.2 nathanw /* skip the received frame */ 1626 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1627 1.2.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1628 1.2.2.2 nathanw return; 1629 1.2.2.2 nathanw } 1630 1.2.2.2 nathanw } 1631 1.2.2.2 nathanw 1632 1.2.2.2 nathanw /* align ip header on word boundary for ipintr */ 1633 1.2.2.2 nathanw m->m_data += pad; 1634 1.2.2.2 nathanw 1635 1.2.2.2 nathanw m->m_len = totlen; 1636 1.2.2.2 nathanw pBuff = mtod(m, u_int16_t *); 1637 1.2.2.2 nathanw 1638 1.2.2.2 nathanw /* now read the data from the chip */ 1639 1.2.2.2 nathanw if (sc->sc_memorymode) { 1640 1.2.2.2 nathanw pBuffLimit = pBuff + (totlen + 1) / 2; /* don't want to go over */ 1641 1.2.2.2 nathanw while (pBuff < pBuffLimit) { 1642 1.2.2.2 nathanw *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1643 1.2.2.2 nathanw frameOffset += 2; 1644 1.2.2.2 nathanw } 1645 1.2.2.2 nathanw } 1646 1.2.2.2 nathanw else { 1647 1.2.2.2 nathanw bus_space_read_multi_2(sc->sc_iot, sc->sc_ioh, PORT_RXTX_DATA, 1648 1.2.2.2 nathanw pBuff, (totlen + 1)>>1); 1649 1.2.2.2 nathanw } 1650 1.2.2.2 nathanw 1651 1.2.2.2 nathanw cs_ether_input(sc, m); 1652 1.2.2.2 nathanw } 1653 1.2.2.2 nathanw 1654 1.2.2.2 nathanw void 1655 1.2.2.2 nathanw cs_process_rx_early(sc) 1656 1.2.2.2 nathanw struct cs_softc *sc; 1657 1.2.2.2 nathanw { 1658 1.2.2.2 nathanw struct ifnet *ifp; 1659 1.2.2.2 nathanw struct mbuf *m; 1660 1.2.2.2 nathanw u_int16_t frameCount, oldFrameCount; 1661 1.2.2.2 nathanw u_int16_t rxEvent; 1662 1.2.2.2 nathanw u_int16_t *pBuff; 1663 1.2.2.2 nathanw int pad; 1664 1.2.2.2 nathanw unsigned int frameOffset; 1665 1.2.2.2 nathanw 1666 1.2.2.2 nathanw 1667 1.2.2.2 nathanw ifp = &sc->sc_ethercom.ec_if; 1668 1.2.2.2 nathanw 1669 1.2.2.2 nathanw /* Initialize the frame offset */ 1670 1.2.2.2 nathanw frameOffset = PKTPG_RX_FRAME; 1671 1.2.2.2 nathanw frameCount = 0; 1672 1.2.2.2 nathanw 1673 1.2.2.2 nathanw MGETHDR(m, M_DONTWAIT, MT_DATA); 1674 1.2.2.2 nathanw if (m == 0) { 1675 1.2.2.2 nathanw printf("%s: cs_process_rx_early: unable to allocate mbuf\n", 1676 1.2.2.2 nathanw sc->sc_dev.dv_xname); 1677 1.2.2.2 nathanw ifp->if_ierrors++; 1678 1.2.2.2 nathanw /* 1679 1.2.2.2 nathanw * couldn't allocate an mbuf so things are not good, may as 1680 1.2.2.2 nathanw * well drop the packet I think. 1681 1.2.2.2 nathanw * 1682 1.2.2.2 nathanw * have already read the length so we should be right to skip 1683 1.2.2.2 nathanw * the packet. 1684 1.2.2.2 nathanw */ 1685 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1686 1.2.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1687 1.2.2.2 nathanw return; 1688 1.2.2.2 nathanw } 1689 1.2.2.2 nathanw m->m_pkthdr.rcvif = ifp; 1690 1.2.2.2 nathanw /* 1691 1.2.2.2 nathanw * save processing by always using a mbuf cluster, guarenteed to fit 1692 1.2.2.2 nathanw * packet 1693 1.2.2.2 nathanw */ 1694 1.2.2.2 nathanw MCLGET(m, M_DONTWAIT); 1695 1.2.2.2 nathanw if ((m->m_flags & M_EXT) == 0) { 1696 1.2.2.2 nathanw /* couldn't allocate an mbuf cluster */ 1697 1.2.2.2 nathanw printf("%s: cs_process_rx_early: unable to allocate a cluster\n", 1698 1.2.2.2 nathanw sc->sc_dev.dv_xname); 1699 1.2.2.2 nathanw m_freem(m); 1700 1.2.2.2 nathanw /* skip the frame */ 1701 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1702 1.2.2.2 nathanw CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1703 1.2.2.2 nathanw return; 1704 1.2.2.2 nathanw } 1705 1.2.2.2 nathanw 1706 1.2.2.2 nathanw /* align ip header on word boundary for ipintr */ 1707 1.2.2.2 nathanw pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1708 1.2.2.2 nathanw m->m_data += pad; 1709 1.2.2.2 nathanw 1710 1.2.2.2 nathanw /* set up the buffer pointer to point to the data area */ 1711 1.2.2.2 nathanw pBuff = mtod(m, u_int16_t *); 1712 1.2.2.2 nathanw 1713 1.2.2.2 nathanw /* 1714 1.2.2.2 nathanw * now read the frame byte counter until we have finished reading the 1715 1.2.2.2 nathanw * frame 1716 1.2.2.2 nathanw */ 1717 1.2.2.2 nathanw oldFrameCount = 0; 1718 1.2.2.2 nathanw frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1719 1.2.2.2 nathanw while ((frameCount != 0) && (frameCount < MCLBYTES)) { 1720 1.2.2.2 nathanw for (; oldFrameCount < frameCount; oldFrameCount += 2) { 1721 1.2.2.2 nathanw *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1722 1.2.2.2 nathanw frameOffset += 2; 1723 1.2.2.2 nathanw } 1724 1.2.2.2 nathanw 1725 1.2.2.2 nathanw /* read the new count from the chip */ 1726 1.2.2.2 nathanw frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1727 1.2.2.2 nathanw } 1728 1.2.2.2 nathanw 1729 1.2.2.2 nathanw /* update the mbuf counts */ 1730 1.2.2.2 nathanw m->m_len = oldFrameCount; 1731 1.2.2.2 nathanw m->m_pkthdr.len = oldFrameCount; 1732 1.2.2.2 nathanw 1733 1.2.2.2 nathanw /* now check the Rx Event register */ 1734 1.2.2.2 nathanw rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1735 1.2.2.2 nathanw 1736 1.2.2.2 nathanw if ((rxEvent & RX_EVENT_RX_OK) != 0) { 1737 1.2.2.2 nathanw /* 1738 1.2.2.2 nathanw * do an implied skip, it seems to be more reliable than a 1739 1.2.2.2 nathanw * forced skip. 1740 1.2.2.2 nathanw */ 1741 1.2.2.2 nathanw rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS); 1742 1.2.2.2 nathanw rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1743 1.2.2.2 nathanw 1744 1.2.2.2 nathanw /* 1745 1.2.2.2 nathanw * now read the RX_EVENT register to perform an implied skip. 1746 1.2.2.2 nathanw */ 1747 1.2.2.2 nathanw rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1748 1.2.2.2 nathanw 1749 1.2.2.2 nathanw cs_ether_input(sc, m); 1750 1.2.2.2 nathanw } else { 1751 1.2.2.2 nathanw m_freem(m); 1752 1.2.2.2 nathanw ifp->if_ierrors++; 1753 1.2.2.2 nathanw } 1754 1.2.2.2 nathanw } 1755 1.2.2.2 nathanw 1756 1.2.2.2 nathanw void 1757 1.2.2.2 nathanw cs_start_output(ifp) 1758 1.2.2.2 nathanw struct ifnet *ifp; 1759 1.2.2.2 nathanw { 1760 1.2.2.2 nathanw struct cs_softc *sc; 1761 1.2.2.2 nathanw struct mbuf *pMbuf; 1762 1.2.2.2 nathanw struct mbuf *pMbufChain; 1763 1.2.2.2 nathanw u_int16_t BusStatus; 1764 1.2.2.2 nathanw u_int16_t Length; 1765 1.2.2.2 nathanw int txLoop = 0; 1766 1.2.2.2 nathanw int dropout = 0; 1767 1.2.2.2 nathanw 1768 1.2.2.2 nathanw sc = ifp->if_softc; 1769 1.2.2.2 nathanw 1770 1.2.2.2 nathanw /* check that the interface is up and running */ 1771 1.2.2.2 nathanw if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1772 1.2.2.2 nathanw return; 1773 1.2.2.2 nathanw } 1774 1.2.2.2 nathanw 1775 1.2.2.2 nathanw /* Don't interrupt a transmission in progress */ 1776 1.2.2.2 nathanw if (sc->sc_txbusy) { 1777 1.2.2.2 nathanw return; 1778 1.2.2.2 nathanw } 1779 1.2.2.2 nathanw 1780 1.2.2.2 nathanw /* this loop will only run through once if transmission is successful */ 1781 1.2.2.2 nathanw /* 1782 1.2.2.2 nathanw * While there are packets to transmit and a transmit is not in 1783 1.2.2.2 nathanw * progress 1784 1.2.2.2 nathanw */ 1785 1.2.2.2 nathanw while (sc->sc_txbusy == 0 && dropout == 0) { 1786 1.2.2.2 nathanw IFQ_DEQUEUE(&ifp->if_snd, pMbufChain); 1787 1.2.2.2 nathanw if (pMbufChain == NULL) 1788 1.2.2.2 nathanw break; 1789 1.2.2.2 nathanw 1790 1.2.2.2 nathanw #if NBPFILTER > 0 1791 1.2.2.2 nathanw /* 1792 1.2.2.2 nathanw * If BPF is listening on this interface, let it see the packet 1793 1.2.2.2 nathanw * before we commit it to the wire. 1794 1.2.2.2 nathanw */ 1795 1.2.2.2 nathanw if (ifp->if_bpf) 1796 1.2.2.2 nathanw bpf_mtap(ifp->if_bpf, pMbufChain); 1797 1.2.2.2 nathanw #endif 1798 1.2.2.2 nathanw 1799 1.2.2.2 nathanw /* Find the total length of the data to transmit */ 1800 1.2.2.2 nathanw Length = 0; 1801 1.2.2.2 nathanw for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next) 1802 1.2.2.2 nathanw Length += pMbuf->m_len; 1803 1.2.2.2 nathanw 1804 1.2.2.2 nathanw do { 1805 1.2.2.2 nathanw /* 1806 1.2.2.2 nathanw * Request that the transmit be started after all 1807 1.2.2.2 nathanw * data has been copied 1808 1.2.2.2 nathanw * 1809 1.2.2.2 nathanw * In IO mode must write to the IO port not the packet 1810 1.2.2.2 nathanw * page address 1811 1.2.2.2 nathanw * 1812 1.2.2.2 nathanw * If this is changed to start transmission after a 1813 1.2.2.2 nathanw * small amount of data has been copied you tend to 1814 1.2.2.2 nathanw * get packet missed errors i think because the ISA 1815 1.2.2.2 nathanw * bus is too slow. Or possibly the copy routine is 1816 1.2.2.2 nathanw * not streamlined enough. 1817 1.2.2.2 nathanw */ 1818 1.2.2.2 nathanw if (sc->sc_memorymode) { 1819 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD, 1820 1.2.2.2 nathanw cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1821 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length); 1822 1.2.2.2 nathanw } 1823 1.2.2.2 nathanw else { 1824 1.2.2.2 nathanw CS_WRITE_PORT(sc, PORT_TX_CMD, 1825 1.2.2.2 nathanw cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1826 1.2.2.2 nathanw CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length); 1827 1.2.2.2 nathanw } 1828 1.2.2.2 nathanw 1829 1.2.2.2 nathanw /* 1830 1.2.2.2 nathanw * Adjust early-transmit machinery. 1831 1.2.2.2 nathanw */ 1832 1.2.2.2 nathanw if (--sc->sc_xe_togo == 0) { 1833 1.2.2.2 nathanw sc->sc_xe_ent = 1834 1.2.2.2 nathanw cs_xmit_early_table[sc->sc_xe_ent].better; 1835 1.2.2.2 nathanw sc->sc_xe_togo = 1836 1.2.2.2 nathanw cs_xmit_early_table[sc->sc_xe_ent].better_count; 1837 1.2.2.2 nathanw } 1838 1.2.2.2 nathanw /* 1839 1.2.2.2 nathanw * Read the BusStatus register which indicates 1840 1.2.2.2 nathanw * success of the request 1841 1.2.2.2 nathanw */ 1842 1.2.2.2 nathanw BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST); 1843 1.2.2.2 nathanw 1844 1.2.2.2 nathanw /* 1845 1.2.2.2 nathanw * If there was an error in the transmit bid free the 1846 1.2.2.2 nathanw * mbuf and go on. This is presuming that mbuf is 1847 1.2.2.2 nathanw * corrupt. 1848 1.2.2.2 nathanw */ 1849 1.2.2.2 nathanw if (BusStatus & BUS_ST_TX_BID_ERR) { 1850 1.2.2.2 nathanw printf("%s: transmit bid error (too big)", 1851 1.2.2.2 nathanw sc->sc_dev.dv_xname); 1852 1.2.2.2 nathanw 1853 1.2.2.2 nathanw /* Discard the bad mbuf chain */ 1854 1.2.2.2 nathanw m_freem(pMbufChain); 1855 1.2.2.2 nathanw sc->sc_ethercom.ec_if.if_oerrors++; 1856 1.2.2.2 nathanw 1857 1.2.2.2 nathanw /* Loop up to transmit the next chain */ 1858 1.2.2.2 nathanw txLoop = 0; 1859 1.2.2.2 nathanw } else { 1860 1.2.2.2 nathanw if (BusStatus & BUS_ST_RDY4TXNOW) { 1861 1.2.2.2 nathanw /* 1862 1.2.2.2 nathanw * The chip is ready for transmission 1863 1.2.2.2 nathanw * now 1864 1.2.2.2 nathanw */ 1865 1.2.2.2 nathanw /* 1866 1.2.2.2 nathanw * Copy the frame to the chip to 1867 1.2.2.2 nathanw * start transmission 1868 1.2.2.2 nathanw */ 1869 1.2.2.2 nathanw cs_copy_tx_frame(sc, pMbufChain); 1870 1.2.2.2 nathanw 1871 1.2.2.2 nathanw /* Free the mbuf chain */ 1872 1.2.2.2 nathanw m_freem(pMbufChain); 1873 1.2.2.2 nathanw 1874 1.2.2.2 nathanw /* Transmission is now in progress */ 1875 1.2.2.2 nathanw sc->sc_txbusy = TRUE; 1876 1.2.2.2 nathanw txLoop = 0; 1877 1.2.2.2 nathanw } else { 1878 1.2.2.2 nathanw /* 1879 1.2.2.2 nathanw * if we get here we want to try 1880 1.2.2.2 nathanw * again with the same mbuf, until 1881 1.2.2.2 nathanw * the chip lets us transmit. 1882 1.2.2.2 nathanw */ 1883 1.2.2.2 nathanw txLoop++; 1884 1.2.2.2 nathanw if (txLoop > CS_OUTPUT_LOOP_MAX) { 1885 1.2.2.2 nathanw /* Free the mbuf chain */ 1886 1.2.2.2 nathanw m_freem(pMbufChain); 1887 1.2.2.2 nathanw /* 1888 1.2.2.2 nathanw * Transmission is not in 1889 1.2.2.2 nathanw * progress 1890 1.2.2.2 nathanw */ 1891 1.2.2.2 nathanw sc->sc_txbusy = FALSE; 1892 1.2.2.2 nathanw /* 1893 1.2.2.2 nathanw * Increment the output error 1894 1.2.2.2 nathanw * count 1895 1.2.2.2 nathanw */ 1896 1.2.2.2 nathanw ifp->if_oerrors++; 1897 1.2.2.2 nathanw /* 1898 1.2.2.2 nathanw * exit the routine and drop 1899 1.2.2.2 nathanw * the packet. 1900 1.2.2.2 nathanw */ 1901 1.2.2.2 nathanw txLoop = 0; 1902 1.2.2.2 nathanw dropout = 1; 1903 1.2.2.2 nathanw } 1904 1.2.2.2 nathanw } 1905 1.2.2.2 nathanw } 1906 1.2.2.2 nathanw } while (txLoop); 1907 1.2.2.2 nathanw } 1908 1.2.2.2 nathanw } 1909 1.2.2.2 nathanw 1910 1.2.2.2 nathanw void 1911 1.2.2.2 nathanw cs_copy_tx_frame(sc, m0) 1912 1.2.2.2 nathanw struct cs_softc *sc; 1913 1.2.2.2 nathanw struct mbuf *m0; 1914 1.2.2.2 nathanw { 1915 1.2.2.2 nathanw struct mbuf *m; 1916 1.2.2.2 nathanw int len, leftover, frameoff; 1917 1.2.2.2 nathanw u_int16_t dbuf; 1918 1.2.2.2 nathanw u_int8_t *p; 1919 1.2.2.2 nathanw #ifdef DIAGNOSTIC 1920 1.2.2.2 nathanw u_int8_t *lim; 1921 1.2.2.2 nathanw #endif 1922 1.2.2.2 nathanw 1923 1.2.2.2 nathanw /* Initialize frame pointer and data port address */ 1924 1.2.2.2 nathanw frameoff = PKTPG_TX_FRAME; 1925 1.2.2.2 nathanw 1926 1.2.2.2 nathanw /* start out with no leftover data */ 1927 1.2.2.2 nathanw leftover = 0; 1928 1.2.2.2 nathanw dbuf = 0; 1929 1.2.2.2 nathanw 1930 1.2.2.2 nathanw /* Process the chain of mbufs */ 1931 1.2.2.2 nathanw for (m = m0; m != NULL; m = m->m_next) { 1932 1.2.2.2 nathanw /* 1933 1.2.2.2 nathanw * Process all of the data in a single mbuf. 1934 1.2.2.2 nathanw */ 1935 1.2.2.2 nathanw p = mtod(m, u_int8_t *); 1936 1.2.2.2 nathanw len = m->m_len; 1937 1.2.2.2 nathanw #ifdef DIAGNOSTIC 1938 1.2.2.2 nathanw lim = p + len; 1939 1.2.2.2 nathanw #endif 1940 1.2.2.2 nathanw 1941 1.2.2.2 nathanw while (len > 0) { 1942 1.2.2.2 nathanw if (leftover) { 1943 1.2.2.2 nathanw /* 1944 1.2.2.2 nathanw * Data left over (from mbuf or realignment). 1945 1.2.2.2 nathanw * Buffer the next byte, and write it and 1946 1.2.2.2 nathanw * the leftover data out. 1947 1.2.2.2 nathanw */ 1948 1.2.2.2 nathanw dbuf |= *p++ << 8; 1949 1.2.2.2 nathanw len--; 1950 1.2.2.2 nathanw if (sc->sc_memorymode) { 1951 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 1952 1.2.2.2 nathanw frameoff += 2; 1953 1.2.2.2 nathanw } 1954 1.2.2.2 nathanw else { 1955 1.2.2.2 nathanw CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 1956 1.2.2.2 nathanw } 1957 1.2.2.2 nathanw leftover = 0; 1958 1.2.2.2 nathanw } else if ((long) p & 1) { 1959 1.2.2.2 nathanw /* 1960 1.2.2.2 nathanw * Misaligned data. Buffer the next byte. 1961 1.2.2.2 nathanw */ 1962 1.2.2.2 nathanw dbuf = *p++; 1963 1.2.2.2 nathanw len--; 1964 1.2.2.2 nathanw leftover = 1; 1965 1.2.2.2 nathanw } else { 1966 1.2.2.2 nathanw /* 1967 1.2.2.2 nathanw * Aligned data. This is the case we like. 1968 1.2.2.2 nathanw * 1969 1.2.2.2 nathanw * Write-region out as much as we can, then 1970 1.2.2.2 nathanw * buffer the remaining byte (if any). 1971 1.2.2.2 nathanw */ 1972 1.2.2.2 nathanw leftover = len & 1; 1973 1.2.2.2 nathanw len &= ~1; 1974 1.2.2.2 nathanw if (sc->sc_memorymode) { 1975 1.2.2.2 nathanw bus_space_write_region_2(sc->sc_memt, sc->sc_memh, frameoff, 1976 1.2.2.2 nathanw (u_int16_t *) p, len >> 1); 1977 1.2.2.2 nathanw frameoff += len; 1978 1.2.2.2 nathanw } 1979 1.2.2.2 nathanw else { 1980 1.2.2.2 nathanw bus_space_write_multi_2(sc->sc_iot, sc->sc_ioh, 1981 1.2.2.2 nathanw PORT_RXTX_DATA, (u_int16_t *)p, len >> 1); 1982 1.2.2.2 nathanw } 1983 1.2.2.2 nathanw p += len; 1984 1.2.2.2 nathanw 1985 1.2.2.2 nathanw if (leftover) 1986 1.2.2.2 nathanw dbuf = *p++; 1987 1.2.2.2 nathanw len = 0; 1988 1.2.2.2 nathanw } 1989 1.2.2.2 nathanw } 1990 1.2.2.2 nathanw if (len < 0) 1991 1.2.2.2 nathanw panic("cs_copy_tx_frame: negative len"); 1992 1.2.2.2 nathanw #ifdef DIAGNOSTIC 1993 1.2.2.2 nathanw if (p != lim) 1994 1.2.2.2 nathanw panic("cs_copy_tx_frame: p != lim"); 1995 1.2.2.2 nathanw #endif 1996 1.2.2.2 nathanw } 1997 1.2.2.2 nathanw if (leftover) { 1998 1.2.2.2 nathanw if (sc->sc_memorymode) { 1999 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2000 1.2.2.2 nathanw } 2001 1.2.2.2 nathanw else { 2002 1.2.2.2 nathanw CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2003 1.2.2.2 nathanw } 2004 1.2.2.2 nathanw } 2005 1.2.2.2 nathanw } 2006 1.2.2.2 nathanw 2007 1.2.2.2 nathanw static int 2008 1.2.2.2 nathanw cs_enable(sc) 2009 1.2.2.2 nathanw struct cs_softc *sc; 2010 1.2.2.2 nathanw { 2011 1.2.2.2 nathanw if (!CS_IS_ENABLED(sc) && sc->sc_enable) { 2012 1.2.2.2 nathanw int error; 2013 1.2.2.2 nathanw 2014 1.2.2.2 nathanw error = (*sc->sc_enable)(sc); 2015 1.2.2.2 nathanw if (error) 2016 1.2.2.2 nathanw return error; 2017 1.2.2.2 nathanw 2018 1.2.2.2 nathanw sc->sc_cfgflags |= CFGFLG_ENABLED; 2019 1.2.2.2 nathanw } 2020 1.2.2.2 nathanw 2021 1.2.2.2 nathanw return 0; 2022 1.2.2.2 nathanw } 2023 1.2.2.2 nathanw 2024 1.2.2.2 nathanw static void 2025 1.2.2.2 nathanw cs_disable(sc) 2026 1.2.2.2 nathanw struct cs_softc *sc; 2027 1.2.2.2 nathanw { 2028 1.2.2.2 nathanw if (CS_IS_ENABLED(sc) && sc->sc_disable) { 2029 1.2.2.2 nathanw (*sc->sc_disable)(sc); 2030 1.2.2.2 nathanw 2031 1.2.2.2 nathanw sc->sc_cfgflags &= ~CFGFLG_ENABLED; 2032 1.2.2.2 nathanw } 2033 1.2.2.2 nathanw } 2034 1.2.2.2 nathanw 2035 1.2.2.2 nathanw static void 2036 1.2.2.2 nathanw cs_stop(ifp, disable) 2037 1.2.2.2 nathanw struct ifnet *ifp; 2038 1.2.2.2 nathanw int disable; 2039 1.2.2.2 nathanw { 2040 1.2.2.2 nathanw struct cs_softc *sc = ifp->if_softc; 2041 1.2.2.2 nathanw 2042 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0); 2043 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0); 2044 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0); 2045 1.2.2.2 nathanw CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0); 2046 1.2.2.2 nathanw 2047 1.2.2.2 nathanw if (disable) { 2048 1.2.2.2 nathanw cs_disable(sc); 2049 1.2.2.2 nathanw } 2050 1.2.2.2 nathanw 2051 1.2.2.2 nathanw ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2052 1.2.2.2 nathanw } 2053 1.2.2.2 nathanw 2054 1.2.2.2 nathanw int 2055 1.2.2.2 nathanw cs_activate(self, act) 2056 1.2.2.2 nathanw struct device *self; 2057 1.2.2.2 nathanw enum devact act; 2058 1.2.2.2 nathanw { 2059 1.2.2.2 nathanw struct cs_softc *sc = (void *)self; 2060 1.2.2.2 nathanw int s, error = 0; 2061 1.2.2.2 nathanw 2062 1.2.2.2 nathanw s = splnet(); 2063 1.2.2.2 nathanw switch (act) { 2064 1.2.2.2 nathanw case DVACT_ACTIVATE: 2065 1.2.2.2 nathanw error = EOPNOTSUPP; 2066 1.2.2.2 nathanw break; 2067 1.2.2.2 nathanw 2068 1.2.2.2 nathanw case DVACT_DEACTIVATE: 2069 1.2.2.2 nathanw if_deactivate(&sc->sc_ethercom.ec_if); 2070 1.2.2.2 nathanw break; 2071 1.2.2.2 nathanw } 2072 1.2.2.2 nathanw splx(s); 2073 1.2.2.2 nathanw 2074 1.2.2.2 nathanw return error; 2075 1.2.2.2 nathanw } 2076 1.2.2.2 nathanw 2077 1.2.2.2 nathanw static void 2078 1.2.2.2 nathanw cs_power(why, arg) 2079 1.2.2.2 nathanw int why; 2080 1.2.2.2 nathanw void *arg; 2081 1.2.2.2 nathanw { 2082 1.2.2.2 nathanw struct cs_softc *sc = arg; 2083 1.2.2.2 nathanw struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2084 1.2.2.2 nathanw int s; 2085 1.2.2.2 nathanw 2086 1.2.2.2 nathanw s = splnet(); 2087 1.2.2.2 nathanw switch (why) { 2088 1.2.2.2 nathanw case PWR_STANDBY: 2089 1.2.2.2 nathanw case PWR_SUSPEND: 2090 1.2.2.2 nathanw cs_stop(ifp, 0); 2091 1.2.2.2 nathanw break; 2092 1.2.2.2 nathanw case PWR_RESUME: 2093 1.2.2.2 nathanw if (ifp->if_flags & IFF_UP) { 2094 1.2.2.2 nathanw cs_init(ifp); 2095 1.2.2.2 nathanw } 2096 1.2.2.2 nathanw break; 2097 1.2.2.2 nathanw case PWR_SOFTSUSPEND: 2098 1.2.2.2 nathanw case PWR_SOFTSTANDBY: 2099 1.2.2.2 nathanw case PWR_SOFTRESUME: 2100 1.2.2.2 nathanw break; 2101 1.2.2.2 nathanw } 2102 1.2.2.2 nathanw splx(s); 2103 1.2.2.2 nathanw } 2104
Indexes created Fri Oct 03 02:09:57 GMT 2025