cs89x0.c revision 1.1
1 /* $NetBSD: cs89x0.c,v 1.1 2001/11/26 19:17:08 yamt Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 **++ 38 ** FACILITY 39 ** 40 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller. 41 ** 42 ** ABSTRACT 43 ** 44 ** This module provides standard ethernet access for INET protocols 45 ** only. 46 ** 47 ** AUTHORS 48 ** 49 ** Peter Dettori SEA - Software Engineering. 50 ** 51 ** CREATION DATE: 52 ** 53 ** 13-Feb-1997. 54 ** 55 ** MODIFICATION HISTORY (Digital): 56 ** 57 ** Revision 1.27 1998/01/20 17:59:40 cgd 58 ** update for moved headers 59 ** 60 ** Revision 1.26 1998/01/12 19:29:36 cgd 61 ** use arm32/isa versions of isadma code. 62 ** 63 ** Revision 1.25 1997/12/12 01:35:27 cgd 64 ** convert to use new arp code (from Brini) 65 ** 66 ** Revision 1.24 1997/12/10 22:31:56 cgd 67 ** trim some fat (get rid of ability to explicitly supply enet addr, since 68 ** it was never used and added a bunch of code which really doesn't belong in 69 ** an enet driver), and clean up slightly. 70 ** 71 ** Revision 1.23 1997/10/06 16:42:12 cgd 72 ** copyright notices 73 ** 74 ** Revision 1.22 1997/06/20 19:38:01 chaiken 75 ** fixes some smartcard problems 76 ** 77 ** Revision 1.21 1997/06/10 02:56:20 grohn 78 ** Added call to ledNetActive 79 ** 80 ** Revision 1.20 1997/06/05 00:47:06 dettori 81 ** Changed cs_process_rx_dma to reset and re-initialise the 82 ** ethernet chip when DMA gets out of sync, or mbufs 83 ** can't be allocated. 84 ** 85 ** Revision 1.19 1997/06/03 03:09:58 dettori 86 ** Turn off sc_txbusy flag when a transmit underrun 87 ** occurs. 88 ** 89 ** Revision 1.18 1997/06/02 00:04:35 dettori 90 ** redefined the transmit table to get around the nfs_timer bug while we are 91 ** looking into it further. 92 ** 93 ** Also changed interrupts from EDGE to LEVEL. 94 ** 95 ** Revision 1.17 1997/05/27 23:31:01 dettori 96 ** Pulled out changes to DMAMODE defines. 97 ** 98 ** Revision 1.16 1997/05/23 04:25:16 cgd 99 ** reformat log so it fits in 80cols 100 ** 101 ** Revision 1.15 1997/05/23 04:22:18 cgd 102 ** remove the existing copyright notice (which Peter Dettori indicated 103 ** was incorrect, copied from an existing NetBSD file only so that the 104 ** file would have a copyright notice on it, and which he'd intended to 105 ** replace). Replace it with a Digital copyright notice, cloned from 106 ** ess.c. It's not really correct either (it indicates that the source 107 ** is Digital confidential!), but is better than nothing and more 108 ** correct than what was there before. 109 ** 110 ** Revision 1.14 1997/05/23 04:12:50 cgd 111 ** use an adaptive transmit start algorithm: start by telling the chip 112 ** to start transmitting after 381 bytes have been fed to it. if that 113 ** gets transmit underruns, ramp down to 1021 bytes then "whole 114 ** packet." If successful at a given level for a while, try the next 115 ** more agressive level. This code doesn't ever try to start 116 ** transmitting after 5 bytes have been sent to the NIC, because 117 ** that underruns rather regularly. The back-off and ramp-up mechanism 118 ** could probably be tuned a little bit, but this works well enough to 119 ** support > 1MB/s transmit rates on a clear ethernet (which is about 120 ** 20-25% better than the driver had previously been getting). 121 ** 122 ** Revision 1.13 1997/05/22 21:06:54 cgd 123 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly 124 ** casting from u_int8_t * to u_int16_t * without worrying about alignment 125 ** issues. This would cause bogus data to be spit out for mbufs with 126 ** misaligned data. For instance, it caused the following bits to appear 127 ** on the wire: 128 ** ... etBND 1S2C .SHA(K) R ... 129 ** 11112222333344445555 130 ** which should have appeared as: 131 ** ... NetBSD 1.2C (SHARK) ... 132 ** 11112222333344445555 133 ** Note the apparent 'rotate' of the bytes in the word, which was due to 134 ** incorrect unaligned accesses. This data corruption was the cause of 135 ** incoming telnet/rlogin hangs. 136 ** 137 ** Revision 1.12 1997/05/22 01:55:32 cgd 138 ** reformat log so it fits in 80cols 139 ** 140 ** Revision 1.11 1997/05/22 01:50:27 cgd 141 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case, 142 ** so packets aimed at other hosts don't get sent to ether_input(). 143 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that 144 ** you can easily tell (`strings`) what version of the driver is in your 145 ** kernel binary. 146 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily 147 ** safe, and not really a performance win anyway. (It was only used when 148 ** setting up the multicast logical address filter, which is an 149 ** infrequent event. It could have been used in the IFF_PROMISCUOUS 150 ** address check above, but the benefit of it vs. memcmp would be 151 ** inconsequential, there.) Use memcmp() instead. 152 ** * restructure csStartOuput to avoid the following bugs in the case where 153 ** txWait was being set: 154 ** * it would accidentally drop the outgoing packet if told to wait 155 ** but the outgoing packet queue was empty. 156 ** * it would bpf_mtap() the outgoing packet multiple times (once for 157 ** each time it was told to wait), and would also recalculate 158 ** the length of the outgoing packet each time it was told to 159 ** wait. 160 ** While there, rename txWait to txLoop, since with the new structure of 161 ** the code, the latter name makes more sense. 162 ** 163 ** Revision 1.10 1997/05/19 02:03:20 cgd 164 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip() 165 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this 166 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC 167 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave 168 ** as before. 169 ** 170 ** Revision 1.9 1997/05/19 01:45:37 cgd 171 ** create a new function, cs_ether_input(), which does received-packet 172 ** BPF and ether_input processing. This code used to be in three places, 173 ** and centralizing it will make adding IFF_PROMISC support much easier. 174 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to 175 ** do copies with bus_space_write_region_2(). It's more correct, and 176 ** potentially more efficient. That function needs to be gutted (to 177 ** deal properly with alignment issues, which it currently does wrong), 178 ** however, and the change doesn't gain much, so there's no point in 179 ** enabling it now. 180 ** 181 ** Revision 1.8 1997/05/19 01:17:10 cgd 182 ** fix a comment re: the setting of the TxConfig register. Clean up 183 ** interface counter maintenance (make it use standard idiom). 184 ** 185 **-- 186 */ 187 188 #include <sys/cdefs.h> 189 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.1 2001/11/26 19:17:08 yamt Exp $"); 190 191 #include "opt_inet.h" 192 193 #include <sys/param.h> 194 #include <sys/systm.h> 195 #include <sys/mbuf.h> 196 #include <sys/syslog.h> 197 #include <sys/socket.h> 198 #include <sys/device.h> 199 #include <sys/malloc.h> 200 #include <sys/ioctl.h> 201 #include <sys/errno.h> 202 203 #include "rnd.h" 204 #if NRND > 0 205 #include <sys/rnd.h> 206 #endif 207 208 #include <net/if.h> 209 #include <net/if_ether.h> 210 #include <net/if_media.h> 211 #ifdef INET 212 #include <netinet/in.h> 213 #include <netinet/if_inarp.h> 214 #endif 215 216 #include "bpfilter.h" 217 #if NBPFILTER > 0 218 #include <net/bpf.h> 219 #include <net/bpfdesc.h> 220 #endif 221 222 #include <uvm/uvm_extern.h> 223 224 #include <machine/bus.h> 225 #include <machine/intr.h> 226 227 #include <dev/ic/cs89x0reg.h> 228 #include <dev/ic/cs89x0var.h> 229 230 #ifdef SHARK 231 #include <arm32/shark/sequoia.h> 232 #endif 233 234 /* 235 * MACRO DEFINITIONS 236 */ 237 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */ 238 239 /* 240 * FUNCTION PROTOTYPES 241 */ 242 void cs_get_default_media __P((struct cs_softc *)); 243 int cs_get_params __P((struct cs_softc *)); 244 int cs_get_enaddr __P((struct cs_softc *)); 245 int cs_reset_chip __P((struct cs_softc *)); 246 void cs_reset __P((void *)); 247 int cs_ioctl __P((struct ifnet *, u_long, caddr_t)); 248 void cs_initChip __P((struct cs_softc *)); 249 void cs_buffer_event __P((struct cs_softc *, u_int16_t)); 250 void cs_transmit_event __P((struct cs_softc *, u_int16_t)); 251 void cs_receive_event __P((struct cs_softc *, u_int16_t)); 252 void cs_process_receive __P((struct cs_softc *)); 253 void cs_process_rx_early __P((struct cs_softc *)); 254 void cs_start_output __P((struct ifnet *)); 255 void cs_copy_tx_frame __P((struct cs_softc *, struct mbuf *)); 256 void cs_set_ladr_filt __P((struct cs_softc *, struct ethercom *)); 257 u_int16_t cs_hash_index __P((char *)); 258 void cs_counter_event __P((struct cs_softc *, u_int16_t)); 259 260 int cs_mediachange __P((struct ifnet *)); 261 void cs_mediastatus __P((struct ifnet *, struct ifmediareq *)); 262 263 static int cs_enable __P((struct cs_softc *)); 264 static void cs_disable __P((struct cs_softc *)); 265 static void cs_stop __P((struct ifnet *, int)); 266 static void cs_power __P((int, void *)); 267 268 /* 269 * GLOBAL DECLARATIONS 270 */ 271 272 /* 273 * Xmit-early table. 274 * 275 * To get better performance, we tell the chip to start packet 276 * transmission before the whole packet is copied to the chip. 277 * However, this can fail under load. When it fails, we back off 278 * to a safer setting for a little while. 279 * 280 * txcmd is the value of txcmd used to indicate when to start transmission. 281 * better is the next 'better' state in the table. 282 * better_count is the number of output packets before transition to the 283 * better state. 284 * worse is the next 'worse' state in the table. 285 * 286 * Transition to the next worse state happens automatically when a 287 * transmittion underrun occurs. 288 */ 289 struct cs_xmit_early { 290 u_int16_t txcmd; 291 int better; 292 int better_count; 293 int worse; 294 } cs_xmit_early_table[3] = { 295 { TX_CMD_START_381, 0, INT_MAX, 1, }, 296 { TX_CMD_START_1021, 0, 50000, 2, }, 297 { TX_CMD_START_ALL, 1, 5000, 2, }, 298 }; 299 300 int cs_default_media[] = { 301 IFM_ETHER|IFM_10_2, 302 IFM_ETHER|IFM_10_5, 303 IFM_ETHER|IFM_10_T, 304 IFM_ETHER|IFM_10_T|IFM_FDX, 305 }; 306 int cs_default_nmedia = sizeof(cs_default_media) / sizeof(cs_default_media[0]); 307 308 int 309 cs_attach(sc, enaddr, media, nmedia, defmedia) 310 struct cs_softc *sc; 311 u_int8_t *enaddr; 312 int *media, nmedia, defmedia; 313 { 314 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 315 const char *chipname, *medname; 316 u_int16_t reg; 317 int i; 318 319 /* Start out in IO mode */ 320 sc->sc_memorymode = FALSE; 321 322 /* make sure we're right */ 323 for (i = 0; i < 10000; i++) { 324 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 325 if (reg == EISA_NUM_CRYSTAL) { 326 break; 327 } 328 } 329 if (i == 10000) { 330 printf("%s: wrong id(0x%x)\n", sc->sc_dev.dv_xname, reg); 331 return 1; /* XXX should panic? */ 332 } 333 334 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID); 335 sc->sc_prodid = reg & PROD_ID_MASK; 336 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8; 337 338 switch (sc->sc_prodid) { 339 case PROD_ID_CS8900: 340 chipname = "CS8900"; 341 break; 342 case PROD_ID_CS8920: 343 chipname = "CS8920"; 344 break; 345 case PROD_ID_CS8920M: 346 chipname = "CS8920M"; 347 break; 348 default: 349 panic("cs_attach: impossible"); 350 } 351 352 /* 353 * the first thing to do is check that the mbuf cluster size is 354 * greater than the MTU for an ethernet frame. The code depends on 355 * this and to port this to a OS where this was not the case would 356 * not be straightforward. 357 */ 358 if (MCLBYTES < ETHER_MAX_LEN) { 359 printf("%s: MCLBYTES too small for Ethernet frame\n", 360 sc->sc_dev.dv_xname); 361 return 1; 362 } 363 364 /* Start out not transmitting */ 365 sc->sc_txbusy = FALSE; 366 367 /* Set up early transmit threshhold */ 368 sc->sc_xe_ent = 0; 369 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count; 370 371 /* Initialize ifnet structure. */ 372 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 373 ifp->if_softc = sc; 374 ifp->if_start = cs_start_output; 375 ifp->if_init = cs_init; 376 ifp->if_ioctl = cs_ioctl; 377 ifp->if_stop = cs_stop; 378 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 379 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | 380 IFF_BROADCAST | IFF_MULTICAST; 381 IFQ_SET_READY(&ifp->if_snd); 382 383 /* Initialize ifmedia structures. */ 384 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus); 385 386 if (media != NULL) { 387 for (i = 0; i < nmedia; i++) 388 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 389 ifmedia_set(&sc->sc_media, defmedia); 390 } else { 391 for (i = 0; i < cs_default_nmedia; i++) 392 ifmedia_add(&sc->sc_media, cs_default_media[i], 393 0, NULL); 394 cs_get_default_media(sc); 395 } 396 397 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 398 /* Get parameters from the EEPROM */ 399 if (cs_get_params(sc) == CS_ERROR) { 400 printf("%s: unable to get settings from EEPROM\n", 401 sc->sc_dev.dv_xname); 402 return 1; 403 } 404 } 405 406 if (enaddr != NULL) 407 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 408 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 409 /* Get and store the Ethernet address */ 410 if (cs_get_enaddr(sc) == CS_ERROR) { 411 printf("%s: unable to read Ethernet address\n", 412 sc->sc_dev.dv_xname); 413 return 1; 414 } 415 } else { 416 printf("%s: no Ethernet address!\n", sc->sc_dev.dv_xname); 417 return 1; 418 } 419 420 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) { 421 case IFM_10_2: 422 medname = "BNC"; 423 break; 424 case IFM_10_5: 425 medname = "AUI"; 426 break; 427 case IFM_10_T: 428 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 429 medname = "UTP <full-duplex>"; 430 else 431 medname = "UTP"; 432 break; 433 default: 434 panic("cs_attach: impossible"); 435 } 436 printf("%s: %s rev. %c, address %s, media %s\n", sc->sc_dev.dv_xname, 437 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr), 438 medname); 439 440 if (sc->sc_dma_attach) 441 (*sc->sc_dma_attach)(sc); 442 443 sc->sc_sh = shutdownhook_establish(cs_reset, sc); 444 if (sc->sc_sh == NULL) { 445 printf("%s: unable to establish shutdownhook\n", 446 sc->sc_dev.dv_xname); 447 cs_detach(sc); 448 return 1; 449 } 450 451 /* Attach the interface. */ 452 if_attach(ifp); 453 ether_ifattach(ifp, sc->sc_enaddr); 454 455 #if NRND > 0 456 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 457 RND_TYPE_NET, 0); 458 #endif 459 sc->sc_cfgflags |= CFGFLG_ATTACHED; 460 461 /* Reset the chip */ 462 if (cs_reset_chip(sc) == CS_ERROR) { 463 printf("%s: reset failed\n", sc->sc_dev.dv_xname); 464 cs_detach(sc); 465 return 1; 466 } 467 468 sc->sc_powerhook = powerhook_establish(cs_power, sc); 469 if (sc->sc_powerhook == 0) 470 printf("%s: warning: powerhook_establish failed\n", 471 sc->sc_dev.dv_xname); 472 473 return 0; 474 } 475 476 int 477 cs_detach(sc) 478 struct cs_softc *sc; 479 { 480 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 481 482 if (sc->sc_powerhook) { 483 powerhook_disestablish(sc->sc_powerhook); 484 sc->sc_powerhook = 0; 485 } 486 487 if (sc->sc_cfgflags & CFGFLG_ATTACHED) { 488 #if NRND > 0 489 rnd_detach_source(&sc->rnd_source); 490 #endif 491 ether_ifdetach(ifp); 492 if_detach(ifp); 493 sc->sc_cfgflags &= ~CFGFLG_ATTACHED; 494 } 495 496 if (sc->sc_sh != NULL) 497 shutdownhook_disestablish(sc->sc_sh); 498 499 #if 0 500 /* 501 * XXX not necessary 502 */ 503 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) { 504 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, sc->sc_dmasize); 505 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, sc->sc_dmasize); 506 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq); 507 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE; 508 } 509 #endif 510 511 return 0; 512 } 513 514 void 515 cs_get_default_media(sc) 516 struct cs_softc *sc; 517 { 518 u_int16_t adp_cfg, xmit_ctl; 519 520 if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 521 printf("%s: cs_get_default_media: EEPROM missing or bad\n", 522 sc->sc_dev.dv_xname); 523 goto fakeit; 524 } 525 526 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ADPTR_CFG, 527 &adp_cfg) == CS_ERROR) { 528 printf("%s: unable to read adapter config from EEPROM\n", 529 sc->sc_dev.dv_xname); 530 goto fakeit; 531 } 532 533 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_XMIT_CTL, 534 &xmit_ctl) == CS_ERROR) { 535 printf("%s: unable to read transmit control from EEPROM\n", 536 sc->sc_dev.dv_xname); 537 goto fakeit; 538 } 539 540 switch (adp_cfg & ADPTR_CFG_MEDIA) { 541 case ADPTR_CFG_AUI: 542 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5); 543 break; 544 case ADPTR_CFG_10BASE2: 545 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2); 546 break; 547 case ADPTR_CFG_10BASET: 548 default: 549 if (xmit_ctl & XMIT_CTL_FDX) 550 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX); 551 else 552 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 553 break; 554 } 555 return; 556 557 fakeit: 558 printf("%s: WARNING: default media setting may be inaccurate\n", 559 sc->sc_dev.dv_xname); 560 /* XXX Arbitrary... */ 561 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 562 } 563 564 int 565 cs_get_params(sc) 566 struct cs_softc *sc; 567 { 568 u_int16_t isaConfig; 569 u_int16_t adapterConfig; 570 571 if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 572 printf("%s: cs_get_params: EEPROM missing or bad\n", 573 sc->sc_dev.dv_xname); 574 return (CS_ERROR); 575 } 576 577 /* Get ISA configuration from the EEPROM */ 578 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ISA_CFG, 579 &isaConfig) == CS_ERROR) 580 goto eeprom_bad; 581 582 /* Get adapter configuration from the EEPROM */ 583 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ADPTR_CFG, 584 &adapterConfig) == CS_ERROR) 585 goto eeprom_bad; 586 587 /* Copy the USE_SA flag */ 588 if (isaConfig & ISA_CFG_USE_SA) 589 sc->sc_cfgflags |= CFGFLG_USE_SA; 590 591 /* Copy the IO Channel Ready flag */ 592 if (isaConfig & ISA_CFG_IOCHRDY) 593 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 594 595 /* Copy the DC/DC Polarity flag */ 596 if (adapterConfig & ADPTR_CFG_DCDC_POL) 597 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 598 599 return (CS_OK); 600 601 eeprom_bad: 602 printf("%s: cs_get_params: unable to read from EEPROM\n", 603 sc->sc_dev.dv_xname); 604 return (CS_ERROR); 605 } 606 607 int 608 cs_get_enaddr(sc) 609 struct cs_softc *sc; 610 { 611 u_int16_t *myea; 612 613 if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 614 printf("%s: cs_get_enaddr: EEPROM missing or bad\n", 615 sc->sc_dev.dv_xname); 616 return (CS_ERROR); 617 } 618 619 myea = (u_int16_t *)sc->sc_enaddr; 620 621 /* Get Ethernet address from the EEPROM */ 622 /* XXX this will likely lose on a big-endian machine. -- cgd */ 623 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_H, 624 &myea[0]) == CS_ERROR) 625 goto eeprom_bad; 626 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_M, 627 &myea[1]) == CS_ERROR) 628 goto eeprom_bad; 629 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_L, 630 &myea[2]) == CS_ERROR) 631 goto eeprom_bad; 632 633 return (CS_OK); 634 635 eeprom_bad: 636 printf("%s: cs_get_enaddr: unable to read from EEPROM\n", 637 sc->sc_dev.dv_xname); 638 return (CS_ERROR); 639 } 640 641 int 642 cs_reset_chip(sc) 643 struct cs_softc *sc; 644 { 645 int intState; 646 int x; 647 648 /* Disable interrupts at the CPU so reset command is atomic */ 649 intState = splnet(); 650 651 /* 652 * We are now resetting the chip 653 * 654 * A spurious interrupt is generated by the chip when it is reset. This 655 * variable informs the interrupt handler to ignore this interrupt. 656 */ 657 sc->sc_resetting = TRUE; 658 659 /* Issue a reset command to the chip */ 660 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET); 661 662 /* Re-enable interrupts at the CPU */ 663 splx(intState); 664 665 /* The chip is always in IO mode after a reset */ 666 sc->sc_memorymode = FALSE; 667 668 /* If transmission was in progress, it is not now */ 669 sc->sc_txbusy = FALSE; 670 671 /* 672 * there was a delay(125); here, but it seems uneccesary 125 usec is 673 * 1/8000 of a second, not 1/8 of a second. the data sheet advises 674 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below 675 * should be sufficient. 676 */ 677 678 /* Transition SBHE to switch chip from 8-bit to 16-bit */ 679 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 0); 680 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 1); 681 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 0); 682 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 1); 683 684 /* Wait until the EEPROM is not busy */ 685 for (x = 0; x < MAXLOOP; x++) { 686 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY)) 687 break; 688 } 689 690 if (x == MAXLOOP) 691 return CS_ERROR; 692 693 /* Wait until initialization is done */ 694 for (x = 0; x < MAXLOOP; x++) { 695 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE) 696 break; 697 } 698 699 if (x == MAXLOOP) 700 return CS_ERROR; 701 702 /* Reset is no longer in progress */ 703 sc->sc_resetting = FALSE; 704 705 return CS_OK; 706 } 707 708 int 709 cs_verify_eeprom(iot, ioh) 710 bus_space_tag_t iot; 711 bus_space_handle_t ioh; 712 { 713 u_int16_t self_status; 714 715 /* Verify that the EEPROM is present and OK */ 716 self_status = CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST); 717 if (((self_status & SELF_ST_EEP_PRES) && 718 (self_status & SELF_ST_EEP_OK)) == 0) 719 return (CS_ERROR); 720 721 return (CS_OK); 722 } 723 724 int 725 cs_read_eeprom(iot, ioh, offset, pValue) 726 bus_space_tag_t iot; 727 bus_space_handle_t ioh; 728 int offset; 729 u_int16_t *pValue; 730 { 731 int x; 732 733 /* Ensure that the EEPROM is not busy */ 734 for (x = 0; x < MAXLOOP; x++) { 735 if (!(CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST) & 736 SELF_ST_SI_BUSY)) 737 break; 738 } 739 740 if (x == MAXLOOP) 741 return (CS_ERROR); 742 743 /* Issue the command to read the offset within the EEPROM */ 744 CS_WRITE_PACKET_PAGE_IO(iot, ioh, PKTPG_EEPROM_CMD, 745 offset | EEPROM_CMD_READ); 746 747 /* Wait until the command is completed */ 748 for (x = 0; x < MAXLOOP; x++) { 749 if (!(CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST) & 750 SELF_ST_SI_BUSY)) 751 break; 752 } 753 754 if (x == MAXLOOP) 755 return (CS_ERROR); 756 757 /* Get the EEPROM data from the EEPROM Data register */ 758 *pValue = CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_EEPROM_DATA); 759 760 return (CS_OK); 761 } 762 763 void 764 cs_initChip(sc) 765 struct cs_softc *sc; 766 { 767 u_int16_t busCtl; 768 u_int16_t selfCtl; 769 u_int16_t *myea; 770 u_int16_t isaId; 771 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media); 772 773 /* Disable reception and transmission of frames */ 774 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 775 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) & 776 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON); 777 778 /* Disable interrupt at the chip */ 779 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 780 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL); 781 782 /* If IOCHRDY is enabled then clear the bit in the busCtl register */ 783 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL); 784 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) { 785 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 786 busCtl & ~BUS_CTL_IOCHRDY); 787 } else { 788 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 789 busCtl | BUS_CTL_IOCHRDY); 790 } 791 792 /* Set the Line Control register to match the media type */ 793 if (media == IFM_10_T) 794 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET); 795 else 796 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY); 797 798 /* 799 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to 800 * enable the DC/DC converter 801 */ 802 selfCtl = SELF_CTL_HC1E; 803 804 /* If the media type is 10Base2 */ 805 if (media == IFM_10_2) { 806 /* 807 * Enable the DC/DC converter if it has a low enable. 808 */ 809 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0) 810 /* 811 * Set the HCB1 bit, which causes the HC1 pin to go 812 * low. 813 */ 814 selfCtl |= SELF_CTL_HCB1; 815 } else { /* Media type is 10BaseT or AUI */ 816 /* 817 * Disable the DC/DC converter if it has a high enable. 818 */ 819 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) { 820 /* 821 * Set the HCB1 bit, which causes the HC1 pin to go 822 * low. 823 */ 824 selfCtl |= SELF_CTL_HCB1; 825 } 826 } 827 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl); 828 829 /* enable normal link pulse */ 830 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M) 831 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE); 832 833 /* Enable full-duplex, if appropriate */ 834 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 835 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX); 836 837 /* RX_CTL set in cs_set_ladr_filt(), below */ 838 839 /* enable all transmission interrupts */ 840 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE); 841 842 /* Accept all receive interrupts */ 843 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE); 844 845 /* 846 * Configure Operational Modes 847 * 848 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this is 849 * a better way to do it because the card has a counter which can be 850 * read to update the RX_MISS counter. This saves many interupts. 851 * 852 * I have turned on the tx and rx overflow interupts to counter using 853 * the receive miss interrupt. This is a better estimate of errors 854 * and requires lower system overhead. 855 */ 856 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE | 857 BUF_CFG_RX_DMA_IE); 858 859 if (sc->sc_dma_chipinit) 860 (*sc->sc_dma_chipinit)(sc); 861 862 /* If memory mode is enabled */ 863 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) { 864 /* If external logic is present for address decoding */ 865 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) { 866 /* 867 * Program the external logic to decode address bits 868 * SA20-SA23 869 */ 870 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD, 871 ((sc->sc_pktpgaddr & 0xffffff) >> 20) | 872 EEPROM_CMD_ELSEL); 873 } 874 875 /* 876 * Write the packet page base physical address to the memory 877 * base register. 878 */ 879 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0, 880 sc->sc_pktpgaddr & 0xFFFF); 881 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2, 882 sc->sc_pktpgaddr >> 16); 883 busCtl = BUS_CTL_MEM_MODE; 884 885 /* tell the chip to read the addresses off the SA pins */ 886 if (sc->sc_cfgflags & CFGFLG_USE_SA) { 887 busCtl |= BUS_CTL_USE_SA; 888 } 889 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 890 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl); 891 892 /* We are in memory mode now! */ 893 sc->sc_memorymode = TRUE; 894 895 /* 896 * wait here (10ms) for the chip to swap over. this is the 897 * maximum time that this could take. 898 */ 899 delay(10000); 900 901 /* Verify that we can read from the chip */ 902 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 903 904 /* 905 * As a last minute sanity check before actually using mapped 906 * memory we verify that we can read the isa number from the 907 * chip in memory mode. 908 */ 909 if (isaId != EISA_NUM_CRYSTAL) { 910 printf("%s: failed to enable memory mode\n", 911 sc->sc_dev.dv_xname); 912 sc->sc_memorymode = FALSE; 913 } else { 914 /* 915 * we are in memory mode so if we aren't using DMA, 916 * then program the chip to interrupt early. 917 */ 918 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) { 919 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 920 BUF_CFG_RX_DEST_IE | 921 BUF_CFG_RX_MISS_OVER_IE | 922 BUF_CFG_TX_COL_OVER_IE); 923 } 924 } 925 926 } 927 928 /* Put Ethernet address into the Individual Address register */ 929 myea = (u_int16_t *)sc->sc_enaddr; 930 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 0, myea[0]); 931 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 2, myea[1]); 932 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 4, myea[2]); 933 934 if (sc->sc_irq != -1) { 935 /* Set the interrupt level in the chip */ 936 if (sc->sc_prodid == PROD_ID_CS8900) { 937 if (sc->sc_irq == 5) { 938 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3); 939 } else { 940 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, (sc->sc_irq) - 10); 941 } 942 } 943 else { /* CS8920 */ 944 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, sc->sc_irq); 945 } 946 } 947 948 /* write the multicast mask to the address filter register */ 949 cs_set_ladr_filt(sc, &sc->sc_ethercom); 950 951 /* Enable reception and transmission of frames */ 952 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 953 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) | 954 LINE_CTL_RX_ON | LINE_CTL_TX_ON); 955 956 /* Enable interrupt at the chip */ 957 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 958 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL); 959 } 960 961 int 962 cs_init(ifp) 963 struct ifnet *ifp; 964 { 965 int intState; 966 int error = CS_OK; 967 struct cs_softc *sc = ifp->if_softc; 968 969 if (cs_enable(sc)) 970 goto out; 971 972 cs_stop(ifp, 0); 973 974 intState = splnet(); 975 976 #if 0 977 /* Mark the interface as down */ 978 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING); 979 #endif 980 981 #ifdef CS_DEBUG 982 /* Enable debugging */ 983 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG; 984 #endif 985 986 /* Reset the chip */ 987 if ((error = cs_reset_chip(sc)) == CS_OK) { 988 /* Initialize the chip */ 989 cs_initChip(sc); 990 991 /* Mark the interface as running */ 992 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 993 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 994 sc->sc_ethercom.ec_if.if_timer = 0; 995 996 /* Assume we have carrier until we are told otherwise. */ 997 sc->sc_carrier = 1; 998 } else { 999 printf("%s: unable to reset chip\n", sc->sc_dev.dv_xname); 1000 } 1001 1002 splx(intState); 1003 out: 1004 if (error == CS_OK) 1005 return 0; 1006 return EIO; 1007 } 1008 1009 void 1010 cs_set_ladr_filt(sc, ec) 1011 struct cs_softc *sc; 1012 struct ethercom *ec; 1013 { 1014 struct ifnet *ifp = &ec->ec_if; 1015 struct ether_multi *enm; 1016 struct ether_multistep step; 1017 u_int16_t af[4]; 1018 u_int16_t port, mask, index; 1019 1020 /* 1021 * Set up multicast address filter by passing all multicast addresses 1022 * through a crc generator, and then using the high order 6 bits as an 1023 * index into the 64 bit logical address filter. The high order bit 1024 * selects the word, while the rest of the bits select the bit within 1025 * the word. 1026 */ 1027 if (ifp->if_flags & IFF_PROMISC) { 1028 /* accept all valid frames. */ 1029 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1030 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A | 1031 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1032 ifp->if_flags |= IFF_ALLMULTI; 1033 return; 1034 } 1035 1036 /* 1037 * accept frames if a. crc valid, b. individual address match c. 1038 * broadcast address,and d. multicast addresses matched in the hash 1039 * filter 1040 */ 1041 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1042 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1043 1044 1045 /* 1046 * start off with all multicast flag clear, set it if we need to 1047 * later, otherwise we will leave it. 1048 */ 1049 ifp->if_flags &= ~IFF_ALLMULTI; 1050 af[0] = af[1] = af[2] = af[3] = 0x0000; 1051 1052 /* 1053 * Loop through all the multicast addresses unless we get a range of 1054 * addresses, in which case we will just accept all packets. 1055 * Justification for this is given in the next comment. 1056 */ 1057 ETHER_FIRST_MULTI(step, ec, enm); 1058 while (enm != NULL) { 1059 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1060 sizeof enm->enm_addrlo)) { 1061 /* 1062 * We must listen to a range of multicast addresses. 1063 * For now, just accept all multicasts, rather than 1064 * trying to set only those filter bits needed to match 1065 * the range. (At this time, the only use of address 1066 * ranges is for IP multicast routing, for which the 1067 * range is big enough to require all bits set.) 1068 */ 1069 ifp->if_flags |= IFF_ALLMULTI; 1070 af[0] = af[1] = af[2] = af[3] = 0xffff; 1071 break; 1072 } else { 1073 /* 1074 * we have got an individual address so just set that 1075 * bit. 1076 */ 1077 index = cs_hash_index(enm->enm_addrlo); 1078 1079 /* Set the bit the Logical address filter. */ 1080 port = (u_int16_t) (index >> 4); 1081 mask = (u_int16_t) (1 << (index & 0xf)); 1082 af[port] |= mask; 1083 1084 ETHER_NEXT_MULTI(step, enm); 1085 } 1086 } 1087 1088 /* now program the chip with the addresses */ 1089 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]); 1090 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]); 1091 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]); 1092 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]); 1093 return; 1094 } 1095 1096 u_int16_t 1097 cs_hash_index(addr) 1098 char *addr; 1099 { 1100 u_int POLY = 0x04c11db6; 1101 u_int crc_value = 0xffffffff; 1102 u_int16_t hash_code = 0; 1103 int i; 1104 u_int current_bit; 1105 char current_byte = *addr; 1106 u_int cur_crc_high; 1107 1108 for (i = 0; i < 6; i++) { 1109 current_byte = *addr; 1110 addr++; 1111 1112 for (current_bit = 8; current_bit; current_bit--) { 1113 cur_crc_high = crc_value >> 31; 1114 crc_value <<= 1; 1115 if (cur_crc_high ^ (current_byte & 0x01)) { 1116 crc_value ^= POLY; 1117 crc_value |= 0x00000001; 1118 } 1119 current_byte >>= 1; 1120 } 1121 } 1122 1123 /* 1124 * The hash code is the 6 least significant bits of the CRC 1125 * in the reverse order: CRC[0] = hash[5],CRC[1] = hash[4],etc. 1126 */ 1127 for (i = 0; i < 6; i++) { 1128 hash_code = (u_int16_t) ((hash_code << 1) | 1129 (u_int16_t) ((crc_value >> i) & 0x00000001)); 1130 } 1131 1132 return hash_code; 1133 } 1134 1135 void 1136 cs_reset(arg) 1137 void *arg; 1138 { 1139 struct cs_softc *sc = arg; 1140 1141 /* Mark the interface as down */ 1142 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1143 1144 /* Reset the chip */ 1145 cs_reset_chip(sc); 1146 } 1147 1148 int 1149 cs_ioctl(ifp, cmd, data) 1150 struct ifnet *ifp; 1151 u_long cmd; 1152 caddr_t data; 1153 { 1154 struct cs_softc *sc = ifp->if_softc; 1155 struct ifreq *ifr = (struct ifreq *) data; 1156 int state; 1157 int result; 1158 1159 state = splnet(); 1160 1161 result = 0; /* only set if something goes wrong */ 1162 1163 switch (cmd) { 1164 case SIOCGIFMEDIA: 1165 case SIOCSIFMEDIA: 1166 result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1167 break; 1168 1169 default: 1170 result = ether_ioctl(ifp, cmd, data); 1171 if (result == ENETRESET) { 1172 if (CS_IS_ENABLED(sc)) { 1173 /* 1174 * Multicast list has changed. Set the 1175 * hardware filter accordingly. 1176 */ 1177 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1178 } 1179 result = 0; 1180 } 1181 break; 1182 } 1183 1184 splx(state); 1185 1186 return result; 1187 } 1188 1189 int 1190 cs_mediachange(ifp) 1191 struct ifnet *ifp; 1192 { 1193 1194 /* 1195 * Current media is already set up. Just reset the interface 1196 * to let the new value take hold. 1197 */ 1198 cs_init(ifp); 1199 return (0); 1200 } 1201 1202 void 1203 cs_mediastatus(ifp, ifmr) 1204 struct ifnet *ifp; 1205 struct ifmediareq *ifmr; 1206 { 1207 struct cs_softc *sc = ifp->if_softc; 1208 1209 /* 1210 * The currently selected media is always the active media. 1211 */ 1212 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media; 1213 1214 if (ifp->if_flags & IFF_UP) { 1215 /* Interface up, status is valid. */ 1216 ifmr->ifm_status = IFM_AVALID | 1217 (sc->sc_carrier ? IFM_ACTIVE : 0); 1218 } 1219 else ifmr->ifm_status = 0; 1220 } 1221 1222 int 1223 cs_intr(arg) 1224 void *arg; 1225 { 1226 struct cs_softc *sc = arg; 1227 u_int16_t Event; 1228 #if NRND > 0 1229 u_int16_t rndEvent; 1230 #endif 1231 1232 /* Ignore any interrupts that happen while the chip is being reset */ 1233 if (sc->sc_resetting) { 1234 printf("%s: cs_intr: reset in progress\n", 1235 sc->sc_dev.dv_xname); 1236 return 1; 1237 } 1238 1239 /* Read an event from the Interrupt Status Queue */ 1240 if (sc->sc_memorymode) 1241 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1242 else 1243 Event = CS_READ_PORT(sc, PORT_ISQ); 1244 1245 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff) 1246 return 0; /* not ours */ 1247 1248 #if NRND > 0 1249 rndEvent = Event; 1250 #endif 1251 1252 /* Process all the events in the Interrupt Status Queue */ 1253 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) { 1254 /* Dispatch to an event handler based on the register number */ 1255 switch (Event & REG_NUM_MASK) { 1256 case REG_NUM_RX_EVENT: 1257 cs_receive_event(sc, Event); 1258 break; 1259 case REG_NUM_TX_EVENT: 1260 cs_transmit_event(sc, Event); 1261 break; 1262 case REG_NUM_BUF_EVENT: 1263 cs_buffer_event(sc, Event); 1264 break; 1265 case REG_NUM_TX_COL: 1266 case REG_NUM_RX_MISS: 1267 cs_counter_event(sc, Event); 1268 break; 1269 default: 1270 printf("%s: unknown interrupt event 0x%x\n", 1271 sc->sc_dev.dv_xname, Event); 1272 break; 1273 } 1274 1275 /* Read another event from the Interrupt Status Queue */ 1276 if (sc->sc_memorymode) 1277 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1278 else 1279 Event = CS_READ_PORT(sc, PORT_ISQ); 1280 } 1281 1282 /* have handled the interupt */ 1283 #if NRND > 0 1284 rnd_add_uint32(&sc->rnd_source, rndEvent); 1285 #endif 1286 return 1; 1287 } 1288 1289 void 1290 cs_counter_event(sc, cntEvent) 1291 struct cs_softc *sc; 1292 u_int16_t cntEvent; 1293 { 1294 struct ifnet *ifp; 1295 u_int16_t errorCount; 1296 1297 ifp = &sc->sc_ethercom.ec_if; 1298 1299 switch (cntEvent & REG_NUM_MASK) { 1300 case REG_NUM_TX_COL: 1301 /* 1302 * the count should be read before an overflow occurs. 1303 */ 1304 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL); 1305 /* 1306 * the tramsit event routine always checks the number of 1307 * collisions for any packet so we don't increment any 1308 * counters here, as they should already have been 1309 * considered. 1310 */ 1311 break; 1312 case REG_NUM_RX_MISS: 1313 /* 1314 * the count should be read before an overflow occurs. 1315 */ 1316 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS); 1317 /* 1318 * Increment the input error count, the first 6bits are the 1319 * register id. 1320 */ 1321 ifp->if_ierrors += ((errorCount & 0xffC0) >> 6); 1322 break; 1323 default: 1324 /* do nothing */ 1325 break; 1326 } 1327 } 1328 1329 void 1330 cs_buffer_event(sc, bufEvent) 1331 struct cs_softc *sc; 1332 u_int16_t bufEvent; 1333 { 1334 struct ifnet *ifp; 1335 1336 ifp = &sc->sc_ethercom.ec_if; 1337 1338 /* 1339 * multiple events can be in the buffer event register at one time so 1340 * a standard switch statement will not suffice, here every event 1341 * must be checked. 1342 */ 1343 1344 /* 1345 * if 128 bits have been rxed by the time we get here, the dest event 1346 * will be cleared and 128 event will be set. 1347 */ 1348 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) { 1349 cs_process_rx_early(sc); 1350 } 1351 1352 if (bufEvent & BUF_EVENT_RX_DMA) { 1353 /* process the receive data */ 1354 if (sc->sc_dma_process_rx) 1355 (*sc->sc_dma_process_rx)(sc); 1356 else 1357 /* should panic? */ 1358 printf("%s: unexpected dma event\n", sc->sc_dev.dv_xname); 1359 } 1360 1361 if (bufEvent & BUF_EVENT_TX_UNDR) { 1362 #if 0 1363 /* 1364 * This can happen occasionally, and it's not worth worrying 1365 * about. 1366 */ 1367 printf("%s: transmit underrun (%d -> %d)\n", 1368 sc->sc_dev.dv_xname, sc->sc_xe_ent, 1369 cs_xmit_early_table[sc->sc_xe_ent].worse); 1370 #endif 1371 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse; 1372 sc->sc_xe_togo = 1373 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1374 1375 /* had an underrun, transmit is finished */ 1376 sc->sc_txbusy = FALSE; 1377 } 1378 1379 if (bufEvent & BUF_EVENT_SW_INT) { 1380 printf("%s: software initiated interrupt\n", 1381 sc->sc_dev.dv_xname); 1382 } 1383 } 1384 1385 void 1386 cs_transmit_event(sc, txEvent) 1387 struct cs_softc *sc; 1388 u_int16_t txEvent; 1389 { 1390 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1391 1392 /* If there were any errors transmitting this frame */ 1393 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | TX_EVENT_OUT_WIN | 1394 TX_EVENT_JABBER | TX_EVENT_16_COLL)) { 1395 /* Increment the output error count */ 1396 ifp->if_oerrors++; 1397 1398 /* Note carrier loss. */ 1399 if (txEvent & TX_EVENT_LOSS_CRS) 1400 sc->sc_carrier = 0; 1401 1402 /* If debugging is enabled then log error messages */ 1403 if (ifp->if_flags & IFF_DEBUG) { 1404 if (txEvent & TX_EVENT_LOSS_CRS) { 1405 printf("%s: lost carrier\n", 1406 sc->sc_dev.dv_xname); 1407 } 1408 if (txEvent & TX_EVENT_SQE_ERR) { 1409 printf("%s: SQE error\n", 1410 sc->sc_dev.dv_xname); 1411 } 1412 if (txEvent & TX_EVENT_OUT_WIN) { 1413 printf("%s: out-of-window collision\n", 1414 sc->sc_dev.dv_xname); 1415 } 1416 if (txEvent & TX_EVENT_JABBER) { 1417 printf("%s: jabber\n", sc->sc_dev.dv_xname); 1418 } 1419 if (txEvent & TX_EVENT_16_COLL) { 1420 printf("%s: 16 collisions\n", 1421 sc->sc_dev.dv_xname); 1422 } 1423 } 1424 } 1425 else { 1426 /* Transmission successful, carrier is up. */ 1427 sc->sc_carrier = 1; 1428 #ifdef SHARK 1429 ledNetActive(); 1430 #endif 1431 } 1432 1433 /* Add the number of collisions for this frame */ 1434 if (txEvent & TX_EVENT_16_COLL) { 1435 ifp->if_collisions += 16; 1436 } else { 1437 ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11); 1438 } 1439 1440 ifp->if_opackets++; 1441 1442 /* Transmission is no longer in progress */ 1443 sc->sc_txbusy = FALSE; 1444 1445 /* If there is more to transmit */ 1446 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 1447 /* Start the next transmission */ 1448 cs_start_output(ifp); 1449 } 1450 } 1451 1452 void 1453 cs_print_rx_errors(sc, rxEvent) 1454 struct cs_softc *sc; 1455 u_int16_t rxEvent; 1456 { 1457 1458 if (rxEvent & RX_EVENT_RUNT) 1459 printf("%s: runt\n", sc->sc_dev.dv_xname); 1460 1461 if (rxEvent & RX_EVENT_X_DATA) 1462 printf("%s: extra data\n", sc->sc_dev.dv_xname); 1463 1464 if (rxEvent & RX_EVENT_CRC_ERR) { 1465 if (rxEvent & RX_EVENT_DRIBBLE) 1466 printf("%s: alignment error\n", sc->sc_dev.dv_xname); 1467 else 1468 printf("%s: CRC error\n", sc->sc_dev.dv_xname); 1469 } else { 1470 if (rxEvent & RX_EVENT_DRIBBLE) 1471 printf("%s: dribble bits\n", sc->sc_dev.dv_xname); 1472 } 1473 } 1474 1475 void 1476 cs_receive_event(sc, rxEvent) 1477 struct cs_softc *sc; 1478 u_int16_t rxEvent; 1479 { 1480 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1481 1482 /* If the frame was not received OK */ 1483 if (!(rxEvent & RX_EVENT_RX_OK)) { 1484 /* Increment the input error count */ 1485 ifp->if_ierrors++; 1486 1487 /* 1488 * If debugging is enabled then log error messages. 1489 */ 1490 if (ifp->if_flags & IFF_DEBUG) { 1491 if (rxEvent != REG_NUM_RX_EVENT) { 1492 cs_print_rx_errors(sc, rxEvent); 1493 1494 /* 1495 * Must read the length of all received 1496 * frames 1497 */ 1498 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1499 1500 /* Skip the received frame */ 1501 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1502 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | 1503 RX_CFG_SKIP); 1504 } else { 1505 printf("%s: implied skip\n", 1506 sc->sc_dev.dv_xname); 1507 } 1508 } 1509 } else { 1510 /* 1511 * process the received frame and pass it up to the upper 1512 * layers. 1513 */ 1514 cs_process_receive(sc); 1515 } 1516 } 1517 1518 void 1519 cs_ether_input(sc, m) 1520 struct cs_softc *sc; 1521 struct mbuf *m; 1522 { 1523 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1524 1525 ifp->if_ipackets++; 1526 1527 #if NBPFILTER > 0 1528 /* 1529 * Check if there's a BPF listener on this interface. 1530 * If so, hand off the raw packet to BPF. 1531 */ 1532 if (ifp->if_bpf) 1533 bpf_mtap(ifp->if_bpf, m); 1534 #endif 1535 1536 /* Pass the packet up. */ 1537 (*ifp->if_input)(ifp, m); 1538 } 1539 1540 void 1541 cs_process_receive(sc) 1542 struct cs_softc *sc; 1543 { 1544 struct ifnet *ifp; 1545 struct mbuf *m; 1546 int totlen; 1547 int len; 1548 u_int16_t *pBuff, *pBuffLimit; 1549 int pad; 1550 unsigned int frameOffset; 1551 1552 #ifdef SHARK 1553 ledNetActive(); 1554 #endif 1555 1556 ifp = &sc->sc_ethercom.ec_if; 1557 1558 /* Received a packet; carrier is up. */ 1559 sc->sc_carrier = 1; 1560 1561 if (sc->sc_memorymode) { 1562 /* Initialize the frame offset */ 1563 frameOffset = PKTPG_RX_LENGTH; 1564 1565 /* Get the length of the received frame */ 1566 totlen = CS_READ_PACKET_PAGE(sc, frameOffset); 1567 frameOffset += 2; 1568 } 1569 else { 1570 /* drop status */ 1571 CS_READ_PORT(sc, PORT_RXTX_DATA); 1572 1573 /* Get the length of the received frame */ 1574 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA); 1575 } 1576 1577 MGETHDR(m, M_DONTWAIT, MT_DATA); 1578 if (m == 0) { 1579 printf("%s: cs_process_receive: unable to allocate mbuf\n", 1580 sc->sc_dev.dv_xname); 1581 ifp->if_ierrors++; 1582 /* 1583 * couldn't allocate an mbuf so things are not good, may as 1584 * well drop the packet I think. 1585 * 1586 * have already read the length so we should be right to skip 1587 * the packet. 1588 */ 1589 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1590 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1591 return; 1592 } 1593 m->m_pkthdr.rcvif = ifp; 1594 m->m_pkthdr.len = totlen; 1595 1596 /* 1597 * save processing by always using a mbuf cluster, guarenteed to fit 1598 * packet, on i386 NetBSD anyway. 1599 */ 1600 MCLGET(m, M_DONTWAIT); 1601 if (m->m_flags & M_EXT) { 1602 len = MCLBYTES; 1603 } else { 1604 /* couldn't allocate an mbuf cluster */ 1605 printf("%s: cs_process_receive: unable to allocate a cluster\n", 1606 sc->sc_dev.dv_xname); 1607 m_freem(m); 1608 1609 /* skip the received frame */ 1610 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1611 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1612 return; 1613 } 1614 1615 /* align ip header on word boundary for ipintr */ 1616 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1617 m->m_data += pad; 1618 len -= pad + 1; 1619 1620 m->m_len = len = min(totlen, len); 1621 pBuff = mtod(m, u_int16_t *); 1622 1623 /* now read the data from the chip */ 1624 if (sc->sc_memorymode) { 1625 pBuffLimit = pBuff + (len + 1) / 2; /* don't want to go over */ 1626 while (pBuff < pBuffLimit) { 1627 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1628 frameOffset += 2; 1629 } 1630 } 1631 else { 1632 bus_space_read_multi_2(sc->sc_iot, sc->sc_ioh, PORT_RXTX_DATA, 1633 pBuff, (len + 1)>>1); 1634 } 1635 1636 cs_ether_input(sc, m); 1637 } 1638 1639 void 1640 cs_process_rx_early(sc) 1641 struct cs_softc *sc; 1642 { 1643 struct ifnet *ifp; 1644 struct mbuf *m; 1645 u_int16_t frameCount, oldFrameCount; 1646 u_int16_t rxEvent; 1647 u_int16_t *pBuff; 1648 int pad; 1649 unsigned int frameOffset; 1650 1651 1652 ifp = &sc->sc_ethercom.ec_if; 1653 1654 /* Initialize the frame offset */ 1655 frameOffset = PKTPG_RX_FRAME; 1656 frameCount = 0; 1657 1658 MGETHDR(m, M_DONTWAIT, MT_DATA); 1659 if (m == 0) { 1660 printf("%s: cs_process_rx_early: unable to allocate mbuf\n", 1661 sc->sc_dev.dv_xname); 1662 ifp->if_ierrors++; 1663 /* 1664 * couldn't allocate an mbuf so things are not good, may as 1665 * well drop the packet I think. 1666 * 1667 * have already read the length so we should be right to skip 1668 * the packet. 1669 */ 1670 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1671 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1672 return; 1673 } 1674 m->m_pkthdr.rcvif = ifp; 1675 /* 1676 * save processing by always using a mbuf cluster, guarenteed to fit 1677 * packet 1678 */ 1679 MCLGET(m, M_DONTWAIT); 1680 if ((m->m_flags & M_EXT) == 0) { 1681 /* couldn't allocate an mbuf cluster */ 1682 printf("%s: cs_process_rx_early: unable to allocate a cluster\n", 1683 sc->sc_dev.dv_xname); 1684 m_freem(m); 1685 /* skip the frame */ 1686 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1687 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1688 return; 1689 } 1690 1691 /* align ip header on word boundary for ipintr */ 1692 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1693 m->m_data += pad; 1694 1695 /* set up the buffer pointer to point to the data area */ 1696 pBuff = mtod(m, u_int16_t *); 1697 1698 /* 1699 * now read the frame byte counter until we have finished reading the 1700 * frame 1701 */ 1702 oldFrameCount = 0; 1703 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1704 while ((frameCount != 0) && (frameCount < MCLBYTES)) { 1705 for (; oldFrameCount < frameCount; oldFrameCount += 2) { 1706 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1707 frameOffset += 2; 1708 } 1709 1710 /* read the new count from the chip */ 1711 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1712 } 1713 1714 /* update the mbuf counts */ 1715 m->m_len = oldFrameCount; 1716 m->m_pkthdr.len = oldFrameCount; 1717 1718 /* now check the Rx Event register */ 1719 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1720 1721 if ((rxEvent & RX_EVENT_RX_OK) != 0) { 1722 /* 1723 * do an implied skip, it seems to be more reliable than a 1724 * forced skip. 1725 */ 1726 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS); 1727 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1728 1729 /* 1730 * now read the RX_EVENT register to perform an implied skip. 1731 */ 1732 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1733 1734 cs_ether_input(sc, m); 1735 } else { 1736 m_freem(m); 1737 ifp->if_ierrors++; 1738 } 1739 } 1740 1741 void 1742 cs_start_output(ifp) 1743 struct ifnet *ifp; 1744 { 1745 struct cs_softc *sc; 1746 struct mbuf *pMbuf; 1747 struct mbuf *pMbufChain; 1748 u_int16_t BusStatus; 1749 u_int16_t Length; 1750 int txLoop = 0; 1751 int dropout = 0; 1752 1753 sc = ifp->if_softc; 1754 1755 /* check that the interface is up and running */ 1756 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1757 return; 1758 } 1759 1760 /* Don't interrupt a transmission in progress */ 1761 if (sc->sc_txbusy) { 1762 return; 1763 } 1764 1765 /* this loop will only run through once if transmission is successful */ 1766 /* 1767 * While there are packets to transmit and a transmit is not in 1768 * progress 1769 */ 1770 while (sc->sc_txbusy == 0 && dropout == 0) { 1771 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain); 1772 if (pMbufChain == NULL) 1773 break; 1774 1775 #if NBPFILTER > 0 1776 /* 1777 * If BPF is listening on this interface, let it see the packet 1778 * before we commit it to the wire. 1779 */ 1780 if (ifp->if_bpf) 1781 bpf_mtap(ifp->if_bpf, pMbufChain); 1782 #endif 1783 1784 /* Find the total length of the data to transmit */ 1785 Length = 0; 1786 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next) 1787 Length += pMbuf->m_len; 1788 1789 do { 1790 /* 1791 * Request that the transmit be started after all 1792 * data has been copied 1793 * 1794 * In IO mode must write to the IO port not the packet 1795 * page address 1796 * 1797 * If this is changed to start transmission after a 1798 * small amount of data has been copied you tend to 1799 * get packet missed errors i think because the ISA 1800 * bus is too slow. Or possibly the copy routine is 1801 * not streamlined enough. 1802 */ 1803 if (sc->sc_memorymode) { 1804 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD, 1805 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1806 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length); 1807 } 1808 else { 1809 CS_WRITE_PORT(sc, PORT_TX_CMD, 1810 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1811 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length); 1812 } 1813 1814 /* 1815 * Adjust early-transmit machinery. 1816 */ 1817 if (--sc->sc_xe_togo == 0) { 1818 sc->sc_xe_ent = 1819 cs_xmit_early_table[sc->sc_xe_ent].better; 1820 sc->sc_xe_togo = 1821 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1822 } 1823 /* 1824 * Read the BusStatus register which indicates 1825 * success of the request 1826 */ 1827 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST); 1828 1829 /* 1830 * If there was an error in the transmit bid free the 1831 * mbuf and go on. This is presuming that mbuf is 1832 * corrupt. 1833 */ 1834 if (BusStatus & BUS_ST_TX_BID_ERR) { 1835 printf("%s: transmit bid error (too big)", 1836 sc->sc_dev.dv_xname); 1837 1838 /* Discard the bad mbuf chain */ 1839 m_freem(pMbufChain); 1840 sc->sc_ethercom.ec_if.if_oerrors++; 1841 1842 /* Loop up to transmit the next chain */ 1843 txLoop = 0; 1844 } else { 1845 if (BusStatus & BUS_ST_RDY4TXNOW) { 1846 /* 1847 * The chip is ready for transmission 1848 * now 1849 */ 1850 /* 1851 * Copy the frame to the chip to 1852 * start transmission 1853 */ 1854 cs_copy_tx_frame(sc, pMbufChain); 1855 1856 /* Free the mbuf chain */ 1857 m_freem(pMbufChain); 1858 1859 /* Transmission is now in progress */ 1860 sc->sc_txbusy = TRUE; 1861 txLoop = 0; 1862 } else { 1863 /* 1864 * if we get here we want to try 1865 * again with the same mbuf, until 1866 * the chip lets us transmit. 1867 */ 1868 txLoop++; 1869 if (txLoop > CS_OUTPUT_LOOP_MAX) { 1870 /* Free the mbuf chain */ 1871 m_freem(pMbufChain); 1872 /* 1873 * Transmission is not in 1874 * progress 1875 */ 1876 sc->sc_txbusy = FALSE; 1877 /* 1878 * Increment the output error 1879 * count 1880 */ 1881 ifp->if_oerrors++; 1882 /* 1883 * exit the routine and drop 1884 * the packet. 1885 */ 1886 txLoop = 0; 1887 dropout = 1; 1888 } 1889 } 1890 } 1891 } while (txLoop); 1892 } 1893 } 1894 1895 void 1896 cs_copy_tx_frame(sc, m0) 1897 struct cs_softc *sc; 1898 struct mbuf *m0; 1899 { 1900 struct mbuf *m; 1901 int len, leftover, frameoff; 1902 u_int16_t dbuf; 1903 u_int8_t *p; 1904 #ifdef DIAGNOSTIC 1905 u_int8_t *lim; 1906 #endif 1907 1908 /* Initialize frame pointer and data port address */ 1909 frameoff = PKTPG_TX_FRAME; 1910 1911 /* start out with no leftover data */ 1912 leftover = 0; 1913 dbuf = 0; 1914 1915 /* Process the chain of mbufs */ 1916 for (m = m0; m != NULL; m = m->m_next) { 1917 /* 1918 * Process all of the data in a single mbuf. 1919 */ 1920 p = mtod(m, u_int8_t *); 1921 len = m->m_len; 1922 #ifdef DIAGNOSTIC 1923 lim = p + len; 1924 #endif 1925 1926 while (len > 0) { 1927 if (leftover) { 1928 /* 1929 * Data left over (from mbuf or realignment). 1930 * Buffer the next byte, and write it and 1931 * the leftover data out. 1932 */ 1933 dbuf |= *p++ << 8; 1934 len--; 1935 if (sc->sc_memorymode) { 1936 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 1937 frameoff += 2; 1938 } 1939 else { 1940 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 1941 } 1942 leftover = 0; 1943 } else if ((long) p & 1) { 1944 /* 1945 * Misaligned data. Buffer the next byte. 1946 */ 1947 dbuf = *p++; 1948 len--; 1949 leftover = 1; 1950 } else { 1951 /* 1952 * Aligned data. This is the case we like. 1953 * 1954 * Write-region out as much as we can, then 1955 * buffer the remaining byte (if any). 1956 */ 1957 leftover = len & 1; 1958 len &= ~1; 1959 if (sc->sc_memorymode) { 1960 bus_space_write_region_2(sc->sc_memt, sc->sc_memh, frameoff, 1961 (u_int16_t *) p, len >> 1); 1962 frameoff += len; 1963 } 1964 else { 1965 bus_space_write_multi_2(sc->sc_iot, sc->sc_ioh, 1966 PORT_RXTX_DATA, (u_int16_t *)p, len >> 1); 1967 } 1968 p += len; 1969 1970 if (leftover) 1971 dbuf = *p++; 1972 len = 0; 1973 } 1974 } 1975 if (len < 0) 1976 panic("cs_copy_tx_frame: negative len"); 1977 #ifdef DIAGNOSTIC 1978 if (p != lim) 1979 panic("cs_copy_tx_frame: p != lim"); 1980 #endif 1981 } 1982 if (leftover) { 1983 if (sc->sc_memorymode) { 1984 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 1985 } 1986 else { 1987 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 1988 } 1989 } 1990 } 1991 1992 static int 1993 cs_enable(sc) 1994 struct cs_softc *sc; 1995 { 1996 if (!CS_IS_ENABLED(sc) && sc->sc_enable) { 1997 int error; 1998 1999 error = (*sc->sc_enable)(sc); 2000 if (error) 2001 return error; 2002 2003 sc->sc_cfgflags |= CFGFLG_ENABLED; 2004 } 2005 2006 return 0; 2007 } 2008 2009 static void 2010 cs_disable(sc) 2011 struct cs_softc *sc; 2012 { 2013 if (CS_IS_ENABLED(sc) && sc->sc_disable) { 2014 (*sc->sc_disable)(sc); 2015 2016 sc->sc_cfgflags &= ~CFGFLG_ENABLED; 2017 } 2018 } 2019 2020 static void 2021 cs_stop(ifp, disable) 2022 struct ifnet *ifp; 2023 int disable; 2024 { 2025 struct cs_softc *sc = ifp->if_softc; 2026 2027 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0); 2028 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0); 2029 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0); 2030 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0); 2031 2032 if (disable) { 2033 cs_disable(sc); 2034 } 2035 2036 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2037 } 2038 2039 int 2040 cs_activate(self, act) 2041 struct device *self; 2042 enum devact act; 2043 { 2044 struct cs_softc *sc = (void *)self; 2045 int s, error = 0; 2046 2047 s = splnet(); 2048 switch (act) { 2049 case DVACT_ACTIVATE: 2050 error = EOPNOTSUPP; 2051 break; 2052 2053 case DVACT_DEACTIVATE: 2054 if_deactivate(&sc->sc_ethercom.ec_if); 2055 break; 2056 } 2057 splx(s); 2058 2059 return error; 2060 } 2061 2062 static void 2063 cs_power(why, arg) 2064 int why; 2065 void *arg; 2066 { 2067 struct cs_softc *sc = arg; 2068 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2069 int s; 2070 2071 s = splnet(); 2072 switch (why) { 2073 case PWR_STANDBY: 2074 case PWR_SUSPEND: 2075 cs_stop(ifp, 0); 2076 break; 2077 case PWR_RESUME: 2078 if (ifp->if_flags & IFF_UP) { 2079 cs_init(ifp); 2080 } 2081 break; 2082 case PWR_SOFTSUSPEND: 2083 case PWR_SOFTSTANDBY: 2084 case PWR_SOFTRESUME: 2085 break; 2086 } 2087 splx(s); 2088 } 2089
Indexes created Fri Oct 03 02:09:57 GMT 2025