cs89x0.c revision 1.3
1 /* $NetBSD: cs89x0.c,v 1.3 2002/02/10 11:48:56 pooka Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 **++ 38 ** FACILITY 39 ** 40 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller. 41 ** 42 ** ABSTRACT 43 ** 44 ** This module provides standard ethernet access for INET protocols 45 ** only. 46 ** 47 ** AUTHORS 48 ** 49 ** Peter Dettori SEA - Software Engineering. 50 ** 51 ** CREATION DATE: 52 ** 53 ** 13-Feb-1997. 54 ** 55 ** MODIFICATION HISTORY (Digital): 56 ** 57 ** Revision 1.27 1998/01/20 17:59:40 cgd 58 ** update for moved headers 59 ** 60 ** Revision 1.26 1998/01/12 19:29:36 cgd 61 ** use arm32/isa versions of isadma code. 62 ** 63 ** Revision 1.25 1997/12/12 01:35:27 cgd 64 ** convert to use new arp code (from Brini) 65 ** 66 ** Revision 1.24 1997/12/10 22:31:56 cgd 67 ** trim some fat (get rid of ability to explicitly supply enet addr, since 68 ** it was never used and added a bunch of code which really doesn't belong in 69 ** an enet driver), and clean up slightly. 70 ** 71 ** Revision 1.23 1997/10/06 16:42:12 cgd 72 ** copyright notices 73 ** 74 ** Revision 1.22 1997/06/20 19:38:01 chaiken 75 ** fixes some smartcard problems 76 ** 77 ** Revision 1.21 1997/06/10 02:56:20 grohn 78 ** Added call to ledNetActive 79 ** 80 ** Revision 1.20 1997/06/05 00:47:06 dettori 81 ** Changed cs_process_rx_dma to reset and re-initialise the 82 ** ethernet chip when DMA gets out of sync, or mbufs 83 ** can't be allocated. 84 ** 85 ** Revision 1.19 1997/06/03 03:09:58 dettori 86 ** Turn off sc_txbusy flag when a transmit underrun 87 ** occurs. 88 ** 89 ** Revision 1.18 1997/06/02 00:04:35 dettori 90 ** redefined the transmit table to get around the nfs_timer bug while we are 91 ** looking into it further. 92 ** 93 ** Also changed interrupts from EDGE to LEVEL. 94 ** 95 ** Revision 1.17 1997/05/27 23:31:01 dettori 96 ** Pulled out changes to DMAMODE defines. 97 ** 98 ** Revision 1.16 1997/05/23 04:25:16 cgd 99 ** reformat log so it fits in 80cols 100 ** 101 ** Revision 1.15 1997/05/23 04:22:18 cgd 102 ** remove the existing copyright notice (which Peter Dettori indicated 103 ** was incorrect, copied from an existing NetBSD file only so that the 104 ** file would have a copyright notice on it, and which he'd intended to 105 ** replace). Replace it with a Digital copyright notice, cloned from 106 ** ess.c. It's not really correct either (it indicates that the source 107 ** is Digital confidential!), but is better than nothing and more 108 ** correct than what was there before. 109 ** 110 ** Revision 1.14 1997/05/23 04:12:50 cgd 111 ** use an adaptive transmit start algorithm: start by telling the chip 112 ** to start transmitting after 381 bytes have been fed to it. if that 113 ** gets transmit underruns, ramp down to 1021 bytes then "whole 114 ** packet." If successful at a given level for a while, try the next 115 ** more agressive level. This code doesn't ever try to start 116 ** transmitting after 5 bytes have been sent to the NIC, because 117 ** that underruns rather regularly. The back-off and ramp-up mechanism 118 ** could probably be tuned a little bit, but this works well enough to 119 ** support > 1MB/s transmit rates on a clear ethernet (which is about 120 ** 20-25% better than the driver had previously been getting). 121 ** 122 ** Revision 1.13 1997/05/22 21:06:54 cgd 123 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly 124 ** casting from u_int8_t * to u_int16_t * without worrying about alignment 125 ** issues. This would cause bogus data to be spit out for mbufs with 126 ** misaligned data. For instance, it caused the following bits to appear 127 ** on the wire: 128 ** ... etBND 1S2C .SHA(K) R ... 129 ** 11112222333344445555 130 ** which should have appeared as: 131 ** ... NetBSD 1.2C (SHARK) ... 132 ** 11112222333344445555 133 ** Note the apparent 'rotate' of the bytes in the word, which was due to 134 ** incorrect unaligned accesses. This data corruption was the cause of 135 ** incoming telnet/rlogin hangs. 136 ** 137 ** Revision 1.12 1997/05/22 01:55:32 cgd 138 ** reformat log so it fits in 80cols 139 ** 140 ** Revision 1.11 1997/05/22 01:50:27 cgd 141 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case, 142 ** so packets aimed at other hosts don't get sent to ether_input(). 143 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that 144 ** you can easily tell (`strings`) what version of the driver is in your 145 ** kernel binary. 146 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily 147 ** safe, and not really a performance win anyway. (It was only used when 148 ** setting up the multicast logical address filter, which is an 149 ** infrequent event. It could have been used in the IFF_PROMISCUOUS 150 ** address check above, but the benefit of it vs. memcmp would be 151 ** inconsequential, there.) Use memcmp() instead. 152 ** * restructure csStartOuput to avoid the following bugs in the case where 153 ** txWait was being set: 154 ** * it would accidentally drop the outgoing packet if told to wait 155 ** but the outgoing packet queue was empty. 156 ** * it would bpf_mtap() the outgoing packet multiple times (once for 157 ** each time it was told to wait), and would also recalculate 158 ** the length of the outgoing packet each time it was told to 159 ** wait. 160 ** While there, rename txWait to txLoop, since with the new structure of 161 ** the code, the latter name makes more sense. 162 ** 163 ** Revision 1.10 1997/05/19 02:03:20 cgd 164 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip() 165 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this 166 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC 167 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave 168 ** as before. 169 ** 170 ** Revision 1.9 1997/05/19 01:45:37 cgd 171 ** create a new function, cs_ether_input(), which does received-packet 172 ** BPF and ether_input processing. This code used to be in three places, 173 ** and centralizing it will make adding IFF_PROMISC support much easier. 174 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to 175 ** do copies with bus_space_write_region_2(). It's more correct, and 176 ** potentially more efficient. That function needs to be gutted (to 177 ** deal properly with alignment issues, which it currently does wrong), 178 ** however, and the change doesn't gain much, so there's no point in 179 ** enabling it now. 180 ** 181 ** Revision 1.8 1997/05/19 01:17:10 cgd 182 ** fix a comment re: the setting of the TxConfig register. Clean up 183 ** interface counter maintenance (make it use standard idiom). 184 ** 185 **-- 186 */ 187 188 #include <sys/cdefs.h> 189 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.3 2002/02/10 11:48:56 pooka Exp $"); 190 191 #include "opt_inet.h" 192 193 #include <sys/param.h> 194 #include <sys/systm.h> 195 #include <sys/mbuf.h> 196 #include <sys/syslog.h> 197 #include <sys/socket.h> 198 #include <sys/device.h> 199 #include <sys/malloc.h> 200 #include <sys/ioctl.h> 201 #include <sys/errno.h> 202 203 #include "rnd.h" 204 #if NRND > 0 205 #include <sys/rnd.h> 206 #endif 207 208 #include <net/if.h> 209 #include <net/if_ether.h> 210 #include <net/if_media.h> 211 #ifdef INET 212 #include <netinet/in.h> 213 #include <netinet/if_inarp.h> 214 #endif 215 216 #include "bpfilter.h" 217 #if NBPFILTER > 0 218 #include <net/bpf.h> 219 #include <net/bpfdesc.h> 220 #endif 221 222 #include <uvm/uvm_extern.h> 223 224 #include <machine/bus.h> 225 #include <machine/intr.h> 226 227 #include <dev/ic/cs89x0reg.h> 228 #include <dev/ic/cs89x0var.h> 229 230 #ifdef SHARK 231 #include <shark/shark/sequoia.h> 232 #endif 233 234 /* 235 * MACRO DEFINITIONS 236 */ 237 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */ 238 239 /* 240 * FUNCTION PROTOTYPES 241 */ 242 void cs_get_default_media __P((struct cs_softc *)); 243 int cs_get_params __P((struct cs_softc *)); 244 int cs_get_enaddr __P((struct cs_softc *)); 245 int cs_reset_chip __P((struct cs_softc *)); 246 void cs_reset __P((void *)); 247 int cs_ioctl __P((struct ifnet *, u_long, caddr_t)); 248 void cs_initChip __P((struct cs_softc *)); 249 void cs_buffer_event __P((struct cs_softc *, u_int16_t)); 250 void cs_transmit_event __P((struct cs_softc *, u_int16_t)); 251 void cs_receive_event __P((struct cs_softc *, u_int16_t)); 252 void cs_process_receive __P((struct cs_softc *)); 253 void cs_process_rx_early __P((struct cs_softc *)); 254 void cs_start_output __P((struct ifnet *)); 255 void cs_copy_tx_frame __P((struct cs_softc *, struct mbuf *)); 256 void cs_set_ladr_filt __P((struct cs_softc *, struct ethercom *)); 257 u_int16_t cs_hash_index __P((char *)); 258 void cs_counter_event __P((struct cs_softc *, u_int16_t)); 259 260 int cs_mediachange __P((struct ifnet *)); 261 void cs_mediastatus __P((struct ifnet *, struct ifmediareq *)); 262 263 static int cs_enable __P((struct cs_softc *)); 264 static void cs_disable __P((struct cs_softc *)); 265 static void cs_stop __P((struct ifnet *, int)); 266 static void cs_power __P((int, void *)); 267 268 /* 269 * GLOBAL DECLARATIONS 270 */ 271 272 /* 273 * Xmit-early table. 274 * 275 * To get better performance, we tell the chip to start packet 276 * transmission before the whole packet is copied to the chip. 277 * However, this can fail under load. When it fails, we back off 278 * to a safer setting for a little while. 279 * 280 * txcmd is the value of txcmd used to indicate when to start transmission. 281 * better is the next 'better' state in the table. 282 * better_count is the number of output packets before transition to the 283 * better state. 284 * worse is the next 'worse' state in the table. 285 * 286 * Transition to the next worse state happens automatically when a 287 * transmittion underrun occurs. 288 */ 289 struct cs_xmit_early { 290 u_int16_t txcmd; 291 int better; 292 int better_count; 293 int worse; 294 } cs_xmit_early_table[3] = { 295 { TX_CMD_START_381, 0, INT_MAX, 1, }, 296 { TX_CMD_START_1021, 0, 50000, 2, }, 297 { TX_CMD_START_ALL, 1, 5000, 2, }, 298 }; 299 300 int cs_default_media[] = { 301 IFM_ETHER|IFM_10_2, 302 IFM_ETHER|IFM_10_5, 303 IFM_ETHER|IFM_10_T, 304 IFM_ETHER|IFM_10_T|IFM_FDX, 305 }; 306 int cs_default_nmedia = sizeof(cs_default_media) / sizeof(cs_default_media[0]); 307 308 int 309 cs_attach(sc, enaddr, media, nmedia, defmedia) 310 struct cs_softc *sc; 311 u_int8_t *enaddr; 312 int *media, nmedia, defmedia; 313 { 314 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 315 const char *chipname, *medname; 316 u_int16_t reg; 317 int i; 318 319 /* Start out in IO mode */ 320 sc->sc_memorymode = FALSE; 321 322 /* make sure we're right */ 323 for (i = 0; i < 10000; i++) { 324 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 325 if (reg == EISA_NUM_CRYSTAL) { 326 break; 327 } 328 } 329 if (i == 10000) { 330 printf("%s: wrong id(0x%x)\n", sc->sc_dev.dv_xname, reg); 331 return 1; /* XXX should panic? */ 332 } 333 334 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID); 335 sc->sc_prodid = reg & PROD_ID_MASK; 336 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8; 337 338 switch (sc->sc_prodid) { 339 case PROD_ID_CS8900: 340 chipname = "CS8900"; 341 break; 342 case PROD_ID_CS8920: 343 chipname = "CS8920"; 344 break; 345 case PROD_ID_CS8920M: 346 chipname = "CS8920M"; 347 break; 348 default: 349 panic("cs_attach: impossible"); 350 } 351 352 /* 353 * the first thing to do is check that the mbuf cluster size is 354 * greater than the MTU for an ethernet frame. The code depends on 355 * this and to port this to a OS where this was not the case would 356 * not be straightforward. 357 * 358 * we need 1 byte spare because our 359 * packet read loop can overrun. 360 * and we may need pad bytes to align ip header. 361 */ 362 if (MCLBYTES < ETHER_MAX_LEN + 1 + 363 ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header)) { 364 printf("%s: MCLBYTES too small for Ethernet frame\n", 365 sc->sc_dev.dv_xname); 366 return 1; 367 } 368 369 /* Start out not transmitting */ 370 sc->sc_txbusy = FALSE; 371 372 /* Set up early transmit threshhold */ 373 sc->sc_xe_ent = 0; 374 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count; 375 376 /* Initialize ifnet structure. */ 377 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 378 ifp->if_softc = sc; 379 ifp->if_start = cs_start_output; 380 ifp->if_init = cs_init; 381 ifp->if_ioctl = cs_ioctl; 382 ifp->if_stop = cs_stop; 383 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 384 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | 385 IFF_BROADCAST | IFF_MULTICAST; 386 IFQ_SET_READY(&ifp->if_snd); 387 388 /* Initialize ifmedia structures. */ 389 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus); 390 391 if (media != NULL) { 392 for (i = 0; i < nmedia; i++) 393 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 394 ifmedia_set(&sc->sc_media, defmedia); 395 } else { 396 for (i = 0; i < cs_default_nmedia; i++) 397 ifmedia_add(&sc->sc_media, cs_default_media[i], 398 0, NULL); 399 cs_get_default_media(sc); 400 } 401 402 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 403 /* Get parameters from the EEPROM */ 404 if (cs_get_params(sc) == CS_ERROR) { 405 printf("%s: unable to get settings from EEPROM\n", 406 sc->sc_dev.dv_xname); 407 return 1; 408 } 409 } 410 411 if (enaddr != NULL) 412 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 413 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 414 /* Get and store the Ethernet address */ 415 if (cs_get_enaddr(sc) == CS_ERROR) { 416 printf("%s: unable to read Ethernet address\n", 417 sc->sc_dev.dv_xname); 418 return 1; 419 } 420 } else { 421 printf("%s: no Ethernet address!\n", sc->sc_dev.dv_xname); 422 return 1; 423 } 424 425 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) { 426 case IFM_10_2: 427 medname = "BNC"; 428 break; 429 case IFM_10_5: 430 medname = "AUI"; 431 break; 432 case IFM_10_T: 433 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 434 medname = "UTP <full-duplex>"; 435 else 436 medname = "UTP"; 437 break; 438 default: 439 panic("cs_attach: impossible"); 440 } 441 printf("%s: %s rev. %c, address %s, media %s\n", sc->sc_dev.dv_xname, 442 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr), 443 medname); 444 445 if (sc->sc_dma_attach) 446 (*sc->sc_dma_attach)(sc); 447 448 sc->sc_sh = shutdownhook_establish(cs_reset, sc); 449 if (sc->sc_sh == NULL) { 450 printf("%s: unable to establish shutdownhook\n", 451 sc->sc_dev.dv_xname); 452 cs_detach(sc); 453 return 1; 454 } 455 456 /* Attach the interface. */ 457 if_attach(ifp); 458 ether_ifattach(ifp, sc->sc_enaddr); 459 460 #if NRND > 0 461 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 462 RND_TYPE_NET, 0); 463 #endif 464 sc->sc_cfgflags |= CFGFLG_ATTACHED; 465 466 /* Reset the chip */ 467 if (cs_reset_chip(sc) == CS_ERROR) { 468 printf("%s: reset failed\n", sc->sc_dev.dv_xname); 469 cs_detach(sc); 470 return 1; 471 } 472 473 sc->sc_powerhook = powerhook_establish(cs_power, sc); 474 if (sc->sc_powerhook == 0) 475 printf("%s: warning: powerhook_establish failed\n", 476 sc->sc_dev.dv_xname); 477 478 return 0; 479 } 480 481 int 482 cs_detach(sc) 483 struct cs_softc *sc; 484 { 485 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 486 487 if (sc->sc_powerhook) { 488 powerhook_disestablish(sc->sc_powerhook); 489 sc->sc_powerhook = 0; 490 } 491 492 if (sc->sc_cfgflags & CFGFLG_ATTACHED) { 493 #if NRND > 0 494 rnd_detach_source(&sc->rnd_source); 495 #endif 496 ether_ifdetach(ifp); 497 if_detach(ifp); 498 sc->sc_cfgflags &= ~CFGFLG_ATTACHED; 499 } 500 501 if (sc->sc_sh != NULL) 502 shutdownhook_disestablish(sc->sc_sh); 503 504 #if 0 505 /* 506 * XXX not necessary 507 */ 508 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) { 509 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, sc->sc_dmasize); 510 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, sc->sc_dmasize); 511 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq); 512 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE; 513 } 514 #endif 515 516 return 0; 517 } 518 519 void 520 cs_get_default_media(sc) 521 struct cs_softc *sc; 522 { 523 u_int16_t adp_cfg, xmit_ctl; 524 525 if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 526 printf("%s: cs_get_default_media: EEPROM missing or bad\n", 527 sc->sc_dev.dv_xname); 528 goto fakeit; 529 } 530 531 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ADPTR_CFG, 532 &adp_cfg) == CS_ERROR) { 533 printf("%s: unable to read adapter config from EEPROM\n", 534 sc->sc_dev.dv_xname); 535 goto fakeit; 536 } 537 538 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_XMIT_CTL, 539 &xmit_ctl) == CS_ERROR) { 540 printf("%s: unable to read transmit control from EEPROM\n", 541 sc->sc_dev.dv_xname); 542 goto fakeit; 543 } 544 545 switch (adp_cfg & ADPTR_CFG_MEDIA) { 546 case ADPTR_CFG_AUI: 547 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5); 548 break; 549 case ADPTR_CFG_10BASE2: 550 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2); 551 break; 552 case ADPTR_CFG_10BASET: 553 default: 554 if (xmit_ctl & XMIT_CTL_FDX) 555 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX); 556 else 557 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 558 break; 559 } 560 return; 561 562 fakeit: 563 printf("%s: WARNING: default media setting may be inaccurate\n", 564 sc->sc_dev.dv_xname); 565 /* XXX Arbitrary... */ 566 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 567 } 568 569 int 570 cs_get_params(sc) 571 struct cs_softc *sc; 572 { 573 u_int16_t isaConfig; 574 u_int16_t adapterConfig; 575 576 if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 577 printf("%s: cs_get_params: EEPROM missing or bad\n", 578 sc->sc_dev.dv_xname); 579 return (CS_ERROR); 580 } 581 582 /* Get ISA configuration from the EEPROM */ 583 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ISA_CFG, 584 &isaConfig) == CS_ERROR) 585 goto eeprom_bad; 586 587 /* Get adapter configuration from the EEPROM */ 588 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ADPTR_CFG, 589 &adapterConfig) == CS_ERROR) 590 goto eeprom_bad; 591 592 /* Copy the USE_SA flag */ 593 if (isaConfig & ISA_CFG_USE_SA) 594 sc->sc_cfgflags |= CFGFLG_USE_SA; 595 596 /* Copy the IO Channel Ready flag */ 597 if (isaConfig & ISA_CFG_IOCHRDY) 598 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 599 600 /* Copy the DC/DC Polarity flag */ 601 if (adapterConfig & ADPTR_CFG_DCDC_POL) 602 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 603 604 return (CS_OK); 605 606 eeprom_bad: 607 printf("%s: cs_get_params: unable to read from EEPROM\n", 608 sc->sc_dev.dv_xname); 609 return (CS_ERROR); 610 } 611 612 int 613 cs_get_enaddr(sc) 614 struct cs_softc *sc; 615 { 616 u_int16_t *myea; 617 618 if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 619 printf("%s: cs_get_enaddr: EEPROM missing or bad\n", 620 sc->sc_dev.dv_xname); 621 return (CS_ERROR); 622 } 623 624 myea = (u_int16_t *)sc->sc_enaddr; 625 626 /* Get Ethernet address from the EEPROM */ 627 /* XXX this will likely lose on a big-endian machine. -- cgd */ 628 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_H, 629 &myea[0]) == CS_ERROR) 630 goto eeprom_bad; 631 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_M, 632 &myea[1]) == CS_ERROR) 633 goto eeprom_bad; 634 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_L, 635 &myea[2]) == CS_ERROR) 636 goto eeprom_bad; 637 638 return (CS_OK); 639 640 eeprom_bad: 641 printf("%s: cs_get_enaddr: unable to read from EEPROM\n", 642 sc->sc_dev.dv_xname); 643 return (CS_ERROR); 644 } 645 646 int 647 cs_reset_chip(sc) 648 struct cs_softc *sc; 649 { 650 int intState; 651 int x; 652 653 /* Disable interrupts at the CPU so reset command is atomic */ 654 intState = splnet(); 655 656 /* 657 * We are now resetting the chip 658 * 659 * A spurious interrupt is generated by the chip when it is reset. This 660 * variable informs the interrupt handler to ignore this interrupt. 661 */ 662 sc->sc_resetting = TRUE; 663 664 /* Issue a reset command to the chip */ 665 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET); 666 667 /* Re-enable interrupts at the CPU */ 668 splx(intState); 669 670 /* The chip is always in IO mode after a reset */ 671 sc->sc_memorymode = FALSE; 672 673 /* If transmission was in progress, it is not now */ 674 sc->sc_txbusy = FALSE; 675 676 /* 677 * there was a delay(125); here, but it seems uneccesary 125 usec is 678 * 1/8000 of a second, not 1/8 of a second. the data sheet advises 679 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below 680 * should be sufficient. 681 */ 682 683 /* Transition SBHE to switch chip from 8-bit to 16-bit */ 684 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 0); 685 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 1); 686 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 0); 687 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 1); 688 689 /* Wait until the EEPROM is not busy */ 690 for (x = 0; x < MAXLOOP; x++) { 691 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY)) 692 break; 693 } 694 695 if (x == MAXLOOP) 696 return CS_ERROR; 697 698 /* Wait until initialization is done */ 699 for (x = 0; x < MAXLOOP; x++) { 700 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE) 701 break; 702 } 703 704 if (x == MAXLOOP) 705 return CS_ERROR; 706 707 /* Reset is no longer in progress */ 708 sc->sc_resetting = FALSE; 709 710 return CS_OK; 711 } 712 713 int 714 cs_verify_eeprom(iot, ioh) 715 bus_space_tag_t iot; 716 bus_space_handle_t ioh; 717 { 718 u_int16_t self_status; 719 720 /* Verify that the EEPROM is present and OK */ 721 self_status = CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST); 722 if (((self_status & SELF_ST_EEP_PRES) && 723 (self_status & SELF_ST_EEP_OK)) == 0) 724 return (CS_ERROR); 725 726 return (CS_OK); 727 } 728 729 int 730 cs_read_eeprom(iot, ioh, offset, pValue) 731 bus_space_tag_t iot; 732 bus_space_handle_t ioh; 733 int offset; 734 u_int16_t *pValue; 735 { 736 int x; 737 738 /* Ensure that the EEPROM is not busy */ 739 for (x = 0; x < MAXLOOP; x++) { 740 if (!(CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST) & 741 SELF_ST_SI_BUSY)) 742 break; 743 } 744 745 if (x == MAXLOOP) 746 return (CS_ERROR); 747 748 /* Issue the command to read the offset within the EEPROM */ 749 CS_WRITE_PACKET_PAGE_IO(iot, ioh, PKTPG_EEPROM_CMD, 750 offset | EEPROM_CMD_READ); 751 752 /* Wait until the command is completed */ 753 for (x = 0; x < MAXLOOP; x++) { 754 if (!(CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST) & 755 SELF_ST_SI_BUSY)) 756 break; 757 } 758 759 if (x == MAXLOOP) 760 return (CS_ERROR); 761 762 /* Get the EEPROM data from the EEPROM Data register */ 763 *pValue = CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_EEPROM_DATA); 764 765 return (CS_OK); 766 } 767 768 void 769 cs_initChip(sc) 770 struct cs_softc *sc; 771 { 772 u_int16_t busCtl; 773 u_int16_t selfCtl; 774 u_int16_t *myea; 775 u_int16_t isaId; 776 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media); 777 778 /* Disable reception and transmission of frames */ 779 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 780 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) & 781 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON); 782 783 /* Disable interrupt at the chip */ 784 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 785 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL); 786 787 /* If IOCHRDY is enabled then clear the bit in the busCtl register */ 788 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL); 789 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) { 790 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 791 busCtl & ~BUS_CTL_IOCHRDY); 792 } else { 793 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 794 busCtl | BUS_CTL_IOCHRDY); 795 } 796 797 /* Set the Line Control register to match the media type */ 798 if (media == IFM_10_T) 799 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET); 800 else 801 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY); 802 803 /* 804 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to 805 * enable the DC/DC converter 806 */ 807 selfCtl = SELF_CTL_HC1E; 808 809 /* If the media type is 10Base2 */ 810 if (media == IFM_10_2) { 811 /* 812 * Enable the DC/DC converter if it has a low enable. 813 */ 814 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0) 815 /* 816 * Set the HCB1 bit, which causes the HC1 pin to go 817 * low. 818 */ 819 selfCtl |= SELF_CTL_HCB1; 820 } else { /* Media type is 10BaseT or AUI */ 821 /* 822 * Disable the DC/DC converter if it has a high enable. 823 */ 824 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) { 825 /* 826 * Set the HCB1 bit, which causes the HC1 pin to go 827 * low. 828 */ 829 selfCtl |= SELF_CTL_HCB1; 830 } 831 } 832 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl); 833 834 /* enable normal link pulse */ 835 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M) 836 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE); 837 838 /* Enable full-duplex, if appropriate */ 839 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 840 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX); 841 842 /* RX_CTL set in cs_set_ladr_filt(), below */ 843 844 /* enable all transmission interrupts */ 845 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE); 846 847 /* Accept all receive interrupts */ 848 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE); 849 850 /* 851 * Configure Operational Modes 852 * 853 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this is 854 * a better way to do it because the card has a counter which can be 855 * read to update the RX_MISS counter. This saves many interupts. 856 * 857 * I have turned on the tx and rx overflow interupts to counter using 858 * the receive miss interrupt. This is a better estimate of errors 859 * and requires lower system overhead. 860 */ 861 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE | 862 BUF_CFG_RX_DMA_IE); 863 864 if (sc->sc_dma_chipinit) 865 (*sc->sc_dma_chipinit)(sc); 866 867 /* If memory mode is enabled */ 868 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) { 869 /* If external logic is present for address decoding */ 870 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) { 871 /* 872 * Program the external logic to decode address bits 873 * SA20-SA23 874 */ 875 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD, 876 ((sc->sc_pktpgaddr & 0xffffff) >> 20) | 877 EEPROM_CMD_ELSEL); 878 } 879 880 /* 881 * Write the packet page base physical address to the memory 882 * base register. 883 */ 884 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0, 885 sc->sc_pktpgaddr & 0xFFFF); 886 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2, 887 sc->sc_pktpgaddr >> 16); 888 busCtl = BUS_CTL_MEM_MODE; 889 890 /* tell the chip to read the addresses off the SA pins */ 891 if (sc->sc_cfgflags & CFGFLG_USE_SA) { 892 busCtl |= BUS_CTL_USE_SA; 893 } 894 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 895 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl); 896 897 /* We are in memory mode now! */ 898 sc->sc_memorymode = TRUE; 899 900 /* 901 * wait here (10ms) for the chip to swap over. this is the 902 * maximum time that this could take. 903 */ 904 delay(10000); 905 906 /* Verify that we can read from the chip */ 907 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 908 909 /* 910 * As a last minute sanity check before actually using mapped 911 * memory we verify that we can read the isa number from the 912 * chip in memory mode. 913 */ 914 if (isaId != EISA_NUM_CRYSTAL) { 915 printf("%s: failed to enable memory mode\n", 916 sc->sc_dev.dv_xname); 917 sc->sc_memorymode = FALSE; 918 } else { 919 /* 920 * we are in memory mode so if we aren't using DMA, 921 * then program the chip to interrupt early. 922 */ 923 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) { 924 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 925 BUF_CFG_RX_DEST_IE | 926 BUF_CFG_RX_MISS_OVER_IE | 927 BUF_CFG_TX_COL_OVER_IE); 928 } 929 } 930 931 } 932 933 /* Put Ethernet address into the Individual Address register */ 934 myea = (u_int16_t *)sc->sc_enaddr; 935 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 0, myea[0]); 936 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 2, myea[1]); 937 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 4, myea[2]); 938 939 if (sc->sc_irq != -1) { 940 /* Set the interrupt level in the chip */ 941 if (sc->sc_prodid == PROD_ID_CS8900) { 942 if (sc->sc_irq == 5) { 943 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3); 944 } else { 945 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, (sc->sc_irq) - 10); 946 } 947 } 948 else { /* CS8920 */ 949 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, sc->sc_irq); 950 } 951 } 952 953 /* write the multicast mask to the address filter register */ 954 cs_set_ladr_filt(sc, &sc->sc_ethercom); 955 956 /* Enable reception and transmission of frames */ 957 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 958 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) | 959 LINE_CTL_RX_ON | LINE_CTL_TX_ON); 960 961 /* Enable interrupt at the chip */ 962 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 963 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL); 964 } 965 966 int 967 cs_init(ifp) 968 struct ifnet *ifp; 969 { 970 int intState; 971 int error = CS_OK; 972 struct cs_softc *sc = ifp->if_softc; 973 974 if (cs_enable(sc)) 975 goto out; 976 977 cs_stop(ifp, 0); 978 979 intState = splnet(); 980 981 #if 0 982 /* Mark the interface as down */ 983 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING); 984 #endif 985 986 #ifdef CS_DEBUG 987 /* Enable debugging */ 988 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG; 989 #endif 990 991 /* Reset the chip */ 992 if ((error = cs_reset_chip(sc)) == CS_OK) { 993 /* Initialize the chip */ 994 cs_initChip(sc); 995 996 /* Mark the interface as running */ 997 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 998 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 999 sc->sc_ethercom.ec_if.if_timer = 0; 1000 1001 /* Assume we have carrier until we are told otherwise. */ 1002 sc->sc_carrier = 1; 1003 } else { 1004 printf("%s: unable to reset chip\n", sc->sc_dev.dv_xname); 1005 } 1006 1007 splx(intState); 1008 out: 1009 if (error == CS_OK) 1010 return 0; 1011 return EIO; 1012 } 1013 1014 void 1015 cs_set_ladr_filt(sc, ec) 1016 struct cs_softc *sc; 1017 struct ethercom *ec; 1018 { 1019 struct ifnet *ifp = &ec->ec_if; 1020 struct ether_multi *enm; 1021 struct ether_multistep step; 1022 u_int16_t af[4]; 1023 u_int16_t port, mask, index; 1024 1025 /* 1026 * Set up multicast address filter by passing all multicast addresses 1027 * through a crc generator, and then using the high order 6 bits as an 1028 * index into the 64 bit logical address filter. The high order bit 1029 * selects the word, while the rest of the bits select the bit within 1030 * the word. 1031 */ 1032 if (ifp->if_flags & IFF_PROMISC) { 1033 /* accept all valid frames. */ 1034 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1035 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A | 1036 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1037 ifp->if_flags |= IFF_ALLMULTI; 1038 return; 1039 } 1040 1041 /* 1042 * accept frames if a. crc valid, b. individual address match c. 1043 * broadcast address,and d. multicast addresses matched in the hash 1044 * filter 1045 */ 1046 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1047 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1048 1049 1050 /* 1051 * start off with all multicast flag clear, set it if we need to 1052 * later, otherwise we will leave it. 1053 */ 1054 ifp->if_flags &= ~IFF_ALLMULTI; 1055 af[0] = af[1] = af[2] = af[3] = 0x0000; 1056 1057 /* 1058 * Loop through all the multicast addresses unless we get a range of 1059 * addresses, in which case we will just accept all packets. 1060 * Justification for this is given in the next comment. 1061 */ 1062 ETHER_FIRST_MULTI(step, ec, enm); 1063 while (enm != NULL) { 1064 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1065 sizeof enm->enm_addrlo)) { 1066 /* 1067 * We must listen to a range of multicast addresses. 1068 * For now, just accept all multicasts, rather than 1069 * trying to set only those filter bits needed to match 1070 * the range. (At this time, the only use of address 1071 * ranges is for IP multicast routing, for which the 1072 * range is big enough to require all bits set.) 1073 */ 1074 ifp->if_flags |= IFF_ALLMULTI; 1075 af[0] = af[1] = af[2] = af[3] = 0xffff; 1076 break; 1077 } else { 1078 /* 1079 * we have got an individual address so just set that 1080 * bit. 1081 */ 1082 index = cs_hash_index(enm->enm_addrlo); 1083 1084 /* Set the bit the Logical address filter. */ 1085 port = (u_int16_t) (index >> 4); 1086 mask = (u_int16_t) (1 << (index & 0xf)); 1087 af[port] |= mask; 1088 1089 ETHER_NEXT_MULTI(step, enm); 1090 } 1091 } 1092 1093 /* now program the chip with the addresses */ 1094 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]); 1095 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]); 1096 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]); 1097 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]); 1098 return; 1099 } 1100 1101 u_int16_t 1102 cs_hash_index(addr) 1103 char *addr; 1104 { 1105 u_int POLY = 0x04c11db6; 1106 u_int crc_value = 0xffffffff; 1107 u_int16_t hash_code = 0; 1108 int i; 1109 u_int current_bit; 1110 char current_byte = *addr; 1111 u_int cur_crc_high; 1112 1113 for (i = 0; i < 6; i++) { 1114 current_byte = *addr; 1115 addr++; 1116 1117 for (current_bit = 8; current_bit; current_bit--) { 1118 cur_crc_high = crc_value >> 31; 1119 crc_value <<= 1; 1120 if (cur_crc_high ^ (current_byte & 0x01)) { 1121 crc_value ^= POLY; 1122 crc_value |= 0x00000001; 1123 } 1124 current_byte >>= 1; 1125 } 1126 } 1127 1128 /* 1129 * The hash code is the 6 least significant bits of the CRC 1130 * in the reverse order: CRC[0] = hash[5],CRC[1] = hash[4],etc. 1131 */ 1132 for (i = 0; i < 6; i++) { 1133 hash_code = (u_int16_t) ((hash_code << 1) | 1134 (u_int16_t) ((crc_value >> i) & 0x00000001)); 1135 } 1136 1137 return hash_code; 1138 } 1139 1140 void 1141 cs_reset(arg) 1142 void *arg; 1143 { 1144 struct cs_softc *sc = arg; 1145 1146 /* Mark the interface as down */ 1147 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1148 1149 /* Reset the chip */ 1150 cs_reset_chip(sc); 1151 } 1152 1153 int 1154 cs_ioctl(ifp, cmd, data) 1155 struct ifnet *ifp; 1156 u_long cmd; 1157 caddr_t data; 1158 { 1159 struct cs_softc *sc = ifp->if_softc; 1160 struct ifreq *ifr = (struct ifreq *) data; 1161 int state; 1162 int result; 1163 1164 state = splnet(); 1165 1166 result = 0; /* only set if something goes wrong */ 1167 1168 switch (cmd) { 1169 case SIOCGIFMEDIA: 1170 case SIOCSIFMEDIA: 1171 result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1172 break; 1173 1174 default: 1175 result = ether_ioctl(ifp, cmd, data); 1176 if (result == ENETRESET) { 1177 if (CS_IS_ENABLED(sc)) { 1178 /* 1179 * Multicast list has changed. Set the 1180 * hardware filter accordingly. 1181 */ 1182 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1183 } 1184 result = 0; 1185 } 1186 break; 1187 } 1188 1189 splx(state); 1190 1191 return result; 1192 } 1193 1194 int 1195 cs_mediachange(ifp) 1196 struct ifnet *ifp; 1197 { 1198 1199 /* 1200 * Current media is already set up. Just reset the interface 1201 * to let the new value take hold. 1202 */ 1203 cs_init(ifp); 1204 return (0); 1205 } 1206 1207 void 1208 cs_mediastatus(ifp, ifmr) 1209 struct ifnet *ifp; 1210 struct ifmediareq *ifmr; 1211 { 1212 struct cs_softc *sc = ifp->if_softc; 1213 1214 /* 1215 * The currently selected media is always the active media. 1216 */ 1217 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media; 1218 1219 if (ifp->if_flags & IFF_UP) { 1220 /* Interface up, status is valid. */ 1221 ifmr->ifm_status = IFM_AVALID | 1222 (sc->sc_carrier ? IFM_ACTIVE : 0); 1223 } 1224 else ifmr->ifm_status = 0; 1225 } 1226 1227 int 1228 cs_intr(arg) 1229 void *arg; 1230 { 1231 struct cs_softc *sc = arg; 1232 u_int16_t Event; 1233 #if NRND > 0 1234 u_int16_t rndEvent; 1235 #endif 1236 1237 /* Ignore any interrupts that happen while the chip is being reset */ 1238 if (sc->sc_resetting) { 1239 printf("%s: cs_intr: reset in progress\n", 1240 sc->sc_dev.dv_xname); 1241 return 1; 1242 } 1243 1244 /* Read an event from the Interrupt Status Queue */ 1245 if (sc->sc_memorymode) 1246 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1247 else 1248 Event = CS_READ_PORT(sc, PORT_ISQ); 1249 1250 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff) 1251 return 0; /* not ours */ 1252 1253 #if NRND > 0 1254 rndEvent = Event; 1255 #endif 1256 1257 /* Process all the events in the Interrupt Status Queue */ 1258 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) { 1259 /* Dispatch to an event handler based on the register number */ 1260 switch (Event & REG_NUM_MASK) { 1261 case REG_NUM_RX_EVENT: 1262 cs_receive_event(sc, Event); 1263 break; 1264 case REG_NUM_TX_EVENT: 1265 cs_transmit_event(sc, Event); 1266 break; 1267 case REG_NUM_BUF_EVENT: 1268 cs_buffer_event(sc, Event); 1269 break; 1270 case REG_NUM_TX_COL: 1271 case REG_NUM_RX_MISS: 1272 cs_counter_event(sc, Event); 1273 break; 1274 default: 1275 printf("%s: unknown interrupt event 0x%x\n", 1276 sc->sc_dev.dv_xname, Event); 1277 break; 1278 } 1279 1280 /* Read another event from the Interrupt Status Queue */ 1281 if (sc->sc_memorymode) 1282 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1283 else 1284 Event = CS_READ_PORT(sc, PORT_ISQ); 1285 } 1286 1287 /* have handled the interupt */ 1288 #if NRND > 0 1289 rnd_add_uint32(&sc->rnd_source, rndEvent); 1290 #endif 1291 return 1; 1292 } 1293 1294 void 1295 cs_counter_event(sc, cntEvent) 1296 struct cs_softc *sc; 1297 u_int16_t cntEvent; 1298 { 1299 struct ifnet *ifp; 1300 u_int16_t errorCount; 1301 1302 ifp = &sc->sc_ethercom.ec_if; 1303 1304 switch (cntEvent & REG_NUM_MASK) { 1305 case REG_NUM_TX_COL: 1306 /* 1307 * the count should be read before an overflow occurs. 1308 */ 1309 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL); 1310 /* 1311 * the tramsit event routine always checks the number of 1312 * collisions for any packet so we don't increment any 1313 * counters here, as they should already have been 1314 * considered. 1315 */ 1316 break; 1317 case REG_NUM_RX_MISS: 1318 /* 1319 * the count should be read before an overflow occurs. 1320 */ 1321 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS); 1322 /* 1323 * Increment the input error count, the first 6bits are the 1324 * register id. 1325 */ 1326 ifp->if_ierrors += ((errorCount & 0xffC0) >> 6); 1327 break; 1328 default: 1329 /* do nothing */ 1330 break; 1331 } 1332 } 1333 1334 void 1335 cs_buffer_event(sc, bufEvent) 1336 struct cs_softc *sc; 1337 u_int16_t bufEvent; 1338 { 1339 struct ifnet *ifp; 1340 1341 ifp = &sc->sc_ethercom.ec_if; 1342 1343 /* 1344 * multiple events can be in the buffer event register at one time so 1345 * a standard switch statement will not suffice, here every event 1346 * must be checked. 1347 */ 1348 1349 /* 1350 * if 128 bits have been rxed by the time we get here, the dest event 1351 * will be cleared and 128 event will be set. 1352 */ 1353 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) { 1354 cs_process_rx_early(sc); 1355 } 1356 1357 if (bufEvent & BUF_EVENT_RX_DMA) { 1358 /* process the receive data */ 1359 if (sc->sc_dma_process_rx) 1360 (*sc->sc_dma_process_rx)(sc); 1361 else 1362 /* should panic? */ 1363 printf("%s: unexpected dma event\n", sc->sc_dev.dv_xname); 1364 } 1365 1366 if (bufEvent & BUF_EVENT_TX_UNDR) { 1367 #if 0 1368 /* 1369 * This can happen occasionally, and it's not worth worrying 1370 * about. 1371 */ 1372 printf("%s: transmit underrun (%d -> %d)\n", 1373 sc->sc_dev.dv_xname, sc->sc_xe_ent, 1374 cs_xmit_early_table[sc->sc_xe_ent].worse); 1375 #endif 1376 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse; 1377 sc->sc_xe_togo = 1378 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1379 1380 /* had an underrun, transmit is finished */ 1381 sc->sc_txbusy = FALSE; 1382 } 1383 1384 if (bufEvent & BUF_EVENT_SW_INT) { 1385 printf("%s: software initiated interrupt\n", 1386 sc->sc_dev.dv_xname); 1387 } 1388 } 1389 1390 void 1391 cs_transmit_event(sc, txEvent) 1392 struct cs_softc *sc; 1393 u_int16_t txEvent; 1394 { 1395 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1396 1397 /* If there were any errors transmitting this frame */ 1398 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | TX_EVENT_OUT_WIN | 1399 TX_EVENT_JABBER | TX_EVENT_16_COLL)) { 1400 /* Increment the output error count */ 1401 ifp->if_oerrors++; 1402 1403 /* Note carrier loss. */ 1404 if (txEvent & TX_EVENT_LOSS_CRS) 1405 sc->sc_carrier = 0; 1406 1407 /* If debugging is enabled then log error messages */ 1408 if (ifp->if_flags & IFF_DEBUG) { 1409 if (txEvent & TX_EVENT_LOSS_CRS) { 1410 printf("%s: lost carrier\n", 1411 sc->sc_dev.dv_xname); 1412 } 1413 if (txEvent & TX_EVENT_SQE_ERR) { 1414 printf("%s: SQE error\n", 1415 sc->sc_dev.dv_xname); 1416 } 1417 if (txEvent & TX_EVENT_OUT_WIN) { 1418 printf("%s: out-of-window collision\n", 1419 sc->sc_dev.dv_xname); 1420 } 1421 if (txEvent & TX_EVENT_JABBER) { 1422 printf("%s: jabber\n", sc->sc_dev.dv_xname); 1423 } 1424 if (txEvent & TX_EVENT_16_COLL) { 1425 printf("%s: 16 collisions\n", 1426 sc->sc_dev.dv_xname); 1427 } 1428 } 1429 } 1430 else { 1431 /* Transmission successful, carrier is up. */ 1432 sc->sc_carrier = 1; 1433 #ifdef SHARK 1434 ledNetActive(); 1435 #endif 1436 } 1437 1438 /* Add the number of collisions for this frame */ 1439 if (txEvent & TX_EVENT_16_COLL) { 1440 ifp->if_collisions += 16; 1441 } else { 1442 ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11); 1443 } 1444 1445 ifp->if_opackets++; 1446 1447 /* Transmission is no longer in progress */ 1448 sc->sc_txbusy = FALSE; 1449 1450 /* If there is more to transmit */ 1451 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 1452 /* Start the next transmission */ 1453 cs_start_output(ifp); 1454 } 1455 } 1456 1457 void 1458 cs_print_rx_errors(sc, rxEvent) 1459 struct cs_softc *sc; 1460 u_int16_t rxEvent; 1461 { 1462 1463 if (rxEvent & RX_EVENT_RUNT) 1464 printf("%s: runt\n", sc->sc_dev.dv_xname); 1465 1466 if (rxEvent & RX_EVENT_X_DATA) 1467 printf("%s: extra data\n", sc->sc_dev.dv_xname); 1468 1469 if (rxEvent & RX_EVENT_CRC_ERR) { 1470 if (rxEvent & RX_EVENT_DRIBBLE) 1471 printf("%s: alignment error\n", sc->sc_dev.dv_xname); 1472 else 1473 printf("%s: CRC error\n", sc->sc_dev.dv_xname); 1474 } else { 1475 if (rxEvent & RX_EVENT_DRIBBLE) 1476 printf("%s: dribble bits\n", sc->sc_dev.dv_xname); 1477 } 1478 } 1479 1480 void 1481 cs_receive_event(sc, rxEvent) 1482 struct cs_softc *sc; 1483 u_int16_t rxEvent; 1484 { 1485 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1486 1487 /* If the frame was not received OK */ 1488 if (!(rxEvent & RX_EVENT_RX_OK)) { 1489 /* Increment the input error count */ 1490 ifp->if_ierrors++; 1491 1492 /* 1493 * If debugging is enabled then log error messages. 1494 */ 1495 if (ifp->if_flags & IFF_DEBUG) { 1496 if (rxEvent != REG_NUM_RX_EVENT) { 1497 cs_print_rx_errors(sc, rxEvent); 1498 1499 /* 1500 * Must read the length of all received 1501 * frames 1502 */ 1503 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1504 1505 /* Skip the received frame */ 1506 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1507 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | 1508 RX_CFG_SKIP); 1509 } else { 1510 printf("%s: implied skip\n", 1511 sc->sc_dev.dv_xname); 1512 } 1513 } 1514 } else { 1515 /* 1516 * process the received frame and pass it up to the upper 1517 * layers. 1518 */ 1519 cs_process_receive(sc); 1520 } 1521 } 1522 1523 void 1524 cs_ether_input(sc, m) 1525 struct cs_softc *sc; 1526 struct mbuf *m; 1527 { 1528 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1529 1530 ifp->if_ipackets++; 1531 1532 #if NBPFILTER > 0 1533 /* 1534 * Check if there's a BPF listener on this interface. 1535 * If so, hand off the raw packet to BPF. 1536 */ 1537 if (ifp->if_bpf) 1538 bpf_mtap(ifp->if_bpf, m); 1539 #endif 1540 1541 /* Pass the packet up. */ 1542 (*ifp->if_input)(ifp, m); 1543 } 1544 1545 void 1546 cs_process_receive(sc) 1547 struct cs_softc *sc; 1548 { 1549 struct ifnet *ifp; 1550 struct mbuf *m; 1551 int totlen; 1552 u_int16_t *pBuff, *pBuffLimit; 1553 int pad; 1554 unsigned int frameOffset; 1555 1556 #ifdef SHARK 1557 ledNetActive(); 1558 #endif 1559 1560 ifp = &sc->sc_ethercom.ec_if; 1561 1562 /* Received a packet; carrier is up. */ 1563 sc->sc_carrier = 1; 1564 1565 if (sc->sc_memorymode) { 1566 /* Initialize the frame offset */ 1567 frameOffset = PKTPG_RX_LENGTH; 1568 1569 /* Get the length of the received frame */ 1570 totlen = CS_READ_PACKET_PAGE(sc, frameOffset); 1571 frameOffset += 2; 1572 } 1573 else { 1574 /* drop status */ 1575 CS_READ_PORT(sc, PORT_RXTX_DATA); 1576 1577 /* Get the length of the received frame */ 1578 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA); 1579 } 1580 1581 if (totlen > ETHER_MAX_LEN) { 1582 printf("%s: invalid packet length\n", sc->sc_dev.dv_xname); 1583 1584 /* skip the received frame */ 1585 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1586 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1587 return; 1588 } 1589 1590 MGETHDR(m, M_DONTWAIT, MT_DATA); 1591 if (m == 0) { 1592 printf("%s: cs_process_receive: unable to allocate mbuf\n", 1593 sc->sc_dev.dv_xname); 1594 ifp->if_ierrors++; 1595 /* 1596 * couldn't allocate an mbuf so things are not good, may as 1597 * well drop the packet I think. 1598 * 1599 * have already read the length so we should be right to skip 1600 * the packet. 1601 */ 1602 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1603 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1604 return; 1605 } 1606 m->m_pkthdr.rcvif = ifp; 1607 m->m_pkthdr.len = totlen; 1608 1609 /* number of bytes to align ip header on word boundary for ipintr */ 1610 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1611 1612 /* 1613 * alloc mbuf cluster if we need. 1614 * we need 1 byte spare because following 1615 * packet read loop can overrun. 1616 */ 1617 if (totlen + pad + 1 > MHLEN) { 1618 MCLGET(m, M_DONTWAIT); 1619 if ((m->m_flags & M_EXT) == 0) { 1620 /* couldn't allocate an mbuf cluster */ 1621 printf("%s: cs_process_receive: unable to allocate a cluster\n", 1622 sc->sc_dev.dv_xname); 1623 m_freem(m); 1624 1625 /* skip the received frame */ 1626 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1627 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1628 return; 1629 } 1630 } 1631 1632 /* align ip header on word boundary for ipintr */ 1633 m->m_data += pad; 1634 1635 m->m_len = totlen; 1636 pBuff = mtod(m, u_int16_t *); 1637 1638 /* now read the data from the chip */ 1639 if (sc->sc_memorymode) { 1640 pBuffLimit = pBuff + (totlen + 1) / 2; /* don't want to go over */ 1641 while (pBuff < pBuffLimit) { 1642 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1643 frameOffset += 2; 1644 } 1645 } 1646 else { 1647 bus_space_read_multi_2(sc->sc_iot, sc->sc_ioh, PORT_RXTX_DATA, 1648 pBuff, (totlen + 1)>>1); 1649 } 1650 1651 cs_ether_input(sc, m); 1652 } 1653 1654 void 1655 cs_process_rx_early(sc) 1656 struct cs_softc *sc; 1657 { 1658 struct ifnet *ifp; 1659 struct mbuf *m; 1660 u_int16_t frameCount, oldFrameCount; 1661 u_int16_t rxEvent; 1662 u_int16_t *pBuff; 1663 int pad; 1664 unsigned int frameOffset; 1665 1666 1667 ifp = &sc->sc_ethercom.ec_if; 1668 1669 /* Initialize the frame offset */ 1670 frameOffset = PKTPG_RX_FRAME; 1671 frameCount = 0; 1672 1673 MGETHDR(m, M_DONTWAIT, MT_DATA); 1674 if (m == 0) { 1675 printf("%s: cs_process_rx_early: unable to allocate mbuf\n", 1676 sc->sc_dev.dv_xname); 1677 ifp->if_ierrors++; 1678 /* 1679 * couldn't allocate an mbuf so things are not good, may as 1680 * well drop the packet I think. 1681 * 1682 * have already read the length so we should be right to skip 1683 * the packet. 1684 */ 1685 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1686 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1687 return; 1688 } 1689 m->m_pkthdr.rcvif = ifp; 1690 /* 1691 * save processing by always using a mbuf cluster, guarenteed to fit 1692 * packet 1693 */ 1694 MCLGET(m, M_DONTWAIT); 1695 if ((m->m_flags & M_EXT) == 0) { 1696 /* couldn't allocate an mbuf cluster */ 1697 printf("%s: cs_process_rx_early: unable to allocate a cluster\n", 1698 sc->sc_dev.dv_xname); 1699 m_freem(m); 1700 /* skip the frame */ 1701 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1702 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1703 return; 1704 } 1705 1706 /* align ip header on word boundary for ipintr */ 1707 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1708 m->m_data += pad; 1709 1710 /* set up the buffer pointer to point to the data area */ 1711 pBuff = mtod(m, u_int16_t *); 1712 1713 /* 1714 * now read the frame byte counter until we have finished reading the 1715 * frame 1716 */ 1717 oldFrameCount = 0; 1718 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1719 while ((frameCount != 0) && (frameCount < MCLBYTES)) { 1720 for (; oldFrameCount < frameCount; oldFrameCount += 2) { 1721 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1722 frameOffset += 2; 1723 } 1724 1725 /* read the new count from the chip */ 1726 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1727 } 1728 1729 /* update the mbuf counts */ 1730 m->m_len = oldFrameCount; 1731 m->m_pkthdr.len = oldFrameCount; 1732 1733 /* now check the Rx Event register */ 1734 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1735 1736 if ((rxEvent & RX_EVENT_RX_OK) != 0) { 1737 /* 1738 * do an implied skip, it seems to be more reliable than a 1739 * forced skip. 1740 */ 1741 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS); 1742 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1743 1744 /* 1745 * now read the RX_EVENT register to perform an implied skip. 1746 */ 1747 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1748 1749 cs_ether_input(sc, m); 1750 } else { 1751 m_freem(m); 1752 ifp->if_ierrors++; 1753 } 1754 } 1755 1756 void 1757 cs_start_output(ifp) 1758 struct ifnet *ifp; 1759 { 1760 struct cs_softc *sc; 1761 struct mbuf *pMbuf; 1762 struct mbuf *pMbufChain; 1763 u_int16_t BusStatus; 1764 u_int16_t Length; 1765 int txLoop = 0; 1766 int dropout = 0; 1767 1768 sc = ifp->if_softc; 1769 1770 /* check that the interface is up and running */ 1771 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1772 return; 1773 } 1774 1775 /* Don't interrupt a transmission in progress */ 1776 if (sc->sc_txbusy) { 1777 return; 1778 } 1779 1780 /* this loop will only run through once if transmission is successful */ 1781 /* 1782 * While there are packets to transmit and a transmit is not in 1783 * progress 1784 */ 1785 while (sc->sc_txbusy == 0 && dropout == 0) { 1786 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain); 1787 if (pMbufChain == NULL) 1788 break; 1789 1790 #if NBPFILTER > 0 1791 /* 1792 * If BPF is listening on this interface, let it see the packet 1793 * before we commit it to the wire. 1794 */ 1795 if (ifp->if_bpf) 1796 bpf_mtap(ifp->if_bpf, pMbufChain); 1797 #endif 1798 1799 /* Find the total length of the data to transmit */ 1800 Length = 0; 1801 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next) 1802 Length += pMbuf->m_len; 1803 1804 do { 1805 /* 1806 * Request that the transmit be started after all 1807 * data has been copied 1808 * 1809 * In IO mode must write to the IO port not the packet 1810 * page address 1811 * 1812 * If this is changed to start transmission after a 1813 * small amount of data has been copied you tend to 1814 * get packet missed errors i think because the ISA 1815 * bus is too slow. Or possibly the copy routine is 1816 * not streamlined enough. 1817 */ 1818 if (sc->sc_memorymode) { 1819 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD, 1820 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1821 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length); 1822 } 1823 else { 1824 CS_WRITE_PORT(sc, PORT_TX_CMD, 1825 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1826 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length); 1827 } 1828 1829 /* 1830 * Adjust early-transmit machinery. 1831 */ 1832 if (--sc->sc_xe_togo == 0) { 1833 sc->sc_xe_ent = 1834 cs_xmit_early_table[sc->sc_xe_ent].better; 1835 sc->sc_xe_togo = 1836 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1837 } 1838 /* 1839 * Read the BusStatus register which indicates 1840 * success of the request 1841 */ 1842 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST); 1843 1844 /* 1845 * If there was an error in the transmit bid free the 1846 * mbuf and go on. This is presuming that mbuf is 1847 * corrupt. 1848 */ 1849 if (BusStatus & BUS_ST_TX_BID_ERR) { 1850 printf("%s: transmit bid error (too big)", 1851 sc->sc_dev.dv_xname); 1852 1853 /* Discard the bad mbuf chain */ 1854 m_freem(pMbufChain); 1855 sc->sc_ethercom.ec_if.if_oerrors++; 1856 1857 /* Loop up to transmit the next chain */ 1858 txLoop = 0; 1859 } else { 1860 if (BusStatus & BUS_ST_RDY4TXNOW) { 1861 /* 1862 * The chip is ready for transmission 1863 * now 1864 */ 1865 /* 1866 * Copy the frame to the chip to 1867 * start transmission 1868 */ 1869 cs_copy_tx_frame(sc, pMbufChain); 1870 1871 /* Free the mbuf chain */ 1872 m_freem(pMbufChain); 1873 1874 /* Transmission is now in progress */ 1875 sc->sc_txbusy = TRUE; 1876 txLoop = 0; 1877 } else { 1878 /* 1879 * if we get here we want to try 1880 * again with the same mbuf, until 1881 * the chip lets us transmit. 1882 */ 1883 txLoop++; 1884 if (txLoop > CS_OUTPUT_LOOP_MAX) { 1885 /* Free the mbuf chain */ 1886 m_freem(pMbufChain); 1887 /* 1888 * Transmission is not in 1889 * progress 1890 */ 1891 sc->sc_txbusy = FALSE; 1892 /* 1893 * Increment the output error 1894 * count 1895 */ 1896 ifp->if_oerrors++; 1897 /* 1898 * exit the routine and drop 1899 * the packet. 1900 */ 1901 txLoop = 0; 1902 dropout = 1; 1903 } 1904 } 1905 } 1906 } while (txLoop); 1907 } 1908 } 1909 1910 void 1911 cs_copy_tx_frame(sc, m0) 1912 struct cs_softc *sc; 1913 struct mbuf *m0; 1914 { 1915 struct mbuf *m; 1916 int len, leftover, frameoff; 1917 u_int16_t dbuf; 1918 u_int8_t *p; 1919 #ifdef DIAGNOSTIC 1920 u_int8_t *lim; 1921 #endif 1922 1923 /* Initialize frame pointer and data port address */ 1924 frameoff = PKTPG_TX_FRAME; 1925 1926 /* start out with no leftover data */ 1927 leftover = 0; 1928 dbuf = 0; 1929 1930 /* Process the chain of mbufs */ 1931 for (m = m0; m != NULL; m = m->m_next) { 1932 /* 1933 * Process all of the data in a single mbuf. 1934 */ 1935 p = mtod(m, u_int8_t *); 1936 len = m->m_len; 1937 #ifdef DIAGNOSTIC 1938 lim = p + len; 1939 #endif 1940 1941 while (len > 0) { 1942 if (leftover) { 1943 /* 1944 * Data left over (from mbuf or realignment). 1945 * Buffer the next byte, and write it and 1946 * the leftover data out. 1947 */ 1948 dbuf |= *p++ << 8; 1949 len--; 1950 if (sc->sc_memorymode) { 1951 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 1952 frameoff += 2; 1953 } 1954 else { 1955 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 1956 } 1957 leftover = 0; 1958 } else if ((long) p & 1) { 1959 /* 1960 * Misaligned data. Buffer the next byte. 1961 */ 1962 dbuf = *p++; 1963 len--; 1964 leftover = 1; 1965 } else { 1966 /* 1967 * Aligned data. This is the case we like. 1968 * 1969 * Write-region out as much as we can, then 1970 * buffer the remaining byte (if any). 1971 */ 1972 leftover = len & 1; 1973 len &= ~1; 1974 if (sc->sc_memorymode) { 1975 bus_space_write_region_2(sc->sc_memt, sc->sc_memh, frameoff, 1976 (u_int16_t *) p, len >> 1); 1977 frameoff += len; 1978 } 1979 else { 1980 bus_space_write_multi_2(sc->sc_iot, sc->sc_ioh, 1981 PORT_RXTX_DATA, (u_int16_t *)p, len >> 1); 1982 } 1983 p += len; 1984 1985 if (leftover) 1986 dbuf = *p++; 1987 len = 0; 1988 } 1989 } 1990 if (len < 0) 1991 panic("cs_copy_tx_frame: negative len"); 1992 #ifdef DIAGNOSTIC 1993 if (p != lim) 1994 panic("cs_copy_tx_frame: p != lim"); 1995 #endif 1996 } 1997 if (leftover) { 1998 if (sc->sc_memorymode) { 1999 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2000 } 2001 else { 2002 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2003 } 2004 } 2005 } 2006 2007 static int 2008 cs_enable(sc) 2009 struct cs_softc *sc; 2010 { 2011 if (!CS_IS_ENABLED(sc) && sc->sc_enable) { 2012 int error; 2013 2014 error = (*sc->sc_enable)(sc); 2015 if (error) 2016 return error; 2017 2018 sc->sc_cfgflags |= CFGFLG_ENABLED; 2019 } 2020 2021 return 0; 2022 } 2023 2024 static void 2025 cs_disable(sc) 2026 struct cs_softc *sc; 2027 { 2028 if (CS_IS_ENABLED(sc) && sc->sc_disable) { 2029 (*sc->sc_disable)(sc); 2030 2031 sc->sc_cfgflags &= ~CFGFLG_ENABLED; 2032 } 2033 } 2034 2035 static void 2036 cs_stop(ifp, disable) 2037 struct ifnet *ifp; 2038 int disable; 2039 { 2040 struct cs_softc *sc = ifp->if_softc; 2041 2042 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0); 2043 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0); 2044 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0); 2045 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0); 2046 2047 if (disable) { 2048 cs_disable(sc); 2049 } 2050 2051 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2052 } 2053 2054 int 2055 cs_activate(self, act) 2056 struct device *self; 2057 enum devact act; 2058 { 2059 struct cs_softc *sc = (void *)self; 2060 int s, error = 0; 2061 2062 s = splnet(); 2063 switch (act) { 2064 case DVACT_ACTIVATE: 2065 error = EOPNOTSUPP; 2066 break; 2067 2068 case DVACT_DEACTIVATE: 2069 if_deactivate(&sc->sc_ethercom.ec_if); 2070 break; 2071 } 2072 splx(s); 2073 2074 return error; 2075 } 2076 2077 static void 2078 cs_power(why, arg) 2079 int why; 2080 void *arg; 2081 { 2082 struct cs_softc *sc = arg; 2083 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2084 int s; 2085 2086 s = splnet(); 2087 switch (why) { 2088 case PWR_STANDBY: 2089 case PWR_SUSPEND: 2090 cs_stop(ifp, 0); 2091 break; 2092 case PWR_RESUME: 2093 if (ifp->if_flags & IFF_UP) { 2094 cs_init(ifp); 2095 } 2096 break; 2097 case PWR_SOFTSUSPEND: 2098 case PWR_SOFTSTANDBY: 2099 case PWR_SOFTRESUME: 2100 break; 2101 } 2102 splx(s); 2103 } 2104
Indexes created Fri Oct 03 02:09:57 GMT 2025