cs89x0.c revision 1.34.4.5
1 /* $NetBSD: cs89x0.c,v 1.34.4.5 2017/08/28 17:52:03 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher Gilbert 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright 1997 31 * Digital Equipment Corporation. All rights reserved. 32 * 33 * This software is furnished under license and may be used and 34 * copied only in accordance with the following terms and conditions. 35 * Subject to these conditions, you may download, copy, install, 36 * use, modify and distribute this software in source and/or binary 37 * form. No title or ownership is transferred hereby. 38 * 39 * 1) Any source code used, modified or distributed must reproduce 40 * and retain this copyright notice and list of conditions as 41 * they appear in the source file. 42 * 43 * 2) No right is granted to use any trade name, trademark, or logo of 44 * Digital Equipment Corporation. Neither the "Digital Equipment 45 * Corporation" name nor any trademark or logo of Digital Equipment 46 * Corporation may be used to endorse or promote products derived 47 * from this software without the prior written permission of 48 * Digital Equipment Corporation. 49 * 50 * 3) This software is provided "AS-IS" and any express or implied 51 * warranties, including but not limited to, any implied warranties 52 * of merchantability, fitness for a particular purpose, or 53 * non-infringement are disclaimed. In no event shall DIGITAL be 54 * liable for any damages whatsoever, and in particular, DIGITAL 55 * shall not be liable for special, indirect, consequential, or 56 * incidental damages or damages for lost profits, loss of 57 * revenue or loss of use, whether such damages arise in contract, 58 * negligence, tort, under statute, in equity, at law or otherwise, 59 * even if advised of the possibility of such damage. 60 */ 61 62 /* 63 **++ 64 ** FACILITY 65 ** 66 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller. 67 ** 68 ** ABSTRACT 69 ** 70 ** This module provides standard ethernet access for INET protocols 71 ** only. 72 ** 73 ** AUTHORS 74 ** 75 ** Peter Dettori SEA - Software Engineering. 76 ** 77 ** CREATION DATE: 78 ** 79 ** 13-Feb-1997. 80 ** 81 ** MODIFICATION HISTORY (Digital): 82 ** 83 ** Revision 1.27 1998/01/20 17:59:40 cgd 84 ** update for moved headers 85 ** 86 ** Revision 1.26 1998/01/12 19:29:36 cgd 87 ** use arm32/isa versions of isadma code. 88 ** 89 ** Revision 1.25 1997/12/12 01:35:27 cgd 90 ** convert to use new arp code (from Brini) 91 ** 92 ** Revision 1.24 1997/12/10 22:31:56 cgd 93 ** trim some fat (get rid of ability to explicitly supply enet addr, since 94 ** it was never used and added a bunch of code which really doesn't belong in 95 ** an enet driver), and clean up slightly. 96 ** 97 ** Revision 1.23 1997/10/06 16:42:12 cgd 98 ** copyright notices 99 ** 100 ** Revision 1.22 1997/06/20 19:38:01 chaiken 101 ** fixes some smartcard problems 102 ** 103 ** Revision 1.21 1997/06/10 02:56:20 grohn 104 ** Added call to ledNetActive 105 ** 106 ** Revision 1.20 1997/06/05 00:47:06 dettori 107 ** Changed cs_process_rx_dma to reset and re-initialise the 108 ** ethernet chip when DMA gets out of sync, or mbufs 109 ** can't be allocated. 110 ** 111 ** Revision 1.19 1997/06/03 03:09:58 dettori 112 ** Turn off sc_txbusy flag when a transmit underrun 113 ** occurs. 114 ** 115 ** Revision 1.18 1997/06/02 00:04:35 dettori 116 ** redefined the transmit table to get around the nfs_timer bug while we are 117 ** looking into it further. 118 ** 119 ** Also changed interrupts from EDGE to LEVEL. 120 ** 121 ** Revision 1.17 1997/05/27 23:31:01 dettori 122 ** Pulled out changes to DMAMODE defines. 123 ** 124 ** Revision 1.16 1997/05/23 04:25:16 cgd 125 ** reformat log so it fits in 80cols 126 ** 127 ** Revision 1.15 1997/05/23 04:22:18 cgd 128 ** remove the existing copyright notice (which Peter Dettori indicated 129 ** was incorrect, copied from an existing NetBSD file only so that the 130 ** file would have a copyright notice on it, and which he'd intended to 131 ** replace). Replace it with a Digital copyright notice, cloned from 132 ** ess.c. It's not really correct either (it indicates that the source 133 ** is Digital confidential!), but is better than nothing and more 134 ** correct than what was there before. 135 ** 136 ** Revision 1.14 1997/05/23 04:12:50 cgd 137 ** use an adaptive transmit start algorithm: start by telling the chip 138 ** to start transmitting after 381 bytes have been fed to it. if that 139 ** gets transmit underruns, ramp down to 1021 bytes then "whole 140 ** packet." If successful at a given level for a while, try the next 141 ** more agressive level. This code doesn't ever try to start 142 ** transmitting after 5 bytes have been sent to the NIC, because 143 ** that underruns rather regularly. The back-off and ramp-up mechanism 144 ** could probably be tuned a little bit, but this works well enough to 145 ** support > 1MB/s transmit rates on a clear ethernet (which is about 146 ** 20-25% better than the driver had previously been getting). 147 ** 148 ** Revision 1.13 1997/05/22 21:06:54 cgd 149 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly 150 ** casting from u_int8_t * to u_int16_t * without worrying about alignment 151 ** issues. This would cause bogus data to be spit out for mbufs with 152 ** misaligned data. For instance, it caused the following bits to appear 153 ** on the wire: 154 ** ... etBND 1S2C .SHA(K) R ... 155 ** 11112222333344445555 156 ** which should have appeared as: 157 ** ... NetBSD 1.2C (SHARK) ... 158 ** 11112222333344445555 159 ** Note the apparent 'rotate' of the bytes in the word, which was due to 160 ** incorrect unaligned accesses. This data corruption was the cause of 161 ** incoming telnet/rlogin hangs. 162 ** 163 ** Revision 1.12 1997/05/22 01:55:32 cgd 164 ** reformat log so it fits in 80cols 165 ** 166 ** Revision 1.11 1997/05/22 01:50:27 cgd 167 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case, 168 ** so packets aimed at other hosts don't get sent to ether_input(). 169 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that 170 ** you can easily tell (`strings`) what version of the driver is in your 171 ** kernel binary. 172 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily 173 ** safe, and not really a performance win anyway. (It was only used when 174 ** setting up the multicast logical address filter, which is an 175 ** infrequent event. It could have been used in the IFF_PROMISCUOUS 176 ** address check above, but the benefit of it vs. memcmp would be 177 ** inconsequential, there.) Use memcmp() instead. 178 ** * restructure csStartOuput to avoid the following bugs in the case where 179 ** txWait was being set: 180 ** * it would accidentally drop the outgoing packet if told to wait 181 ** but the outgoing packet queue was empty. 182 ** * it would bpf_mtap() the outgoing packet multiple times (once for 183 ** each time it was told to wait), and would also recalculate 184 ** the length of the outgoing packet each time it was told to 185 ** wait. 186 ** While there, rename txWait to txLoop, since with the new structure of 187 ** the code, the latter name makes more sense. 188 ** 189 ** Revision 1.10 1997/05/19 02:03:20 cgd 190 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip() 191 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this 192 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC 193 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave 194 ** as before. 195 ** 196 ** Revision 1.9 1997/05/19 01:45:37 cgd 197 ** create a new function, cs_ether_input(), which does received-packet 198 ** BPF and ether_input processing. This code used to be in three places, 199 ** and centralizing it will make adding IFF_PROMISC support much easier. 200 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to 201 ** do copies with bus_space_write_region_2(). It's more correct, and 202 ** potentially more efficient. That function needs to be gutted (to 203 ** deal properly with alignment issues, which it currently does wrong), 204 ** however, and the change doesn't gain much, so there's no point in 205 ** enabling it now. 206 ** 207 ** Revision 1.8 1997/05/19 01:17:10 cgd 208 ** fix a comment re: the setting of the TxConfig register. Clean up 209 ** interface counter maintenance (make it use standard idiom). 210 ** 211 **-- 212 */ 213 214 #include <sys/cdefs.h> 215 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.34.4.5 2017/08/28 17:52:03 skrll Exp $"); 216 217 #include "opt_inet.h" 218 219 #include <sys/param.h> 220 #include <sys/systm.h> 221 #include <sys/mbuf.h> 222 #include <sys/syslog.h> 223 #include <sys/socket.h> 224 #include <sys/device.h> 225 #include <sys/malloc.h> 226 #include <sys/ioctl.h> 227 #include <sys/errno.h> 228 229 #include <sys/rndsource.h> 230 231 #include <net/if.h> 232 #include <net/if_ether.h> 233 #include <net/if_media.h> 234 #ifdef INET 235 #include <netinet/in.h> 236 #include <netinet/if_inarp.h> 237 #endif 238 239 #include <net/bpf.h> 240 #include <net/bpfdesc.h> 241 242 #include <sys/bus.h> 243 #include <sys/intr.h> 244 245 #include <dev/ic/cs89x0reg.h> 246 #include <dev/ic/cs89x0var.h> 247 248 #ifdef SHARK 249 #include <shark/shark/sequoia.h> 250 #endif 251 252 /* 253 * MACRO DEFINITIONS 254 */ 255 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */ 256 257 /* 258 * FUNCTION PROTOTYPES 259 */ 260 static void cs_get_default_media(struct cs_softc *); 261 static int cs_get_params(struct cs_softc *); 262 static int cs_get_enaddr(struct cs_softc *); 263 static int cs_reset_chip(struct cs_softc *); 264 static void cs_reset(struct cs_softc *); 265 static int cs_ioctl(struct ifnet *, u_long, void *); 266 static void cs_initChip(struct cs_softc *); 267 static void cs_buffer_event(struct cs_softc *, u_int16_t); 268 static void cs_transmit_event(struct cs_softc *, u_int16_t); 269 static void cs_receive_event(struct cs_softc *, u_int16_t); 270 static void cs_process_receive(struct cs_softc *); 271 static void cs_process_rx_early(struct cs_softc *); 272 static void cs_start_output(struct ifnet *); 273 static void cs_copy_tx_frame(struct cs_softc *, struct mbuf *); 274 static void cs_set_ladr_filt(struct cs_softc *, struct ethercom *); 275 static u_int16_t cs_hash_index(char *); 276 static void cs_counter_event(struct cs_softc *, u_int16_t); 277 278 static int cs_mediachange(struct ifnet *); 279 static void cs_mediastatus(struct ifnet *, struct ifmediareq *); 280 281 static bool cs_shutdown(device_t, int); 282 static int cs_enable(struct cs_softc *); 283 static void cs_disable(struct cs_softc *); 284 static void cs_stop(struct ifnet *, int); 285 static int cs_scan_eeprom(struct cs_softc *); 286 static int cs_read_pktpg_from_eeprom(struct cs_softc *, int, u_int16_t *); 287 288 289 /* 290 * GLOBAL DECLARATIONS 291 */ 292 293 /* 294 * Xmit-early table. 295 * 296 * To get better performance, we tell the chip to start packet 297 * transmission before the whole packet is copied to the chip. 298 * However, this can fail under load. When it fails, we back off 299 * to a safer setting for a little while. 300 * 301 * txcmd is the value of txcmd used to indicate when to start transmission. 302 * better is the next 'better' state in the table. 303 * better_count is the number of output packets before transition to the 304 * better state. 305 * worse is the next 'worse' state in the table. 306 * 307 * Transition to the next worse state happens automatically when a 308 * transmittion underrun occurs. 309 */ 310 struct cs_xmit_early { 311 u_int16_t txcmd; 312 int better; 313 int better_count; 314 int worse; 315 } cs_xmit_early_table[3] = { 316 { TX_CMD_START_381, 0, INT_MAX, 1, }, 317 { TX_CMD_START_1021, 0, 50000, 2, }, 318 { TX_CMD_START_ALL, 1, 5000, 2, }, 319 }; 320 321 int cs_default_media[] = { 322 IFM_ETHER|IFM_10_2, 323 IFM_ETHER|IFM_10_5, 324 IFM_ETHER|IFM_10_T, 325 IFM_ETHER|IFM_10_T|IFM_FDX, 326 }; 327 int cs_default_nmedia = sizeof(cs_default_media) / sizeof(cs_default_media[0]); 328 329 int 330 cs_attach(struct cs_softc *sc, u_int8_t *enaddr, int *media, 331 int nmedia, int defmedia) 332 { 333 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 334 const char *chipname, *medname; 335 u_int16_t reg; 336 int i; 337 338 /* Start out in IO mode */ 339 sc->sc_memorymode = FALSE; 340 341 /* make sure we're right */ 342 for (i = 0; i < 10000; i++) { 343 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 344 if (reg == EISA_NUM_CRYSTAL) { 345 break; 346 } 347 } 348 if (i == 10000) { 349 aprint_error_dev(sc->sc_dev, "wrong id(0x%x)\n", reg); 350 return 1; /* XXX should panic? */ 351 } 352 353 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID); 354 sc->sc_prodid = reg & PROD_ID_MASK; 355 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8; 356 357 switch (sc->sc_prodid) { 358 case PROD_ID_CS8900: 359 chipname = "CS8900"; 360 break; 361 case PROD_ID_CS8920: 362 chipname = "CS8920"; 363 break; 364 case PROD_ID_CS8920M: 365 chipname = "CS8920M"; 366 break; 367 default: 368 panic("cs_attach: impossible"); 369 } 370 371 /* 372 * the first thing to do is check that the mbuf cluster size is 373 * greater than the MTU for an ethernet frame. The code depends on 374 * this and to port this to a OS where this was not the case would 375 * not be straightforward. 376 * 377 * we need 1 byte spare because our 378 * packet read loop can overrun. 379 * and we may need pad bytes to align ip header. 380 */ 381 if (MCLBYTES < ETHER_MAX_LEN + 1 + 382 ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header)) { 383 printf("%s: MCLBYTES too small for Ethernet frame\n", 384 device_xname(sc->sc_dev)); 385 return 1; 386 } 387 388 /* Start out not transmitting */ 389 sc->sc_txbusy = FALSE; 390 391 /* Set up early transmit threshhold */ 392 sc->sc_xe_ent = 0; 393 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count; 394 395 /* Initialize ifnet structure. */ 396 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 397 ifp->if_softc = sc; 398 ifp->if_start = cs_start_output; 399 ifp->if_init = cs_init; 400 ifp->if_ioctl = cs_ioctl; 401 ifp->if_stop = cs_stop; 402 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 403 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | 404 IFF_BROADCAST | IFF_MULTICAST; 405 IFQ_SET_READY(&ifp->if_snd); 406 407 /* Initialize ifmedia structures. */ 408 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus); 409 410 if (media != NULL) { 411 for (i = 0; i < nmedia; i++) 412 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 413 ifmedia_set(&sc->sc_media, defmedia); 414 } else { 415 for (i = 0; i < cs_default_nmedia; i++) 416 ifmedia_add(&sc->sc_media, cs_default_media[i], 417 0, NULL); 418 cs_get_default_media(sc); 419 } 420 421 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 422 if (cs_scan_eeprom(sc) == CS_ERROR) { 423 /* failed to scan the eeprom, pretend there isn't an eeprom */ 424 aprint_error_dev(sc->sc_dev, "unable to scan EEPROM\n"); 425 sc->sc_cfgflags |= CFGFLG_NOT_EEPROM; 426 } 427 } 428 429 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 430 /* Get parameters from the EEPROM */ 431 if (cs_get_params(sc) == CS_ERROR) { 432 aprint_error_dev(sc->sc_dev, 433 "unable to get settings from EEPROM\n"); 434 return 1; 435 } 436 } 437 438 if (enaddr != NULL) 439 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 440 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 441 /* Get and store the Ethernet address */ 442 if (cs_get_enaddr(sc) == CS_ERROR) { 443 aprint_error_dev(sc->sc_dev, 444 "unable to read Ethernet address\n"); 445 return 1; 446 } 447 } else { 448 #if 1 449 int j; 450 uint v; 451 452 for (j = 0; j < 6; j += 2) { 453 v = CS_READ_PACKET_PAGE(sc, PKTPG_IND_ADDR + j); 454 sc->sc_enaddr[j + 0] = v; 455 sc->sc_enaddr[j + 1] = v >> 8; 456 } 457 #else 458 printf("%s: no Ethernet address!\n", device_xname(sc->sc_dev)); 459 return 1; 460 #endif 461 } 462 463 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) { 464 case IFM_10_2: 465 medname = "BNC"; 466 break; 467 case IFM_10_5: 468 medname = "AUI"; 469 break; 470 case IFM_10_T: 471 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 472 medname = "UTP <full-duplex>"; 473 else 474 medname = "UTP"; 475 break; 476 default: 477 panic("cs_attach: impossible"); 478 } 479 printf("%s: %s rev. %c, address %s, media %s\n", 480 device_xname(sc->sc_dev), 481 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr), 482 medname); 483 484 if (sc->sc_dma_attach) 485 (*sc->sc_dma_attach)(sc); 486 487 /* Attach the interface. */ 488 if_attach(ifp); 489 if_deferred_start_init(ifp, NULL); 490 ether_ifattach(ifp, sc->sc_enaddr); 491 492 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 493 RND_TYPE_NET, RND_FLAG_DEFAULT); 494 sc->sc_cfgflags |= CFGFLG_ATTACHED; 495 496 if (pmf_device_register1(sc->sc_dev, NULL, NULL, cs_shutdown)) 497 pmf_class_network_register(sc->sc_dev, ifp); 498 else 499 aprint_error_dev(sc->sc_dev, 500 "couldn't establish power handler\n"); 501 502 /* Reset the chip */ 503 if (cs_reset_chip(sc) == CS_ERROR) { 504 aprint_error_dev(sc->sc_dev, "reset failed\n"); 505 cs_detach(sc); 506 return 1; 507 } 508 509 return 0; 510 } 511 512 int 513 cs_detach(struct cs_softc *sc) 514 { 515 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 516 517 if (sc->sc_cfgflags & CFGFLG_ATTACHED) { 518 rnd_detach_source(&sc->rnd_source); 519 ether_ifdetach(ifp); 520 if_detach(ifp); 521 sc->sc_cfgflags &= ~CFGFLG_ATTACHED; 522 } 523 524 #if 0 525 /* 526 * XXX not necessary 527 */ 528 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) { 529 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, sc->sc_dmasize); 530 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, sc->sc_dmasize); 531 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq); 532 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE; 533 } 534 #endif 535 536 pmf_device_deregister(sc->sc_dev); 537 538 return 0; 539 } 540 541 bool 542 cs_shutdown(device_t self, int howto) 543 { 544 struct cs_softc *sc; 545 546 sc = device_private(self); 547 cs_reset(sc); 548 549 return true; 550 } 551 552 void 553 cs_get_default_media(struct cs_softc *sc) 554 { 555 u_int16_t adp_cfg, xmit_ctl; 556 557 if (cs_verify_eeprom(sc) == CS_ERROR) { 558 aprint_error_dev(sc->sc_dev, 559 "cs_get_default_media: EEPROM missing or bad\n"); 560 goto fakeit; 561 } 562 563 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adp_cfg) == CS_ERROR) { 564 aprint_error_dev(sc->sc_dev, 565 "unable to read adapter config from EEPROM\n"); 566 goto fakeit; 567 } 568 569 if (cs_read_eeprom(sc, EEPROM_XMIT_CTL, &xmit_ctl) == CS_ERROR) { 570 aprint_error_dev(sc->sc_dev, 571 "unable to read transmit control from EEPROM\n"); 572 goto fakeit; 573 } 574 575 switch (adp_cfg & ADPTR_CFG_MEDIA) { 576 case ADPTR_CFG_AUI: 577 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5); 578 break; 579 case ADPTR_CFG_10BASE2: 580 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2); 581 break; 582 case ADPTR_CFG_10BASET: 583 default: 584 if (xmit_ctl & XMIT_CTL_FDX) 585 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX); 586 else 587 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 588 break; 589 } 590 return; 591 592 fakeit: 593 aprint_error_dev(sc->sc_dev, 594 "WARNING: default media setting may be inaccurate\n"); 595 /* XXX Arbitrary... */ 596 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 597 } 598 599 /* 600 * cs_scan_eeprom 601 * 602 * Attempt to take a complete copy of the eeprom into main memory. 603 * this will allow faster parsing of the eeprom data. 604 * 605 * Only tested against a 8920M's eeprom, but the data sheet for the 606 * 8920A indicates that is uses the same layout. 607 */ 608 int 609 cs_scan_eeprom(struct cs_softc *sc) 610 { 611 u_int16_t result; 612 int i; 613 int eeprom_size; 614 u_int8_t checksum = 0; 615 616 if (cs_verify_eeprom(sc) == CS_ERROR) { 617 aprint_error_dev(sc->sc_dev, 618 "cs_scan_params: EEPROM missing or bad\n"); 619 return (CS_ERROR); 620 } 621 622 /* 623 * read the 0th word from the eeprom, it will tell us the length 624 * and if the eeprom is valid 625 */ 626 cs_read_eeprom(sc, 0, &result); 627 628 /* check the eeprom signature */ 629 if ((result & 0xE000) != 0xA000) { 630 /* empty eeprom */ 631 return (CS_ERROR); 632 } 633 634 /* 635 * take the eeprom size (note the read value doesn't include the header 636 * word) 637 */ 638 eeprom_size = (result & 0xff) + 2; 639 640 sc->eeprom_data = malloc(eeprom_size, M_DEVBUF, M_WAITOK); 641 if (sc->eeprom_data == NULL) { 642 /* no memory, treat this as if there's no eeprom */ 643 return (CS_ERROR); 644 } 645 646 sc->eeprom_size = eeprom_size; 647 648 /* read the eeprom into the buffer, also calculate the checksum */ 649 for (i = 0; i < (eeprom_size >> 1); i++) { 650 cs_read_eeprom(sc, i, &(sc->eeprom_data[i])); 651 checksum += (sc->eeprom_data[i] & 0xff00) >> 8; 652 checksum += (sc->eeprom_data[i] & 0x00ff); 653 } 654 655 /* 656 * validate checksum calculation, the sum of all the bytes should be 0, 657 * as the high byte of the last word is the 2's complement of the 658 * sum to that point. 659 */ 660 if (checksum != 0) { 661 aprint_error_dev(sc->sc_dev, "eeprom checksum failure\n"); 662 return (CS_ERROR); 663 } 664 665 return (CS_OK); 666 } 667 668 static int 669 cs_read_pktpg_from_eeprom(struct cs_softc *sc, int pktpg, u_int16_t *pValue) 670 { 671 int x, maxword; 672 673 /* Check that we have eeprom data */ 674 if ((sc->eeprom_data == NULL) || (sc->eeprom_size < 2)) 675 return (CS_ERROR); 676 677 /* 678 * We only want to read the data words, the last word contains the 679 * checksum 680 */ 681 maxword = (sc->eeprom_size - 2) >> 1; 682 683 /* start 1 word in, as the first word is the length and signature */ 684 x = 1; 685 686 while ( x < (maxword)) { 687 u_int16_t header; 688 int group_size; 689 int offset; 690 int offset_max; 691 692 /* read in the group header word */ 693 header = sc->eeprom_data[x]; 694 x++; /* skip group header */ 695 696 /* 697 * size of group in words is in the top 4 bits, note that it 698 * is one less than the number of words 699 */ 700 group_size = header & 0xF000; 701 702 /* 703 * CS8900 Data sheet says this should be 0x01ff, 704 * but my cs8920 eeprom has higher offsets, 705 * perhaps the 8920 allows higher offsets, otherwise 706 * it's writing to places that it shouldn't 707 */ 708 /* work out the offsets this group covers */ 709 offset = header & 0x0FFF; 710 offset_max = offset + (group_size << 1); 711 712 /* check if the pkgpg we're after is in this group */ 713 if ((offset <= pktpg) && (pktpg <= offset_max)) { 714 /* the pkgpg value we want is in here */ 715 int eeprom_location; 716 717 eeprom_location = ((pktpg - offset) >> 1) ; 718 719 *pValue = sc->eeprom_data[x + eeprom_location]; 720 return (CS_OK); 721 } else { 722 /* skip this group (+ 1 for first entry) */ 723 x += group_size + 1; 724 } 725 } 726 727 /* 728 * if we've fallen out here then we don't have a value in the EEPROM 729 * for this pktpg so return an error 730 */ 731 return (CS_ERROR); 732 } 733 734 int 735 cs_get_params(struct cs_softc *sc) 736 { 737 u_int16_t isaConfig; 738 u_int16_t adapterConfig; 739 740 if (cs_verify_eeprom(sc) == CS_ERROR) { 741 aprint_error_dev(sc->sc_dev, 742 "cs_get_params: EEPROM missing or bad\n"); 743 return (CS_ERROR); 744 } 745 746 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 747 /* Get ISA configuration from the EEPROM */ 748 if (cs_read_pktpg_from_eeprom(sc, PKTPG_BUS_CTL, &isaConfig) 749 == CS_ERROR) { 750 /* eeprom doesn't have this value, use data sheet default */ 751 isaConfig = 0x0017; 752 } 753 754 /* Get adapter configuration from the EEPROM */ 755 if (cs_read_pktpg_from_eeprom(sc, PKTPG_SELF_CTL, &adapterConfig) 756 == CS_ERROR) { 757 /* eeprom doesn't have this value, use data sheet default */ 758 adapterConfig = 0x0015; 759 } 760 761 /* Copy the USE_SA flag */ 762 if (isaConfig & BUS_CTL_USE_SA) 763 sc->sc_cfgflags |= CFGFLG_USE_SA; 764 765 /* Copy the IO Channel Ready flag */ 766 if (isaConfig & BUS_CTL_IOCHRDY) 767 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 768 769 /* Copy the DC/DC Polarity flag */ 770 if (adapterConfig & SELF_CTL_HCB1) 771 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 772 } else { 773 /* Get ISA configuration from the EEPROM */ 774 if (cs_read_eeprom(sc, EEPROM_ISA_CFG, &isaConfig) == CS_ERROR) 775 goto eeprom_bad; 776 777 /* Get adapter configuration from the EEPROM */ 778 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adapterConfig) == CS_ERROR) 779 goto eeprom_bad; 780 781 /* Copy the USE_SA flag */ 782 if (isaConfig & ISA_CFG_USE_SA) 783 sc->sc_cfgflags |= CFGFLG_USE_SA; 784 785 /* Copy the IO Channel Ready flag */ 786 if (isaConfig & ISA_CFG_IOCHRDY) 787 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 788 789 /* Copy the DC/DC Polarity flag */ 790 if (adapterConfig & ADPTR_CFG_DCDC_POL) 791 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 792 } 793 794 return (CS_OK); 795 eeprom_bad: 796 aprint_error_dev(sc->sc_dev, 797 "cs_get_params: unable to read from EEPROM\n"); 798 return (CS_ERROR); 799 } 800 801 int 802 cs_get_enaddr(struct cs_softc *sc) 803 { 804 uint16_t myea[ETHER_ADDR_LEN / sizeof(uint16_t)]; 805 int i; 806 807 if (cs_verify_eeprom(sc) == CS_ERROR) { 808 aprint_error_dev(sc->sc_dev, 809 "cs_get_enaddr: EEPROM missing or bad\n"); 810 return (CS_ERROR); 811 } 812 813 /* Get Ethernet address from the EEPROM */ 814 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 815 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR, &myea[0]) 816 == CS_ERROR) 817 goto eeprom_bad; 818 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 2, &myea[1]) 819 == CS_ERROR) 820 goto eeprom_bad; 821 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 4, &myea[2]) 822 == CS_ERROR) 823 goto eeprom_bad; 824 } else { 825 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_H, &myea[0]) == CS_ERROR) 826 goto eeprom_bad; 827 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_M, &myea[1]) == CS_ERROR) 828 goto eeprom_bad; 829 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_L, &myea[2]) == CS_ERROR) 830 goto eeprom_bad; 831 } 832 833 for (i = 0; i < __arraycount(myea); i++) { 834 sc->sc_enaddr[i * 2 + 0] = myea[i]; 835 sc->sc_enaddr[i * 2 + 1] = myea[i] >> 8; 836 } 837 838 return (CS_OK); 839 840 eeprom_bad: 841 aprint_error_dev(sc->sc_dev, 842 "cs_get_enaddr: unable to read from EEPROM\n"); 843 return (CS_ERROR); 844 } 845 846 int 847 cs_reset_chip(struct cs_softc *sc) 848 { 849 int intState; 850 int x; 851 852 /* Disable interrupts at the CPU so reset command is atomic */ 853 intState = splnet(); 854 855 /* 856 * We are now resetting the chip 857 * 858 * A spurious interrupt is generated by the chip when it is reset. This 859 * variable informs the interrupt handler to ignore this interrupt. 860 */ 861 sc->sc_resetting = TRUE; 862 863 /* Issue a reset command to the chip */ 864 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET); 865 866 /* Re-enable interrupts at the CPU */ 867 splx(intState); 868 869 /* The chip is always in IO mode after a reset */ 870 sc->sc_memorymode = FALSE; 871 872 /* If transmission was in progress, it is not now */ 873 sc->sc_txbusy = FALSE; 874 875 /* 876 * there was a delay(125); here, but it seems uneccesary 125 usec is 877 * 1/8000 of a second, not 1/8 of a second. the data sheet advises 878 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below 879 * should be sufficient. 880 */ 881 882 /* Transition SBHE to switch chip from 8-bit to 16-bit */ 883 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 884 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 885 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 886 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 887 888 /* Wait until the EEPROM is not busy */ 889 for (x = 0; x < MAXLOOP; x++) { 890 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY)) 891 break; 892 } 893 894 if (x == MAXLOOP) 895 return CS_ERROR; 896 897 /* Wait until initialization is done */ 898 for (x = 0; x < MAXLOOP; x++) { 899 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE) 900 break; 901 } 902 903 if (x == MAXLOOP) 904 return CS_ERROR; 905 906 /* Reset is no longer in progress */ 907 sc->sc_resetting = FALSE; 908 909 return CS_OK; 910 } 911 912 int 913 cs_verify_eeprom(struct cs_softc *sc) 914 { 915 u_int16_t self_status; 916 917 /* Verify that the EEPROM is present and OK */ 918 self_status = CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST); 919 if (((self_status & SELF_ST_EEP_PRES) && 920 (self_status & SELF_ST_EEP_OK)) == 0) 921 return (CS_ERROR); 922 923 return (CS_OK); 924 } 925 926 int 927 cs_read_eeprom(struct cs_softc *sc, int offset, u_int16_t *pValue) 928 { 929 int x; 930 931 /* Ensure that the EEPROM is not busy */ 932 for (x = 0; x < MAXLOOP; x++) { 933 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 934 SELF_ST_SI_BUSY)) 935 break; 936 } 937 938 if (x == MAXLOOP) 939 return (CS_ERROR); 940 941 /* Issue the command to read the offset within the EEPROM */ 942 CS_WRITE_PACKET_PAGE_IO(sc, PKTPG_EEPROM_CMD, 943 offset | EEPROM_CMD_READ); 944 945 /* Wait until the command is completed */ 946 for (x = 0; x < MAXLOOP; x++) { 947 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 948 SELF_ST_SI_BUSY)) 949 break; 950 } 951 952 if (x == MAXLOOP) 953 return (CS_ERROR); 954 955 /* Get the EEPROM data from the EEPROM Data register */ 956 *pValue = CS_READ_PACKET_PAGE_IO(sc, PKTPG_EEPROM_DATA); 957 958 return (CS_OK); 959 } 960 961 void 962 cs_initChip(struct cs_softc *sc) 963 { 964 u_int16_t busCtl; 965 u_int16_t selfCtl; 966 u_int16_t v; 967 u_int16_t isaId; 968 int i; 969 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media); 970 971 /* Disable reception and transmission of frames */ 972 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 973 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) & 974 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON); 975 976 /* Disable interrupt at the chip */ 977 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 978 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL); 979 980 /* If IOCHRDY is enabled then clear the bit in the busCtl register */ 981 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL); 982 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) { 983 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 984 busCtl & ~BUS_CTL_IOCHRDY); 985 } else { 986 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 987 busCtl | BUS_CTL_IOCHRDY); 988 } 989 990 /* Set the Line Control register to match the media type */ 991 if (media == IFM_10_T) 992 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET); 993 else 994 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY); 995 996 /* 997 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to 998 * enable the DC/DC converter 999 */ 1000 selfCtl = SELF_CTL_HC1E; 1001 1002 /* If the media type is 10Base2 */ 1003 if (media == IFM_10_2) { 1004 /* 1005 * Enable the DC/DC converter if it has a low enable. 1006 */ 1007 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0) 1008 /* 1009 * Set the HCB1 bit, which causes the HC1 pin to go 1010 * low. 1011 */ 1012 selfCtl |= SELF_CTL_HCB1; 1013 } else { /* Media type is 10BaseT or AUI */ 1014 /* 1015 * Disable the DC/DC converter if it has a high enable. 1016 */ 1017 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) { 1018 /* 1019 * Set the HCB1 bit, which causes the HC1 pin to go 1020 * low. 1021 */ 1022 selfCtl |= SELF_CTL_HCB1; 1023 } 1024 } 1025 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl); 1026 1027 /* enable normal link pulse */ 1028 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M) 1029 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE); 1030 1031 /* Enable full-duplex, if appropriate */ 1032 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 1033 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX); 1034 1035 /* RX_CTL set in cs_set_ladr_filt(), below */ 1036 1037 /* enable all transmission interrupts */ 1038 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE); 1039 1040 /* Accept all receive interrupts */ 1041 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE); 1042 1043 /* 1044 * Configure Operational Modes 1045 * 1046 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this is 1047 * a better way to do it because the card has a counter which can be 1048 * read to update the RX_MISS counter. This saves many interrupts. 1049 * 1050 * I have turned on the tx and rx overflow interrupts to counter using 1051 * the receive miss interrupt. This is a better estimate of errors 1052 * and requires lower system overhead. 1053 */ 1054 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE | 1055 BUF_CFG_RX_DMA_IE); 1056 1057 if (sc->sc_dma_chipinit) 1058 (*sc->sc_dma_chipinit)(sc); 1059 1060 /* If memory mode is enabled */ 1061 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) { 1062 /* If external logic is present for address decoding */ 1063 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) { 1064 /* 1065 * Program the external logic to decode address bits 1066 * SA20-SA23 1067 */ 1068 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD, 1069 ((sc->sc_pktpgaddr & 0xffffff) >> 20) | 1070 EEPROM_CMD_ELSEL); 1071 } 1072 1073 /* 1074 * Write the packet page base physical address to the memory 1075 * base register. 1076 */ 1077 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0, 1078 sc->sc_pktpgaddr & 0xFFFF); 1079 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2, 1080 sc->sc_pktpgaddr >> 16); 1081 busCtl = BUS_CTL_MEM_MODE; 1082 1083 /* tell the chip to read the addresses off the SA pins */ 1084 if (sc->sc_cfgflags & CFGFLG_USE_SA) { 1085 busCtl |= BUS_CTL_USE_SA; 1086 } 1087 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1088 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl); 1089 1090 /* We are in memory mode now! */ 1091 sc->sc_memorymode = TRUE; 1092 1093 /* 1094 * wait here (10ms) for the chip to swap over. this is the 1095 * maximum time that this could take. 1096 */ 1097 delay(10000); 1098 1099 /* Verify that we can read from the chip */ 1100 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 1101 1102 /* 1103 * As a last minute sanity check before actually using mapped 1104 * memory we verify that we can read the isa number from the 1105 * chip in memory mode. 1106 */ 1107 if (isaId != EISA_NUM_CRYSTAL) { 1108 aprint_error_dev(sc->sc_dev, 1109 "failed to enable memory mode\n"); 1110 sc->sc_memorymode = FALSE; 1111 } else { 1112 /* 1113 * we are in memory mode so if we aren't using DMA, 1114 * then program the chip to interrupt early. 1115 */ 1116 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) { 1117 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 1118 BUF_CFG_RX_DEST_IE | 1119 BUF_CFG_RX_MISS_OVER_IE | 1120 BUF_CFG_TX_COL_OVER_IE); 1121 } 1122 } 1123 1124 } 1125 1126 /* Put Ethernet address into the Individual Address register */ 1127 for (i = 0; i < 6; i += 2) { 1128 v = sc->sc_enaddr[i + 0] | (sc->sc_enaddr[i + 1]) << 8; 1129 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + i, v); 1130 } 1131 1132 if (sc->sc_irq != -1) { 1133 /* Set the interrupt level in the chip */ 1134 if (sc->sc_prodid == PROD_ID_CS8900) { 1135 if (sc->sc_irq == 5) { 1136 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3); 1137 } else { 1138 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, (sc->sc_irq) - 10); 1139 } 1140 } 1141 else { /* CS8920 */ 1142 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, sc->sc_irq); 1143 } 1144 } 1145 1146 /* write the multicast mask to the address filter register */ 1147 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1148 1149 /* Enable reception and transmission of frames */ 1150 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 1151 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) | 1152 LINE_CTL_RX_ON | LINE_CTL_TX_ON); 1153 1154 /* Enable interrupt at the chip */ 1155 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1156 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL); 1157 } 1158 1159 int 1160 cs_init(struct ifnet *ifp) 1161 { 1162 int intState; 1163 int error = CS_OK; 1164 struct cs_softc *sc = ifp->if_softc; 1165 1166 if (cs_enable(sc)) 1167 goto out; 1168 1169 cs_stop(ifp, 0); 1170 1171 intState = splnet(); 1172 1173 #if 0 1174 /* Mark the interface as down */ 1175 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING); 1176 #endif 1177 1178 #ifdef CS_DEBUG 1179 /* Enable debugging */ 1180 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG; 1181 #endif 1182 1183 /* Reset the chip */ 1184 if ((error = cs_reset_chip(sc)) == CS_OK) { 1185 /* Initialize the chip */ 1186 cs_initChip(sc); 1187 1188 /* Mark the interface as running */ 1189 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 1190 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1191 sc->sc_ethercom.ec_if.if_timer = 0; 1192 1193 /* Assume we have carrier until we are told otherwise. */ 1194 sc->sc_carrier = 1; 1195 } else { 1196 aprint_error_dev(sc->sc_dev, "unable to reset chip\n"); 1197 } 1198 1199 splx(intState); 1200 out: 1201 if (error == CS_OK) 1202 return 0; 1203 return EIO; 1204 } 1205 1206 void 1207 cs_set_ladr_filt(struct cs_softc *sc, struct ethercom *ec) 1208 { 1209 struct ifnet *ifp = &ec->ec_if; 1210 struct ether_multi *enm; 1211 struct ether_multistep step; 1212 u_int16_t af[4]; 1213 u_int16_t port, mask, index; 1214 1215 /* 1216 * Set up multicast address filter by passing all multicast addresses 1217 * through a crc generator, and then using the high order 6 bits as an 1218 * index into the 64 bit logical address filter. The high order bit 1219 * selects the word, while the rest of the bits select the bit within 1220 * the word. 1221 */ 1222 if (ifp->if_flags & IFF_PROMISC) { 1223 /* accept all valid frames. */ 1224 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1225 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A | 1226 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1227 ifp->if_flags |= IFF_ALLMULTI; 1228 return; 1229 } 1230 1231 /* 1232 * accept frames if a. crc valid, b. individual address match c. 1233 * broadcast address,and d. multicast addresses matched in the hash 1234 * filter 1235 */ 1236 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1237 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1238 1239 1240 /* 1241 * start off with all multicast flag clear, set it if we need to 1242 * later, otherwise we will leave it. 1243 */ 1244 ifp->if_flags &= ~IFF_ALLMULTI; 1245 af[0] = af[1] = af[2] = af[3] = 0x0000; 1246 1247 /* 1248 * Loop through all the multicast addresses unless we get a range of 1249 * addresses, in which case we will just accept all packets. 1250 * Justification for this is given in the next comment. 1251 */ 1252 ETHER_FIRST_MULTI(step, ec, enm); 1253 while (enm != NULL) { 1254 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1255 sizeof enm->enm_addrlo)) { 1256 /* 1257 * We must listen to a range of multicast addresses. 1258 * For now, just accept all multicasts, rather than 1259 * trying to set only those filter bits needed to match 1260 * the range. (At this time, the only use of address 1261 * ranges is for IP multicast routing, for which the 1262 * range is big enough to require all bits set.) 1263 */ 1264 ifp->if_flags |= IFF_ALLMULTI; 1265 af[0] = af[1] = af[2] = af[3] = 0xffff; 1266 break; 1267 } else { 1268 /* 1269 * we have got an individual address so just set that 1270 * bit. 1271 */ 1272 index = cs_hash_index(enm->enm_addrlo); 1273 1274 /* Set the bit the Logical address filter. */ 1275 port = (u_int16_t) (index >> 4); 1276 mask = (u_int16_t) (1 << (index & 0xf)); 1277 af[port] |= mask; 1278 1279 ETHER_NEXT_MULTI(step, enm); 1280 } 1281 } 1282 1283 /* now program the chip with the addresses */ 1284 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]); 1285 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]); 1286 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]); 1287 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]); 1288 return; 1289 } 1290 1291 u_int16_t 1292 cs_hash_index(char *addr) 1293 { 1294 uint32_t crc; 1295 uint16_t hash_code; 1296 1297 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1298 1299 hash_code = crc >> 26; 1300 return (hash_code); 1301 } 1302 1303 void 1304 cs_reset(struct cs_softc *sc) 1305 { 1306 1307 /* Mark the interface as down */ 1308 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1309 1310 /* Reset the chip */ 1311 cs_reset_chip(sc); 1312 } 1313 1314 int 1315 cs_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1316 { 1317 struct cs_softc *sc = ifp->if_softc; 1318 struct ifreq *ifr = data; 1319 int state; 1320 int result; 1321 1322 state = splnet(); 1323 1324 result = 0; /* only set if something goes wrong */ 1325 1326 switch (cmd) { 1327 case SIOCGIFMEDIA: 1328 case SIOCSIFMEDIA: 1329 result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1330 break; 1331 1332 default: 1333 result = ether_ioctl(ifp, cmd, data); 1334 if (result == ENETRESET) { 1335 if (ifp->if_flags & IFF_RUNNING) { 1336 /* 1337 * Multicast list has changed. Set the 1338 * hardware filter accordingly. 1339 */ 1340 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1341 } 1342 result = 0; 1343 } 1344 break; 1345 } 1346 1347 splx(state); 1348 1349 return result; 1350 } 1351 1352 int 1353 cs_mediachange(struct ifnet *ifp) 1354 { 1355 1356 /* 1357 * Current media is already set up. Just reset the interface 1358 * to let the new value take hold. 1359 */ 1360 cs_init(ifp); 1361 return (0); 1362 } 1363 1364 void 1365 cs_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1366 { 1367 struct cs_softc *sc = ifp->if_softc; 1368 1369 /* 1370 * The currently selected media is always the active media. 1371 */ 1372 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media; 1373 1374 if (ifp->if_flags & IFF_UP) { 1375 /* Interface up, status is valid. */ 1376 ifmr->ifm_status = IFM_AVALID | 1377 (sc->sc_carrier ? IFM_ACTIVE : 0); 1378 } 1379 else ifmr->ifm_status = 0; 1380 } 1381 1382 int 1383 cs_intr(void *arg) 1384 { 1385 struct cs_softc *sc = arg; 1386 u_int16_t Event; 1387 u_int16_t rndEvent; 1388 1389 /*printf("cs_intr %p\n", sc);*/ 1390 /* Ignore any interrupts that happen while the chip is being reset */ 1391 if (sc->sc_resetting) { 1392 printf("%s: cs_intr: reset in progress\n", 1393 device_xname(sc->sc_dev)); 1394 return 1; 1395 } 1396 1397 /* Read an event from the Interrupt Status Queue */ 1398 if (sc->sc_memorymode) 1399 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1400 else 1401 Event = CS_READ_PORT(sc, PORT_ISQ); 1402 1403 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff) 1404 return 0; /* not ours */ 1405 1406 rndEvent = Event; 1407 1408 /* Process all the events in the Interrupt Status Queue */ 1409 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) { 1410 /* Dispatch to an event handler based on the register number */ 1411 switch (Event & REG_NUM_MASK) { 1412 case REG_NUM_RX_EVENT: 1413 cs_receive_event(sc, Event); 1414 break; 1415 case REG_NUM_TX_EVENT: 1416 cs_transmit_event(sc, Event); 1417 break; 1418 case REG_NUM_BUF_EVENT: 1419 cs_buffer_event(sc, Event); 1420 break; 1421 case REG_NUM_TX_COL: 1422 case REG_NUM_RX_MISS: 1423 cs_counter_event(sc, Event); 1424 break; 1425 default: 1426 printf("%s: unknown interrupt event 0x%x\n", 1427 device_xname(sc->sc_dev), Event); 1428 break; 1429 } 1430 1431 /* Read another event from the Interrupt Status Queue */ 1432 if (sc->sc_memorymode) 1433 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1434 else 1435 Event = CS_READ_PORT(sc, PORT_ISQ); 1436 } 1437 1438 /* have handled the interrupt */ 1439 rnd_add_uint32(&sc->rnd_source, rndEvent); 1440 return 1; 1441 } 1442 1443 void 1444 cs_counter_event(struct cs_softc *sc, u_int16_t cntEvent) 1445 { 1446 struct ifnet *ifp; 1447 u_int16_t errorCount; 1448 1449 ifp = &sc->sc_ethercom.ec_if; 1450 1451 switch (cntEvent & REG_NUM_MASK) { 1452 case REG_NUM_TX_COL: 1453 /* 1454 * the count should be read before an overflow occurs. 1455 */ 1456 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL); 1457 /* 1458 * the tramsit event routine always checks the number of 1459 * collisions for any packet so we don't increment any 1460 * counters here, as they should already have been 1461 * considered. 1462 */ 1463 break; 1464 case REG_NUM_RX_MISS: 1465 /* 1466 * the count should be read before an overflow occurs. 1467 */ 1468 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS); 1469 /* 1470 * Increment the input error count, the first 6bits are the 1471 * register id. 1472 */ 1473 ifp->if_ierrors += ((errorCount & 0xffC0) >> 6); 1474 break; 1475 default: 1476 /* do nothing */ 1477 break; 1478 } 1479 } 1480 1481 void 1482 cs_buffer_event(struct cs_softc *sc, u_int16_t bufEvent) 1483 { 1484 1485 /* 1486 * multiple events can be in the buffer event register at one time so 1487 * a standard switch statement will not suffice, here every event 1488 * must be checked. 1489 */ 1490 1491 /* 1492 * if 128 bits have been rxed by the time we get here, the dest event 1493 * will be cleared and 128 event will be set. 1494 */ 1495 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) { 1496 cs_process_rx_early(sc); 1497 } 1498 1499 if (bufEvent & BUF_EVENT_RX_DMA) { 1500 /* process the receive data */ 1501 if (sc->sc_dma_process_rx) 1502 (*sc->sc_dma_process_rx)(sc); 1503 else 1504 /* should panic? */ 1505 aprint_error_dev(sc->sc_dev, "unexpected DMA event\n"); 1506 } 1507 1508 if (bufEvent & BUF_EVENT_TX_UNDR) { 1509 #if 0 1510 /* 1511 * This can happen occasionally, and it's not worth worrying 1512 * about. 1513 */ 1514 printf("%s: transmit underrun (%d -> %d)\n", 1515 device_xname(sc->sc_dev), sc->sc_xe_ent, 1516 cs_xmit_early_table[sc->sc_xe_ent].worse); 1517 #endif 1518 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse; 1519 sc->sc_xe_togo = 1520 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1521 1522 /* had an underrun, transmit is finished */ 1523 sc->sc_txbusy = FALSE; 1524 } 1525 1526 if (bufEvent & BUF_EVENT_SW_INT) { 1527 printf("%s: software initiated interrupt\n", 1528 device_xname(sc->sc_dev)); 1529 } 1530 } 1531 1532 void 1533 cs_transmit_event(struct cs_softc *sc, u_int16_t txEvent) 1534 { 1535 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1536 1537 /* If there were any errors transmitting this frame */ 1538 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | TX_EVENT_OUT_WIN | 1539 TX_EVENT_JABBER | TX_EVENT_16_COLL)) { 1540 /* Increment the output error count */ 1541 ifp->if_oerrors++; 1542 1543 /* Note carrier loss. */ 1544 if (txEvent & TX_EVENT_LOSS_CRS) 1545 sc->sc_carrier = 0; 1546 1547 /* If debugging is enabled then log error messages */ 1548 if (ifp->if_flags & IFF_DEBUG) { 1549 if (txEvent & TX_EVENT_LOSS_CRS) { 1550 aprint_error_dev(sc->sc_dev, "lost carrier\n"); 1551 } 1552 if (txEvent & TX_EVENT_SQE_ERR) { 1553 aprint_error_dev(sc->sc_dev, "SQE error\n"); 1554 } 1555 if (txEvent & TX_EVENT_OUT_WIN) { 1556 aprint_error_dev(sc->sc_dev, 1557 "out-of-window collision\n"); 1558 } 1559 if (txEvent & TX_EVENT_JABBER) { 1560 aprint_error_dev(sc->sc_dev, "jabber\n"); 1561 } 1562 if (txEvent & TX_EVENT_16_COLL) { 1563 aprint_error_dev(sc->sc_dev, "16 collisions\n"); 1564 } 1565 } 1566 } 1567 else { 1568 /* Transmission successful, carrier is up. */ 1569 sc->sc_carrier = 1; 1570 #ifdef SHARK 1571 ledNetActive(); 1572 #endif 1573 } 1574 1575 /* Add the number of collisions for this frame */ 1576 if (txEvent & TX_EVENT_16_COLL) { 1577 ifp->if_collisions += 16; 1578 } else { 1579 ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11); 1580 } 1581 1582 ifp->if_opackets++; 1583 1584 /* Transmission is no longer in progress */ 1585 sc->sc_txbusy = FALSE; 1586 1587 /* If there is more to transmit, start the next transmission */ 1588 if_schedule_deferred_start(ifp); 1589 } 1590 1591 void 1592 cs_print_rx_errors(struct cs_softc *sc, u_int16_t rxEvent) 1593 { 1594 1595 if (rxEvent & RX_EVENT_RUNT) 1596 aprint_error_dev(sc->sc_dev, "runt\n"); 1597 1598 if (rxEvent & RX_EVENT_X_DATA) 1599 aprint_error_dev(sc->sc_dev, "extra data\n"); 1600 1601 if (rxEvent & RX_EVENT_CRC_ERR) { 1602 if (rxEvent & RX_EVENT_DRIBBLE) 1603 aprint_error_dev(sc->sc_dev, "alignment error\n"); 1604 else 1605 aprint_error_dev(sc->sc_dev, "CRC error\n"); 1606 } else { 1607 if (rxEvent & RX_EVENT_DRIBBLE) 1608 aprint_error_dev(sc->sc_dev, "dribble bits\n"); 1609 } 1610 } 1611 1612 void 1613 cs_receive_event(struct cs_softc *sc, u_int16_t rxEvent) 1614 { 1615 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1616 1617 /* If the frame was not received OK */ 1618 if (!(rxEvent & RX_EVENT_RX_OK)) { 1619 /* Increment the input error count */ 1620 ifp->if_ierrors++; 1621 1622 /* 1623 * If debugging is enabled then log error messages. 1624 */ 1625 if (ifp->if_flags & IFF_DEBUG) { 1626 if (rxEvent != REG_NUM_RX_EVENT) { 1627 cs_print_rx_errors(sc, rxEvent); 1628 1629 /* 1630 * Must read the length of all received 1631 * frames 1632 */ 1633 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1634 1635 /* Skip the received frame */ 1636 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1637 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | 1638 RX_CFG_SKIP); 1639 } else { 1640 aprint_error_dev(sc->sc_dev, "implied skip\n"); 1641 } 1642 } 1643 } else { 1644 /* 1645 * process the received frame and pass it up to the upper 1646 * layers. 1647 */ 1648 cs_process_receive(sc); 1649 } 1650 } 1651 1652 void 1653 cs_ether_input(struct cs_softc *sc, struct mbuf *m) 1654 { 1655 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1656 1657 /* Pass the packet up. */ 1658 if_percpuq_enqueue(ifp->if_percpuq, m); 1659 } 1660 1661 void 1662 cs_process_receive(struct cs_softc *sc) 1663 { 1664 struct ifnet *ifp; 1665 struct mbuf *m; 1666 int totlen; 1667 u_int16_t *pBuff, *pBuffLimit; 1668 int pad; 1669 unsigned int frameOffset = 0; /* XXX: gcc */ 1670 1671 #ifdef SHARK 1672 ledNetActive(); 1673 #endif 1674 1675 ifp = &sc->sc_ethercom.ec_if; 1676 1677 /* Received a packet; carrier is up. */ 1678 sc->sc_carrier = 1; 1679 1680 if (sc->sc_memorymode) { 1681 /* Initialize the frame offset */ 1682 frameOffset = PKTPG_RX_LENGTH; 1683 1684 /* Get the length of the received frame */ 1685 totlen = CS_READ_PACKET_PAGE(sc, frameOffset); 1686 frameOffset += 2; 1687 } 1688 else { 1689 /* drop status */ 1690 CS_READ_PORT(sc, PORT_RXTX_DATA); 1691 1692 /* Get the length of the received frame */ 1693 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA); 1694 } 1695 1696 if (totlen > ETHER_MAX_LEN) { 1697 aprint_error_dev(sc->sc_dev, "invalid packet length %d\n", 1698 totlen); 1699 1700 /* skip the received frame */ 1701 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1702 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1703 return; 1704 } 1705 1706 MGETHDR(m, M_DONTWAIT, MT_DATA); 1707 if (m == 0) { 1708 aprint_error_dev(sc->sc_dev, 1709 "cs_process_receive: unable to allocate mbuf\n"); 1710 ifp->if_ierrors++; 1711 /* 1712 * couldn't allocate an mbuf so things are not good, may as 1713 * well drop the packet I think. 1714 * 1715 * have already read the length so we should be right to skip 1716 * the packet. 1717 */ 1718 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1719 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1720 return; 1721 } 1722 m_set_rcvif(m, ifp); 1723 m->m_pkthdr.len = totlen; 1724 1725 /* number of bytes to align ip header on word boundary for ipintr */ 1726 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1727 1728 /* 1729 * alloc mbuf cluster if we need. 1730 * we need 1 byte spare because following 1731 * packet read loop can overrun. 1732 */ 1733 if (totlen + pad + 1 > MHLEN) { 1734 MCLGET(m, M_DONTWAIT); 1735 if ((m->m_flags & M_EXT) == 0) { 1736 /* couldn't allocate an mbuf cluster */ 1737 aprint_error_dev(sc->sc_dev, 1738 "cs_process_receive: " 1739 "unable to allocate a cluster\n"); 1740 m_freem(m); 1741 1742 /* skip the received frame */ 1743 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1744 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1745 return; 1746 } 1747 } 1748 1749 /* align ip header on word boundary for ipintr */ 1750 m->m_data += pad; 1751 1752 m->m_len = totlen; 1753 pBuff = mtod(m, u_int16_t *); 1754 1755 /* now read the data from the chip */ 1756 if (sc->sc_memorymode) { 1757 pBuffLimit = pBuff + (totlen + 1) / 2; /* don't want to go over */ 1758 while (pBuff < pBuffLimit) { 1759 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1760 frameOffset += 2; 1761 } 1762 } 1763 else { 1764 IO_READ_MULTI_2(sc, PORT_RXTX_DATA, pBuff, (totlen + 1)>>1); 1765 } 1766 1767 cs_ether_input(sc, m); 1768 } 1769 1770 void 1771 cs_process_rx_early(struct cs_softc *sc) 1772 { 1773 struct ifnet *ifp; 1774 struct mbuf *m; 1775 u_int16_t frameCount, oldFrameCount; 1776 u_int16_t rxEvent; 1777 u_int16_t *pBuff; 1778 int pad; 1779 unsigned int frameOffset; 1780 1781 1782 ifp = &sc->sc_ethercom.ec_if; 1783 1784 /* Initialize the frame offset */ 1785 frameOffset = PKTPG_RX_FRAME; 1786 frameCount = 0; 1787 1788 MGETHDR(m, M_DONTWAIT, MT_DATA); 1789 if (m == 0) { 1790 aprint_error_dev(sc->sc_dev, 1791 "cs_process_rx_early: unable to allocate mbuf\n"); 1792 ifp->if_ierrors++; 1793 /* 1794 * couldn't allocate an mbuf so things are not good, may as 1795 * well drop the packet I think. 1796 * 1797 * have already read the length so we should be right to skip 1798 * the packet. 1799 */ 1800 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1801 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1802 return; 1803 } 1804 m_set_rcvif(m, ifp); 1805 /* 1806 * save processing by always using a mbuf cluster, guaranteed to fit 1807 * packet 1808 */ 1809 MCLGET(m, M_DONTWAIT); 1810 if ((m->m_flags & M_EXT) == 0) { 1811 /* couldn't allocate an mbuf cluster */ 1812 aprint_error_dev(sc->sc_dev, 1813 "cs_process_rx_early: unable to allocate a cluster\n"); 1814 m_freem(m); 1815 /* skip the frame */ 1816 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1817 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1818 return; 1819 } 1820 1821 /* align ip header on word boundary for ipintr */ 1822 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1823 m->m_data += pad; 1824 1825 /* set up the buffer pointer to point to the data area */ 1826 pBuff = mtod(m, u_int16_t *); 1827 1828 /* 1829 * now read the frame byte counter until we have finished reading the 1830 * frame 1831 */ 1832 oldFrameCount = 0; 1833 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1834 while ((frameCount != 0) && (frameCount < MCLBYTES)) { 1835 for (; oldFrameCount < frameCount; oldFrameCount += 2) { 1836 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1837 frameOffset += 2; 1838 } 1839 1840 /* read the new count from the chip */ 1841 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1842 } 1843 1844 /* update the mbuf counts */ 1845 m->m_len = oldFrameCount; 1846 m->m_pkthdr.len = oldFrameCount; 1847 1848 /* now check the Rx Event register */ 1849 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1850 1851 if ((rxEvent & RX_EVENT_RX_OK) != 0) { 1852 /* 1853 * do an implied skip, it seems to be more reliable than a 1854 * forced skip. 1855 */ 1856 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS); 1857 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1858 1859 /* 1860 * now read the RX_EVENT register to perform an implied skip. 1861 */ 1862 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1863 1864 cs_ether_input(sc, m); 1865 } else { 1866 m_freem(m); 1867 ifp->if_ierrors++; 1868 } 1869 } 1870 1871 void 1872 cs_start_output(struct ifnet *ifp) 1873 { 1874 struct cs_softc *sc; 1875 struct mbuf *pMbuf; 1876 struct mbuf *pMbufChain; 1877 u_int16_t BusStatus; 1878 u_int16_t Length; 1879 int txLoop = 0; 1880 int dropout = 0; 1881 1882 sc = ifp->if_softc; 1883 1884 /* check that the interface is up and running */ 1885 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1886 return; 1887 } 1888 1889 /* Don't interrupt a transmission in progress */ 1890 if (sc->sc_txbusy) { 1891 return; 1892 } 1893 1894 /* this loop will only run through once if transmission is successful */ 1895 /* 1896 * While there are packets to transmit and a transmit is not in 1897 * progress 1898 */ 1899 while (sc->sc_txbusy == 0 && dropout == 0) { 1900 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain); 1901 if (pMbufChain == NULL) 1902 break; 1903 1904 /* 1905 * If BPF is listening on this interface, let it see the packet 1906 * before we commit it to the wire. 1907 */ 1908 bpf_mtap(ifp, pMbufChain); 1909 1910 /* Find the total length of the data to transmit */ 1911 Length = 0; 1912 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next) 1913 Length += pMbuf->m_len; 1914 1915 do { 1916 /* 1917 * Request that the transmit be started after all 1918 * data has been copied 1919 * 1920 * In IO mode must write to the IO port not the packet 1921 * page address 1922 * 1923 * If this is changed to start transmission after a 1924 * small amount of data has been copied you tend to 1925 * get packet missed errors i think because the ISA 1926 * bus is too slow. Or possibly the copy routine is 1927 * not streamlined enough. 1928 */ 1929 if (sc->sc_memorymode) { 1930 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD, 1931 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1932 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length); 1933 } 1934 else { 1935 CS_WRITE_PORT(sc, PORT_TX_CMD, 1936 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1937 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length); 1938 } 1939 1940 /* 1941 * Adjust early-transmit machinery. 1942 */ 1943 if (--sc->sc_xe_togo == 0) { 1944 sc->sc_xe_ent = 1945 cs_xmit_early_table[sc->sc_xe_ent].better; 1946 sc->sc_xe_togo = 1947 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1948 } 1949 /* 1950 * Read the BusStatus register which indicates 1951 * success of the request 1952 */ 1953 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST); 1954 1955 /* 1956 * If there was an error in the transmit bid free the 1957 * mbuf and go on. This is presuming that mbuf is 1958 * corrupt. 1959 */ 1960 if (BusStatus & BUS_ST_TX_BID_ERR) { 1961 aprint_error_dev(sc->sc_dev, 1962 "transmit bid error (too big)"); 1963 1964 /* Discard the bad mbuf chain */ 1965 m_freem(pMbufChain); 1966 sc->sc_ethercom.ec_if.if_oerrors++; 1967 1968 /* Loop up to transmit the next chain */ 1969 txLoop = 0; 1970 } else { 1971 if (BusStatus & BUS_ST_RDY4TXNOW) { 1972 /* 1973 * The chip is ready for transmission 1974 * now 1975 */ 1976 /* 1977 * Copy the frame to the chip to 1978 * start transmission 1979 */ 1980 cs_copy_tx_frame(sc, pMbufChain); 1981 1982 /* Free the mbuf chain */ 1983 m_freem(pMbufChain); 1984 1985 /* Transmission is now in progress */ 1986 sc->sc_txbusy = TRUE; 1987 txLoop = 0; 1988 } else { 1989 /* 1990 * if we get here we want to try 1991 * again with the same mbuf, until 1992 * the chip lets us transmit. 1993 */ 1994 txLoop++; 1995 if (txLoop > CS_OUTPUT_LOOP_MAX) { 1996 /* Free the mbuf chain */ 1997 m_freem(pMbufChain); 1998 /* 1999 * Transmission is not in 2000 * progress 2001 */ 2002 sc->sc_txbusy = FALSE; 2003 /* 2004 * Increment the output error 2005 * count 2006 */ 2007 ifp->if_oerrors++; 2008 /* 2009 * exit the routine and drop 2010 * the packet. 2011 */ 2012 txLoop = 0; 2013 dropout = 1; 2014 } 2015 } 2016 } 2017 } while (txLoop); 2018 } 2019 } 2020 2021 void 2022 cs_copy_tx_frame(struct cs_softc *sc, struct mbuf *m0) 2023 { 2024 struct mbuf *m; 2025 int len, leftover, frameoff; 2026 u_int16_t dbuf; 2027 u_int8_t *p; 2028 #ifdef DIAGNOSTIC 2029 u_int8_t *lim; 2030 #endif 2031 2032 /* Initialize frame pointer and data port address */ 2033 frameoff = PKTPG_TX_FRAME; 2034 2035 /* start out with no leftover data */ 2036 leftover = 0; 2037 dbuf = 0; 2038 2039 /* Process the chain of mbufs */ 2040 for (m = m0; m != NULL; m = m->m_next) { 2041 /* 2042 * Process all of the data in a single mbuf. 2043 */ 2044 p = mtod(m, u_int8_t *); 2045 len = m->m_len; 2046 #ifdef DIAGNOSTIC 2047 lim = p + len; 2048 #endif 2049 2050 while (len > 0) { 2051 if (leftover) { 2052 /* 2053 * Data left over (from mbuf or realignment). 2054 * Buffer the next byte, and write it and 2055 * the leftover data out. 2056 */ 2057 dbuf |= *p++ << 8; 2058 len--; 2059 if (sc->sc_memorymode) { 2060 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2061 frameoff += 2; 2062 } 2063 else { 2064 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2065 } 2066 leftover = 0; 2067 } else if ((long) p & 1) { 2068 /* 2069 * Misaligned data. Buffer the next byte. 2070 */ 2071 dbuf = *p++; 2072 len--; 2073 leftover = 1; 2074 } else { 2075 /* 2076 * Aligned data. This is the case we like. 2077 * 2078 * Write-region out as much as we can, then 2079 * buffer the remaining byte (if any). 2080 */ 2081 leftover = len & 1; 2082 len &= ~1; 2083 if (sc->sc_memorymode) { 2084 MEM_WRITE_REGION_2(sc, frameoff, 2085 (u_int16_t *) p, len >> 1); 2086 frameoff += len; 2087 } 2088 else { 2089 IO_WRITE_MULTI_2(sc, 2090 PORT_RXTX_DATA, (u_int16_t *)p, len >> 1); 2091 } 2092 p += len; 2093 2094 if (leftover) 2095 dbuf = *p++; 2096 len = 0; 2097 } 2098 } 2099 if (len < 0) 2100 panic("cs_copy_tx_frame: negative len"); 2101 #ifdef DIAGNOSTIC 2102 if (p != lim) 2103 panic("cs_copy_tx_frame: p != lim"); 2104 #endif 2105 } 2106 if (leftover) { 2107 if (sc->sc_memorymode) { 2108 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2109 } 2110 else { 2111 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2112 } 2113 } 2114 } 2115 2116 static int 2117 cs_enable(struct cs_softc *sc) 2118 { 2119 2120 if (CS_IS_ENABLED(sc) == 0) { 2121 if (sc->sc_enable != NULL) { 2122 int error; 2123 2124 error = (*sc->sc_enable)(sc); 2125 if (error) 2126 return (error); 2127 } 2128 sc->sc_cfgflags |= CFGFLG_ENABLED; 2129 } 2130 2131 return (0); 2132 } 2133 2134 static void 2135 cs_disable(struct cs_softc *sc) 2136 { 2137 2138 if (CS_IS_ENABLED(sc)) { 2139 if (sc->sc_disable != NULL) 2140 (*sc->sc_disable)(sc); 2141 2142 sc->sc_cfgflags &= ~CFGFLG_ENABLED; 2143 } 2144 } 2145 2146 static void 2147 cs_stop(struct ifnet *ifp, int disable) 2148 { 2149 struct cs_softc *sc = ifp->if_softc; 2150 2151 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0); 2152 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0); 2153 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0); 2154 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0); 2155 2156 if (disable) { 2157 cs_disable(sc); 2158 } 2159 2160 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2161 } 2162 2163 int 2164 cs_activate(device_t self, enum devact act) 2165 { 2166 struct cs_softc *sc = device_private(self); 2167 2168 switch (act) { 2169 case DVACT_DEACTIVATE: 2170 if_deactivate(&sc->sc_ethercom.ec_if); 2171 return 0; 2172 default: 2173 return EOPNOTSUPP; 2174 } 2175 } 2176
Indexes created Thu Oct 02 14:10:14 GMT 2025