cs89x0.c revision 1.4
1 /* $NetBSD: cs89x0.c,v 1.4 2002/04/18 21:58:02 thorpej Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 **++ 38 ** FACILITY 39 ** 40 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller. 41 ** 42 ** ABSTRACT 43 ** 44 ** This module provides standard ethernet access for INET protocols 45 ** only. 46 ** 47 ** AUTHORS 48 ** 49 ** Peter Dettori SEA - Software Engineering. 50 ** 51 ** CREATION DATE: 52 ** 53 ** 13-Feb-1997. 54 ** 55 ** MODIFICATION HISTORY (Digital): 56 ** 57 ** Revision 1.27 1998/01/20 17:59:40 cgd 58 ** update for moved headers 59 ** 60 ** Revision 1.26 1998/01/12 19:29:36 cgd 61 ** use arm32/isa versions of isadma code. 62 ** 63 ** Revision 1.25 1997/12/12 01:35:27 cgd 64 ** convert to use new arp code (from Brini) 65 ** 66 ** Revision 1.24 1997/12/10 22:31:56 cgd 67 ** trim some fat (get rid of ability to explicitly supply enet addr, since 68 ** it was never used and added a bunch of code which really doesn't belong in 69 ** an enet driver), and clean up slightly. 70 ** 71 ** Revision 1.23 1997/10/06 16:42:12 cgd 72 ** copyright notices 73 ** 74 ** Revision 1.22 1997/06/20 19:38:01 chaiken 75 ** fixes some smartcard problems 76 ** 77 ** Revision 1.21 1997/06/10 02:56:20 grohn 78 ** Added call to ledNetActive 79 ** 80 ** Revision 1.20 1997/06/05 00:47:06 dettori 81 ** Changed cs_process_rx_dma to reset and re-initialise the 82 ** ethernet chip when DMA gets out of sync, or mbufs 83 ** can't be allocated. 84 ** 85 ** Revision 1.19 1997/06/03 03:09:58 dettori 86 ** Turn off sc_txbusy flag when a transmit underrun 87 ** occurs. 88 ** 89 ** Revision 1.18 1997/06/02 00:04:35 dettori 90 ** redefined the transmit table to get around the nfs_timer bug while we are 91 ** looking into it further. 92 ** 93 ** Also changed interrupts from EDGE to LEVEL. 94 ** 95 ** Revision 1.17 1997/05/27 23:31:01 dettori 96 ** Pulled out changes to DMAMODE defines. 97 ** 98 ** Revision 1.16 1997/05/23 04:25:16 cgd 99 ** reformat log so it fits in 80cols 100 ** 101 ** Revision 1.15 1997/05/23 04:22:18 cgd 102 ** remove the existing copyright notice (which Peter Dettori indicated 103 ** was incorrect, copied from an existing NetBSD file only so that the 104 ** file would have a copyright notice on it, and which he'd intended to 105 ** replace). Replace it with a Digital copyright notice, cloned from 106 ** ess.c. It's not really correct either (it indicates that the source 107 ** is Digital confidential!), but is better than nothing and more 108 ** correct than what was there before. 109 ** 110 ** Revision 1.14 1997/05/23 04:12:50 cgd 111 ** use an adaptive transmit start algorithm: start by telling the chip 112 ** to start transmitting after 381 bytes have been fed to it. if that 113 ** gets transmit underruns, ramp down to 1021 bytes then "whole 114 ** packet." If successful at a given level for a while, try the next 115 ** more agressive level. This code doesn't ever try to start 116 ** transmitting after 5 bytes have been sent to the NIC, because 117 ** that underruns rather regularly. The back-off and ramp-up mechanism 118 ** could probably be tuned a little bit, but this works well enough to 119 ** support > 1MB/s transmit rates on a clear ethernet (which is about 120 ** 20-25% better than the driver had previously been getting). 121 ** 122 ** Revision 1.13 1997/05/22 21:06:54 cgd 123 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly 124 ** casting from u_int8_t * to u_int16_t * without worrying about alignment 125 ** issues. This would cause bogus data to be spit out for mbufs with 126 ** misaligned data. For instance, it caused the following bits to appear 127 ** on the wire: 128 ** ... etBND 1S2C .SHA(K) R ... 129 ** 11112222333344445555 130 ** which should have appeared as: 131 ** ... NetBSD 1.2C (SHARK) ... 132 ** 11112222333344445555 133 ** Note the apparent 'rotate' of the bytes in the word, which was due to 134 ** incorrect unaligned accesses. This data corruption was the cause of 135 ** incoming telnet/rlogin hangs. 136 ** 137 ** Revision 1.12 1997/05/22 01:55:32 cgd 138 ** reformat log so it fits in 80cols 139 ** 140 ** Revision 1.11 1997/05/22 01:50:27 cgd 141 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case, 142 ** so packets aimed at other hosts don't get sent to ether_input(). 143 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that 144 ** you can easily tell (`strings`) what version of the driver is in your 145 ** kernel binary. 146 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily 147 ** safe, and not really a performance win anyway. (It was only used when 148 ** setting up the multicast logical address filter, which is an 149 ** infrequent event. It could have been used in the IFF_PROMISCUOUS 150 ** address check above, but the benefit of it vs. memcmp would be 151 ** inconsequential, there.) Use memcmp() instead. 152 ** * restructure csStartOuput to avoid the following bugs in the case where 153 ** txWait was being set: 154 ** * it would accidentally drop the outgoing packet if told to wait 155 ** but the outgoing packet queue was empty. 156 ** * it would bpf_mtap() the outgoing packet multiple times (once for 157 ** each time it was told to wait), and would also recalculate 158 ** the length of the outgoing packet each time it was told to 159 ** wait. 160 ** While there, rename txWait to txLoop, since with the new structure of 161 ** the code, the latter name makes more sense. 162 ** 163 ** Revision 1.10 1997/05/19 02:03:20 cgd 164 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip() 165 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this 166 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC 167 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave 168 ** as before. 169 ** 170 ** Revision 1.9 1997/05/19 01:45:37 cgd 171 ** create a new function, cs_ether_input(), which does received-packet 172 ** BPF and ether_input processing. This code used to be in three places, 173 ** and centralizing it will make adding IFF_PROMISC support much easier. 174 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to 175 ** do copies with bus_space_write_region_2(). It's more correct, and 176 ** potentially more efficient. That function needs to be gutted (to 177 ** deal properly with alignment issues, which it currently does wrong), 178 ** however, and the change doesn't gain much, so there's no point in 179 ** enabling it now. 180 ** 181 ** Revision 1.8 1997/05/19 01:17:10 cgd 182 ** fix a comment re: the setting of the TxConfig register. Clean up 183 ** interface counter maintenance (make it use standard idiom). 184 ** 185 **-- 186 */ 187 188 #include <sys/cdefs.h> 189 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.4 2002/04/18 21:58:02 thorpej Exp $"); 190 191 #include "opt_inet.h" 192 193 #include <sys/param.h> 194 #include <sys/systm.h> 195 #include <sys/mbuf.h> 196 #include <sys/syslog.h> 197 #include <sys/socket.h> 198 #include <sys/device.h> 199 #include <sys/malloc.h> 200 #include <sys/ioctl.h> 201 #include <sys/errno.h> 202 203 #include "rnd.h" 204 #if NRND > 0 205 #include <sys/rnd.h> 206 #endif 207 208 #include <net/if.h> 209 #include <net/if_ether.h> 210 #include <net/if_media.h> 211 #ifdef INET 212 #include <netinet/in.h> 213 #include <netinet/if_inarp.h> 214 #endif 215 216 #include "bpfilter.h" 217 #if NBPFILTER > 0 218 #include <net/bpf.h> 219 #include <net/bpfdesc.h> 220 #endif 221 222 #include <uvm/uvm_extern.h> 223 224 #include <machine/bus.h> 225 #include <machine/intr.h> 226 227 #include <dev/ic/cs89x0reg.h> 228 #include <dev/ic/cs89x0var.h> 229 230 #ifdef SHARK 231 #include <shark/shark/sequoia.h> 232 #endif 233 234 /* 235 * MACRO DEFINITIONS 236 */ 237 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */ 238 239 /* 240 * FUNCTION PROTOTYPES 241 */ 242 void cs_get_default_media __P((struct cs_softc *)); 243 int cs_get_params __P((struct cs_softc *)); 244 int cs_get_enaddr __P((struct cs_softc *)); 245 int cs_reset_chip __P((struct cs_softc *)); 246 void cs_reset __P((void *)); 247 int cs_ioctl __P((struct ifnet *, u_long, caddr_t)); 248 void cs_initChip __P((struct cs_softc *)); 249 void cs_buffer_event __P((struct cs_softc *, u_int16_t)); 250 void cs_transmit_event __P((struct cs_softc *, u_int16_t)); 251 void cs_receive_event __P((struct cs_softc *, u_int16_t)); 252 void cs_process_receive __P((struct cs_softc *)); 253 void cs_process_rx_early __P((struct cs_softc *)); 254 void cs_start_output __P((struct ifnet *)); 255 void cs_copy_tx_frame __P((struct cs_softc *, struct mbuf *)); 256 void cs_set_ladr_filt __P((struct cs_softc *, struct ethercom *)); 257 u_int16_t cs_hash_index __P((char *)); 258 void cs_counter_event __P((struct cs_softc *, u_int16_t)); 259 260 int cs_mediachange __P((struct ifnet *)); 261 void cs_mediastatus __P((struct ifnet *, struct ifmediareq *)); 262 263 static int cs_enable __P((struct cs_softc *)); 264 static void cs_disable __P((struct cs_softc *)); 265 static void cs_stop __P((struct ifnet *, int)); 266 static void cs_power __P((int, void *)); 267 268 /* 269 * GLOBAL DECLARATIONS 270 */ 271 272 /* 273 * Xmit-early table. 274 * 275 * To get better performance, we tell the chip to start packet 276 * transmission before the whole packet is copied to the chip. 277 * However, this can fail under load. When it fails, we back off 278 * to a safer setting for a little while. 279 * 280 * txcmd is the value of txcmd used to indicate when to start transmission. 281 * better is the next 'better' state in the table. 282 * better_count is the number of output packets before transition to the 283 * better state. 284 * worse is the next 'worse' state in the table. 285 * 286 * Transition to the next worse state happens automatically when a 287 * transmittion underrun occurs. 288 */ 289 struct cs_xmit_early { 290 u_int16_t txcmd; 291 int better; 292 int better_count; 293 int worse; 294 } cs_xmit_early_table[3] = { 295 { TX_CMD_START_381, 0, INT_MAX, 1, }, 296 { TX_CMD_START_1021, 0, 50000, 2, }, 297 { TX_CMD_START_ALL, 1, 5000, 2, }, 298 }; 299 300 int cs_default_media[] = { 301 IFM_ETHER|IFM_10_2, 302 IFM_ETHER|IFM_10_5, 303 IFM_ETHER|IFM_10_T, 304 IFM_ETHER|IFM_10_T|IFM_FDX, 305 }; 306 int cs_default_nmedia = sizeof(cs_default_media) / sizeof(cs_default_media[0]); 307 308 int 309 cs_attach(sc, enaddr, media, nmedia, defmedia) 310 struct cs_softc *sc; 311 u_int8_t *enaddr; 312 int *media, nmedia, defmedia; 313 { 314 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 315 const char *chipname, *medname; 316 u_int16_t reg; 317 int i; 318 319 /* Start out in IO mode */ 320 sc->sc_memorymode = FALSE; 321 322 /* make sure we're right */ 323 for (i = 0; i < 10000; i++) { 324 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 325 if (reg == EISA_NUM_CRYSTAL) { 326 break; 327 } 328 } 329 if (i == 10000) { 330 printf("%s: wrong id(0x%x)\n", sc->sc_dev.dv_xname, reg); 331 return 1; /* XXX should panic? */ 332 } 333 334 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID); 335 sc->sc_prodid = reg & PROD_ID_MASK; 336 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8; 337 338 switch (sc->sc_prodid) { 339 case PROD_ID_CS8900: 340 chipname = "CS8900"; 341 break; 342 case PROD_ID_CS8920: 343 chipname = "CS8920"; 344 break; 345 case PROD_ID_CS8920M: 346 chipname = "CS8920M"; 347 break; 348 default: 349 panic("cs_attach: impossible"); 350 } 351 352 /* 353 * the first thing to do is check that the mbuf cluster size is 354 * greater than the MTU for an ethernet frame. The code depends on 355 * this and to port this to a OS where this was not the case would 356 * not be straightforward. 357 * 358 * we need 1 byte spare because our 359 * packet read loop can overrun. 360 * and we may need pad bytes to align ip header. 361 */ 362 if (MCLBYTES < ETHER_MAX_LEN + 1 + 363 ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header)) { 364 printf("%s: MCLBYTES too small for Ethernet frame\n", 365 sc->sc_dev.dv_xname); 366 return 1; 367 } 368 369 /* Start out not transmitting */ 370 sc->sc_txbusy = FALSE; 371 372 /* Set up early transmit threshhold */ 373 sc->sc_xe_ent = 0; 374 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count; 375 376 /* Initialize ifnet structure. */ 377 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 378 ifp->if_softc = sc; 379 ifp->if_start = cs_start_output; 380 ifp->if_init = cs_init; 381 ifp->if_ioctl = cs_ioctl; 382 ifp->if_stop = cs_stop; 383 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 384 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | 385 IFF_BROADCAST | IFF_MULTICAST; 386 IFQ_SET_READY(&ifp->if_snd); 387 388 /* Initialize ifmedia structures. */ 389 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus); 390 391 if (media != NULL) { 392 for (i = 0; i < nmedia; i++) 393 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 394 ifmedia_set(&sc->sc_media, defmedia); 395 } else { 396 for (i = 0; i < cs_default_nmedia; i++) 397 ifmedia_add(&sc->sc_media, cs_default_media[i], 398 0, NULL); 399 cs_get_default_media(sc); 400 } 401 402 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 403 /* Get parameters from the EEPROM */ 404 if (cs_get_params(sc) == CS_ERROR) { 405 printf("%s: unable to get settings from EEPROM\n", 406 sc->sc_dev.dv_xname); 407 return 1; 408 } 409 } 410 411 if (enaddr != NULL) 412 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 413 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 414 /* Get and store the Ethernet address */ 415 if (cs_get_enaddr(sc) == CS_ERROR) { 416 printf("%s: unable to read Ethernet address\n", 417 sc->sc_dev.dv_xname); 418 return 1; 419 } 420 } else { 421 printf("%s: no Ethernet address!\n", sc->sc_dev.dv_xname); 422 return 1; 423 } 424 425 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) { 426 case IFM_10_2: 427 medname = "BNC"; 428 break; 429 case IFM_10_5: 430 medname = "AUI"; 431 break; 432 case IFM_10_T: 433 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 434 medname = "UTP <full-duplex>"; 435 else 436 medname = "UTP"; 437 break; 438 default: 439 panic("cs_attach: impossible"); 440 } 441 printf("%s: %s rev. %c, address %s, media %s\n", sc->sc_dev.dv_xname, 442 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr), 443 medname); 444 445 if (sc->sc_dma_attach) 446 (*sc->sc_dma_attach)(sc); 447 448 sc->sc_sh = shutdownhook_establish(cs_reset, sc); 449 if (sc->sc_sh == NULL) { 450 printf("%s: unable to establish shutdownhook\n", 451 sc->sc_dev.dv_xname); 452 cs_detach(sc); 453 return 1; 454 } 455 456 /* Attach the interface. */ 457 if_attach(ifp); 458 ether_ifattach(ifp, sc->sc_enaddr); 459 460 #if NRND > 0 461 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 462 RND_TYPE_NET, 0); 463 #endif 464 sc->sc_cfgflags |= CFGFLG_ATTACHED; 465 466 /* Reset the chip */ 467 if (cs_reset_chip(sc) == CS_ERROR) { 468 printf("%s: reset failed\n", sc->sc_dev.dv_xname); 469 cs_detach(sc); 470 return 1; 471 } 472 473 sc->sc_powerhook = powerhook_establish(cs_power, sc); 474 if (sc->sc_powerhook == 0) 475 printf("%s: warning: powerhook_establish failed\n", 476 sc->sc_dev.dv_xname); 477 478 return 0; 479 } 480 481 int 482 cs_detach(sc) 483 struct cs_softc *sc; 484 { 485 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 486 487 if (sc->sc_powerhook) { 488 powerhook_disestablish(sc->sc_powerhook); 489 sc->sc_powerhook = 0; 490 } 491 492 if (sc->sc_cfgflags & CFGFLG_ATTACHED) { 493 #if NRND > 0 494 rnd_detach_source(&sc->rnd_source); 495 #endif 496 ether_ifdetach(ifp); 497 if_detach(ifp); 498 sc->sc_cfgflags &= ~CFGFLG_ATTACHED; 499 } 500 501 if (sc->sc_sh != NULL) 502 shutdownhook_disestablish(sc->sc_sh); 503 504 #if 0 505 /* 506 * XXX not necessary 507 */ 508 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) { 509 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, sc->sc_dmasize); 510 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, sc->sc_dmasize); 511 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq); 512 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE; 513 } 514 #endif 515 516 return 0; 517 } 518 519 void 520 cs_get_default_media(sc) 521 struct cs_softc *sc; 522 { 523 u_int16_t adp_cfg, xmit_ctl; 524 525 if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 526 printf("%s: cs_get_default_media: EEPROM missing or bad\n", 527 sc->sc_dev.dv_xname); 528 goto fakeit; 529 } 530 531 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ADPTR_CFG, 532 &adp_cfg) == CS_ERROR) { 533 printf("%s: unable to read adapter config from EEPROM\n", 534 sc->sc_dev.dv_xname); 535 goto fakeit; 536 } 537 538 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_XMIT_CTL, 539 &xmit_ctl) == CS_ERROR) { 540 printf("%s: unable to read transmit control from EEPROM\n", 541 sc->sc_dev.dv_xname); 542 goto fakeit; 543 } 544 545 switch (adp_cfg & ADPTR_CFG_MEDIA) { 546 case ADPTR_CFG_AUI: 547 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5); 548 break; 549 case ADPTR_CFG_10BASE2: 550 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2); 551 break; 552 case ADPTR_CFG_10BASET: 553 default: 554 if (xmit_ctl & XMIT_CTL_FDX) 555 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX); 556 else 557 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 558 break; 559 } 560 return; 561 562 fakeit: 563 printf("%s: WARNING: default media setting may be inaccurate\n", 564 sc->sc_dev.dv_xname); 565 /* XXX Arbitrary... */ 566 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 567 } 568 569 int 570 cs_get_params(sc) 571 struct cs_softc *sc; 572 { 573 u_int16_t isaConfig; 574 u_int16_t adapterConfig; 575 576 if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 577 printf("%s: cs_get_params: EEPROM missing or bad\n", 578 sc->sc_dev.dv_xname); 579 return (CS_ERROR); 580 } 581 582 /* Get ISA configuration from the EEPROM */ 583 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ISA_CFG, 584 &isaConfig) == CS_ERROR) 585 goto eeprom_bad; 586 587 /* Get adapter configuration from the EEPROM */ 588 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_ADPTR_CFG, 589 &adapterConfig) == CS_ERROR) 590 goto eeprom_bad; 591 592 /* Copy the USE_SA flag */ 593 if (isaConfig & ISA_CFG_USE_SA) 594 sc->sc_cfgflags |= CFGFLG_USE_SA; 595 596 /* Copy the IO Channel Ready flag */ 597 if (isaConfig & ISA_CFG_IOCHRDY) 598 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 599 600 /* Copy the DC/DC Polarity flag */ 601 if (adapterConfig & ADPTR_CFG_DCDC_POL) 602 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 603 604 return (CS_OK); 605 606 eeprom_bad: 607 printf("%s: cs_get_params: unable to read from EEPROM\n", 608 sc->sc_dev.dv_xname); 609 return (CS_ERROR); 610 } 611 612 int 613 cs_get_enaddr(sc) 614 struct cs_softc *sc; 615 { 616 u_int16_t *myea; 617 618 if (cs_verify_eeprom(sc->sc_iot, sc->sc_ioh) == CS_ERROR) { 619 printf("%s: cs_get_enaddr: EEPROM missing or bad\n", 620 sc->sc_dev.dv_xname); 621 return (CS_ERROR); 622 } 623 624 myea = (u_int16_t *)sc->sc_enaddr; 625 626 /* Get Ethernet address from the EEPROM */ 627 /* XXX this will likely lose on a big-endian machine. -- cgd */ 628 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_H, 629 &myea[0]) == CS_ERROR) 630 goto eeprom_bad; 631 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_M, 632 &myea[1]) == CS_ERROR) 633 goto eeprom_bad; 634 if (cs_read_eeprom(sc->sc_iot, sc->sc_ioh, EEPROM_IND_ADDR_L, 635 &myea[2]) == CS_ERROR) 636 goto eeprom_bad; 637 638 return (CS_OK); 639 640 eeprom_bad: 641 printf("%s: cs_get_enaddr: unable to read from EEPROM\n", 642 sc->sc_dev.dv_xname); 643 return (CS_ERROR); 644 } 645 646 int 647 cs_reset_chip(sc) 648 struct cs_softc *sc; 649 { 650 int intState; 651 int x; 652 653 /* Disable interrupts at the CPU so reset command is atomic */ 654 intState = splnet(); 655 656 /* 657 * We are now resetting the chip 658 * 659 * A spurious interrupt is generated by the chip when it is reset. This 660 * variable informs the interrupt handler to ignore this interrupt. 661 */ 662 sc->sc_resetting = TRUE; 663 664 /* Issue a reset command to the chip */ 665 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET); 666 667 /* Re-enable interrupts at the CPU */ 668 splx(intState); 669 670 /* The chip is always in IO mode after a reset */ 671 sc->sc_memorymode = FALSE; 672 673 /* If transmission was in progress, it is not now */ 674 sc->sc_txbusy = FALSE; 675 676 /* 677 * there was a delay(125); here, but it seems uneccesary 125 usec is 678 * 1/8000 of a second, not 1/8 of a second. the data sheet advises 679 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below 680 * should be sufficient. 681 */ 682 683 /* Transition SBHE to switch chip from 8-bit to 16-bit */ 684 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 0); 685 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 1); 686 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 0); 687 bus_space_read_1(sc->sc_iot, sc->sc_ioh, PORT_PKTPG_PTR + 1); 688 689 /* Wait until the EEPROM is not busy */ 690 for (x = 0; x < MAXLOOP; x++) { 691 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY)) 692 break; 693 } 694 695 if (x == MAXLOOP) 696 return CS_ERROR; 697 698 /* Wait until initialization is done */ 699 for (x = 0; x < MAXLOOP; x++) { 700 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE) 701 break; 702 } 703 704 if (x == MAXLOOP) 705 return CS_ERROR; 706 707 /* Reset is no longer in progress */ 708 sc->sc_resetting = FALSE; 709 710 return CS_OK; 711 } 712 713 int 714 cs_verify_eeprom(iot, ioh) 715 bus_space_tag_t iot; 716 bus_space_handle_t ioh; 717 { 718 u_int16_t self_status; 719 720 /* Verify that the EEPROM is present and OK */ 721 self_status = CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST); 722 if (((self_status & SELF_ST_EEP_PRES) && 723 (self_status & SELF_ST_EEP_OK)) == 0) 724 return (CS_ERROR); 725 726 return (CS_OK); 727 } 728 729 int 730 cs_read_eeprom(iot, ioh, offset, pValue) 731 bus_space_tag_t iot; 732 bus_space_handle_t ioh; 733 int offset; 734 u_int16_t *pValue; 735 { 736 int x; 737 738 /* Ensure that the EEPROM is not busy */ 739 for (x = 0; x < MAXLOOP; x++) { 740 if (!(CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST) & 741 SELF_ST_SI_BUSY)) 742 break; 743 } 744 745 if (x == MAXLOOP) 746 return (CS_ERROR); 747 748 /* Issue the command to read the offset within the EEPROM */ 749 CS_WRITE_PACKET_PAGE_IO(iot, ioh, PKTPG_EEPROM_CMD, 750 offset | EEPROM_CMD_READ); 751 752 /* Wait until the command is completed */ 753 for (x = 0; x < MAXLOOP; x++) { 754 if (!(CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_SELF_ST) & 755 SELF_ST_SI_BUSY)) 756 break; 757 } 758 759 if (x == MAXLOOP) 760 return (CS_ERROR); 761 762 /* Get the EEPROM data from the EEPROM Data register */ 763 *pValue = CS_READ_PACKET_PAGE_IO(iot, ioh, PKTPG_EEPROM_DATA); 764 765 return (CS_OK); 766 } 767 768 void 769 cs_initChip(sc) 770 struct cs_softc *sc; 771 { 772 u_int16_t busCtl; 773 u_int16_t selfCtl; 774 u_int16_t *myea; 775 u_int16_t isaId; 776 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media); 777 778 /* Disable reception and transmission of frames */ 779 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 780 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) & 781 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON); 782 783 /* Disable interrupt at the chip */ 784 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 785 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL); 786 787 /* If IOCHRDY is enabled then clear the bit in the busCtl register */ 788 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL); 789 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) { 790 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 791 busCtl & ~BUS_CTL_IOCHRDY); 792 } else { 793 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 794 busCtl | BUS_CTL_IOCHRDY); 795 } 796 797 /* Set the Line Control register to match the media type */ 798 if (media == IFM_10_T) 799 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET); 800 else 801 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY); 802 803 /* 804 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to 805 * enable the DC/DC converter 806 */ 807 selfCtl = SELF_CTL_HC1E; 808 809 /* If the media type is 10Base2 */ 810 if (media == IFM_10_2) { 811 /* 812 * Enable the DC/DC converter if it has a low enable. 813 */ 814 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0) 815 /* 816 * Set the HCB1 bit, which causes the HC1 pin to go 817 * low. 818 */ 819 selfCtl |= SELF_CTL_HCB1; 820 } else { /* Media type is 10BaseT or AUI */ 821 /* 822 * Disable the DC/DC converter if it has a high enable. 823 */ 824 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) { 825 /* 826 * Set the HCB1 bit, which causes the HC1 pin to go 827 * low. 828 */ 829 selfCtl |= SELF_CTL_HCB1; 830 } 831 } 832 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl); 833 834 /* enable normal link pulse */ 835 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M) 836 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE); 837 838 /* Enable full-duplex, if appropriate */ 839 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 840 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX); 841 842 /* RX_CTL set in cs_set_ladr_filt(), below */ 843 844 /* enable all transmission interrupts */ 845 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE); 846 847 /* Accept all receive interrupts */ 848 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE); 849 850 /* 851 * Configure Operational Modes 852 * 853 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this is 854 * a better way to do it because the card has a counter which can be 855 * read to update the RX_MISS counter. This saves many interupts. 856 * 857 * I have turned on the tx and rx overflow interupts to counter using 858 * the receive miss interrupt. This is a better estimate of errors 859 * and requires lower system overhead. 860 */ 861 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE | 862 BUF_CFG_RX_DMA_IE); 863 864 if (sc->sc_dma_chipinit) 865 (*sc->sc_dma_chipinit)(sc); 866 867 /* If memory mode is enabled */ 868 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) { 869 /* If external logic is present for address decoding */ 870 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) { 871 /* 872 * Program the external logic to decode address bits 873 * SA20-SA23 874 */ 875 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD, 876 ((sc->sc_pktpgaddr & 0xffffff) >> 20) | 877 EEPROM_CMD_ELSEL); 878 } 879 880 /* 881 * Write the packet page base physical address to the memory 882 * base register. 883 */ 884 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0, 885 sc->sc_pktpgaddr & 0xFFFF); 886 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2, 887 sc->sc_pktpgaddr >> 16); 888 busCtl = BUS_CTL_MEM_MODE; 889 890 /* tell the chip to read the addresses off the SA pins */ 891 if (sc->sc_cfgflags & CFGFLG_USE_SA) { 892 busCtl |= BUS_CTL_USE_SA; 893 } 894 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 895 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl); 896 897 /* We are in memory mode now! */ 898 sc->sc_memorymode = TRUE; 899 900 /* 901 * wait here (10ms) for the chip to swap over. this is the 902 * maximum time that this could take. 903 */ 904 delay(10000); 905 906 /* Verify that we can read from the chip */ 907 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 908 909 /* 910 * As a last minute sanity check before actually using mapped 911 * memory we verify that we can read the isa number from the 912 * chip in memory mode. 913 */ 914 if (isaId != EISA_NUM_CRYSTAL) { 915 printf("%s: failed to enable memory mode\n", 916 sc->sc_dev.dv_xname); 917 sc->sc_memorymode = FALSE; 918 } else { 919 /* 920 * we are in memory mode so if we aren't using DMA, 921 * then program the chip to interrupt early. 922 */ 923 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) { 924 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 925 BUF_CFG_RX_DEST_IE | 926 BUF_CFG_RX_MISS_OVER_IE | 927 BUF_CFG_TX_COL_OVER_IE); 928 } 929 } 930 931 } 932 933 /* Put Ethernet address into the Individual Address register */ 934 myea = (u_int16_t *)sc->sc_enaddr; 935 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 0, myea[0]); 936 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 2, myea[1]); 937 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + 4, myea[2]); 938 939 if (sc->sc_irq != -1) { 940 /* Set the interrupt level in the chip */ 941 if (sc->sc_prodid == PROD_ID_CS8900) { 942 if (sc->sc_irq == 5) { 943 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3); 944 } else { 945 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, (sc->sc_irq) - 10); 946 } 947 } 948 else { /* CS8920 */ 949 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, sc->sc_irq); 950 } 951 } 952 953 /* write the multicast mask to the address filter register */ 954 cs_set_ladr_filt(sc, &sc->sc_ethercom); 955 956 /* Enable reception and transmission of frames */ 957 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 958 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) | 959 LINE_CTL_RX_ON | LINE_CTL_TX_ON); 960 961 /* Enable interrupt at the chip */ 962 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 963 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL); 964 } 965 966 int 967 cs_init(ifp) 968 struct ifnet *ifp; 969 { 970 int intState; 971 int error = CS_OK; 972 struct cs_softc *sc = ifp->if_softc; 973 974 if (cs_enable(sc)) 975 goto out; 976 977 cs_stop(ifp, 0); 978 979 intState = splnet(); 980 981 #if 0 982 /* Mark the interface as down */ 983 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING); 984 #endif 985 986 #ifdef CS_DEBUG 987 /* Enable debugging */ 988 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG; 989 #endif 990 991 /* Reset the chip */ 992 if ((error = cs_reset_chip(sc)) == CS_OK) { 993 /* Initialize the chip */ 994 cs_initChip(sc); 995 996 /* Mark the interface as running */ 997 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 998 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 999 sc->sc_ethercom.ec_if.if_timer = 0; 1000 1001 /* Assume we have carrier until we are told otherwise. */ 1002 sc->sc_carrier = 1; 1003 } else { 1004 printf("%s: unable to reset chip\n", sc->sc_dev.dv_xname); 1005 } 1006 1007 splx(intState); 1008 out: 1009 if (error == CS_OK) 1010 return 0; 1011 return EIO; 1012 } 1013 1014 void 1015 cs_set_ladr_filt(sc, ec) 1016 struct cs_softc *sc; 1017 struct ethercom *ec; 1018 { 1019 struct ifnet *ifp = &ec->ec_if; 1020 struct ether_multi *enm; 1021 struct ether_multistep step; 1022 u_int16_t af[4]; 1023 u_int16_t port, mask, index; 1024 1025 /* 1026 * Set up multicast address filter by passing all multicast addresses 1027 * through a crc generator, and then using the high order 6 bits as an 1028 * index into the 64 bit logical address filter. The high order bit 1029 * selects the word, while the rest of the bits select the bit within 1030 * the word. 1031 */ 1032 if (ifp->if_flags & IFF_PROMISC) { 1033 /* accept all valid frames. */ 1034 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1035 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A | 1036 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1037 ifp->if_flags |= IFF_ALLMULTI; 1038 return; 1039 } 1040 1041 /* 1042 * accept frames if a. crc valid, b. individual address match c. 1043 * broadcast address,and d. multicast addresses matched in the hash 1044 * filter 1045 */ 1046 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1047 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1048 1049 1050 /* 1051 * start off with all multicast flag clear, set it if we need to 1052 * later, otherwise we will leave it. 1053 */ 1054 ifp->if_flags &= ~IFF_ALLMULTI; 1055 af[0] = af[1] = af[2] = af[3] = 0x0000; 1056 1057 /* 1058 * Loop through all the multicast addresses unless we get a range of 1059 * addresses, in which case we will just accept all packets. 1060 * Justification for this is given in the next comment. 1061 */ 1062 ETHER_FIRST_MULTI(step, ec, enm); 1063 while (enm != NULL) { 1064 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1065 sizeof enm->enm_addrlo)) { 1066 /* 1067 * We must listen to a range of multicast addresses. 1068 * For now, just accept all multicasts, rather than 1069 * trying to set only those filter bits needed to match 1070 * the range. (At this time, the only use of address 1071 * ranges is for IP multicast routing, for which the 1072 * range is big enough to require all bits set.) 1073 */ 1074 ifp->if_flags |= IFF_ALLMULTI; 1075 af[0] = af[1] = af[2] = af[3] = 0xffff; 1076 break; 1077 } else { 1078 /* 1079 * we have got an individual address so just set that 1080 * bit. 1081 */ 1082 index = cs_hash_index(enm->enm_addrlo); 1083 1084 /* Set the bit the Logical address filter. */ 1085 port = (u_int16_t) (index >> 4); 1086 mask = (u_int16_t) (1 << (index & 0xf)); 1087 af[port] |= mask; 1088 1089 ETHER_NEXT_MULTI(step, enm); 1090 } 1091 } 1092 1093 /* now program the chip with the addresses */ 1094 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]); 1095 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]); 1096 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]); 1097 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]); 1098 return; 1099 } 1100 1101 u_int16_t 1102 cs_hash_index(addr) 1103 char *addr; 1104 { 1105 uint32_t crc; 1106 uint16_t hash_code; 1107 1108 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1109 1110 hash_code = crc >> 26; 1111 return (hash_code); 1112 } 1113 1114 void 1115 cs_reset(arg) 1116 void *arg; 1117 { 1118 struct cs_softc *sc = arg; 1119 1120 /* Mark the interface as down */ 1121 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1122 1123 /* Reset the chip */ 1124 cs_reset_chip(sc); 1125 } 1126 1127 int 1128 cs_ioctl(ifp, cmd, data) 1129 struct ifnet *ifp; 1130 u_long cmd; 1131 caddr_t data; 1132 { 1133 struct cs_softc *sc = ifp->if_softc; 1134 struct ifreq *ifr = (struct ifreq *) data; 1135 int state; 1136 int result; 1137 1138 state = splnet(); 1139 1140 result = 0; /* only set if something goes wrong */ 1141 1142 switch (cmd) { 1143 case SIOCGIFMEDIA: 1144 case SIOCSIFMEDIA: 1145 result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1146 break; 1147 1148 default: 1149 result = ether_ioctl(ifp, cmd, data); 1150 if (result == ENETRESET) { 1151 if (CS_IS_ENABLED(sc)) { 1152 /* 1153 * Multicast list has changed. Set the 1154 * hardware filter accordingly. 1155 */ 1156 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1157 } 1158 result = 0; 1159 } 1160 break; 1161 } 1162 1163 splx(state); 1164 1165 return result; 1166 } 1167 1168 int 1169 cs_mediachange(ifp) 1170 struct ifnet *ifp; 1171 { 1172 1173 /* 1174 * Current media is already set up. Just reset the interface 1175 * to let the new value take hold. 1176 */ 1177 cs_init(ifp); 1178 return (0); 1179 } 1180 1181 void 1182 cs_mediastatus(ifp, ifmr) 1183 struct ifnet *ifp; 1184 struct ifmediareq *ifmr; 1185 { 1186 struct cs_softc *sc = ifp->if_softc; 1187 1188 /* 1189 * The currently selected media is always the active media. 1190 */ 1191 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media; 1192 1193 if (ifp->if_flags & IFF_UP) { 1194 /* Interface up, status is valid. */ 1195 ifmr->ifm_status = IFM_AVALID | 1196 (sc->sc_carrier ? IFM_ACTIVE : 0); 1197 } 1198 else ifmr->ifm_status = 0; 1199 } 1200 1201 int 1202 cs_intr(arg) 1203 void *arg; 1204 { 1205 struct cs_softc *sc = arg; 1206 u_int16_t Event; 1207 #if NRND > 0 1208 u_int16_t rndEvent; 1209 #endif 1210 1211 /* Ignore any interrupts that happen while the chip is being reset */ 1212 if (sc->sc_resetting) { 1213 printf("%s: cs_intr: reset in progress\n", 1214 sc->sc_dev.dv_xname); 1215 return 1; 1216 } 1217 1218 /* Read an event from the Interrupt Status Queue */ 1219 if (sc->sc_memorymode) 1220 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1221 else 1222 Event = CS_READ_PORT(sc, PORT_ISQ); 1223 1224 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff) 1225 return 0; /* not ours */ 1226 1227 #if NRND > 0 1228 rndEvent = Event; 1229 #endif 1230 1231 /* Process all the events in the Interrupt Status Queue */ 1232 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) { 1233 /* Dispatch to an event handler based on the register number */ 1234 switch (Event & REG_NUM_MASK) { 1235 case REG_NUM_RX_EVENT: 1236 cs_receive_event(sc, Event); 1237 break; 1238 case REG_NUM_TX_EVENT: 1239 cs_transmit_event(sc, Event); 1240 break; 1241 case REG_NUM_BUF_EVENT: 1242 cs_buffer_event(sc, Event); 1243 break; 1244 case REG_NUM_TX_COL: 1245 case REG_NUM_RX_MISS: 1246 cs_counter_event(sc, Event); 1247 break; 1248 default: 1249 printf("%s: unknown interrupt event 0x%x\n", 1250 sc->sc_dev.dv_xname, Event); 1251 break; 1252 } 1253 1254 /* Read another event from the Interrupt Status Queue */ 1255 if (sc->sc_memorymode) 1256 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1257 else 1258 Event = CS_READ_PORT(sc, PORT_ISQ); 1259 } 1260 1261 /* have handled the interupt */ 1262 #if NRND > 0 1263 rnd_add_uint32(&sc->rnd_source, rndEvent); 1264 #endif 1265 return 1; 1266 } 1267 1268 void 1269 cs_counter_event(sc, cntEvent) 1270 struct cs_softc *sc; 1271 u_int16_t cntEvent; 1272 { 1273 struct ifnet *ifp; 1274 u_int16_t errorCount; 1275 1276 ifp = &sc->sc_ethercom.ec_if; 1277 1278 switch (cntEvent & REG_NUM_MASK) { 1279 case REG_NUM_TX_COL: 1280 /* 1281 * the count should be read before an overflow occurs. 1282 */ 1283 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL); 1284 /* 1285 * the tramsit event routine always checks the number of 1286 * collisions for any packet so we don't increment any 1287 * counters here, as they should already have been 1288 * considered. 1289 */ 1290 break; 1291 case REG_NUM_RX_MISS: 1292 /* 1293 * the count should be read before an overflow occurs. 1294 */ 1295 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS); 1296 /* 1297 * Increment the input error count, the first 6bits are the 1298 * register id. 1299 */ 1300 ifp->if_ierrors += ((errorCount & 0xffC0) >> 6); 1301 break; 1302 default: 1303 /* do nothing */ 1304 break; 1305 } 1306 } 1307 1308 void 1309 cs_buffer_event(sc, bufEvent) 1310 struct cs_softc *sc; 1311 u_int16_t bufEvent; 1312 { 1313 struct ifnet *ifp; 1314 1315 ifp = &sc->sc_ethercom.ec_if; 1316 1317 /* 1318 * multiple events can be in the buffer event register at one time so 1319 * a standard switch statement will not suffice, here every event 1320 * must be checked. 1321 */ 1322 1323 /* 1324 * if 128 bits have been rxed by the time we get here, the dest event 1325 * will be cleared and 128 event will be set. 1326 */ 1327 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) { 1328 cs_process_rx_early(sc); 1329 } 1330 1331 if (bufEvent & BUF_EVENT_RX_DMA) { 1332 /* process the receive data */ 1333 if (sc->sc_dma_process_rx) 1334 (*sc->sc_dma_process_rx)(sc); 1335 else 1336 /* should panic? */ 1337 printf("%s: unexpected dma event\n", sc->sc_dev.dv_xname); 1338 } 1339 1340 if (bufEvent & BUF_EVENT_TX_UNDR) { 1341 #if 0 1342 /* 1343 * This can happen occasionally, and it's not worth worrying 1344 * about. 1345 */ 1346 printf("%s: transmit underrun (%d -> %d)\n", 1347 sc->sc_dev.dv_xname, sc->sc_xe_ent, 1348 cs_xmit_early_table[sc->sc_xe_ent].worse); 1349 #endif 1350 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse; 1351 sc->sc_xe_togo = 1352 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1353 1354 /* had an underrun, transmit is finished */ 1355 sc->sc_txbusy = FALSE; 1356 } 1357 1358 if (bufEvent & BUF_EVENT_SW_INT) { 1359 printf("%s: software initiated interrupt\n", 1360 sc->sc_dev.dv_xname); 1361 } 1362 } 1363 1364 void 1365 cs_transmit_event(sc, txEvent) 1366 struct cs_softc *sc; 1367 u_int16_t txEvent; 1368 { 1369 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1370 1371 /* If there were any errors transmitting this frame */ 1372 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | TX_EVENT_OUT_WIN | 1373 TX_EVENT_JABBER | TX_EVENT_16_COLL)) { 1374 /* Increment the output error count */ 1375 ifp->if_oerrors++; 1376 1377 /* Note carrier loss. */ 1378 if (txEvent & TX_EVENT_LOSS_CRS) 1379 sc->sc_carrier = 0; 1380 1381 /* If debugging is enabled then log error messages */ 1382 if (ifp->if_flags & IFF_DEBUG) { 1383 if (txEvent & TX_EVENT_LOSS_CRS) { 1384 printf("%s: lost carrier\n", 1385 sc->sc_dev.dv_xname); 1386 } 1387 if (txEvent & TX_EVENT_SQE_ERR) { 1388 printf("%s: SQE error\n", 1389 sc->sc_dev.dv_xname); 1390 } 1391 if (txEvent & TX_EVENT_OUT_WIN) { 1392 printf("%s: out-of-window collision\n", 1393 sc->sc_dev.dv_xname); 1394 } 1395 if (txEvent & TX_EVENT_JABBER) { 1396 printf("%s: jabber\n", sc->sc_dev.dv_xname); 1397 } 1398 if (txEvent & TX_EVENT_16_COLL) { 1399 printf("%s: 16 collisions\n", 1400 sc->sc_dev.dv_xname); 1401 } 1402 } 1403 } 1404 else { 1405 /* Transmission successful, carrier is up. */ 1406 sc->sc_carrier = 1; 1407 #ifdef SHARK 1408 ledNetActive(); 1409 #endif 1410 } 1411 1412 /* Add the number of collisions for this frame */ 1413 if (txEvent & TX_EVENT_16_COLL) { 1414 ifp->if_collisions += 16; 1415 } else { 1416 ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11); 1417 } 1418 1419 ifp->if_opackets++; 1420 1421 /* Transmission is no longer in progress */ 1422 sc->sc_txbusy = FALSE; 1423 1424 /* If there is more to transmit */ 1425 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 1426 /* Start the next transmission */ 1427 cs_start_output(ifp); 1428 } 1429 } 1430 1431 void 1432 cs_print_rx_errors(sc, rxEvent) 1433 struct cs_softc *sc; 1434 u_int16_t rxEvent; 1435 { 1436 1437 if (rxEvent & RX_EVENT_RUNT) 1438 printf("%s: runt\n", sc->sc_dev.dv_xname); 1439 1440 if (rxEvent & RX_EVENT_X_DATA) 1441 printf("%s: extra data\n", sc->sc_dev.dv_xname); 1442 1443 if (rxEvent & RX_EVENT_CRC_ERR) { 1444 if (rxEvent & RX_EVENT_DRIBBLE) 1445 printf("%s: alignment error\n", sc->sc_dev.dv_xname); 1446 else 1447 printf("%s: CRC error\n", sc->sc_dev.dv_xname); 1448 } else { 1449 if (rxEvent & RX_EVENT_DRIBBLE) 1450 printf("%s: dribble bits\n", sc->sc_dev.dv_xname); 1451 } 1452 } 1453 1454 void 1455 cs_receive_event(sc, rxEvent) 1456 struct cs_softc *sc; 1457 u_int16_t rxEvent; 1458 { 1459 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1460 1461 /* If the frame was not received OK */ 1462 if (!(rxEvent & RX_EVENT_RX_OK)) { 1463 /* Increment the input error count */ 1464 ifp->if_ierrors++; 1465 1466 /* 1467 * If debugging is enabled then log error messages. 1468 */ 1469 if (ifp->if_flags & IFF_DEBUG) { 1470 if (rxEvent != REG_NUM_RX_EVENT) { 1471 cs_print_rx_errors(sc, rxEvent); 1472 1473 /* 1474 * Must read the length of all received 1475 * frames 1476 */ 1477 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1478 1479 /* Skip the received frame */ 1480 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1481 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | 1482 RX_CFG_SKIP); 1483 } else { 1484 printf("%s: implied skip\n", 1485 sc->sc_dev.dv_xname); 1486 } 1487 } 1488 } else { 1489 /* 1490 * process the received frame and pass it up to the upper 1491 * layers. 1492 */ 1493 cs_process_receive(sc); 1494 } 1495 } 1496 1497 void 1498 cs_ether_input(sc, m) 1499 struct cs_softc *sc; 1500 struct mbuf *m; 1501 { 1502 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1503 1504 ifp->if_ipackets++; 1505 1506 #if NBPFILTER > 0 1507 /* 1508 * Check if there's a BPF listener on this interface. 1509 * If so, hand off the raw packet to BPF. 1510 */ 1511 if (ifp->if_bpf) 1512 bpf_mtap(ifp->if_bpf, m); 1513 #endif 1514 1515 /* Pass the packet up. */ 1516 (*ifp->if_input)(ifp, m); 1517 } 1518 1519 void 1520 cs_process_receive(sc) 1521 struct cs_softc *sc; 1522 { 1523 struct ifnet *ifp; 1524 struct mbuf *m; 1525 int totlen; 1526 u_int16_t *pBuff, *pBuffLimit; 1527 int pad; 1528 unsigned int frameOffset; 1529 1530 #ifdef SHARK 1531 ledNetActive(); 1532 #endif 1533 1534 ifp = &sc->sc_ethercom.ec_if; 1535 1536 /* Received a packet; carrier is up. */ 1537 sc->sc_carrier = 1; 1538 1539 if (sc->sc_memorymode) { 1540 /* Initialize the frame offset */ 1541 frameOffset = PKTPG_RX_LENGTH; 1542 1543 /* Get the length of the received frame */ 1544 totlen = CS_READ_PACKET_PAGE(sc, frameOffset); 1545 frameOffset += 2; 1546 } 1547 else { 1548 /* drop status */ 1549 CS_READ_PORT(sc, PORT_RXTX_DATA); 1550 1551 /* Get the length of the received frame */ 1552 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA); 1553 } 1554 1555 if (totlen > ETHER_MAX_LEN) { 1556 printf("%s: invalid packet length\n", sc->sc_dev.dv_xname); 1557 1558 /* skip the received frame */ 1559 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1560 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1561 return; 1562 } 1563 1564 MGETHDR(m, M_DONTWAIT, MT_DATA); 1565 if (m == 0) { 1566 printf("%s: cs_process_receive: unable to allocate mbuf\n", 1567 sc->sc_dev.dv_xname); 1568 ifp->if_ierrors++; 1569 /* 1570 * couldn't allocate an mbuf so things are not good, may as 1571 * well drop the packet I think. 1572 * 1573 * have already read the length so we should be right to skip 1574 * the packet. 1575 */ 1576 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1577 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1578 return; 1579 } 1580 m->m_pkthdr.rcvif = ifp; 1581 m->m_pkthdr.len = totlen; 1582 1583 /* number of bytes to align ip header on word boundary for ipintr */ 1584 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1585 1586 /* 1587 * alloc mbuf cluster if we need. 1588 * we need 1 byte spare because following 1589 * packet read loop can overrun. 1590 */ 1591 if (totlen + pad + 1 > MHLEN) { 1592 MCLGET(m, M_DONTWAIT); 1593 if ((m->m_flags & M_EXT) == 0) { 1594 /* couldn't allocate an mbuf cluster */ 1595 printf("%s: cs_process_receive: unable to allocate a cluster\n", 1596 sc->sc_dev.dv_xname); 1597 m_freem(m); 1598 1599 /* skip the received frame */ 1600 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1601 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1602 return; 1603 } 1604 } 1605 1606 /* align ip header on word boundary for ipintr */ 1607 m->m_data += pad; 1608 1609 m->m_len = totlen; 1610 pBuff = mtod(m, u_int16_t *); 1611 1612 /* now read the data from the chip */ 1613 if (sc->sc_memorymode) { 1614 pBuffLimit = pBuff + (totlen + 1) / 2; /* don't want to go over */ 1615 while (pBuff < pBuffLimit) { 1616 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1617 frameOffset += 2; 1618 } 1619 } 1620 else { 1621 bus_space_read_multi_2(sc->sc_iot, sc->sc_ioh, PORT_RXTX_DATA, 1622 pBuff, (totlen + 1)>>1); 1623 } 1624 1625 cs_ether_input(sc, m); 1626 } 1627 1628 void 1629 cs_process_rx_early(sc) 1630 struct cs_softc *sc; 1631 { 1632 struct ifnet *ifp; 1633 struct mbuf *m; 1634 u_int16_t frameCount, oldFrameCount; 1635 u_int16_t rxEvent; 1636 u_int16_t *pBuff; 1637 int pad; 1638 unsigned int frameOffset; 1639 1640 1641 ifp = &sc->sc_ethercom.ec_if; 1642 1643 /* Initialize the frame offset */ 1644 frameOffset = PKTPG_RX_FRAME; 1645 frameCount = 0; 1646 1647 MGETHDR(m, M_DONTWAIT, MT_DATA); 1648 if (m == 0) { 1649 printf("%s: cs_process_rx_early: unable to allocate mbuf\n", 1650 sc->sc_dev.dv_xname); 1651 ifp->if_ierrors++; 1652 /* 1653 * couldn't allocate an mbuf so things are not good, may as 1654 * well drop the packet I think. 1655 * 1656 * have already read the length so we should be right to skip 1657 * the packet. 1658 */ 1659 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1660 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1661 return; 1662 } 1663 m->m_pkthdr.rcvif = ifp; 1664 /* 1665 * save processing by always using a mbuf cluster, guarenteed to fit 1666 * packet 1667 */ 1668 MCLGET(m, M_DONTWAIT); 1669 if ((m->m_flags & M_EXT) == 0) { 1670 /* couldn't allocate an mbuf cluster */ 1671 printf("%s: cs_process_rx_early: unable to allocate a cluster\n", 1672 sc->sc_dev.dv_xname); 1673 m_freem(m); 1674 /* skip the frame */ 1675 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1676 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1677 return; 1678 } 1679 1680 /* align ip header on word boundary for ipintr */ 1681 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1682 m->m_data += pad; 1683 1684 /* set up the buffer pointer to point to the data area */ 1685 pBuff = mtod(m, u_int16_t *); 1686 1687 /* 1688 * now read the frame byte counter until we have finished reading the 1689 * frame 1690 */ 1691 oldFrameCount = 0; 1692 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1693 while ((frameCount != 0) && (frameCount < MCLBYTES)) { 1694 for (; oldFrameCount < frameCount; oldFrameCount += 2) { 1695 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1696 frameOffset += 2; 1697 } 1698 1699 /* read the new count from the chip */ 1700 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1701 } 1702 1703 /* update the mbuf counts */ 1704 m->m_len = oldFrameCount; 1705 m->m_pkthdr.len = oldFrameCount; 1706 1707 /* now check the Rx Event register */ 1708 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1709 1710 if ((rxEvent & RX_EVENT_RX_OK) != 0) { 1711 /* 1712 * do an implied skip, it seems to be more reliable than a 1713 * forced skip. 1714 */ 1715 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS); 1716 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1717 1718 /* 1719 * now read the RX_EVENT register to perform an implied skip. 1720 */ 1721 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1722 1723 cs_ether_input(sc, m); 1724 } else { 1725 m_freem(m); 1726 ifp->if_ierrors++; 1727 } 1728 } 1729 1730 void 1731 cs_start_output(ifp) 1732 struct ifnet *ifp; 1733 { 1734 struct cs_softc *sc; 1735 struct mbuf *pMbuf; 1736 struct mbuf *pMbufChain; 1737 u_int16_t BusStatus; 1738 u_int16_t Length; 1739 int txLoop = 0; 1740 int dropout = 0; 1741 1742 sc = ifp->if_softc; 1743 1744 /* check that the interface is up and running */ 1745 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1746 return; 1747 } 1748 1749 /* Don't interrupt a transmission in progress */ 1750 if (sc->sc_txbusy) { 1751 return; 1752 } 1753 1754 /* this loop will only run through once if transmission is successful */ 1755 /* 1756 * While there are packets to transmit and a transmit is not in 1757 * progress 1758 */ 1759 while (sc->sc_txbusy == 0 && dropout == 0) { 1760 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain); 1761 if (pMbufChain == NULL) 1762 break; 1763 1764 #if NBPFILTER > 0 1765 /* 1766 * If BPF is listening on this interface, let it see the packet 1767 * before we commit it to the wire. 1768 */ 1769 if (ifp->if_bpf) 1770 bpf_mtap(ifp->if_bpf, pMbufChain); 1771 #endif 1772 1773 /* Find the total length of the data to transmit */ 1774 Length = 0; 1775 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next) 1776 Length += pMbuf->m_len; 1777 1778 do { 1779 /* 1780 * Request that the transmit be started after all 1781 * data has been copied 1782 * 1783 * In IO mode must write to the IO port not the packet 1784 * page address 1785 * 1786 * If this is changed to start transmission after a 1787 * small amount of data has been copied you tend to 1788 * get packet missed errors i think because the ISA 1789 * bus is too slow. Or possibly the copy routine is 1790 * not streamlined enough. 1791 */ 1792 if (sc->sc_memorymode) { 1793 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD, 1794 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1795 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length); 1796 } 1797 else { 1798 CS_WRITE_PORT(sc, PORT_TX_CMD, 1799 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1800 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length); 1801 } 1802 1803 /* 1804 * Adjust early-transmit machinery. 1805 */ 1806 if (--sc->sc_xe_togo == 0) { 1807 sc->sc_xe_ent = 1808 cs_xmit_early_table[sc->sc_xe_ent].better; 1809 sc->sc_xe_togo = 1810 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1811 } 1812 /* 1813 * Read the BusStatus register which indicates 1814 * success of the request 1815 */ 1816 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST); 1817 1818 /* 1819 * If there was an error in the transmit bid free the 1820 * mbuf and go on. This is presuming that mbuf is 1821 * corrupt. 1822 */ 1823 if (BusStatus & BUS_ST_TX_BID_ERR) { 1824 printf("%s: transmit bid error (too big)", 1825 sc->sc_dev.dv_xname); 1826 1827 /* Discard the bad mbuf chain */ 1828 m_freem(pMbufChain); 1829 sc->sc_ethercom.ec_if.if_oerrors++; 1830 1831 /* Loop up to transmit the next chain */ 1832 txLoop = 0; 1833 } else { 1834 if (BusStatus & BUS_ST_RDY4TXNOW) { 1835 /* 1836 * The chip is ready for transmission 1837 * now 1838 */ 1839 /* 1840 * Copy the frame to the chip to 1841 * start transmission 1842 */ 1843 cs_copy_tx_frame(sc, pMbufChain); 1844 1845 /* Free the mbuf chain */ 1846 m_freem(pMbufChain); 1847 1848 /* Transmission is now in progress */ 1849 sc->sc_txbusy = TRUE; 1850 txLoop = 0; 1851 } else { 1852 /* 1853 * if we get here we want to try 1854 * again with the same mbuf, until 1855 * the chip lets us transmit. 1856 */ 1857 txLoop++; 1858 if (txLoop > CS_OUTPUT_LOOP_MAX) { 1859 /* Free the mbuf chain */ 1860 m_freem(pMbufChain); 1861 /* 1862 * Transmission is not in 1863 * progress 1864 */ 1865 sc->sc_txbusy = FALSE; 1866 /* 1867 * Increment the output error 1868 * count 1869 */ 1870 ifp->if_oerrors++; 1871 /* 1872 * exit the routine and drop 1873 * the packet. 1874 */ 1875 txLoop = 0; 1876 dropout = 1; 1877 } 1878 } 1879 } 1880 } while (txLoop); 1881 } 1882 } 1883 1884 void 1885 cs_copy_tx_frame(sc, m0) 1886 struct cs_softc *sc; 1887 struct mbuf *m0; 1888 { 1889 struct mbuf *m; 1890 int len, leftover, frameoff; 1891 u_int16_t dbuf; 1892 u_int8_t *p; 1893 #ifdef DIAGNOSTIC 1894 u_int8_t *lim; 1895 #endif 1896 1897 /* Initialize frame pointer and data port address */ 1898 frameoff = PKTPG_TX_FRAME; 1899 1900 /* start out with no leftover data */ 1901 leftover = 0; 1902 dbuf = 0; 1903 1904 /* Process the chain of mbufs */ 1905 for (m = m0; m != NULL; m = m->m_next) { 1906 /* 1907 * Process all of the data in a single mbuf. 1908 */ 1909 p = mtod(m, u_int8_t *); 1910 len = m->m_len; 1911 #ifdef DIAGNOSTIC 1912 lim = p + len; 1913 #endif 1914 1915 while (len > 0) { 1916 if (leftover) { 1917 /* 1918 * Data left over (from mbuf or realignment). 1919 * Buffer the next byte, and write it and 1920 * the leftover data out. 1921 */ 1922 dbuf |= *p++ << 8; 1923 len--; 1924 if (sc->sc_memorymode) { 1925 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 1926 frameoff += 2; 1927 } 1928 else { 1929 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 1930 } 1931 leftover = 0; 1932 } else if ((long) p & 1) { 1933 /* 1934 * Misaligned data. Buffer the next byte. 1935 */ 1936 dbuf = *p++; 1937 len--; 1938 leftover = 1; 1939 } else { 1940 /* 1941 * Aligned data. This is the case we like. 1942 * 1943 * Write-region out as much as we can, then 1944 * buffer the remaining byte (if any). 1945 */ 1946 leftover = len & 1; 1947 len &= ~1; 1948 if (sc->sc_memorymode) { 1949 bus_space_write_region_2(sc->sc_memt, sc->sc_memh, frameoff, 1950 (u_int16_t *) p, len >> 1); 1951 frameoff += len; 1952 } 1953 else { 1954 bus_space_write_multi_2(sc->sc_iot, sc->sc_ioh, 1955 PORT_RXTX_DATA, (u_int16_t *)p, len >> 1); 1956 } 1957 p += len; 1958 1959 if (leftover) 1960 dbuf = *p++; 1961 len = 0; 1962 } 1963 } 1964 if (len < 0) 1965 panic("cs_copy_tx_frame: negative len"); 1966 #ifdef DIAGNOSTIC 1967 if (p != lim) 1968 panic("cs_copy_tx_frame: p != lim"); 1969 #endif 1970 } 1971 if (leftover) { 1972 if (sc->sc_memorymode) { 1973 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 1974 } 1975 else { 1976 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 1977 } 1978 } 1979 } 1980 1981 static int 1982 cs_enable(sc) 1983 struct cs_softc *sc; 1984 { 1985 1986 if (CS_IS_ENABLED(sc) == 0) { 1987 if (sc->sc_enable != NULL) { 1988 int error; 1989 1990 error = (*sc->sc_enable)(sc); 1991 if (error) 1992 return (error); 1993 } 1994 sc->sc_cfgflags |= CFGFLG_ENABLED; 1995 } 1996 1997 return (0); 1998 } 1999 2000 static void 2001 cs_disable(sc) 2002 struct cs_softc *sc; 2003 { 2004 2005 if (CS_IS_ENABLED(sc)) { 2006 if (sc->sc_disable != NULL) 2007 (*sc->sc_disable)(sc); 2008 2009 sc->sc_cfgflags &= ~CFGFLG_ENABLED; 2010 } 2011 } 2012 2013 static void 2014 cs_stop(ifp, disable) 2015 struct ifnet *ifp; 2016 int disable; 2017 { 2018 struct cs_softc *sc = ifp->if_softc; 2019 2020 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0); 2021 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0); 2022 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0); 2023 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0); 2024 2025 if (disable) { 2026 cs_disable(sc); 2027 } 2028 2029 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2030 } 2031 2032 int 2033 cs_activate(self, act) 2034 struct device *self; 2035 enum devact act; 2036 { 2037 struct cs_softc *sc = (void *)self; 2038 int s, error = 0; 2039 2040 s = splnet(); 2041 switch (act) { 2042 case DVACT_ACTIVATE: 2043 error = EOPNOTSUPP; 2044 break; 2045 2046 case DVACT_DEACTIVATE: 2047 if_deactivate(&sc->sc_ethercom.ec_if); 2048 break; 2049 } 2050 splx(s); 2051 2052 return error; 2053 } 2054 2055 static void 2056 cs_power(why, arg) 2057 int why; 2058 void *arg; 2059 { 2060 struct cs_softc *sc = arg; 2061 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2062 int s; 2063 2064 s = splnet(); 2065 switch (why) { 2066 case PWR_STANDBY: 2067 case PWR_SUSPEND: 2068 cs_stop(ifp, 0); 2069 break; 2070 case PWR_RESUME: 2071 if (ifp->if_flags & IFF_UP) { 2072 cs_init(ifp); 2073 } 2074 break; 2075 case PWR_SOFTSUSPEND: 2076 case PWR_SOFTSTANDBY: 2077 case PWR_SOFTRESUME: 2078 break; 2079 } 2080 splx(s); 2081 } 2082
Indexes created Fri Oct 03 02:09:57 GMT 2025